Semiconductor structure and manufacturing method thereof
By forming an opening with a specific dopant distribution in the semiconductor structure, the serious problem of leakage in the semiconductor structure is solved, and the process yield and capacitance performance are improved.
Patent Information
- Application Number
- CN202510067940.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-09-25
- Filing Date
- 2025-01-16
- Publication Date
- 2025-04-25
AI Technical Summary
As the size of the semiconductor structure decreases, leakage becomes more serious, affecting the process yield of the semiconductor structure.
By forming a multi-layer support layer and oxide layer on the active device layer and etching on these layers, openings with a specific dopant distribution are formed to reduce leakage.
This method effectively reduces leakage, improves the process yield of semiconductor structures, and improves capacitor and leakage performance.
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Figure CN119893989A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a semiconductor structure and a manufacturing method thereof. Background Art
[0002] As electronic devices become lighter and thinner, semiconductor devices such as dynamic random access memory (DRAM) are becoming more highly integrated. In addition, the performance of DRAM is improved by shortening the pitch between semiconductor structures in DRAM. As the size of semiconductor structures decreases, in addition to increasing the difficulty of the process, the components in the semiconductor structure are also prone to leakage due to the close pitch.
[0003] Therefore, in the semiconductor manufacturing process, how to reduce leakage to improve the process yield of the semiconductor structure becomes an important issue. Summary of the invention
[0004] Some embodiments of the present invention provide a method for manufacturing a semiconductor structure, comprising the following steps: forming a first support layer on an active device layer; depositing an oxide layer on the first support layer, wherein the oxide layer includes a dopant, and the concentration of the dopant gradually increases from an upper portion of the oxide layer to a lower portion of the oxide layer; forming a second support layer on the oxide layer; etching the second support layer, the oxide layer, and the first support layer to form a first opening to expose a portion of a top surface of the active device layer.
[0005] In some embodiments, the dopant is boron.
[0006] In some embodiments, the etch selectivity of the lower portion of the oxide layer is greater than the etch selectivity of the upper portion of the oxide layer.
[0007] In some embodiments, the concentration of the etchant that etches the oxide layer is positively correlated to the concentration of the dopant in the oxide layer.
[0008] In some embodiments, a width of the opening in the upper portion of the oxide layer is substantially equal to a width of the opening in the lower portion of the oxide layer.
[0009] In some embodiments, the method further comprises the following steps: After forming the first opening, depositing a first conductive layer in the first opening; removing the oxide layer to form a second opening to expose a portion of an outer surface of the first conductive layer.
[0010] In some embodiments, the method further comprises the following steps: forming an insulating layer on the first conductive layer in the first opening and forming an inner conductive layer in the second opening, conformally depositing a second conductive layer on the insulating layer and conformally depositing a second inner conductive layer on the inner conductive layer, forming a third conductive layer on the second conductive layer and forming a third inner conductive layer on the second inner conductive layer, respectively.
[0011] Some other embodiments of the present invention provide a method for manufacturing a semiconductor structure, comprising the following steps: forming a first supporting layer on an active device layer; depositing an oxide layer containing a dopant on the first supporting layer, wherein an upper portion of the oxide layer has a first doping concentration, a middle portion of the oxide layer has a second doping concentration greater than the first doping concentration, and a lower portion of the oxide layer has a third doping concentration greater than the second doping concentration; forming a second supporting layer on the oxide layer; etching the second supporting layer, the oxide layer, and the first supporting layer to form a first opening to expose a portion of the top surface of the active device layer.
[0012] In some embodiments, etching the second supporting layer, the oxide layer, and the first supporting layer includes a wet etching process.
[0013] In some embodiments, the concentration of the etchant that etches the upper portion of the oxide layer is less than the concentration of the etchant that etches the middle portion of the oxide layer, and the concentration of the etchant that etches the middle portion of the oxide layer is less than the concentration of the etchant that etches the lower portion of the oxide layer.
[0014] In some embodiments, after etching, a side surface of an upper portion of the oxide layer exposed by the first opening, a side surface of a middle portion of the oxide layer exposed by the first opening, and a side surface of a lower portion of the oxide layer exposed by the first opening are coplanar.
[0015] In some embodiments, the method further comprises the following steps: After forming the first opening, conformally depositing a first conductive layer in the first opening; and removing the oxide layer to form a second opening.
[0016] In some embodiments, the method further comprises the following steps: A sidewall of the first conductive layer is substantially perpendicular to a top surface of the active device layer.
[0017] In some embodiments, the method further comprises the following steps: forming an insulating layer on the first conductive layer in the first opening and forming an inner insulating layer in the second opening, conformally depositing a second conductive layer on the insulating layer and conformally depositing a second inner conductive layer on the inner insulating layer, forming a third conductive layer on the second conductive layer to fill the first opening, and forming a third inner conductive layer on the second conductive layer to fill the second opening.
[0018] Some other embodiments of the present invention provide a semiconductor structure. The semiconductor structure includes an active device layer disposed above a substrate and a capacitor structure disposed on the active device layer. The capacitor structure includes a first conductive layer disposed on the active device layer, an insulating layer disposed on the first conductive layer, a second conductive layer disposed on the insulating layer, a third conductive layer disposed on the second conductive layer, a bottom inner insulating layer surrounding the first conductive layer in a top view, a second inner conductive layer surrounding the bottom inner insulating layer in a top view, and a third inner conductive layer surrounding the second inner conductive layer in a top view.
[0019] In some embodiments, the capacitor structure further includes a first dielectric layer disposed on the active device layer and surrounding a bottom of the first conductive layer, wherein a side surface of the bottom inner insulating layer contacting a sidewall of the first conductive layer is substantially perpendicular to a top surface of the first dielectric layer.
[0020] In some embodiments, the capacitor structure further includes a second dielectric layer disposed on the bottom inner insulating layer and surrounding a sidewall of the first conductive layer, wherein a side surface of the bottom inner insulating layer contacting the sidewall of the first conductive layer is substantially perpendicular to a bottom surface of the second dielectric layer.
[0021] In some embodiments, the capacitor structure further includes a top inner insulating layer disposed on the second dielectric layer and surrounding the first conductive layer in a top view, a top second inner conductive layer surrounding the top inner insulating layer in a top view, and a top third inner conductive layer surrounding the top second inner conductive layer in a top view.
[0022] In some embodiments, in the cross-sectional view, the first conductive layer has a height and a width, and a ratio of the height to the width is greater than 30.
[0023] In some embodiments, the capacitor structure further includes a third dielectric layer disposed on the top second inner insulating layer and surrounding a sidewall of the first conductive layer, wherein a top surface of the third dielectric layer is coplanar with a top surface of the first conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The following embodiments are read with the accompanying drawings to clearly understand the concept of the present invention. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily enlarged or reduced for clear discussion.
[0025] Figure 1 and Figure 2 is a cross-sectional view of a method for manufacturing a semiconductor structure according to some embodiments of the present invention during formation of a first opening;
[0026] Figures 3 to 5 is a cross-sectional view of a method of manufacturing a semiconductor structure during formation of a capacitor structure according to some embodiments of the present invention; and
[0027] Figure 6 is based on Figure 5 Top view of the section line XX'. DETAILED DESCRIPTION
[0028] Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.
[0029] In addition, for ease of description, spatially relative terms such as "on", "above", "below", "between", etc. may be used in the present invention to describe the relationship of one element or feature to another element as shown in the drawings) or function. In addition to the orientation depicted in the drawings, spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used in the present invention should be interpreted accordingly.
[0030] The terms "including", "having", "comprising" and the like used in the present invention are open terms, meaning including but not limited to.
[0031] It should be noted that when the following drawings (such as Figures 1 to 6 ) is described and illustrated as a series of operations or steps, the order in which these operations or steps are described should not be limited. For example, some operations or steps may be performed in a different order than in the present invention, or some operations or steps may occur simultaneously, or some operations may not be performed, and / or some operations or steps may be repeated. In addition, the actual operations or steps of the process stage may be different in the formation of the semiconductor structure (for example, Figure 6 Additional operations or steps are performed before, during, or after the semiconductor structure 100 in the embodiment to form the semiconductor structure 100. Therefore, the present invention may briefly describe some of these additional operations or steps. In addition, unless otherwise specified, for the following figures (e.g. Figures 1 to 6 )The same explanations discussed above can be directly applied to the other figures.
[0032] As the size of DRAM becomes smaller and smaller, the prior art uses a high aspect ratio contact (HARC) process to form a capacitor structure with a high aspect ratio. However, after the high aspect ratio contact process, each opening configured to form the capacitor structure is tapered. Since the tapered opening does not have enough space to completely fill the capacitor material (especially the bottom of the capacitor structure), the capacitance of the capacitor structure will deteriorate. In view of this, an embodiment of the present invention provides a solution to the above problem.
[0033] See also Figure 1 and Figure 2 . Figure 1 and Figure 2 is a cross-sectional view of a method for manufacturing a semiconductor structure according to some embodiments of the present invention during the formation of a first opening. Figure 1 In the embodiment, an active device layer 112 is provided on a substrate 110. In some embodiments, the substrate 110 includes silicon, such as crystalline silicon, polycrystalline silicon, or amorphous silicon. The substrate 110 may include an elemental semiconductor, such as germanium. In some embodiments, the substrate 110 may include an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium indium phosphide, or other suitable materials. In some embodiments, the substrate 110 may include a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), indium arsenide (InAs), or other suitable materials. In addition, in some embodiments, the substrate 110 may optionally have a semiconductor-on-insulator (SOI) structure. In addition, the active device layer 112 includes a gate structure, a bit line structure, a contact plug, and other active devices.
[0034] Next, a first supporting layer 120 is formed on the active device layer 112. In some embodiments, the first supporting layer 120 includes a dielectric material, such as a nitride. In some embodiments, the first supporting layer 120 includes SiN. In some embodiments, the first supporting layer 120 is formed by a deposition process, such as chemical vapor deposition (CVD). Then, a bottom oxide layer 130 is deposited on the first supporting layer 120. In addition, the bottom oxide layer 130 includes a dopant, and the concentration of the dopant gradually increases from the upper portion 136 of the bottom oxide layer 130 to the lower portion 132 of the bottom oxide layer 130. In some embodiments, the dopant is boron. Figure 1 As shown, the bottom oxide layer 130 may basically include three layers, namely, an upper portion 136, a middle portion 134, and a lower portion 132 of the bottom oxide layer 130. In addition, the upper portion 136 of the bottom oxide layer 130 has a first doping concentration, the middle portion 134 of the bottom oxide layer 130 has a second doping concentration greater than the first doping concentration, and the lower portion 132 of the bottom oxide layer 130 has a third doping concentration greater than the second doping concentration.
[0035] In addition, a second supporting layer 140 is formed on the bottom oxide layer 130. In some embodiments, the second supporting layer 140 includes a dielectric material, such as a nitride, such as SiN. In some embodiments, the second supporting layer 140 is formed by a deposition process, such as CVD. Then, a top oxide layer 150 is deposited on the second supporting layer 140. Similarly, the top oxide layer 150 includes a dopant, and the concentration of the dopant gradually increases from an upper portion 156 of the top oxide layer 150 to a lower portion 152 of the top oxide layer 150. In some embodiments, the dopant is boron. The upper portion 156 of the top oxide layer 150 has a first doping concentration, the middle portion 154 of the top oxide layer 150 has a second doping concentration greater than the first doping concentration, and the lower portion 152 of the top oxide layer 150 has a third doping concentration greater than the second doping concentration.
[0036] Then, a third supporting layer 160 is formed on the top oxide layer 150. In some embodiments, the third supporting layer 160 includes a dielectric material, such as a nitride, such as SiN. In some embodiments, the second supporting layer 140 is formed by a deposition process, such as CVD.
[0037] Then, in Figure 2 In the embodiment of the present invention, the third supporting layer 160, the top oxide layer 150, the second supporting layer 140, the bottom oxide layer 130 and the first supporting layer 120 are etched to form a first opening OP1 to expose a portion of the top surface of the active device layer 112. In some embodiments, the third supporting layer 160, the top oxide layer 150, the second supporting layer 140, the bottom oxide layer 130 and the first supporting layer 120 are etched by a wet etching process. In addition, the etchant concentration of the wet etching process for etching the bottom oxide layer 130 and the top oxide layer 150 is positively correlated with the dopant concentration in the bottom oxide layer 130 and the top oxide layer 150. Specifically, taking the bottom oxide layer 130 as an example, since the first doping concentration of the upper portion 136 of the bottom oxide layer 130 is less than the second doping concentration of the middle portion 134 of the bottom oxide layer 130, the etchant concentration for etching the upper portion 136 of the bottom oxide layer 130 is less than the etchant concentration for etching the middle portion 134 of the bottom oxide layer 130. Furthermore, since the second doping concentration of the middle portion 134 of the bottom oxide layer 130 is less than the third doping concentration of the lower portion 132 of the bottom oxide layer 130 , the etchant concentration in the middle portion 134 of the bottom oxide layer 130 is less than the etchant concentration in the lower portion 132 of the bottom oxide layer 130 .
[0038] Specifically, by doping the bottom oxide layer 130 with dopants of different concentrations, the etching selectivity of the lower portion 132 of the bottom oxide layer 130 is greater than the etching selectivity of the middle portion 134 of the bottom oxide layer 130, and the etching selectivity of the middle portion 134 of the bottom oxide layer 130 is greater than the etching selectivity of the upper portion 136 of the bottom oxide layer 130. In addition, the etching mechanism for etching the top oxide layer 150 (including dopant distribution, etchant distribution, and etching selectivity of the oxide layer based on the dopant distribution) is also similar to the concentration mechanism for etching the bottom oxide layer 130, which will not be described in detail herein.
[0039] Based on the etching mechanism, the opening width W1 of the upper portion 136 of the bottom oxide layer 130 is substantially equal to the opening width W2 of the middle portion 134 of the bottom oxide layer 130, and the opening width W2 of the middle portion 134 of the bottom oxide layer 130 is substantially equal to the opening width W3 of the lower portion 132 of the bottom oxide layer 130. Figure 2 Although not shown, the opening width of the upper portion 156 of the top oxide layer 150 is substantially equal to the opening width of the middle portion 154 of the top oxide layer 150, and the opening width of the middle portion 154 of the top oxide layer 150 is substantially equal to the opening width of the lower portion 152 of the top oxide layer 150. In other words, the first opening OP1 is not tapered in the cross-sectional view by the etching mechanism.
[0040] Next, see Figures 3 to 6 . Figures 3 to 6 is a cross-sectional view of a method of manufacturing a semiconductor structure according to some embodiments of the present invention during formation of a capacitor structure, and Figure 6 is based on Figure 5 Top view of the section line XX'.
[0041] exist Figure 3 In the embodiment, after forming the first opening OP1, the first conductive layer 170 is conformally formed in the first opening OP1. Specifically, the first conductive layer 170 is formed on the bottom and sidewalls of the first opening OP1. In some embodiments, the first conductive layer 170 includes TiN. In addition, the sidewalls of the first conductive layer 170 are substantially perpendicular to the top surface of the active device layer 112. Then, the bottom oxide layer 130 (such as Figure 2 ) and a top oxide layer 150 (as shown Figure 2 As shown), two second openings OP2 are formed to allow the bottom oxide layer 130 (as shown) to be Figure 2 ) and the top oxide layer 150 (as shown Figure 2Specifically, one of the two second openings OP2 exposes the outer surface of the upper portion of the first conductive layer 170, while the other of the two second openings OP2 exposes the outer surface of the bottom of the first conductive layer 170. In addition, after the two second openings OP2 are formed, the first supporting layer 120, the second supporting layer 140, and the third supporting layer 160 still surround the first conductive layer 170, so that the structure of the first conductive layer 170 and the first opening OP1 may not collapse and the structure may still be maintained. In some embodiments, the bottom oxide layer 130 (as shown in FIG. 1 ) is removed by an etching process. Figure 2 ) and a top oxide layer 150 (as shown Figure 2 shown).
[0042] Then, in Figure 4 , the insulating layer 180 is conformally deposited on the first opening OP1, and the inner insulating layer 180i is conformally deposited on the outer surface of the first conductive layer 170 of each second opening OP2. Specifically, the inner insulating layer 180i is conformally deposited on the outer surface of the upper portion of the first conductive layer 170, the bottom surface of the third supporting layer 160, and the top surface of the second supporting layer 140 exposed by one of the two second openings OP2, and the inner insulating layer 180i is also conformally deposited on the outer surface of the bottom of the first conductive layer 170, the bottom surface of the second supporting layer 140, and the top surface of the second supporting layer 140 exposed by the other of the two second openings OP2. In some embodiments, the insulating layer 180 and the inner insulating layer 180i include a high-K material, such as a material with a K value higher than that of silicon dioxide.
[0043] Further, in Figure 5 In the embodiment, after the insulating layer 180 and the inner insulating layer 180i are formed, the second conductive layer 190 is conformally formed in the first opening OP1 (eg Figure 4 ) on the insulating layer 180, and the second inner conductive layer 190i is conformally formed in each second opening OP2 (eg Figure 4 ) on the inner insulating layer 180i. In some embodiments, the second conductive layer 190 and the second inner conductive layer 190i include TiN.
[0044] Next, a third conductive layer 210 is formed on the second conductive layer 190 to fill the first opening OP1 (eg, Figure 4 ), and a third inner conductive layer 210i is formed on the second inner conductive layer 190i to fill each second opening OP2 (eg Figure 4 ). In some embodiments, the third conductive layer 210 and the third inner conductive layer 210i include polysilicon. Figure 6In the top view, with the center of the capacitor structure CP as the inner side, after forming the third conductive layer 210 and the third inner conductive layer 210i, the capacitor structure CP includes the third inner conductive layer 210i, the second inner conductive layer 190i, the inner insulating layer 180i, the first conductive layer 170, the insulating layer 180, the second conductive layer 190 and the third conductive layer 210 from the outer side to the inner side. Figure 6 The bottom portion BP of the capacitor structure CP is shown, and the upper portion UP of the capacitor structure CP is not shown. Figure 6 However, the upper portion UP of the capacitor structure CP includes the above-mentioned layers similar to the bottom portion BP of the capacitor structure CP. It is worth mentioning that since the first opening OP1 (such as Figure 2 ), the number of layers formed in the bottom portion BP of the capacitor structure CP is equal to the number of layers formed in the upper portion UP of the capacitor structure CP.
[0045] The method for manufacturing the capacitor structure CP provided by the embodiment of the present invention can manufacture a capacitor structure CP having a relatively straight profile (for example, in a cross section, the sidewall of the first conductive layer 170 is perpendicular to the top surface of the active device layer 112) without generating a tapered profile. In this way, the method for manufacturing the capacitor structure CP provided by the embodiment of the present invention can improve the capacitance and leakage performance of the capacitor structure CP.
[0046] Embodiments of the present invention also provide Figure 5 and Figure 6 The semiconductor structure 100 includes an active device layer 112 disposed above a substrate 110 and a capacitor structure CP disposed on the active device layer 112. The capacitor structure CP includes a third conductive layer 210, a second conductive layer 190 surrounding the third conductive layer 210, an insulating layer 180 surrounding the second conductive layer 190, and a first conductive layer 170 surrounding the insulating layer 180. The capacitor structure CP also includes a first dielectric layer 120 located on the active device layer 112 and surrounding the bottom of the first conductive layer 170. In some embodiments, the first conductive layer 170 has a width W and a height H, and the aspect ratio (ratio of the height H to the width W (H / W)) of the capacitor structure CP is greater than 30.
[0047] In addition, the capacitor structure CP may be based on the second dielectric layer 140 (as described later), and the capacitor structure CP may be defined to include a bottom portion BP and an upper portion UP. Figure 6In the top view of FIG. 1 , the bottom portion BP of the capacitor structure CP includes an inner insulating layer 180i (or referred to as the bottom inner insulating layer 180i) surrounding the first conductive layer 170, a second inner conductive layer 190i (or referred to as the bottom second inner insulating layer 190i) surrounding the inner insulating layer 180i, and a third inner conductive layer 210i (or referred to as the bottom third inner insulating layer 210i) surrounding the second inner conductive layer 190i. In some embodiments, the bottom surface of the bottom inner insulating layer 180i directly contacts the top surface of the first dielectric layer 120, such as Figure 5 In some embodiments, a side surface of the bottom inner insulating layer 180 i contacting the sidewall of the first conductive layer 170 is substantially perpendicular to the top surface of the first dielectric layer 120 .
[0048] exist Figure 5 In the embodiment, the capacitor structure CP further includes a second dielectric layer 140 located on the bottom inner insulating layer 180i and surrounding the middle of the sidewall of the first conductive layer 170. In some embodiments, the side surface of the inner insulating layer 180i contacting the sidewall of the first conductive layer 170 is substantially perpendicular to the second dielectric layer 140. In some embodiments, the top surface of the top inner insulating layer 180i contacts the bottom surface of the second dielectric layer 140, such as Figure 5 shown.
[0049] In addition, in the top view, the upper portion UP of the capacitor structure CP includes an inner insulating layer 180i (or referred to as a top inner insulating layer 180i) located on the second dielectric layer 140 and surrounding the first conductive layer 170, a second inner conductive layer 190i (or referred to as a top second inner conductive layer 190i) surrounding the top inner insulating layer 180i, and a third inner conductive layer 210i (or referred to as a top third inner conductive layer 210i) surrounding the top second inner conductive layer 190i. In some embodiments, the bottom surface of the top inner insulating layer 180i contacts the top surface of the second dielectric layer 140, as shown in FIG. Figure 5 In some embodiments, a side surface of the inner insulating layer 180 i contacting a sidewall of the first conductive layer 170 is substantially perpendicular to a top surface of the second dielectric layer 140 .
[0050] exist Figure 5 In the embodiment, the capacitor structure CP further includes a third dielectric layer 160 on the top inner insulating layer 180i and surrounding the upper portion of the sidewall of the first conductive layer 170. In some embodiments, the top surface of the top inner insulating layer 180i contacts the bottom surface of the third dielectric layer 160. In some embodiments, the side surface of the top inner insulating layer 180i contacting the sidewall of the first conductive layer 170 is substantially perpendicular to the third dielectric layer 160. In some embodiments, the top surfaces of the third dielectric layer 160, the first conductive layer 170, the insulating layer 180, the second conductive layer 190, and the third conductive layer 210 are coplanar.
[0051] In summary, the capacitor structure CP provided by the embodiment of the present invention has a high aspect ratio contact (HARC) and does not have a tapered profile. Therefore, the capacitance and leakage performance of the capacitor structure CP can be improved through the straight critical dimension (CD) of the HARC.
[0052] Although some embodiments of the present invention have been described in considerable detail, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described herein.
[0053] The above briefly describes the features of multiple embodiments of the present invention so that those skilled in the art can more easily understand the present invention. Any person skilled in the art should understand that the present invention can easily serve as a basis for the change or design of other structures or processes to achieve the same purpose and / or obtain the same advantages as the embodiments of the present invention. Any person skilled in the art should also understand that the structures equivalent to the above do not depart from the spirit and scope of the present invention, and can be changed, replaced and modified without departing from the spirit and scope of the present invention.
[0054]
Explanation of symbols
[0055] 100:Semiconductor structure
[0056] 110:Substrate
[0057] 112: Active device layer
[0058] 120: first supporting layer / first dielectric layer
[0059] 130: Bottom oxide layer
[0060] 132,152:lower part
[0061] 134,154: Central
[0062] 136,156: upper part
[0063] 140: second supporting layer / second dielectric layer
[0064] 150: Top oxide layer
[0065] 160: third supporting layer / third dielectric layer
[0066] 170: first conductive layer
[0067] 180: Insulation layer
[0068] 180i: Inner insulation layer / Bottom inner insulation layer / Top inner insulation layer
[0069] 190: second conductive layer
[0070] 190i: second inner conductive layer / second bottom inner conductive layer / second top inner conductive layer
[0071] 210: third conductive layer
[0072] 210i: third inner conductive layer / third bottom inner conductive layer / third top inner conductive layer
[0073] BP: bottom part
[0074] CP: Capacitor structure
[0075] H: Height
[0076] UP: Upper part
[0077] OP1: First opening
[0078] OP2: Second opening
[0079] W1, W2, W3: opening width
[0080] W: Width
[0081] X-X': section line.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: include: forming a first supporting layer on the active device layer; Depositing an oxide layer on the first supporting layer, wherein the oxide layer includes a dopant, and a concentration of the dopant gradually increases from an upper portion of the oxide layer to a lower portion of the oxide layer; forming a second supporting layer on the oxide layer; as well as The second supporting layer, the oxide layer, and the first supporting layer are etched to form a first opening to expose a portion of a top surface of the active device layer.
2. The method according to claim 1, characterized in that The dopant is boron.
3. The method according to claim 1, characterized in that The etching selectivity of the lower portion of the oxide layer is greater than the etching selectivity of the upper portion of the oxide layer.
4. The method according to claim 3, characterized in that The concentration of the etchant for etching the oxide layer is positively correlated with the concentration of the dopant in the oxide layer.
5. The method according to claim 1, characterized in that The opening width of the upper portion of the oxide layer is substantially equal to the opening width of the lower portion of the oxide layer.
6. The method according to claim 1, characterized in that Further including: After forming the first opening, depositing a first conductive layer in the first opening; as well as The oxide layer is removed to form a second opening to expose a portion of the outer surface of the first conductive layer.
7. The method according to claim 6, characterized in that Further including: forming an insulating layer on the first conductive layer in the first opening and forming an inner insulating layer in the second opening respectively; Conformally depositing a second conductive layer on the insulating layer and conformally depositing a second inner conductive layer on the inner insulating layer, respectively; as well as A third conductive layer is formed on the second conductive layer and a third inner conductive layer is formed on the second inner conductive layer respectively.
8. A method for manufacturing a semiconductor structure, characterized in that: include: forming a first supporting layer on the active device layer; Depositing an oxide layer containing a dopant on the first supporting layer, wherein an upper portion of the oxide layer has a first doping concentration, a middle portion of the oxide layer has a second doping concentration greater than the first doping concentration, and a lower portion of the oxide layer has a third doping concentration greater than the second doping concentration; forming a second supporting layer on the oxide layer; as well as The second supporting layer, the oxide layer and the first supporting layer are etched to form a first opening to expose a portion of a top surface of the active device layer.
9. The method according to claim 8, characterized in that Etching the second supporting layer, the oxide layer, and the first supporting layer includes a wet etching process.
10. The method according to claim 8, characterized in that The concentration of the etchant etching the upper portion of the oxide layer is lower than the concentration of the etchant etching the middle portion of the oxide layer, and the concentration of the etchant etching the middle portion of the oxide layer is lower than the concentration of the etchant etching the lower portion of the oxide layer.
11. The method according to claim 8, characterized in that After etching, a side surface of the upper portion of the oxide layer exposed through the first opening, a side surface of the middle portion of the oxide layer exposed through the first opening, and a side surface of the lower portion of the oxide layer exposed through the first opening are coplanar.
12. The method according to claim 8, characterized in that Further including: After forming the first opening, conformally depositing a first conductive layer in the first opening; as well as The oxide layer is removed to form a second opening.
13. The method according to claim 12, characterized in that The sidewall of the first conductive layer is substantially perpendicular to the top surface of the active device layer.
14. The method according to claim 12, characterized in that Further including: forming an insulating layer on the first conductive layer in the first opening and forming an inner insulating layer in the second opening respectively; Conformally depositing a second conductive layer on the insulating layer and conformally depositing a second inner conductive layer on the inner insulating layer; as well as A third conductive layer is formed on the second conductive layer to fill the first opening, and a third inner conductive layer is formed on the second conductive layer to fill the second opening.
15. A semiconductor structure, characterized in that: include: An active device layer is disposed above the substrate; as well as A capacitor structure is disposed on the active device layer, wherein the capacitor structure comprises: A first conductive layer is disposed on the active device layer; An insulating layer, disposed on the first conductive layer; A second conductive layer is disposed on the insulating layer; A third conductive layer is disposed on the second conductive layer; a bottom inner insulating layer, surrounding the first conductive layer in a top view; a second inner conductive layer, in the top view, surrounding the bottom inner insulating layer; and The third inner conductive layer, in the top view, surrounds the second inner conductive layer.
16. The semiconductor structure according to claim 15, characterized in that The capacitor structure further comprises: A first dielectric layer is disposed on the active device layer and surrounds the bottom of the first conductive layer. The side surface of the bottom inner insulating layer contacting the side wall of the first conductive layer is substantially perpendicular to the top surface of the first dielectric layer.
17. The semiconductor structure according to claim 16, characterized in that: The capacitor structure further comprises: a second dielectric layer disposed on the bottom inner insulating layer and surrounding the side wall of the first conductive layer, The side surface of the bottom inner insulating layer contacting the side wall of the first conductive layer is substantially perpendicular to the bottom surface of the second dielectric layer.
18. The semiconductor structure according to claim 17, characterized in that: The capacitor structure further comprises: A top inner insulating layer is disposed on the second dielectric layer and surrounds the first conductive layer in the top view; a top second inner conductive layer, in the top view, surrounding the top inner insulating layer; and The top third inner conductive layer, in the top view, surrounds the top second inner conductive layer.
19. The semiconductor structure according to claim 18, characterized in that In the cross-sectional view, the first conductive layer has a height and a width, and a ratio of the height to the width is greater than 30.
20. The semiconductor structure according to claim 18, characterized in that The capacitor structure further comprises: a third dielectric layer disposed on the top inner insulating layer and surrounding the sidewall of the first conductive layer, The top surface of the third dielectric layer is coplanar with the top surface of the first conductive layer.