Formation method of semiconductor structure

Abstract

A method for forming a semiconductor structure is characterized in that polymer impurities are easily generated in the step of performing dry etching on a first oxide layer on the surface of a first region in a substrate, and generally, the polymer impurities are attached to the side walls of stacked gate structures on the two sides of the first region; the thickness of the first oxide layer on the side walls of the stacked gate structures on the two sides of the first region is greater than that of the first oxide layer on the surface of the first region; in the cleaning process, polymer impurities on the side walls of the stacked gate structures on the two sides of the first region can be removed, so that the polymer impurities are not easy to block an etching solution during wet etching, and when the first oxide layer on the surface of the first region is removed by wet etching, the first oxide layer on the side walls of the stacked gate structures on the two sides of the first region is thinned; and part of thickness can be reserved after thinning, so that smooth proceeding of a subsequent semiconductor process is facilitated, and a subsequently formed semiconductor structure has high performance and reliability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] Non-volatile memory is a storage technology that can continue to retain data after power failure. Non-volatile memory plays an important role in modern technology and life. Its importance is reflected in the following aspects: Data persistence: Non-volatile memory ensures that data continues to be retained after power failure, preventing data loss and ensuring system reliability. High-speed read and write: Non-volatile memory such as flash memory provides fast data read and write speeds, improving the performance and responsiveness of devices. Large-capacity storage: Modern non-volatile memory can provide huge storage capacity to meet the growing demand for data storage. Low power consumption: Compared with volatile memory, non-volatile memory generally has lower power consumption, which helps to extend battery life and reduce energy consumption. Programmability: Some non-volatile memories (such as EEPROM and Flash) are programmable, allowing data to be modified and updated, providing flexibility and customizability.

[0003] Split gate non-volatile memory cells are known in the art, where two different portions of the channel region are controlled by two different gates (a floating gate structure and a select gate). The memory cell additionally includes a control gate structure above the floating gate structure and an erase gate structure above the source region. Split gate memory cells are advantageous because the operating voltage is relatively low, which means that the on-board power supply can be smaller and more efficient. Split gate memory cells are disadvantageous because the memory cell size is enlarged to accommodate two separate gates that are laterally shifted to control the two separate portions of the channel region. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure to optimize the electrical performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of stacked gate groups on the substrate, wherein a first region is formed between adjacent stacked gate groups, the stacked gate group comprises at least two stacked gate structures, and in an extension direction perpendicular to the stacked gate structures, the stacked gate structures are arranged at intervals, and the region between adjacent stacked gate structures in the same stacked gate group is a second region; forming a first oxide layer on the sidewalls and top walls of the stacked gate structure, and on the first region and the second region of the substrate; dry etching the first oxide layer on the surface of the first region in the substrate to remove a portion of the thickness of the first oxide layer; after the dry etching step, cleaning the surface of the first region in the substrate and the sidewalls of the stacked gate structure on both sides of the first region; after the cleaning step, using a wet etching process to remove the remaining first oxide layer on the surface of the first region in the substrate, and at the same time, the first oxide layer on the sidewalls of the stacked gate structure on both sides of the first region is thinned and a portion of the thickness is retained.

[0006] Optionally, the gas used in the cleaning step is an oxygen-containing gas, and the oxygen-containing gas includes oxygen.

[0007] Optionally, the parameters of the cleaning step include: the RF power is less than 100 W, and the process time is 5 seconds to 10 seconds.

[0008] Optionally, after the dry etching and before the cleaning step, the thickness of the first oxide layer remaining on the surface of the first region in the substrate is 200 angstroms to 400 angstroms.

[0009] Optionally, in the wet etching step, the thickness of the first oxide layer retained on the sidewalls of the stacked gate structure on both sides of the first region is 200 angstroms to 300 angstroms.

[0010] Optionally, the process parameters of the wet etching include: the etching solution includes hydrofluoric acid and ammonium fluoride.

[0011] Optionally, the first oxide layer is formed by a high temperature oxidation process.

[0012] Optionally, the material of the first oxide layer includes silicon oxide.

[0013] Optionally, in the step of forming a first oxide layer on the stacked gate structure and the substrate, the thickness of the first oxide layer is 300 angstroms to 500 angstroms.

[0014] Optionally, the method for forming the semiconductor structure also includes: after forming the first oxide layer, before performing the dry etching, forming a shielding layer covering the stacked gate group and the second region and exposing the first region; in the dry etching step, etching the first oxide layer on the surface of the first region in the substrate using the shielding layer as a mask; in the cleaning step, cleaning the surface of the first region in the substrate and the side walls of the stacked gate structure on both sides of the first region using the shielding layer as a mask; in the wet etching process, removing the remaining first oxide layer on the surface of the first region in the substrate using the shielding layer as a mask; the method for forming the semiconductor structure also includes: after the wet etching process, removing the shielding layer.

[0015] Optionally, the first region is a low-voltage region, and the second region is a high-voltage region; the semiconductor structure also includes: after the wet etching process, a second oxide layer is formed on the stacked gate structure and the substrate exposed by the stacked gate structure, and the second oxide layer is located on the surface of the first region in the substrate, and on the remaining first oxide layer.

[0016] Optionally, in the step of forming the second oxidation layer, the thickness of the second oxide layer is 15 angstroms to 25 angstroms.

[0017] Optionally, in the step of forming a plurality of stacked gate groups on the substrate, the stacked gate structure includes: a floating gate structure, an intergate dielectric layer located on the floating gate structure, and a control gate structure located on the intergate dielectric layer; the method for forming the semiconductor structure also includes: after forming the second oxide layer, forming an erase gate structure on the second oxide layer in the second region of the substrate, and forming a select gate on the second oxide layer in the first region of the substrate.

[0018] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0019] In the method for forming a semiconductor structure provided by an embodiment of the present invention, polymer impurities are easily generated in the step of dry etching the first oxide layer on the surface of the first region in the substrate. Usually, the polymer impurities will adhere to the side walls of the stacked gate structure on both sides of the first region. Combined with the anisotropic characteristics of dry etching and the protective effect of the polymer impurities, the thickness of the first oxide layer on the side walls of the stacked gate structure on both sides of the first region will be greater than the thickness of the first oxide layer on the surface of the first region. The cleaning step can remove the polymer impurities on the side walls of the stacked gate structure on both sides of the first region, so that the polymer impurities are not easy to be removed during the wet etching process. The etching solution is blocked so that when the etching solution contacts the first oxide layer on the surface of the first region, it can also contact the first oxide layer on the side walls of the stacked gate structure on both sides of the first region. However, because the thickness of the first oxide layer on the surface of the first region is less than the thickness of the first oxide layer on the stacked gate structure on both sides of the first region, under the isotropic characteristic of wet etching, when the remaining first oxide layer on the surface of the first region is removed by wet etching, the first oxide layer on the side walls of the stacked gate structure on both sides of the first region is thinned, and part of the thickness can still remain, which is beneficial to the smooth progress of subsequent semiconductor processes and enables the subsequently formed semiconductor structure to have high performance and high reliability.

[0020] In an optional solution, the first region is a low voltage region, and the second region is a high voltage region; the semiconductor structure further comprises: after the wet etching process, a second oxide layer is formed on the stacked gate structure and the substrate exposed by the stacked gate structure, the second oxide layer being located on the surface of the first region in the substrate and on the remaining first oxide layer; the stacked gate structure comprises: a floating gate structure, an inter-gate dielectric layer located on the floating gate structure, and a control gate structure located on the inter-gate dielectric layer; the method for forming the semiconductor structure further comprises: after forming the second oxide layer, forming an erase gate structure on the second oxide layer of the second region of the substrate, and forming a select gate on the second oxide layer of the first region of the substrate. The method for forming the semiconductor structure provided by the embodiment of the present invention enables the erase gate structure of the second region and the substrate to be separated by the first oxide layer and the second oxide layer, so as to meet the high voltage design requirements of the second region, enables the select gate and the substrate to have only the second oxide layer, and enables the low voltage design requirements of the first region, enables the select gate and the floating gate structure to be separated by the second oxide layer and the thinned first oxide layer, so that the select gate can smoothly read and program the floating gate structure, which is conducive to improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1 to 6 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0022] Figures 7 to 15It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] As can be seen from the background art, the semiconductor structures currently formed still have the problem of poor performance. The reasons for the poor performance of the semiconductor structure are now analyzed in conjunction with a method for forming a semiconductor structure.

[0024] refer to Figures 1 to 6 , showing a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0025] like Figure 1 As shown, a substrate 1 is provided; a plurality of stacked gate groups 2 are formed on the substrate 1, and a first region I is formed between adjacent stacked gate groups 2, the stacked gate group 2 includes at least two stacked gate structures 20, and in an extension direction perpendicular to the stacked gate structures 20, the stacked gate structures 20 are arranged at intervals, and the region between adjacent stacked gate structures 20 in the same stacked gate group 2 is a second region II, the first region I is a low-voltage region, and the second region II is a high-voltage region.

[0026] In this embodiment, the stacked gate structure 20 includes: a floating gate structure 21 , an inter-gate dielectric layer 22 located on the floating gate structure 21 , and a control gate structure 23 located on the inter-gate dielectric layer 22 .

[0027] like Figure 2 As shown, a first oxide layer 3 is formed on the sidewalls and top wall of the stacked gate structure 20 and the first region I and the second region II of the substrate 1, forming a shielding layer 4 covering the stacked gate group 2 and the second region II and exposing the first region I.

[0028] like Figure 3 As shown, the first oxide layer 3 on the surface of the first region I in the substrate 1 is dry-etched.

[0029] Because the first oxide layer 3 on the surface of the first region I in the substrate 1 has been dry-etched, the thickness of the first oxide layer 3 on the side walls of the stacked gate structure 20 on both sides of the first region I is greater than the thickness of the first oxide layer 3 on the surface of the first region I, so that when the first oxide layer 3 in the first region I is removed by wet etching, part of the thickness of the first oxide layer 3 on the side walls of the stacked gate structure 20 on both sides of the first region I still remains.

[0030] like Figure 4 As shown, a wet etching process is used to remove the remaining first oxide layer 3 on the surface of the first region I in the substrate 1.

[0031] like Figure 5As shown, after the wet etching process, the blocking layer 4 is removed by an ashing process; after removing the blocking layer 4, a second oxide layer 6 is formed on the stacked gate structure 20 and the substrate 1 exposed by the stacked gate structure 20, and the second oxide layer 6 is located on the surface of the first region I in the substrate 1, and on the remaining first oxide layer 3.

[0032] like Figure 6 As shown, after the second oxide layer 6 is formed, an erase gate structure 7 is formed in the area surrounded by the second oxide layer 6 on the surface of the second region II of the substrate 1 and the second oxide layer 6 on the side wall of the stacked gate structure 20, and a selection gate 8 is formed on the second oxide layer 6 on the side wall of the stacked gate structure 20 in the first region I of the substrate 1.

[0033] In the method for forming the semiconductor structure, a portion of the first oxide layer 3 is removed, and the etching gas easily reacts with the shielding layer 4 to generate polymer impurities 5 (such as Figure 3 As shown in the figure, the polymer impurities 5 will adhere to the side walls of the stacked gate structure 20 on both sides of the first region I, so that in the process of removing the remaining first oxide layer 3 on the surface of the first region I in the substrate 1 by a wet etching process, the polymer impurities 5 on the side walls of the stacked gate structure 20 on both sides of the first region I are likely to block the etching solution, and the first oxide layer 3 on the side walls of the stacked gate structure 20 cannot be thinned during the wet etching process. Therefore, in the semiconductor structure finally formed, the sum of the second oxide layer 6 and the remaining first oxide layer 3 between the selection gate 8 and the floating gate structure 21 is too large, and the corresponding resistance between the selection gate 8 and the floating gate structure 21 is too large, resulting in the selection gate 8 being unable to smoothly read and program the floating gate structure 21 when the semiconductor structure is working, resulting in poor performance of the semiconductor structure.

[0034] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] Figures 7 to 15 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0036] refer to Figure 7 , providing a substrate 100.

[0037] The substrate 100 provides a process operation basis for a formation process of a semiconductor structure, wherein the semiconductor structure belongs to a non-volatile memory device, and specifically, the semiconductor structure is a split-gate memory structure.

[0038] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate 100 may also be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium. The substrate 100 may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates 100. The material of the substrate 100 may be a material suitable for process requirements or easy to integrate.

[0039] Continue to refer Figure 7 A plurality of stacked gate groups 300 are formed on the substrate 100, and a first region I is formed between adjacent stacked gate groups 300. The stacked gate group 300 includes at least two stacked gate structures 200, and the stacked gate structures 200 are arranged at intervals in an extension direction perpendicular to the stacked gate structures 200. The region between adjacent stacked gate structures 200 in the same stacked gate group 300 is a second region II.

[0040] The adjacent stacked gate groups 300 define the position of the first region I, which is a low voltage region for forming a select gate and a drain, wherein the select gate is used for access control, data transmission, and selection and erasure operations of the memory cell, and the drain is used to connect to the bit line to realize data reading and writing of the memory cell. The position of the second region II is defined between adjacent stacked gate structures 200 in the same stacked gate group 300, and the second region II is a high voltage region for subsequent formation of an erase gate structure.

[0041] The stacked gate structure 200 plays a role in the reading, writing and erasing operations of data of the memory.

[0042] Specifically, in the step of forming a plurality of stacked gate groups 300 on the substrate 100 , the stacked gate structure 200 includes: a floating gate structure (Floating Gate) 201 , an intergate dielectric layer 202 located on the floating gate structure 201 , and a control gate structure (Control Gate, CG) 203 located on the intergate dielectric layer 202 .

[0043] The floating gate structure 201 is used as a unit structure for storing data and maintaining data status in a memory. By storing or not storing electrons in the floating gate structure 201 , the memory is in a state of storing information or erasing information.

[0044] In this embodiment, the floating gate structure 201 is made of polysilicon. N-type ions are doped in the floating gate structure 201. The N-type ions include one or more of phosphorus, arsenic and antimony.

[0045] During the writing and erasing process, the N-type ions cause a large difference between the writing threshold voltage and the erasing threshold voltage of the floating gate structure 201. When the memory is in use, the fluctuation of the voltage loaded at both ends of the floating gate structure 201 will not affect the normal writing or erasing operation of the floating gate structure 201.

[0046] The control gate structure 203 is used to connect to the outside to control the longitudinal electric field of the floating gate structure 201. During the read operation, the data stored in the floating gate structure 201 is read; during the write operation, the injection or movement of the electron flow in the floating gate structure 201 is controlled to change the charge state of the floating gate structure 201; during the erase operation, the control gate structure 203 and the erase gate work together to create an erase electric field.

[0047] The control gate structure 203 is used to inject electrons into the floating gate structure 201 or pull electrons out of the floating gate structure 201 during the process of writing or erasing data in the memory. When reading data from the memory, an operating voltage is applied to the control gate structure 203, and the charged state of the floating gate structure 201 is used to control the on / off state of the channel region at the bottom of the floating gate structure 201.

[0048] In this embodiment, the material of the control gate structure 203 is polysilicon.

[0049] It should be noted that the control gate structure 203 is doped with P-type ions, so that the control gate structure 203 is not easily in a depletion state, and thus the control gate structure 203 is in a conductive state.

[0050] The P-type ions include one or more of boron, gallium and indium.

[0051] The inter-gate dielectric layer 202 is used to electrically isolate the floating gate structure 201 from the control gate structure 203 .

[0052] In this embodiment, the material of the intergate dielectric layer 202 is a dielectric material. Specifically, the material of the intergate dielectric layer 202 includes one or both of silicon oxide and silicon nitride. In this embodiment, the material of the intergate dielectric layer 202 is a sandwich structure composed of silicon oxide, silicon nitride and silicon oxide (ONO).

[0053] The semiconductor structure further includes a floating gate dielectric layer 101 (Floating Gate oxide), which is located between the substrate 100 and the stacked gate structure 200 and is used to isolate the stacked gate structure 200 from the substrate 100 .

[0054] In this embodiment, the floating gate dielectric layer 101 is made of a dielectric material, such as silicon oxide. In other embodiments, the floating gate dielectric layer may also be a stack of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

[0055] It should be noted that the stacked gate structure 200 further includes: a hard mask layer 204 located on the top of the control gate structure 203 .

[0056] The hard mask layer 204 is used to protect the control gate structure 203 on the top of the stacked gate structure 200 from being damaged.

[0057] In this embodiment, the hard mask layer 204 is a nitride-oxide-nitride (NON) structure.

[0058] refer to Figure 8 A first oxide layer 102 is formed on the sidewalls and top wall of the stacked gate structure 200 , and the first region I and the second region II of the substrate 100 .

[0059] The first oxide layer 102 formed in this step is prepared for subsequent dry etching and wet etching.

[0060] In this embodiment, the material of the first oxide layer 102 includes silicon oxide, which is a commonly used dielectric material with low cost and high process compatibility, which is conducive to reducing the process difficulty and process cost of forming the first oxide layer 102 .

[0061] In this embodiment, a high temperature oxidation process is used to form the first oxide layer 102. The first oxide layer 102 formed by the high temperature oxidation process has good thickness uniformity and density, and plays a good electrical isolation role.

[0062] It should be noted that in the step of forming the first oxide layer 102 on the stacked gate structure 200 and the substrate 100, the first oxide layer 102 should not be too thick or too thin. In the subsequent process, it is necessary to remove the first oxide layer 102 on the surface of the first region I in the substrate 100, and thin the first oxide layer 102 on the sidewalls of the stacked gate structure 200 on both sides of the first region I. If the first oxide layer 102 formed by the high-temperature oxidation process is too thick, it will cause the first oxide layer 102 on the surface of the first region I in the substrate 100 to take more time to remove, which is not conducive to shortening the preparation cycle of the semiconductor structure. If the first oxide layer 102 formed by the high-temperature oxidation process is too thin, in the subsequent process, the first oxide layer 102 on the surface of the first region I in the substrate 100 will be removed too quickly, the top of the substrate will be exposed too early, and the material on the top of the substrate 100 is easily damaged, resulting in the subsequent formation of the second oxide layer 104 on the surface of the first region I of the substrate 100. A good interface cannot be provided for the second oxide layer 104, thereby resulting in poor formation quality of the second oxide layer 104. In this embodiment, in the step of forming the first oxide layer 102 on the stacked gate structure 200 and the substrate 100 , the thickness of the first oxide layer 102 is 300 angstroms to 500 angstroms.

[0063] refer to Fig. 9 and Fig.10 , dry-etching the first oxide layer 102 on the surface of the first region I in the substrate 100 to remove a portion of the thickness of the first oxide layer 102.

[0064] The first oxide layer 102 of a partial thickness on the surface of the first region I of the substrate 100 is removed to prepare for the subsequent complete removal of the first oxide layer 102 on the surface of the first region I in the substrate 100. In addition, the reason why the first oxide layer 102 is not completely removed by the dry etching process is that the first oxide layer 102 on the side walls of the stacked gate structure 200 on both sides of the first region I needs to be thinned. If in this step, the first oxide layer 102 on the surface of the first region I in the substrate 100 does not reserve a partial thickness, when the first oxide layer 102 on the side walls of the stacked gate structure 200 on both sides of the first region I is subsequently thinned by wet etching, the wet solution will directly contact the substrate 100 in the first region I, and the top of the first region I in the substrate 100 is easily damaged, and cannot provide a good interface for the subsequent formation of the second oxide layer 104.

[0065] The dry etching process has anisotropic etching characteristics, and can specifically etch the first oxide layer 102 on the surface of the first area I in the substrate 100. Moreover, the dry etching process is easy to accurately control the removal amount of the first oxide layer 102, and it is not easy to etch through the first oxide layer 102 on the surface of the first area I in the substrate 100.

[0066] It should be noted that after the first oxide layer 102 on the surface of the first region I in the substrate 100 is dry-etched, the thickness of the first oxide layer 102 remaining in the first region I in the substrate 100 should not be too large or too small. After the subsequent cleaning operation, a wet etching process will be used to remove the remaining first oxide layer 102 on the surface of the first region I in the substrate 100. In order to reduce the damage of the wet etching solution to the first region I in the substrate 100, after several etchings, the thickness of the first oxide layer 102 remaining in the first region I in the substrate 100 is too small, which will result in the first oxide layer 102 on the surface of the first region I in the substrate 100 being quickly removed, and the substrate 100 in the first region I is exposed to the etching solution too early, resulting in damage to the top of the first region I in the substrate 100, and failing to provide a good interface for the subsequent formation of the second oxide layer 104. After several etching methods, the thickness of the first oxide layer 102 remaining on the surface of the first region I in the substrate 100 is too large, and it takes too much time to perform wet etching. However, the wet etching process has the problem of weak process controllability, and the material on the top of the substrate 100 may be etched, which is not conducive to improving the reliability of the semiconductor structure. In this embodiment, after dry etching, the thickness of the first oxide layer 102 remaining on the surface of the first region I in the substrate 100 is 200nm to 400nm.

[0067] It should be noted that, during the dry etching process, the etching gas easily reacts with the shielding layer 103 to produce polymer impurities, and the polymer impurities are usually attached to the side walls of the stacked gate structure 200 on both sides of the first region I. Combined with the anisotropic characteristics of dry etching and the protective effect of the polymer impurities on the first oxide layer 102 on the side walls of the stacked gate structure 200, the thickness of the first oxide layer 102 on the side walls of the stacked gate structure 200 on both sides of the first region I will be greater than the thickness of the first oxide layer 102 on the surface of the first region I.

[0068] It should be noted that the material of the first oxide layer 102 is a dielectric material, and the dry etching gas used includes a fluorine-based gas.

[0069] In this embodiment, the method for forming the semiconductor structure also includes: after forming the first oxide layer 102, before performing the dry etching, forming a blocking layer 103 covering the stacked gate group 300 and the second region II and exposing the first region I, and in the dry etching step, using the blocking layer 103 as a mask to etch the first oxide layer 102 on the surface of the first region I in the substrate 100.

[0070] The shielding layer 103 is used to protect the top of the stacked gate structure 200 , the first oxide layer 102 on the second region II in the substrate 100 , and the first oxide layer 102 on the sidewalls of the stacked gate structure 200 on both sides of the second region II.

[0071] In this embodiment, the shielding layer 103 is made of a material that is easy to form and easy to remove. For example, the material of the shielding layer 103 is photoresist.

[0072] refer to Fig.11 After the dry etching step, the surface of the first region I in the substrate 100 and the side walls of the stacked gate structure 200 on both sides of the first region I are cleaned.

[0073] In the cleaning process provided by the embodiment of the present invention, polymer impurities on the side walls of the stacked gate structure 200 on both sides of the first region I can be removed, so that during the wet etching process, the polymer impurities are not easy to block the etching solution, and the etching solution can contact the first oxide layer 102 on the side walls of the stacked gate structure 200 on both sides of the first region I while contacting the first oxide layer 102 on the surface of the first region I. However, because the thickness of the first oxide layer 102 on the surface of the first region I is less than the thickness of the first oxide layer 102 on the stacked gate structure 200 on both sides of the first region I, under the isotropic characteristic of wet etching, when the first oxide layer 102 on the surface of the first region I is removed by wet etching, the first oxide layer 102 on the side walls of the stacked gate structure 200 on both sides of the first region I is thinned, and some thickness can still be retained, which is conducive to the smooth progress of subsequent semiconductor processes and enables the subsequently formed semiconductor structure to have high performance and reliability.

[0074] In this embodiment, the gas used in the cleaning step is an oxygen-containing gas, and the oxygen-containing gas includes oxygen. Oxygen can react with polymer impurities on the sidewalls of the stacked gate structure 200 on both sides of the first region I at high temperature to generate gas that is easy to discharge.

[0075] It should be noted that, in the cleaning step, the surface of the first region I in the substrate and the sidewalls of the stacked gate structure 200 on both sides of the first region I are cleaned using the blocking layer 103 as a mask.

[0076] In this embodiment, the parameters of the cleaning step include: the RF power is less than 100 W, and the process time of the cleaning step is 5 seconds to 10 seconds.

[0077] It should be noted that the RF power of the cleaning step should not be too large. If the RF power of the cleaning step is too large, the shielding layer 103 is easily consumed quickly, which may cause damage to the top of the stacked gate structure 200, the first oxide layer 102 on the second region II in the substrate, and the first oxide layer 102 on the sidewalls of the stacked gate structure on both sides of the second region II, and the corresponding stacked gate structure 200 and the material on the top of the substrate 100 in the second region II will also be damaged. In this embodiment, the RF process of the cleaning step is less than 100W.

[0078] It should be noted that the process time of the cleaning step should not be too long or too short. If the process time of the cleaning step is too long, the shielding layer 103 is easily consumed, which may cause damage to the top of the stacked gate structure 200, the first oxide layer 102 on the second region II in the substrate, and the first oxide layer 102 on the sidewalls of the stacked gate structure on both sides of the second region II, and the corresponding stacked gate structure 200 and the material on the top of the substrate 100 in the second region II will also be damaged. If the process time of the cleaning step is too short, the polymer impurities on the sidewalls of the stacked gate structure 200 on both sides of the first region I are not removed, and the first oxide layer 102 on the sidewalls of the stacked gate structure 200 on both sides of the first region I is not exposed. In the subsequent wet etching process, the first oxide layer 102 on the sidewalls of the stacked gate structure 200 on both sides of the first region I is difficult to contact with the wet etching, and the first oxide layer 102 on the sidewalls of the stacked gate structure 200 on both sides of the first region I is not easy to be thinned. In this embodiment, the process time of the cleaning step is 5 seconds to 10 seconds.

[0079] refer to Fig.12 After the cleaning step, a wet etching process is used to remove the remaining first oxide layer 102 on the surface of the first region I in the substrate 100. At the same time, the first oxide layer 102 on the side walls of the stacked gate structure 200 on both sides of the first region I is thinned, and the first oxide layer 102 with a partial thickness of the side walls of the stacked gate structure 200 on both sides of the first region I is retained.

[0080] The first region I is a low-voltage area. Removing the remaining first oxide layer 102 on the surface of the first region I in the substrate 100 is to meet the low-voltage design requirements of the first region I; thinning the first oxide layer 102 on the side walls of the stacked gate structure 200 on both sides of the first region I is to reduce the thickness of the dielectric material subsequently formed between the selection gate and the floating gate structure 201 in the first region.

[0081] In this embodiment, the wet etching process is isotropic etching, which is simple to operate and has low process cost.

[0082] It should be noted that, in the wet etching step, the first oxide layer 102 retained on the sidewalls of the stacked gate structure 200 on both sides of the first region I should not be too thick or too thin. If the retained first oxide layer 102 is too thick, after the second oxide layer 104 is subsequently formed, the sum of the thickness of the second oxide layer 104 between the selection gate and the floating gate structure 201 and the first oxide layer 102 remaining after dry etching is too large, and the resistance between the corresponding selection gate and the floating gate structure 201 is too large. Therefore, when the semiconductor structure is working, the selection gate cannot smoothly perform reading and programming operations on the floating gate structure 201, resulting in failure of the semiconductor structure. If the retained first oxide layer 102 is too thin, electrons in the floating gate structure 201 may be lost, or when the selection gate is loaded with a high voltage, electrons are likely to enter the floating gate structure 201, which will have an adverse effect on the reading of information in the floating gate structure 201. In this embodiment, in the wet etching step, the thickness of the first oxide layer 102 retained on the sidewalls of the stacked gate structure 200 on both sides of the first region I is 200 angstroms to 300 angstroms.

[0083] In this embodiment, the process parameters of the wet etching include: the etching solution includes hydrofluoric acid and ammonium fluoride.

[0084] It should be noted that, in the wet etching process, the blocking layer 103 is used as a mask to remove the remaining first oxide layer 102 on the surface of the first region I in the substrate 100. The method for forming a semiconductor structure further includes: removing the blocking layer 103 after the wet etching process.

[0085] In this embodiment, an ashing process is used to remove the shielding layer 103 .

[0086] refer to Fig.13 The semiconductor structure also includes: after the wet etching process, a second oxide layer 104 is formed on the stacked gate structure 200 and the substrate 100 exposed by the stacked gate structure 200, and the second oxide layer 104 is located on the surface of the first region I in the substrate 100 and on the remaining first oxide layer 102.

[0087] Subsequently, an erase gate structure is formed on the second oxide layer 104 of the second region II of the substrate 100, and a select gate is formed on the second oxide layer 104 of the first region I of the substrate 100. Therefore, in the second region II, the erase gate structure of the second region II and the substrate 100 are spaced apart by the first oxide layer 102 and the second oxide layer 104, which is to meet the high-voltage design requirements of the second region II; in the first region I, the select gate and the substrate 100 are spaced apart only by the second oxide layer 104, which meets the low-voltage design requirements of the first region I. In addition, the select gate and the floating gate structure 201 are isolated by the second oxide layer 104 and the thinned first oxide layer 102, so that the select gate can smoothly read and program the floating gate structure 201, which is conducive to improving the performance of the semiconductor structure.

[0088] In this embodiment, the material of the second oxide layer 104 includes silicon oxide, which is a commonly used dielectric material with low cost and high process compatibility, which is conducive to reducing the process difficulty and process cost of forming the second oxide layer 104 .

[0089] In this embodiment, a high temperature oxidation process is used to form the second oxide layer 104. The second oxide layer 104 formed by the high temperature oxidation process has good thickness uniformity and density, and plays a good role in electrical isolation.

[0090] It should be noted that, in the step of forming the second oxide layer 104 on the stacked gate structure 200 and the substrate 100, the second oxide layer 104 should not be too thick or too thin. If the second oxide layer 104 is too thick, the resistance between the subsequently formed selection gate and the substrate of the first region will be too large, resulting in a higher operating voltage required when the selection gate works. If the first oxide layer 102 is too thin, there will be a risk of leakage between the selection gate and the substrate of the second region, causing the semiconductor structure to fail to work properly. In this embodiment, in the step of forming the second oxide layer 104 on the stacked gate structure 200 and the substrate 100, the thickness of the second oxide layer 104 is 15 angstroms to 25 angstroms.

[0091] refer to Fig.14 and Fig.15 The method for forming the semiconductor structure also includes: after forming the second oxide layer 104, forming an erase gate structure (Erase Gate, EG) 205 on the second oxide layer 104 in the second area II of the substrate 100, and forming a select gate (Select Gate, EG) 206 on the second oxide layer 104 in the first area I of the substrate 100.

[0092] The erase gate structure 205 is used to realize the signal erasure of the memory. By applying a high voltage to the erase gate structure 205 end, a potential difference is formed on the inter-gate dielectric layer 202 between the erase gate structure 205 and the floating gate structure 201 due to the coupling capacitance, which can pull the electrons in the floating gate structure 201 to the erase gate structure 205 through tunneling. As the electrons in the floating gate structure 201 are pulled out, the potential of the floating gate structure 201 increases, and the difference between its potential and the erase gate structure 205 will be reduced, weakening the potential difference of the inter-gate dielectric layer 202, and finally the electrons in the floating gate structure 201 are completely pulled out, realizing the signal erasure of the memory.

[0093] The main function of the select gate 206 is to perform write and read operations on specific memory cells, which are usually composed of a floating gate structure 201, a control gate structure 203, and an erase gate structure 205. The presence of the select gate 206 also provides electrical isolation for the memory cells to ensure that only the selected memory cells are affected by the operation. The select gate 206 also helps to enhance the data protection and security of the memory. By controlling the voltage of the select gate 206, unauthorized access or unwanted operations can be prevented, thereby improving the security of the data.

[0094] In this embodiment, the erase gate structure 205 and the select gate 206 are formed in the same step.

[0095] In this embodiment, the erase gate structure 205 and the select gate 206 are both made of polysilicon.

[0096] Specifically, the steps of forming the erase gate structure 205 and the select gate 206 include: forming a gate material layer 207 (such as Fig.14 As shown), the top of the gate material layer 207 is higher than the top of the stacked gate structure 200; a mask layer is formed on the gate material layer 207 directly above the stacked gate structure 200, and the gate material layer 207 is etched using the mask layer as a mask, and the gate material layer 207 located in the second oxide layer 104 of the second region II of the substrate 100 serves as an erase gate structure, and the gate material layer 207 on the second oxide layer 104 in the first region I of the substrate 100 serves as a selection gate 206.

[0097] In other embodiments, the steps of forming the erase gate structure and the select gate may also include: forming a gate material layer on the stacked gate structure and the substrate, the top of the gate material layer being higher than the top of the stacked gate structure; performing maskless etching on the gate material layer, and the gate material layer located on the second oxide layer in the second area of ​​the substrate serves as the erase gate structure, and the gate material layer on the second oxide layer in the first area of ​​the substrate serves as the select gate.

[0098] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; A plurality of stacked gate groups are formed on the substrate, wherein a first region is formed between adjacent stacked gate groups, the stacked gate group includes at least two stacked gate structures, and the stacked gate structures are arranged at intervals in an extension direction perpendicular to the stacked gate structures, and a region between adjacent stacked gate structures in the same stacked gate group is a second region; forming a first oxide layer on the sidewalls and top wall of the stacked gate structure, and the first region and the second region of the substrate; Performing dry etching on the first oxide layer on the surface of the first region of the substrate to remove a portion of the thickness of the first oxide layer; After the dry etching step, cleaning the surface of the first region in the substrate and the sidewalls of the stacked gate structure on both sides of the first region; After the cleaning step, a wet etching process is used to remove the remaining first oxide layer on the surface of the first region in the substrate, and at the same time, the first oxide layer on the side walls of the stacked gate structure on both sides of the first region is thinned and a partial thickness is retained.

2. The method for forming a semiconductor structure according to claim 1, wherein: The gas used in the cleaning step is an oxygen-containing gas, and the oxygen-containing gas includes oxygen.

3. The method for forming a semiconductor structure according to claim 1, wherein: The parameters of the cleaning step include: The RF power is less than 100W and the process time is 5 to 10 seconds.

4. The method for forming a semiconductor structure according to claim 1, wherein: After the dry etching and before the cleaning step, the thickness of the first oxide layer remaining on the surface of the first region in the substrate is 200 angstroms to 400 angstroms.

5. The method for forming a semiconductor structure according to claim 1, wherein: In the wet etching step, the thickness of the first oxide layer retained on the sidewalls of the stacked gate structure on both sides of the first region is 200 angstroms to 300 angstroms.

6. The method for forming a semiconductor structure according to claim 1, wherein: The process parameters of the wet etching include: the etching solution includes hydrofluoric acid and ammonium fluoride.

7. The method for forming a semiconductor structure according to claim 1, wherein: The first oxide layer is formed by a high temperature oxidation process.

8. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first oxide layer includes silicon oxide.

9. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming a first oxide layer on the stacked gate structure and the substrate, the thickness of the first oxide layer is 300 angstroms to 500 angstroms.

10. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming a semiconductor structure further comprises: after forming the first oxide layer and before performing the dry etching, forming a shielding layer covering the stacked gate group and the second region and exposing the first region; In the dry etching step, the first oxide layer on the surface of the first region in the substrate is etched using the blocking layer as a mask; In the cleaning step, the surface of the first region in the substrate and the sidewalls of the stacked gate structure on both sides of the first region are cleaned using the shielding layer as a mask; In the step of the wet etching process, the remaining first oxide layer on the surface of the first region in the substrate is removed by using the blocking layer as a mask; The method for forming a semiconductor structure further includes: removing the blocking layer after the wet etching process.

11. The method for forming a semiconductor structure according to claim 1, wherein: The first region is a low pressure region, and the second region is a high pressure region; The semiconductor structure further includes: after the wet etching process, a second oxide layer is formed on the stacked gate structure and the substrate exposed by the stacked gate structure, and the second oxide layer is located on the surface of the first region in the substrate and on the remaining first oxide layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: In the step of forming the second oxide layer, the thickness of the second oxide layer is 15 angstroms to 25 angstroms.

13. The method for forming a semiconductor structure according to claim 11, wherein: In the step of forming a plurality of stacked gate groups on the substrate, the stacked gate structure comprises: a floating gate structure, an inter-gate dielectric layer located on the floating gate structure, and a control gate structure located on the inter-gate dielectric layer; The method for forming the semiconductor structure further includes: after forming the second oxide layer, forming an erase gate structure on the second oxide layer in the second region of the substrate, and forming a select gate on the second oxide layer in the first region of the substrate.

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