Semiconductor device, preparation method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device, a preparation method thereof and electronic equipment. The semiconductor device comprises an N + substrate; the first N-buffer layer is positioned on the N + substrate and is in contact with the first N-buffer layer; the N-drift layer is positioned on one side, far away from the N + substrate, of the first N-buffer layer; the P-well layer is embedded into the N-drift layer at one side, far away from the N + substrate, of the N-drift layer; the P + cathode is in contact with the P-well layer on one side, far away from the N + substrate, of the P-well layer; and the P-layer is located between the N-drift layer and the first N-buffer layer, and the P-layer is in contact with the first N-buffer layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a method for manufacturing the same, and an electronic device. Background Art

[0002] When bipolar power devices are turned on, both holes and electrons participate in conduction. The number of minority carriers in the drift layer is much higher than the background doping concentration, so a conductivity modulation effect occurs in the drift layer, greatly reducing the on-resistance of the drift layer. Therefore, bipolar power devices are widely used in applications requiring high voltage and high current.

[0003] Conventional bipolar devices, such as IGBTs, GTOs, and MOS-controlled thyristors (MCTs), lack reverse conduction capability. However, in most applications, freewheeling of reverse current is required, often achieved with an external anti-parallel diode. Integrating the freewheeling diode within the bipolar device not only reduces the parasitic inductance and resistance of the connecting leads, but also reduces terminal area, thereby increasing device power density, improving device performance, and reducing system size. Furthermore, during the forward conduction phase of the device, a voltage snapback phenomenon may occur, where the on-state voltage drop decreases sharply. This can cause localized overcurrent and device failure. Summary of the Invention

[0004] The embodiments of the present disclosure provide a semiconductor device, a preparation method thereof, and an electronic device for preparing an N-type IGBT based on an N-type substrate, while integrating a freewheeling diode inside the device, and the introduction of the freewheeling diode does not cause a voltage rebound phenomenon in the device.

[0005] The present disclosure provides a semiconductor device, a method for manufacturing the same, and an electronic device. The specific solutions are as follows: In one aspect, an embodiment of the present disclosure provides a semiconductor device, comprising: N+ substrate; a first N-buffer layer, located on the N+ substrate and in contact with the first N-buffer layer; An N-drift layer is located on a side of the first N-buffer layer away from the N+ substrate; A P-well layer embedded in the N-drift layer on a side of the N-drift layer away from the N+ substrate; A P+ cathode, contacting the P-well layer on a side of the P-well layer away from the N+ substrate; A P-layer is located between the N-drift layer and the first N-buffer layer, and the P-layer is in contact with the first N-buffer layer.

[0006] In some embodiments, the above-mentioned semiconductor device provided by the embodiments of the present disclosure further includes a second N-buffer layer and a P+ anode, wherein the second N-buffer layer contacts the N-drift layer on a side of the N-drift layer close to the N+ substrate, and the P+ anode is embedded in the second N-buffer layer on a side of the second N-buffer layer close to the N+ substrate.

[0007] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the P-layer is in contact with the second N-buffer layer.

[0008] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the P-layer is in contact with the N-drift layer.

[0009] In some embodiments, the above-mentioned semiconductor device provided in the embodiments of the present disclosure further includes an anode conductive layer and a groove, wherein the groove penetrates the N+ substrate, the first N-buffer layer and the P-layer, and extends to the plane where the lower surface of the P+ anode is located, and the anode conductive layer is in contact with the P+ anode in the groove and is spaced apart from the side wall of the groove.

[0010] In some embodiments, the semiconductor device provided in the embodiments of the present disclosure further includes an anode dielectric layer, which fills the gap between the anode conductive layer and the sidewall of the trench.

[0011] On the other hand, an embodiment of the present disclosure provides a method for manufacturing the above-mentioned semiconductor device, comprising: epitaxially growing a first N-buffer layer, a P-layer and an N-drift layer on an N+ substrate in sequence; A P-well layer and a P+ cathode are selectively formed on the surface of the N-drift layer by using ion implantation technology.

[0012] In some embodiments, in the above-mentioned preparation method provided by the embodiment of the present disclosure, after epitaxially growing the P-layer and before epitaxially growing the N-drift layer, the method further includes: epitaxially growing a second N-buffer layer; After selectively forming a P-well layer and a P+ cathode on the surface of the N-drift layer by ion implantation technology, the method further includes: forming a trench penetrating the N+ substrate, the first N-buffer layer, and the P-layer, and penetrating at most partially the second N-buffer layer; At the trench, P-type impurities are implanted into the second N-buffer layer to form a P+ anode.

[0013] In some embodiments, in the above-mentioned preparation method provided in the embodiments of the present disclosure, after selectively forming a P-well layer and a P+ cathode on the surface of the N-drift layer using ion implantation technology, the method further includes: forming a trench penetrating the N+ substrate, the first N-buffer layer, and the P-layer, and penetrating at most partially the N-drift layer; Injecting N-type impurities into the N-drift layer at the trench to form a second N-buffer layer; At the trench, P-type impurities are implanted into the second N-buffer layer to form a P+ anode.

[0014] On the other hand, an embodiment of the present disclosure provides an electronic device, including the above-mentioned semiconductor device provided by an embodiment of the present disclosure.

[0015] The beneficial effects of the present disclosure are as follows: The semiconductor device, preparation method, and electronic device provided by the embodiments of the present disclosure include: an N+ substrate; a first N-buffer layer located on the N+ substrate and in contact with the first N-buffer layer; an N-drift layer located on the side of the first N-buffer layer away from the N+ substrate; a P-well layer embedded in the N-drift layer on the side of the N-drift layer away from the N+ substrate; a P+ cathode in contact with the P-well layer on the side of the P-well layer away from the N+ substrate; and a P-layer located between the N-drift layer and the first N-buffer layer, with the P-layer in contact with the first N-buffer layer. Thus, a PNPN freewheeling diode structure including the P+ cathode, P-well layer, N-drift layer, P-layer, first N-buffer layer, and N+ substrate is integrated within the device, eliminating the need for an external anti-parallel diode to achieve the freewheeling function, thereby increasing power density and reducing system volume. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic structural diagram of a semiconductor device provided in an embodiment of the present disclosure; Figure 2 for Figure 1 Schematic diagram of current distribution when the semiconductor device is reversely conducting; Figure 3 for Figure 1 Schematic diagram of current distribution when the semiconductor device is forward-conducting; Figure 4 A schematic diagram of another structure of a semiconductor device provided in an embodiment of the present disclosure; Figure 5 A schematic diagram of another structure of a semiconductor device provided in an embodiment of the present disclosure; Figure 6 A schematic diagram of another structure of a semiconductor device provided in an embodiment of the present disclosure; Figure 7 A flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure; Figure 8(a) shows Figure 1 A schematic diagram of the structure of a semiconductor device during the preparation process is shown; Figure 8(b) shows Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown; Figure 8(c) shows Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown; Figure 8(d) shows Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown; Figure 8(e) shows Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown; Figure 8(f) shows Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown; Figure 8(g) shows Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown; Figure 9(a) shows Figure 4 A schematic diagram of the structure of a semiconductor device during the preparation process is shown; Figure 9(b) shows Figure 4 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown; Figure 9(c) shows Figure 4 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown; Figure 9(d) shows Figure 4 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown; Figure 9(e) shows Figure 4 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown; Figure 9(f) shows Figure 4 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown; Figure 9(g) shows Figure 4 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown; Figure 9 (h) shows Figure 4 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown; Figure 9 (i) shows Figure 4 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown; Figure 9(j) shows Figure 4 Another structural schematic diagram of a semiconductor device during the preparation process is shown. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. It should be noted that the sizes and shapes of the figures in the drawings do not reflect the actual proportions, and the purpose is only to illustrate the contents of the present disclosure. And the same or similar numbers throughout represent the same or similar elements or elements with the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0018] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in this disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0019] Based on this, the present disclosure provides a semiconductor device that can be fabricated based on semiconductor materials such as silicon, silicon carbide, gallium nitride, etc., through processes such as epitaxy and ion implantation. In some embodiments, Figure 1 As shown, the semiconductor device provided by the present disclosure may include: N+ substrate 101 , which may be relatively thick, so that the device maintains sufficient mechanical strength.

[0020] The first N-buffer layer 102 is located on the N+ substrate 101 and is in contact with the first N-buffer layer 102 . In other words, the lower surface of the first N-buffer layer 102 is in contact with the upper surface of the N+ substrate 101 .

[0021] The N-drift layer 103 is located on a side of the first N-buffer layer 102 away from the N+ substrate 101 .

[0022] The P-well layer 104 is embedded in the N-drift layer 103 on a side of the N-drift layer 103 away from the N+ substrate 101 , which means that both the bottom surface and the side surface of the P-well layer 104 are in contact with the N-drift layer 103 .

[0023] The P+ cathode 105 contacts the P-well layer 104 at a side of the P-well layer 104 away from the N+ substrate 101 , such that the lower surface of the P+ cathode 105 contacts the upper surface of the P-well layer 104 .

[0024] The P-layer 106 is located between the N-drift layer 103 and the first N-buffer layer 102 , and the P-layer 106 contacts the first N-buffer layer 102 . Specifically, the lower surface of the P-layer 106 contacts the upper surface of the first N-buffer layer 102 .

[0025] In the semiconductor device provided by the embodiment of the present disclosure, a P-layer 106 in contact with the first N-buffer layer 102 is added between the N-drift layer 103 and the first N-buffer layer 102, so that a PNPN diode structure including a P+ cathode 105, a P-well layer 104, an N-drift layer 103, a P-layer 106, a first N-buffer layer 102, and an N+ substrate 101 is integrated inside the device. Figure 2 As shown, in the reverse conduction mode, with the device cathode connected to zero potential, the device anode connected to a negative potential, and the gate voltage at zero or negative potential, the PNPN diode structure within the device, including the P+ cathode 105, P-well layer 104, N-drift layer 103, P-layer 106, first N-buffer layer 102, and N+ substrate 101, conducts, thereby achieving a freewheeling function. Therefore, the present disclosure integrates a freewheeling diode within the device, eliminating the need for an external anti-parallel diode for freewheeling, thereby increasing power density and reducing system size.

[0026] In some embodiments, in the above-mentioned semiconductor device provided by the embodiments of the present disclosure, as Figure 1 As shown, it may further include a second N-buffer layer 107 and a P+ anode 108, wherein the second N-buffer layer 107 contacts the N-drift layer 103 on the side thereof close to the N+ substrate 101, and the P+ anode 108 is embedded in the second N-buffer layer 107 on the side thereof close to the N+ substrate 101, that is, the upper surface of the second N-buffer layer 107 contacts the lower surface of the N-drift layer 103, and the upper surface and side surfaces of the P+ anode 108 contact the second N-buffer layer 107. Figure 3 As shown, in the forward conduction mode, the cathode of the device is connected to zero potential and the anode of the device is connected to a positive potential. When the gate voltage changes from zero potential or negative potential to a positive potential, the surface of the P-well layer 104 under the gate dielectric layer is inverted to form an electron channel. Since the PN junction between the P-layer 106 and the first N-buffer layer 102 is in a reverse biased state, the N+ substrate 101 will not be turned on, while the PN junction between the P+ anode 108 and the second N-buffer layer 107 is in a forward biased state. This PN junction between the P+ anode 108 and the second N-buffer layer 107 will gradually turn on, and the device enters a bipolar conduction mode. Therefore, the existence of the N+ substrate 101 will not affect the normal forward conduction process of the device, and there will be no voltage rebound phenomenon in which the conduction voltage drop decreases sharply, thereby avoiding the problem of local overcurrent and failure of the device caused by the voltage rebound phenomenon.

[0027] Furthermore, due to the high defect density of SiC P-type substrates, epitaxial wafers grown on P-type substrates have a high defect density, resulting in poor performance and reliability for bipolar devices fabricated from them. Furthermore, due to the high defect density of P-type substrates, their resistivity is high, and thicker P-type substrates result in additional on-resistance. Thinning the substrate overall reduces the mechanical strength of the substrate, increasing the probability of fragmentation. Therefore, bipolar power devices are currently typically fabricated on N-type substrates. However, devices fabricated on N-type substrates, such as IGBTs, are typically P-type IGBTs, which have the opposite electrical polarity to the currently common N-type IGBTs. Application circuits and driver circuits are complex and incompatible with commonly used application circuits, hindering device applications. The present disclosure allows trenching through the N+ substrate 101, the first N-buffer layer 102, and the P-layer 106, followed by ion implantation to form a P+ anode 108, or a P+ anode 108 and a second N-buffer layer 107. This allows for the formation of an N-type IGBT structure based on the N+ substrate 101, while retaining a relatively thick N+ substrate 101 to ensure sufficient mechanical strength for the device.

[0028] In some embodiments, in the above-mentioned semiconductor device provided by the embodiments of the present disclosure, as Figure 1 As shown, the upper surface of the P-layer 106 can be in contact with the lower surface of the second N-buffer layer 107. In this case, the second N-buffer layer 107 not only wraps the P+ anode 108 but also covers the P-layer 106. The freewheeling diode of the present disclosure further includes the second N-buffer layer 107; or Figure 4 As shown, the upper surface of the P-layer 106 contacts the lower surface of the N-drift layer 103. At this time, the second N-buffer layer 107 only wraps the P+ anode 108. The freewheeling diode of the present disclosure does not include the second N-buffer layer 107, and the freewheeling diode can be more easily turned on. In some embodiments, the P+ anode 108 of the present disclosure can be formed by ion implantation. Figure 1 The second N-buffer layer 107 in the embodiment may be formed by epitaxial growth. Figure 4 The second N-buffer layer 107 can be formed by ion implantation, which is a simple process.

[0029] In some embodiments, in the above-mentioned semiconductor device provided by the embodiments of the present disclosure, as Figure 1 and Figure 4As shown, it may also include an anode conductive layer 109 and a trench T, wherein the trench T penetrates the N+ substrate 101, the first N-buffer layer 102 and the P-layer 106, and extends to the plane where the lower surface of the P+ anode 108 is located. The anode conductive layer 109 is in contact with the P+ anode 108 in the trench T and is spaced from the sidewall of the trench T, while covering the lower surface of the N+ substrate 101. In this way, the anode conductive layer 109 can be insulated from the first N-buffer layer 102, the P-layer 106, and the second N-buffer layer 107, thereby avoiding mutual influence between the forward conduction current and the reverse conduction current of the device. In some embodiments, the gap between the anode conductive layer 109 and the sidewall of the trench T can be filled with the anode dielectric layer 110, so that the anode conductive layer 109 is separated from the sidewall of the second N-buffer layer 107, the sidewall of the first N-buffer layer 102, the sidewall of the P-layer 106, and the sidewall of the N+ substrate 101 by the anode dielectric layer 110, and the anode conductive layer 109 can be led out as the device anode.

[0030] In some embodiments, in the above-mentioned semiconductor device provided by the embodiments of the present disclosure, as Figure 1 and Figure 4 As shown, it may further include an N+ cathode 111, a cathode conductive layer 112, a gate dielectric layer 113, a gate conductive layer 114, and an isolation dielectric layer 115. A cell may include multiple P-well layers 104, multiple N+ cathodes 111, and multiple P+ cathodes 105. The N+ cathodes 111 are embedded in the P-well layer 104, and the P+ cathodes 105 are embedded in the N+ cathodes 111. The lower surfaces of the P+ cathodes 105 and the N+ cathodes 111 are both in contact with the upper surface of the P-well layer 104, and the lower surface of the cathode conductive layer 112 is in contact with the upper surfaces of the N+ cathodes 111 and the P+ cathodes 105. The gate dielectric layer 113 contacts the upper surface of the P-well layer 104 and the upper surface of the N+ cathode 111. The gate conductive layer 114 is located on the upper surface of the gate dielectric layer 113. The upper surface and side surfaces of the gate conductive layer 114 contact the isolation dielectric layer 115. The upper surface and side surfaces of the isolation dielectric layer 115 contact the cathode conductive layer 112. The isolation dielectric layer 115 and the gate dielectric layer 113 completely encase the gate conductive layer 114. The gate conductive layer 114 can be extended to form a device gate, and the cathode conductive layer 112 can be extended to form a device cathode.

[0031] In some embodiments, the P-well layer 104, N+ cathode 111, P+ cathode 105, and cathode conductive layer 112 of the present disclosure may belong to the cathode region, the gate dielectric layer 113, gate conductive layer 114, and isolation dielectric layer 115 may belong to the gate region, the N-drift layer 103 belongs to the drift region, and the N+ substrate 101, the first N-buffer layer 102, the P-layer 106, the second N-buffer layer 107, the P+ anode 108, the anode conductive layer 109, and the anode dielectric layer 110 belong to the anode region. Figure 1and Figure 4 FIG1 shows a drift region, a cathode region, and a gate region disposed on an anode region. In some embodiments, multiple repeated drift regions, cathode regions, and gate regions may be disposed on an anode region according to process capabilities and required device performance. Figure 5 and Figure 6 It shows that two drift regions, two cathode regions and two gate regions are set on an anode region, wherein the two drift regions are set as one, the P-well layer 104 on the adjacent sides of the two cathode regions are set as one, the P+ cathode 105 is set as one, and the cathode conductive layer 112 is set as one, and the two gate regions are separated by the cathode conductive layer 112.

[0032] Based on the same inventive concept, an embodiment of the present disclosure provides a method for preparing the above-mentioned semiconductor device. Since the principle of solving the problem by the preparation method is similar to the principle of solving the problem by the above-mentioned semiconductor device, the implementation of the preparation method provided by the embodiment of the present disclosure can refer to the implementation of the above-mentioned semiconductor device provided by the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0033] In some embodiments, in the above-mentioned preparation method provided in the embodiments of the present disclosure, if Figure 7 As shown, the following steps may be included: S701, epitaxially growing a first N-buffer layer, a P-layer and an N-drift layer on an N+ substrate in sequence; S702 , selectively forming a P-well layer and a P+ cathode on the surface of the N-drift layer using ion implantation technology.

[0034] In order to better understand the above preparation method provided by the embodiment of the present disclosure, the following Figure 1 and Figure 4 The manufacturing process of the semiconductor device shown is described in detail.

[0035] In some embodiments, Figure 1 The manufacturing process of the semiconductor device may include the following steps: Step (1): As shown in FIG8( a ), a first N-buffer layer 102 , a P-layer 106 , a second N-buffer layer 107 and an N-drift layer 103 are epitaxially grown on an N+ substrate 101 in sequence.

[0036] Step (2): As shown in FIG8( b ), a P-well layer 104 , an N+ cathode 111 , and a P+ cathode 105 are selectively formed on the surface of the N-drift layer 103 by ion implantation technology.

[0037] Step (3): As shown in FIG8 (c), a hard mask HM is formed on the back side of the N+ substrate 101, and then selective etching is performed. The N+ substrate 101, the first N-buffer layer 102, and the P-layer 106 are etched by dry etching until at least the second N-buffer layer 107 is exposed, thereby forming a trench T that penetrates the N+ substrate 101, the first N-buffer layer 102 and the P-layer 106, and at most partially penetrates the second N-buffer layer 107.

[0038] Step (4): As shown in Figure 8(d), while maintaining the hard mask HM state, P-type impurities are implanted from the back side of the N+ substrate 101 into the second N-buffer layer 107 at the trench T, thereby forming a P+ anode 108. Subsequently, the hard mask HM is stripped off. An annealing process is then performed to activate the implanted ions and repair lattice damage.

[0039] Step (5): As shown in FIG8(e), a gate dielectric layer 113, a gate conductive layer 114, an isolation dielectric layer 115 and a cathode conductive layer 112 are sequentially formed on the surface of the device.

[0040] Step (6): As shown in FIG8(f), an anode dielectric layer 110 is deposited on the back side of the device.

[0041] Step (7): As shown in FIG8(g), a reactive ion ICP etching method is used on the back of the device to etch away the anode dielectric layer 110 in the middle area of ​​the lower surface of the N+ substrate 101 and the lower surface of the P+ anode 108, leaving only the anode dielectric layer 110 on the side wall of the trench T.

[0042] Step (8): If Figure 1 As shown, an anode conductive layer 109 is formed on the back side of the device by, for example, sputtering.

[0043] So far, it is completed Figure 1 Preparation of the semiconductor device shown.

[0044] In some embodiments, Figure 4 The manufacturing process of the semiconductor device may include the following steps: Step (1): As shown in FIG9( a ), a first N-buffer layer 102 , a P-layer 106 and an N-drift layer 103 are epitaxially grown on an N+ substrate 101 in sequence.

[0045] Step (2): As shown in FIG9( b ), a P-well layer 104 , an N+ cathode 111 , and a P+ cathode 105 are selectively formed on the surface of the N-drift layer 103 by ion implantation technology.

[0046] Step (3): As shown in FIG9 (c), a first hard mask HM1 is formed on the back side of the N+ substrate 101, and then selective etching is performed. The N+ substrate 101, the first N-buffer layer 102, and the P-layer 106 are etched by dry etching until at least the N-drift layer 103 is exposed, thereby forming a trench T that penetrates the N+ substrate 101, the first N-buffer layer 102 and the P-layer 106, and at most partially penetrates the N-drift layer 103.

[0047] Step (4): As shown in FIG9( d ), while maintaining the first hard mask HM1 state, N-type impurities are injected into the N-drift layer 103 at the trench T from the back side of the N+ substrate 101 , thereby forming a second N-buffer layer 107 .

[0048] Step (5): As shown in FIG9(e), the first hard mask HM1 is maintained in the state and a second hard mask HM2 is grown on the back side.

[0049] Step (6): As shown in FIG9(f), the second hard mask HM2 on the back side is etched by using a reactive ion ICP etching method until the second hard mask HM2 in the middle of the surface of the second N-buffer layer 107 is removed.

[0050] Step (7): As shown in FIG9(g), P-type impurities are implanted from the back side of the N+ substrate 101 into the second N-buffer layer 107 at the trench T, thereby forming a P+ anode 108. Subsequently, the first hard mask HM1 on the back side of the N+ substrate 101 and the second hard mask HM2 on the sidewall of the trench T are stripped. An annealing process is then performed to activate the implanted ions and repair lattice damage.

[0051] Step (8): As shown in FIG9(h), a gate dielectric layer 113, a gate conductive layer 114, an isolation dielectric layer 115 and a cathode conductive layer 112 are sequentially formed on the surface of the device.

[0052] Step (9): As shown in FIG9(i), an anode dielectric layer 110 is deposited on the back side of the device.

[0053] Step (10): As shown in FIG9(j), a reactive ion ICP etching method is used on the back of the device to etch away the anode dielectric layer 110 in the middle area of ​​the lower surface of the N+ substrate 101 and the lower surface of the P+ anode 108, leaving only the anode dielectric layer 110 on the side wall of the trench T.

[0054] Step (11): If Figure 4 As shown, an anode conductive layer 109 is formed on the back side of the device by, for example, sputtering.

[0055] So far, it is completed Figure 4 Preparation of the semiconductor device shown.

[0056] Based on the same inventive concept, embodiments of the present disclosure provide an electronic device including the aforementioned semiconductor device provided in embodiments of the present disclosure. Because the principles underlying the problems solved by the electronic device are similar to those of the aforementioned semiconductor device, the implementation of the electronic device provided in embodiments of the present disclosure can refer to the implementation of the aforementioned semiconductor device provided in embodiments of the present disclosure, and any repetitions will not be repeated.

[0057] In some embodiments, the electronic devices provided by the embodiments of the present disclosure may include, but are not limited to, radio frequency amplifiers, mixers, radars, satellites, power supplies, automotive electronics, energy-saving lamps, and household appliances. Of course, the electronic devices provided by the present disclosure may include not only semiconductor devices but also other structures. For example, when the electronic device is a radar, it may also include structures such as a transmitter, antenna, and receiver; when the electronic device is a mixer, it may also include structures such as input ports, output ports, and other structures.

[0058] As can be seen from the above, the present disclosure achieves the goal of fabricating an N-type IGBT based on an N+ substrate, which can retain a relatively thick N+ substrate, ensuring sufficient mechanical strength for the device. Furthermore, by introducing a P-layer above the N+ substrate, the present disclosure forms a PNPN diode structure within the device, comprising a P+ cathode, a P-well layer, an N-drift layer, a second N-buffer layer (optional), a P-layer, a first N-buffer layer, and an N+ substrate. This integrates a freewheeling diode within the device, achieving a freewheeling function. Furthermore, the introduction of this freewheeling diode does not cause the voltage rebound phenomenon that occurs with conventional reverse-conducting IGBTs.

[0059] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0060] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A semiconductor device, characterized in that: include: N+ substrate; a first N-buffer layer, located on the N+ substrate and in contact with the first N-buffer layer; An N-drift layer, located on a side of the first N-buffer layer away from the N+ substrate; A P-well layer embedded in the N-drift layer on a side of the N-drift layer away from the N+ substrate; A P+ cathode, contacting the P-well layer at a side of the P-well layer away from the N+ substrate; The P-layer is located between the N-drift layer and the first N-buffer layer, and the P-layer is in contact with the first N-buffer layer.

2. The semiconductor device according to claim 1, wherein It also includes a second N-buffer layer and a P+ anode, wherein the second N-buffer layer contacts the N-drift layer on a side of the N-drift layer close to the N+ substrate, and the P+ anode is embedded in the second N-buffer layer on a side of the second N-buffer layer close to the N+ substrate.

3. The semiconductor device according to claim 2, wherein: The P-layer contacts the second N-buffer layer.

4. The semiconductor device according to claim 2, wherein: The P-layer is in contact with the N-drift layer.

5. The semiconductor device according to any one of claims 2 to 4, characterized in that: It also includes an anode conductive layer and a groove, wherein the groove penetrates the N+ substrate, the first N-buffer layer and the P-layer, and extends to the plane where the lower surface of the P+ anode is located, and the anode conductive layer is in contact with the P+ anode in the groove and is spaced apart from the side wall of the groove.

6. The semiconductor device according to claim 5, characterized in that The invention also includes an anode dielectric layer, wherein the anode dielectric layer fills a gap between the anode conductive layer and the sidewall of the trench.

7. A method for preparing a semiconductor device according to any one of claims 1 to 6, characterized in that: include: epitaxially growing a first N-buffer layer, a P-layer and an N-drift layer in sequence on an N+ substrate; A P-well layer and a P+ cathode are selectively formed on the surface of the N-drift layer by using ion implantation technology.

8. The preparation method according to claim 7, characterized in that: After epitaxially growing the P-layer and before epitaxially growing the N-drift layer, the method further includes: epitaxially growing a second N-buffer layer; After selectively forming a P-well layer and a P+ cathode on the surface of the N-drift layer by ion implantation technology, the method further comprises: forming a trench penetrating the N+ substrate, the first N-buffer layer and the P-layer, and penetrating at most partially the second N-buffer layer; At the trench, P-type impurities are implanted into the second N-buffer layer to form a P+ anode.

9. The preparation method according to claim 7, characterized in that: After selectively forming a P-well layer and a P+ cathode on the surface of the N-drift layer by ion implantation technology, the method further comprises: forming a trench penetrating the N+ substrate, the first N-buffer layer and the P-layer, and penetrating at most partially the N-drift layer; In the trench, injecting N-type impurities into the N-drift layer to form a second N-buffer layer; At the trench, P-type impurities are implanted into the second N-buffer layer to form a P+ anode.

10. An electronic device, characterized in that: Comprising a semiconductor device as described in any one of claims 1 to 6.

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