Semiconductor device, preparation method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device, a preparation method thereof and electronic equipment. The semiconductor device comprises a P + anode; a first N-buffer layer, wherein the P + anode is embedded into the first N-buffer layer; the N-drift layer is positioned on one side, far away from the P + anode, of the first N-buffer layer; the P-layer is in contact with the N-drift layer on the side, facing the first N-buffer layer, of the N-drift layer, and the first N-buffer layer is embedded into the P-layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a method for preparing the same, and an electronic device. Background Art

[0002] When bipolar power devices are turned on, both holes and electrons participate in conduction. The number of minority carriers in the drift layer is much higher than the background doping concentration, so a conductivity modulation effect occurs in the drift layer, greatly reducing the on-resistance of the drift layer. Therefore, bipolar power devices are widely used in applications that require high voltage and high current. Summary of the invention

[0003] The embodiments of the present disclosure provide a semiconductor device, a method for manufacturing the same, and an electronic device, which can manufacture an N-type IGBT based on an N-type substrate, integrate a freewheeling diode inside the device, and reduce the turn-off loss of the device.

[0004] The present disclosure provides a semiconductor device, a method for manufacturing the same, and an electronic device, and the specific scheme is as follows: In one aspect, an embodiment of the present disclosure provides a semiconductor device, including: P+ anode; a first N-buffer layer, wherein the P+ anode is embedded in the first N-buffer layer; An N-drift layer, located on a side of the first N-buffer layer away from the P+ anode; A P-layer is in contact with the N-drift layer at a side of the N-drift layer facing the first N-buffer layer, and the first N-buffer layer is embedded in the P-layer.

[0005] In some embodiments, the above-mentioned semiconductor device provided in the embodiments of the present disclosure further includes an N+ substrate, a second N-buffer layer, a P-well layer and a P+ cathode, wherein the N+ substrate, the second N-buffer layer, the P-layer, the N-drift layer, the P-well layer and the P+ cathode are stacked in sequence, and the first N-buffer layer and the second N-buffer layer are spaced apart.

[0006] In some embodiments, the above-mentioned semiconductor device provided by the embodiments of the present disclosure further includes a groove, wherein the groove partially penetrates the P-layer on a side of the P-layer away from the N-drift layer; the first N-buffer layer is embedded in the P-layer at the groove, and the second N-buffer layer is in contact with the P-layer outside the groove.

[0007] In some embodiments, the above-mentioned semiconductor device provided in the embodiments of the present disclosure further includes an anode conductive layer, and the groove also penetrates the N+ substrate and the second N-buffer layer, and the anode conductive layer contacts the P+ anode at the groove and is spaced apart from the N+ substrate, the second N-buffer layer, and the P-layer.

[0008] In some embodiments, the semiconductor device provided in the embodiments of the present disclosure further includes an anode dielectric layer, which fills the gap between the anode conductive layer and the N+ substrate, the second N-buffer layer, and the P-layer.

[0009] On the other hand, an embodiment of the present disclosure provides a method for preparing the semiconductor device, comprising: sequentially forming a stacked P-layer and an N-drift layer; forming a groove partially penetrating the P-layer on a side of the P-layer away from the N-drift layer; Implanting N-type impurities into the P-layer at the trench to form a first N-buffer layer; P-type impurities are implanted into the first N-buffer layer to form a P+ anode.

[0010] In some embodiments, in the above-mentioned preparation method provided by the embodiment of the present disclosure, before sequentially forming the stacked P-layer and the N-drift layer, it further includes: forming a second N-buffer layer on the N+ substrate; While forming a groove partially penetrating the P-layer on a side of the P-layer away from the N-drift layer, the method further includes: forming the groove penetrating the N+ substrate and the second N-buffer layer; After injecting N-type impurities into the P-layer at the trench to form a first N-buffer layer, and before injecting P-type impurities into the first N-buffer layer to form a P+ anode, the method further includes: forming a first hard mask covering the sidewalls of the trench and the N+ substrate; After implanting P-type impurities into the first N-buffer layer to form a P+ anode, the method further includes: removing the first hard mask.

[0011] In some embodiments, in the above-mentioned preparation method provided by the embodiment of the present disclosure, forming a groove penetrating the N+ substrate and the second N-buffer layer and partially penetrating the P-layer specifically includes: Under the protection of the second hard mask, forming a trench penetrating the N+ substrate and the second N-buffer layer and partially penetrating the P-layer; While removing the first hard mask, the method further includes: removing the second hard mask.

[0012] In some embodiments, in the above-mentioned preparation method provided in the embodiment of the present disclosure, after removing the first hard mask and the second hard mask, the method further includes: forming an anode dielectric layer covering the sidewalls of the trench; An anode conductive layer is formed to contact the lower surface of the P+ anode, the surface of the anode dielectric layer away from the trench sidewall, and the lower surface of the N+ substrate.

[0013] On the other hand, an embodiment of the present disclosure further provides an electronic device, comprising the above-mentioned semiconductor device provided by an embodiment of the present disclosure.

[0014] The beneficial effects of the present disclosure are as follows: The semiconductor device, preparation method thereof and electronic device provided by the embodiment of the present disclosure include: a P+ anode; a first N-buffer layer, the P+ anode is embedded in the first N-buffer layer; an N-drift layer is located on the side of the first N-buffer layer away from the P+ anode; a P-layer is in contact with the N-drift layer on the side of the N-drift layer facing the first N-buffer layer, and the first N-buffer layer is embedded in the P-layer. The present disclosure introduces a P-layer on the side of the N-drift layer facing the first N-buffer layer, and the P-layer can be used together with the N-drift layer as a device drift region. Therefore, part of the drift region of the present disclosure is undertaken by the P-layer, which is equivalent to introducing heterogeneous impurity doping in the drift region, so that the equivalent doping concentration of the device drift region is reduced, which is conducive to accelerating the establishment speed of the electric field in the drift region when the device is turned off, thereby reducing the turn-off loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of a structure of a semiconductor device provided by an embodiment of the present disclosure; Figure 2 for Figure 1 A schematic diagram of current distribution when the semiconductor device is forward-conducting; Figure 3 for Figure 1 A schematic diagram of current distribution when the semiconductor device is reversely conducted; Figure 4 A schematic diagram of another structure of a semiconductor device provided in an embodiment of the present disclosure; Figure 5 A flow chart of a method for preparing a semiconductor device provided in an embodiment of the present disclosure; Figure 6 (a) shows Figure 1 A schematic diagram of the structure of a semiconductor device during the preparation process shown; Figure 6(b) shows Figure 1 Another structural schematic diagram of the semiconductor device during the preparation process shown; Figure 6(c) shows Figure 1 Another structural schematic diagram of the semiconductor device during the preparation process shown; Figure 6(d) Figure 1 Another structural schematic diagram of the semiconductor device during the preparation process shown; Figure 6(e) shows Figure 1 Another structural schematic diagram of the semiconductor device during the preparation process shown; Figure 6(f) shows Figure 1 Another structural schematic diagram of the semiconductor device during the preparation process shown; Figure 6(g) shows Figure 1 Another structural schematic diagram of the semiconductor device during the preparation process shown; Figure 6 (h) shows Figure 1 Another structural schematic diagram of the semiconductor device during the preparation process shown; Figure 6 (i) shows Figure 1 Another structural schematic diagram of the semiconductor device during the preparation process shown; Figure 6(j) is Figure 1 Another structural schematic diagram of a semiconductor device during the preparation process is shown. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solution and advantages of the embodiment of the present disclosure clearer, the technical solution of the embodiment of the present disclosure will be clearly and completely described in conjunction with the drawings of the embodiment of the present disclosure. It should be noted that the size and shape of each figure in the drawings do not reflect the actual proportion, and the purpose is only to illustrate the content of the present disclosure. And the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. In order to keep the following description of the embodiment of the present disclosure clear and concise, the present disclosure omits the detailed description of known functions and known parts.

[0017] Unless otherwise defined, the technical or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0018] The present disclosure provides a semiconductor device that can be fabricated based on semiconductor materials such as silicon, silicon carbide, gallium nitride, etc., through processes such as epitaxy and ion implantation. Figure 1 As shown, the semiconductor device provided by the present disclosure may include: P+ anode 101, optionally, the P+ anode 101 is formed by an ion implantation process.

[0019] The first N-buffer layer 102 covers the upper surface and side surfaces of the P+ anode 101 , which is equivalent to the P+ anode 101 being embedded in the first N-buffer layer 102 . In some embodiments, the first N-buffer layer 102 can be prepared by an ion implantation process.

[0020] The N-drift layer 103 is located on a side of the first N-buffer layer 102 away from the P+ anode 101 . The N-drift layer 103 may be formed by an epitaxial growth process.

[0021] The P-layer 104 contacts the N-drift layer 103 at a side of the N-drift layer 103 facing the first N-buffer layer 102 , and the first N-buffer layer 102 is embedded in the P-layer 104 . The present disclosure can form the P-layer 104 using an epitaxial growth process.

[0022] In the above-mentioned semiconductor device provided by the embodiment of the present disclosure, a P-layer 104 is introduced on the side of the N-drift layer 103 facing the first N-buffer layer 102. The P-layer 104 can be used together with the N-drift layer 103 as a device drift region. Therefore, part of the drift region of the present disclosure is borne by the P-layer 104, which is equivalent to introducing heterogeneous impurity doping in the drift region, so that the equivalent doping concentration of the device drift region is reduced, which is beneficial to speed up the establishment speed of the drift region electric field when the device is turned off, thereby reducing the turn-off loss.

[0023] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, Figure 1 As shown, it may also include an N+ substrate 105, a second N-buffer layer 106, a P-well layer 107 and a P+ cathode 108. The N+ substrate 105, the second N-buffer layer 106, the P-layer 104, the N-drift layer 103, the P-well layer 107, and the P+ cathode 108 are stacked in sequence, and the first N-buffer layer 102 and the second N-buffer layer 106 are spaced apart.

[0024] Conventional bipolar devices such as bipolar junction transistors IGBT, thyristors GTO, MOS controlled thyristors MCT, etc. do not have reverse conduction capability, but in most applications, reverse current needs to be freewheeled, so external anti-parallel diodes are often used to achieve freewheeling. If the freewheeling diode can be integrated inside the bipolar device, it can not only reduce the parasitic inductance and parasitic resistance of the connecting leads, but also improve the device power density by saving the terminal area, improve the device performance, and reduce the system volume. The present disclosure is provided by arranging the P-layer 104 and stacking it with the N+ substrate 105, the second N-buffer layer 106, the N-drift layer 103, the P-well layer 107, and the P+ cathode 108, so that a PNPN diode structure composed of the P+ cathode 108, the P-well layer 107, the N-drift layer 103, the P-layer 104, the second N-buffer layer 106, and the N+ substrate 105 is formed inside the device, thereby integrating the freewheeling diode in the device to achieve the freewheeling function.

[0025] In some embodiments, Figure 2 As shown, in the forward conduction mode, the cathode of the device is connected to zero potential and the anode of the device is connected to positive potential. When the gate voltage changes from zero potential or negative potential to positive potential, the surface of the P-well layer 107 under the gate dielectric layer 113 is inverted to form an electron channel. Since the PN junction between the P-layer 104 and the second N-buffer layer 106 is in a reverse biased state, the N+ substrate 105 will not be turned on, and the PN junction between the P+ anode 101 and the first N-buffer layer 102 is in a forward biased state. The PN junction between the P+ anode 101 and the first N-buffer layer 102 will gradually open. As the hole current increases, the PNPN diode composed of the P+ anode 101, the first N-buffer layer 102, the P-layer 104, and the N-drift layer 103 will open, and the device enters the bipolar conduction mode. Therefore, the existence of the N+ substrate 105 will not affect the normal forward conduction process of the device. Figure 3 As shown, in the reverse conduction mode, the cathode of the device is connected to zero potential, the anode of the device is connected to a negative potential, and the gate voltage is zero potential or negative potential. The PNPN diode structure composed of the P+ cathode 108, the P-well layer 107, the N-drift layer 103, the P-layer 104, the second N-buffer layer 106, and the N+ substrate 105 inside the device will be turned on, thereby realizing the freewheeling function. In the present disclosure, the first N-buffer layer 102 and the second N-buffer layer 106 are arranged at intervals to avoid mutual interference between the forward conduction current and the reverse conduction current.

[0026] In addition, due to the high defects of the SiC P-type substrate, the defect density of the epitaxial wafer grown based on the P-type substrate is high, and the performance and reliability of the bipolar device prepared thereby are poor. And due to the high defects of the P-type substrate, its resistivity is large, and the thicker P-type substrate will cause additional on-resistance. If the substrate is thinned as a whole, the mechanical strength of the substrate will be reduced, thereby increasing the probability of fragmentation. Therefore, bipolar power devices are usually made based on N-type substrates. However, devices prepared based on N-type substrates, such as IGBT devices, are usually P-type IGBTs, which are opposite to the current common N-type IGBT electrical polarity. The application circuit and the drive circuit are relatively complex and incompatible with the commonly used application circuits, which affects the application of the device. The present disclosure can form an N-type IGBT structure based on the N+ substrate 105 by digging grooves, digging through the N+ substrate 105 and the second N-buffer layer 106, and digging into the P-layer 104, and then forming the first N-buffer layer 102 and the P+ anode 101 through an ion implantation process. The process is simple, and the thicker N+ substrate 105 can be retained to keep the device with sufficient mechanical strength.

[0027] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, Figure 1 As shown, it may also include a trench T, which partially penetrates the P-layer 104 on a side of the P-layer 104 away from the N-drift layer 103; the first N-buffer layer 102 is embedded in the P-layer 104 at the trench T, and the second N-buffer layer 106 is in contact with the P-layer 104 outside the trench T, thereby utilizing the trench T to separate the first N-buffer layer 102 and the second N-buffer layer 106, thereby effectively avoiding mutual interference between the forward conduction current and the reverse conduction current.

[0028] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, Figure 1 As shown, it can also include an anode conductive layer 109, and the groove T also penetrates the N+ substrate 105 and the second N-buffer layer 106. The anode conductive layer 109 contacts the P+ anode 101 at the groove T, and is spaced apart from the N+ substrate 105, the second N-buffer layer 106, and the P-layer 104. At the same time, the anode conductive layer 109 also covers the lower surface of the N+ substrate 105, so that the anode conductive layer 109 and the N+ substrate 105, the second N-buffer layer 106, and the P-layer 104 can be insulated from each other, thereby avoiding the mutual influence between the forward conduction current and the reverse conduction current of the device. In some embodiments, the gaps between the anode conductive layer 109 and the N+ substrate 105, the second N-buffer layer 106, and the P-layer 104 may be filled with the anode dielectric layer 110, so that the anode conductive layer 109 is separated from the side walls of the N+ substrate 105, the side walls of the second N-buffer layer 106, and the side walls of the P-layer 104 by the anode dielectric layer 110, and the anode conductive layer 109 may be led out as the device anode.

[0029] In some embodiments, in the semiconductor device provided in the embodiments of the present disclosure, Figure 1 As shown, it may also include an N+ cathode 111, a cathode conductive layer 112, a gate dielectric layer 113, a gate conductive layer 114 and an isolation dielectric layer 115. Among them, a unit cell may include multiple P-well layers 107, multiple N+ cathodes 111 and multiple P+ cathodes 108, the N+ cathode 111 is embedded in the P-well layer 107, the P+ cathode 108 is embedded in the N+ cathode 111, and the lower surface of the P+ cathode 108 and the lower surface of the N+ cathode 111 are in contact with the upper surface of the P-well layer 107, and the lower surface of the cathode conductive layer 112 is in contact with the upper surface of the N+ cathode 111 and the upper surface of the P+ cathode 108 at the same time. The gate dielectric layer 113 contacts the upper surface of the P-well layer 107 and the upper surface of the N+ cathode 111, the gate conductive layer 114 is located on the upper surface of the gate dielectric layer 113, the upper surface and side surfaces of the gate conductive layer 114 contact the isolation dielectric layer 115, the upper surface and side surfaces of the isolation dielectric layer 115 contact the cathode conductive layer 112, and the isolation dielectric layer 115 and the gate dielectric layer 113 completely wrap the gate conductive layer 114. The gate conductive layer 114 can be led out as a device gate, and the cathode conductive layer 112 can be led out as a device cathode.

[0030] In some embodiments, the P-well layer 107, P+ cathode 108, N+ cathode 111, and cathode conductive layer 112 of the present disclosure may belong to the cathode region, the gate dielectric layer 113, gate conductive layer 114, and isolation dielectric layer 115 may belong to the gate region, the N-drift layer 103 and the P-layer 104 may belong to the drift region, and the P+ anode 101, the first N-buffer layer 102, the N+ substrate 105, the second N-buffer layer 106, the anode conductive layer 109, and the anode dielectric layer 110 may belong to the anode region. Figure 1 FIG. 1 shows a drift region, a cathode region, and a gate region disposed on an anode region. In some embodiments, multiple repeated drift regions, cathode regions, and gate regions may be disposed on an anode region according to process capabilities and required device performance. Figure 4 It shows that two drift regions, two cathode regions and two gate regions are arranged on an anode region, wherein the two drift regions are arranged integrally, the P-well layers 107 on adjacent sides of the two cathode regions are arranged integrally, the P+ cathode 108 is arranged integrally, the cathode conductive layer 112 is arranged integrally, and the two gate regions are arranged apart by the cathode conductive layer 112.

[0031] Based on the same inventive concept, an embodiment of the present disclosure provides a method for preparing the above-mentioned semiconductor device. Since the principle of solving the problem by the preparation method is similar to the principle of solving the problem by the above-mentioned semiconductor device, the implementation of the preparation method provided by the embodiment of the present disclosure can refer to the implementation of the above-mentioned semiconductor device provided by the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0032] In some embodiments, in the above-mentioned preparation method provided in the embodiments of the present disclosure, if Figure 5 As shown, the following steps may be included: S501, sequentially forming a stacked P-layer and an N-drift layer; S502, forming a groove partially penetrating the P-layer on a side of the P-layer away from the N-drift layer; S503, injecting N-type impurities into the P-layer at the trench to form a first N-buffer layer; S504 , injecting P-type impurities into the first N-buffer layer to form a P+ anode.

[0033] In order to better understand the above preparation method provided by the embodiments of the present disclosure, Figure 1 The manufacturing process of the semiconductor device shown is described in detail.

[0034] In some embodiments, Figure 1 The manufacturing process of the semiconductor device shown may include the following steps: Step (1): As shown in FIG. 6( a ), a second N-buffer layer 106 , a P-layer 104 and an N-drift layer 103 are epitaxially grown in sequence on an N+ substrate 105 .

[0035] Step (2): As shown in FIG. 6( b ), a P-well layer 107 , an N+ cathode 111 , and a P+ cathode 108 are selectively formed on the surface of the N-drift layer 103 by ion implantation technology.

[0036] Step (3): As shown in FIG6(c), a second hard mask HM2 is formed on the back side of the N+ substrate 105, and then selective etching is performed to etch the N+ substrate 105, the second N-buffer layer 106, and the P-layer 104 using a dry etching method until the etching reaches the P-layer 104, thereby forming a trench T that penetrates the N+ substrate 105, the second N-buffer layer 106, and partially penetrates the P-layer 104.

[0037] Step (4): As shown in FIG. 6( d ), while maintaining the second hard mask HM2 , N-type impurities are injected into the N-drift layer 103 at the trench T from the back side of the N+ substrate 105 , thereby forming a first N-buffer layer 102 .

[0038] Step (5): As shown in FIG6( e), the second hard mask HM2 is maintained in the state and another layer of the first hard mask HM1 is grown on the back side.

[0039] Step (6): As shown in FIG. 6( f ), a reactive ion ICP etching method is used to etch the first hard mask HM1 on the back side until the first hard mask HM1 in the middle of the surface of the first N-buffer layer 102 is removed.

[0040] Step (7): As shown in FIG6(g), P-type impurities are implanted from the back of the N+ substrate 105 into the first N-buffer layer 102 at the trench T, thereby forming a P+ anode 101. Subsequently, the second hard mask HM2 on the back of the N+ substrate 105 and the first hard mask HM1 on the sidewall of the trench T are stripped off. Then, an annealing treatment is performed to activate the implanted ions and repair lattice damage.

[0041] Step (8): As shown in FIG6(h), a gate dielectric layer 113, a gate conductive layer 114, an isolation dielectric layer 115 and a cathode conductive layer 112 are sequentially formed on the surface of the device.

[0042] Step (9): As shown in FIG6(i), an anode dielectric layer 110 is deposited on the back side of the device.

[0043] Step (10): As shown in FIG6(j), a reactive ion ICP etching method is used on the back side of the device to etch away the anode dielectric layer 110 in the middle area of ​​the lower surface of the N+ substrate 105 and the lower surface of the P+ anode 101, leaving only the anode dielectric layer 110 on the side wall of the trench T.

[0044] Step (11): If Figure 1 As shown, an anode conductive layer 109 is formed on the back side of the device by, for example, sputtering.

[0045] So far, it is completed Figure 1 Preparation of the semiconductor device shown.

[0046] Based on the same inventive concept, an embodiment of the present disclosure provides an electronic device, including the semiconductor device provided in the embodiment of the present disclosure. Since the principle of solving the problem by the electronic device is similar to the principle of solving the problem by the semiconductor device, the implementation of the electronic device provided in the embodiment of the present disclosure can refer to the implementation of the semiconductor device provided in the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0047] In some embodiments, the electronic devices provided by the embodiments of the present disclosure may include, but are not limited to: radio frequency amplifiers, mixers, radars, satellites, power supplies, automotive electronics, energy-saving lamps, household appliances, etc. Of course, the electronic devices provided by the present disclosure may include other structures in addition to semiconductor devices. For example, when the electronic device is a radar, it may also include: transmitters, antennas, receivers, etc.; when the electronic device is a mixer, it may also include: input ports, output ports, etc.

[0048] From the above content, it can be seen that the present disclosure achieves the purpose of preparing an N-type IGBT based on an N+ substrate, which can retain a thicker N+ substrate to maintain sufficient mechanical strength of the device. The present disclosure also forms a PNPN diode structure composed of a P+ cathode, a P-type well layer, an N-drift layer, a P-layer, a second N-buffer layer, and an N+ substrate inside the device by introducing a P-layer above the N+ substrate and the first N-buffer layer, thereby integrating a freewheeling diode in the device to achieve a freewheeling function. Moreover, when the device in the present disclosure is forward-conducted, the PNPN diode composed of a P+ anode, a first N-buffer layer, a P-layer, and an N-drift layer is turned on, and the presence of the N+ substrate does not affect the normal forward conduction process of the device. In addition, since part of the drift region is borne by the P-type region, the equivalent doping concentration of the drift region of the device decreases, which is conducive to accelerating the establishment of the drift region electric field when turning off, thereby reducing the turn-off loss. In addition, based on the N+ substrate epitaxy, the device epitaxial layer (including the first N-buffer layer, the P-layer, and the N-drift layer) can achieve a lower defect density. The back side only needs to dig a groove and form the P+ anode and the first N- buffer layer through ion implantation process, which is a relatively simple process.

[0049] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0050] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A semiconductor device, characterized in that: include: P+ anode; a first N-buffer layer, wherein the P+ anode is embedded in the first N-buffer layer; An N-drift layer, located on a side of the first N-buffer layer away from the P+ anode; A P-layer is in contact with the N-drift layer at a side of the N-drift layer facing the first N-buffer layer, and the first N-buffer layer is embedded in the P-layer.

2. The semiconductor device according to claim 1, wherein It also includes an N+ substrate, a second N-buffer layer, a P-well layer and a P+ cathode. The N+ substrate, the second N-buffer layer, the P-layer, the N-drift layer, the P-well layer and the P+ cathode are stacked in sequence, and the first N-buffer layer and the second N-buffer layer are spaced apart.

3. The semiconductor device according to claim 2, wherein: It also includes a groove, which penetrates the P-layer at a side of the P-layer away from the N-drift layer; the first N-buffer layer is embedded in the P-layer at the groove, and the second N-buffer layer is in contact with the P-layer at the periphery of the groove.

4. The semiconductor device according to claim 3, characterized in that It also includes an anode conductive layer, the groove also penetrates the N+ substrate and the second N-buffer layer, the anode conductive layer contacts the P+ anode at the groove, and is spaced apart from the N+ substrate, the second N-buffer layer, and the P-layer.

5. The semiconductor device according to claim 4, wherein: The invention also includes an anode dielectric layer, wherein the anode dielectric layer fills the gaps between the anode conductive layer and the N+ substrate, the second N-buffer layer, and the P-layer.

6. A method for preparing a semiconductor device according to any one of claims 1 to 5, characterized in that: include: sequentially forming a stacked P-layer and an N-drift layer; forming a groove partially penetrating the P-layer on a side of the P-layer away from the N-drift layer; Implanting N-type impurities into the P-layer at the trench to form a first N-buffer layer; P-type impurities are implanted into the first N-buffer layer to form a P+ anode.

7. The preparation method according to claim 6, characterized in that: Before sequentially forming the stacked P-layer and the N-drift layer, the method further includes: forming a second N-buffer layer on the N+ substrate; While forming a groove partially penetrating the P-layer on a side of the P-layer away from the N-drift layer, the method further includes: forming the groove penetrating the N+ substrate and the second N-buffer layer; After injecting N-type impurities into the P-layer at the trench to form a first N-buffer layer, and before injecting P-type impurities into the first N-buffer layer to form a P+ anode, the method further includes: forming a first hard mask covering the sidewalls of the trench and the N+ substrate; After implanting P-type impurities into the first N-buffer layer to form a P+ anode, the method further includes: removing the first hard mask.

8. The preparation method according to claim 7, characterized in that: Forming a trench penetrating the N+ substrate and the second N-buffer layer and partially penetrating the P-layer specifically includes: Under the protection of the second hard mask, forming a trench penetrating the N+ substrate and the second N-buffer layer and partially penetrating the P-layer; While removing the first hard mask, the method further includes: removing the second hard mask.

9. The preparation method according to claim 8, characterized in that: After removing the first hard mask and the second hard mask, the method further includes: forming an anode dielectric layer covering the sidewalls of the trench; An anode conductive layer is formed to contact the lower surface of the P+ anode, the surface of the anode dielectric layer away from the trench sidewall, and the lower surface of the N+ substrate.

10. An electronic device, characterized in that: Comprising a semiconductor device as described in any one of claims 1 to 5.

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