Formation method of semiconductor structure

Abstract

A semiconductor structure forming method comprises the steps that a substrate comprises a base, a first fin part and a second fin part, the first fin part and the second fin part are located on the base, the first fin part comprises a first channel region, and the second fin part comprises a second channel region; forming an isolation structure on the surface of the substrate, wherein the isolation structure exposes the first channel region and the second channel region; performing first plasma dry etching processing on the first channel region and the second channel region, wherein the etching amount of the first plasma dry etching processing on the second channel region is greater than that on the first channel region; after the first plasma dry etching treatment is carried out, the second plasma dry etching treatment is carried out on the first channel region and the second channel region, and after the second plasma dry etching treatment, the roughness of the surface of the first channel region is reduced, the roughness of the surface of the second channel region is reduced, and the roughness of the surface of the first channel region is reduced. Therefore, scattering of electrons on the surface of the first channel region is reduced, and the effective current of the channel is improved so as to improve the performance of the device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In the existing semiconductor field, the fin field effect transistor (FinFET) is an emerging multi-gate device. Compared with the planar metal-oxide semiconductor field effect transistor (MOSFET), the fin field effect transistor has stronger short channel suppression capability and stronger operating current, and is now widely used in various semiconductor devices.

[0003] Germanium silicon material has become a hot spot in the research of new channel materials due to its high carrier mobility, higher device reliability and compatibility with existing silicon-based processes. Using germanium silicon material to make the channel (fin) of fin field effect transistors can make fin field effect transistors have larger driving current, faster switching speed and lower driving voltage.

[0004] However, the fins formed by the germanium-silicon material in the prior art have poor morphology, which limits the advantages of the germanium-silicon channel. Therefore, the existing method for forming the fin field effect transistor needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: forming a substrate, the substrate comprising a base, a first fin and a second fin located on the base, the first fin comprising a first channel region, the second fin comprising a second channel region, the first channel region and the second channel region are made of different materials, and the width of the second channel region is greater than the width of the first channel region; forming an isolation structure on the surface of the substrate, the isolation structure exposing the first channel region and the second channel region; performing a first plasma dry etching treatment on the first channel region and the second channel region, the first plasma dry etching treatment etching the second channel region more than the etching amount of the first channel region; after performing the first plasma dry etching treatment, performing a second plasma dry etching treatment on the first channel region and the second channel region, and after the second plasma dry etching treatment, the roughness of the surface of the first channel region is reduced, and the roughness of the surface of the second channel region is reduced.

[0007] Optionally, the etching selectivity ratio of the first plasma dry etching treatment to the second channel region and the first channel region ranges from 1:1 to 50:1; and the etching selectivity ratio of the second plasma dry etching treatment to the second channel region and the first channel region is less than 1:1.

[0008] Optionally, it includes: the first plasma dry etching treatment and the second plasma dry etching treatment both use free radicals as active particles; the etching gas of the first plasma dry etching treatment includes hydrogen; the etching gas of the second plasma dry etching treatment does not include hydrogen; the etching gas of the second plasma dry etching treatment includes a hydrogen-containing compound gas, and the hydrogen-containing compound gas includes one or both of hydrogen fluoride and ammonia.

[0009] Optionally, the first plasma dry etching treatment process parameters include: the etching gas also includes at least three gases of carbon tetrafluoride gas, nitrogen trifluoride gas, argon gas, hydrogen fluoride and ammonia gas; the RF power range is 200 watts to 1200 watts; the reaction temperature range is -50 degrees Celsius to 200 degrees Celsius.

[0010] Optionally, the second plasma dry etching treatment process parameters include: the etching gas also includes one or more of carbon tetrafluoride gas, nitrogen trifluoride gas and argon gas; the RF power range is 200 watts to 1200 watts; the reaction temperature range is -50 degrees Celsius to 200 degrees Celsius.

[0011] Optionally, after the second plasma dry etching treatment, it also includes: forming a gate on a portion of the surface of the isolation structure, the gate spanning the first fin and the second fin, and the gate is located on a portion of the side walls and top surface of the first channel region, and the gate is located on a portion of the side walls and top surface of the second channel region.

[0012] Optionally, after the second plasma dry etching process and before forming the gate, the method further includes: forming a second protective layer on surfaces of the first channel region and the second channel region.

[0013] Optionally, the material of the second protective layer includes silicon.

[0014] Optionally, the material of the gate includes polysilicon.

[0015] Optionally, the method for forming the isolation structure includes: forming a dielectric material layer on the surface of the substrate, the top surface of the dielectric material layer being higher than the top surfaces of the first fin and the second fin; planarizing the dielectric material layer; after the planarization process, etching back the dielectric material layer until the side walls of the first channel region and the second channel region are exposed, thereby forming an isolation structure with the dielectric material layer.

[0016] Optionally, the dielectric material layer includes a first dielectric layer and a second dielectric layer located on the first dielectric layer, the top surface of the first dielectric layer is higher than the top surfaces of the first fin and the second fin, and the density of the second dielectric layer is higher than the density of the first dielectric layer.

[0017] Optionally, the process for forming the first dielectric layer includes a fluid chemical vapor deposition process; and the process for forming the second dielectric layer includes a plasma enhanced chemical vapor deposition process.

[0018] Optionally, before forming the isolation structure, a first protection layer is further formed on surfaces of the first fin and the second fin.

[0019] Optionally, the material of the first protective layer includes silicon or silicon nitride.

[0020] Optionally, the material of the first channel region includes silicon germanium; and the material of the second channel region includes silicon.

[0021] Optionally, the first fin also includes a first bottom region, which is located between the substrate and the first channel region; the second fin also includes a second bottom region, which is located between the substrate and the second channel region; and the isolation structure is located on the side walls of the first bottom region and the second bottom region.

[0022] Optionally, the method for forming the substrate includes: providing an initial substrate; etching the initial substrate to form a groove in the initial substrate; forming a channel material layer in the groove; forming a hard mask layer on a portion of the initial substrate and the channel material layer; using the hard mask layer as a mask, etching the initial substrate and the channel material layer to form the first channel region with the channel material layer, and forming the base and the second channel region with the initial substrate.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0024] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the first channel region and the second channel region are subjected to two plasma dry etching treatments, wherein the etching amount of the second channel region in the first plasma dry etching treatment is greater than the etching amount of the first channel region, which is beneficial to reducing the size difference between the second channel region and the first channel region, and the second plasma dry etching process is used to repair the etching damage caused to the first channel region by the first plasma dry etching process, reduce the roughness of the surface of the first channel region, thereby reducing the scattering of electrons by the surface of the first channel region, and increase the effective current of the channel to improve the performance of the device.

[0025] Furthermore, both the first plasma dry etching process and the second plasma dry etching process use free radicals as active particles. Using free radicals for etching can achieve isotropic etching with less etching damage to the etched surface.

[0026] Furthermore, the etching gas in the first plasma dry etching process includes hydrogen, while the etching gas in the second plasma dry etching process does not include hydrogen. Here, hydrogen is used to improve the etching selectivity between the second channel region and the first channel region, but it is easy to cause the accumulation of low-valent oxides on the surface of the first channel region during the etching process, which is not conducive to further etching and makes the surface roughness of the first channel region larger. The second plasma dry etching process does not use hydrogen as an etching gas, and is used to repair the etching damage caused to the first channel region by the first plasma dry etching process.

[0027] Furthermore, the etching gas of the second plasma dry etching treatment includes a hydrogen-containing compound gas, and the hydrogen-containing compound gas includes one or both of hydrogen fluoride and ammonia. Here, hydrogen fluoride and ammonia can remove oxides, thereby avoiding the situation where the surface roughness of the first channel region is affected by the accumulation of oxides, which is beneficial to improving the smoothness of the surface of the first channel region. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 4 It is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure;

[0029] Figures 5 to 10 It is a schematic cross-sectional structure diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0031] As described in the background art, the prior art technology for forming fins in a fin field effect transistor structure needs to be improved. Now, a semiconductor structure is used for illustration and analysis.

[0032] Figures 1 to 4 The invention is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure.

[0033] Please refer to Figure 1, providing a substrate, the substrate comprising a base 100, a first fin 101 and a second fin 102 located on the base 100, the first fin 101 comprising a first bottom region 101a and a first channel region 101b located on the first bottom region 101a, the second fin 102 comprising a second bottom region 102a and a second channel region 102b located on the second bottom region 102a, the first fin 101 and the second fin 102 having a mask layer 103 on their top surfaces; forming a protective material layer 104 on the surfaces of the base 100, the first fin 101, the fin 102 and the mask layer 103.

[0034] Please refer to Figure 2 , a dielectric material layer 105 is formed on the surface of the substrate, and the top surface of the dielectric material layer 105 is higher than the top surface of the mask layer 103 .

[0035] Please refer to Figure 3 , the dielectric material layer 105 and the protective material layer 104 are etched back until the sidewalls of the first channel region 101b and the second channel region 102b are exposed, an isolation structure 106 is formed with the dielectric material layer 105, and a protective layer 107 is formed with the protective material layer 104.

[0036] Please refer to Figure 4 , the second channel region 102b is reduced so that the width of the second channel region 102b is equal to the width of the first channel region 101b.

[0037] The above method is used to form a fin field effect transistor device, wherein the first fin 101 and the second fin 102 are used to form different devices, the material of the first channel region 101b is germanium silicon, which is used to improve the carrier mobility of the PMOS device and improve the device performance, and the material of the second channel region 102b is silicon, which is used to form an NMOS device. Due to the different etching rates of germanium silicon and silicon materials, the widths of the first channel region 101b and the second channel region 102b are different. Specifically, the width of the second channel region 102b is greater than the width of the first channel region 101b. The reduction process usually adopts a wet etching process, which is conducive to the etching solution having a larger etching selectivity ratio of the second channel region 102b relative to the first channel region 101b, and the second channel region 102b is reduced so that the second channel region 102b and the first channel region 101b reach the same width.

[0038] However, during the heat treatment process such as the annealing process for forming the dielectric material layer 105, the germanium silicon material is more easily oxidized than the silicon material, and thus the germanium silicon material is more easily lost during the etching process, resulting in the difficulty in controlling the surface roughness of the first channel region 101b. Since the surface roughness affects the scattering of electrons and the effective current of the channel, the advantage of the germanium silicon material for PMOS devices is greatly reduced.

[0039] In order to improve the roughness problem of the surface of the first channel region formed by the germanium silicon material, in another embodiment, the surface oxidation of the first channel region is reduced by reducing the annealing temperature of the dielectric material layer. However, this method will result in poor quality of the isolation structure, and it is easy to cause the isolation structure to be over-etched during the reduction process, resulting in dishing defects and other abnormalities on the surface of the isolation structure.

[0040] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, performing two plasma dry etching treatments on a first channel region and a second channel region, wherein the etching amount of the second channel region in the first plasma dry etching treatment is greater than the etching amount of the first channel region, which is beneficial to reducing the size difference between the second channel region and the first channel region, and the second plasma dry etching process is used to repair the etching damage caused to the first channel region by the first plasma dry etching process, reduce the roughness of the surface of the first channel region, thereby reducing the scattering of electrons by the surface of the first channel region, and increase the effective current of the channel to improve the performance of the device.

[0041] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] Figures 5 to 10 It is a structural schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention.

[0043] Please refer to Figure 5 , forming a substrate, the substrate comprising a base 200, a first fin 201 and a second fin 202 located on the base 200, the first fin 201 comprising a first channel region 201b, the second fin 202 comprising a second channel region 202b, the first channel region 201b and the second channel region 202b having different materials, and a width of the second channel region 202b being greater than a width of the first channel region 201b.

[0044] It should be noted that the width refers to the dimension perpendicular to the channel direction.

[0045] In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0046] In this embodiment, the first fin 201 further includes a first bottom region 201a, which is located between the substrate 200 and the first channel region 201b; the second fin 202 further includes a second bottom region 202a, which is located between the substrate 200 and the second channel region 202b.

[0047] In this embodiment, the material of the first channel region 201b includes silicon germanium; the material of the second channel region 202b includes silicon.

[0048] In this embodiment, the material of the first bottom region 201a is silicon germanium, and the material of the second bottom region 202a is silicon. In another embodiment, the materials of the first bottom region and the second bottom region are both silicon.

[0049] In this embodiment, the method for forming the substrate includes: providing an initial substrate (not shown in the figure); etching the initial substrate to form a groove (not shown in the figure) in the initial substrate; forming a channel material layer (not shown in the figure) in the groove; forming a hard mask layer 203 on a portion of the initial substrate and the channel material layer; using the hard mask layer 203 as a mask, etching the initial substrate and the channel material layer, forming the first channel region 201b with the channel material layer, and forming the base 200 and the second channel region 202b with the initial substrate.

[0050] In this embodiment, the materials of the first bottom region 201a and the first channel region 201b are the same, that is, the channel material layer is also used to form the first bottom region 201a. Specifically, the channel material layer under the first channel region 201b is also etched to form the first bottom region 201a, and the initial substrate under the second channel region is etched to form the second bottom region 202a. In another embodiment, the materials of the first bottom region and the first channel region are different, that is, the initial substrate is used to form the first bottom region and the second bottom region. Specifically, the initial substrate under the first channel region is used to form the first bottom region, and the initial substrate is used to form the second bottom region.

[0051] In this embodiment, the first channel region 201b and the second channel region 202a are both single layers. In other embodiments, the first channel region 201b and the second channel region 202a may be a composite layer structure of a channel layer and a sacrificial layer, that is, a Nanosheet structure.

[0052] The material of the mask layer 203 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon carbon oxynitride.

[0053] The mask layer 203 may be a single-layer material film or a multi-layer material film. In this embodiment, the mask layer 203 is composed of three-layer material films: a silicon oxide film, a silicon nitride film, and a silicon oxide film.

[0054] Subsequently, an isolation structure is formed on the surface of the substrate, wherein the isolation structure exposes the first channel region 201 b and the second channel region 202 b .

[0055] In this embodiment, before forming the isolation structure, a first protection layer 204 is formed on the surface of the first fin 201 and the second fin 202. The first protection layer 204 is used to protect the first fin 201 and the second fin 202 during the process of forming the isolation structure.

[0056] The material of the first protection layer 204 includes silicon or silicon nitride. In this embodiment, the material of the first protection layer 204 is silicon.

[0057] In this embodiment, the method for forming the isolation structure is shown in FIG. Figures 6 to 8 .

[0058] Please refer to Figure 6 A dielectric material layer is formed on the surface of the substrate, wherein a top surface of the dielectric material layer is higher than top surfaces of the first fin 201 and the second fin 202 .

[0059] In this embodiment, the dielectric material layer includes a first dielectric layer 205 and a second dielectric layer 206 located on the first dielectric layer 205, the top surface of the first dielectric layer 205 is higher than the top surfaces of the first fin 201 and the second fin 202, and the density of the second dielectric layer 206 is higher than the density of the first dielectric layer 205. The density of the second dielectric layer 206 is higher than the density of the first dielectric layer 205, which is beneficial to improving the surface flatness of the dielectric material layer in the planarization process.

[0060] The material of the first dielectric layer 205 includes dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon carbon oxynitride. In this embodiment, the material of the first dielectric layer 205 is silicon oxide.

[0061] The material of the second dielectric layer 206 includes dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon carbon oxynitride. In this embodiment, the material of the second dielectric layer 206 is silicon oxide.

[0062] In this embodiment, the formation process of the first dielectric layer 205 includes a flowable chemical vapor deposition (FCVD) process, which has good gap filling capability, is conducive to forming a low-defect material film, and improves the performance of the formed isolation structure.

[0063] In this embodiment, the formation process of the second dielectric layer 206 includes a plasma enhanced chemical vapor deposition (PECVD) process. The PECVD process is conducive to forming a film with high density and flat surface, and is conducive to improving the surface flatness of the dielectric material layer in the flattening process.

[0064] Please refer to Figure 7 , planarizing the dielectric material layer.

[0065] The planarization process includes a mechanochemical polishing process.

[0066] Please refer to Figure 8 After the planarization process, the dielectric material layer is etched back until the sidewalls of the first channel region 201b and the second channel region 202b are exposed, and an isolation structure 207 is formed with the dielectric material layer.

[0067] In this embodiment, the isolation structure 207 is located on the side walls of the first bottom region 201 a and the second bottom region 201 b .

[0068] In this embodiment, during the process of etching back the dielectric material layer, the first protection layer 204 is also etched simultaneously.

[0069] Please refer to Fig. 9, performing a first plasma dry etching treatment on the first channel region 201b and the second channel region 202b, wherein the etching amount of the second channel region 202b by the first plasma dry etching treatment is greater than the etching amount of the first channel region 201b.

[0070] In this embodiment, the etching selectivity ratio of the first plasma dry etching process to the first channel region 201 b and the second channel region ranges from 1:1 to 50:1.

[0071] In this embodiment, the first plasma dry etching process uses free radicals as active particles. The free radicals are obtained by stripping charged particles after the plasma is generated, and are electrically neutral. Using free radicals for etching can achieve isotropic etching and cause less etching damage to the etched surface.

[0072] In this embodiment, the etching gas of the first plasma dry etching process includes hydrogen. Here, hydrogen is used to improve the etching selectivity of the second channel region 202b and the first channel region 201b, but it is easy to cause the accumulation of low-valent oxides on the surface of the first channel region 201b during the etching process, which is not conducive to further etching, making the surface roughness of the first channel region 201b relatively large. The subsequent second plasma dry etching process does not use hydrogen as an etching gas, and is used to repair the etching damage caused to the first channel region 201b by the first plasma dry etching process.

[0073] In this embodiment, the first plasma dry etching process parameters include: the etching gas also includes at least three gases of carbon tetrafluoride gas, nitrogen trifluoride gas, argon gas, hydrogen fluoride and ammonia gas; the RF power range is 200 watts to 1200 watts; the reaction temperature range is -50 degrees Celsius to 200 degrees Celsius.

[0074] Please continue to refer to Fig. 9 After the first plasma dry etching treatment, the first channel region 201b and the second channel region 202b are subjected to a second plasma dry etching treatment, and after the second plasma dry etching treatment, the roughness of the surface of the first channel region 201b is reduced, and the roughness of the surface of the second channel region 202b is reduced.

[0075] At this point, the first channel region 201b and the second channel region 202b are subjected to two plasma dry etching treatments, wherein the etching amount of the second channel region 202b in the first plasma dry etching treatment is greater than the etching amount of the first channel region 201b, which is beneficial to reducing the size difference between the second channel region 202b and the first channel region 201b, and the second plasma dry etching process is used to repair the etching damage to the first channel region 201b caused by the first plasma dry etching process, reduce the roughness of the surface of the first channel region 201b, thereby reducing the scattering of electrons on the surface of the first channel region 201b, and increase the effective current of the channel to improve the performance of the device.

[0076] In this embodiment, the etching selection ratio of the second plasma dry etching process to the second channel region 202b and the first channel region 201b is less than 1:1.

[0077] In this embodiment, the second plasma dry etching process also uses free radicals as active species.

[0078] In this embodiment, the etching gas used in the second plasma dry etching process does not include hydrogen.

[0079] In this embodiment, the etching gas of the second plasma dry etching process includes a hydrogen-containing compound gas, and the hydrogen-containing compound gas includes one or both of hydrogen fluoride and ammonia. Here, hydrogen fluoride and ammonia can remove oxides, avoid the situation where the surface roughness of the first channel region is affected by the accumulation of oxides, and help improve the smoothness of the surface of the first channel region.

[0080] In this embodiment, the second plasma dry etching treatment process parameters include: the etching gas also includes one or more of carbon tetrafluoride gas, nitrogen trifluoride gas and argon gas; the RF power range is 200 watts to 1200 watts; the reaction temperature range is -50 degrees Celsius to 200 degrees Celsius.

[0081] In this embodiment, after the second plasma dry etching process, please refer to Fig.10 .

[0082] Please refer to Fig.10 A gate 208 is formed on a portion of the surface of the isolation structure 207, the gate 208 spans the first fin 201 and the second fin 202, and the gate 208 is located on a portion of the sidewalls and top surface of the first channel region 201b, and the gate 208 is located on a portion of the sidewalls and top surface of the second channel region 202b.

[0083] In this embodiment, before forming the gate 208 , a gate oxide layer (not shown in the figure) is formed between the gate 208 and the first fin 201 and between the gate 208 and the second fin 202 .

[0084] The material of the gate 208 includes polysilicon. In this embodiment, the gate 208 is used as a dummy gate, and the gate 208 is subsequently replaced by a metal gate.

[0085] In this embodiment, after the second plasma dry etching process and before forming the gate 208 , a second protection layer 209 is formed on the surfaces of the first channel region 201 b and the second channel region 202 b .

[0086] The material of the second protection layer 209 includes silicon. In this embodiment, the material of the second protection layer 209 is silicon. The second protection layer 209 is used to protect the first channel region 201b and the second channel region 202b, and is also used to form the gate oxide layer.

[0087] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Forming a substrate, the substrate comprising a base, a first fin and a second fin located on the base, the first fin comprising a first channel region, the second fin comprising a second channel region, the first channel region and the second channel region being made of different materials, and a width of the second channel region being greater than a width of the first channel region; forming an isolation structure on the surface of the substrate, wherein the isolation structure exposes the first channel region and the second channel region; Performing a first plasma dry etching process on the first channel region and the second channel region, wherein the etching amount of the second channel region by the first plasma dry etching process is greater than the etching amount of the first channel region; After the first plasma dry etching treatment, the first channel region and the second channel region are subjected to a second plasma dry etching treatment, and after the second plasma dry etching treatment, the surface roughness of the first channel region is reduced, and the surface roughness of the second channel region is reduced.

2. The method for forming a semiconductor structure according to claim 1, wherein: The etching selectivity ratio of the first plasma dry etching treatment to the second channel region and the first channel region ranges from 1:1 to 50:1; the etching selectivity ratio of the second plasma dry etching treatment to the second channel region and the first channel region is less than 1:

1.

3. The method for forming a semiconductor structure according to claim 1, wherein: include: The first plasma dry etching process and the second plasma dry etching process both use free radicals as active species; The etching gas of the first plasma dry etching treatment includes hydrogen; the etching gas of the second plasma dry etching treatment does not include hydrogen; the etching gas of the second plasma dry etching treatment includes a hydrogen-containing compound gas, and the hydrogen-containing compound gas includes one or both of hydrogen fluoride and ammonia.

4. The method for forming a semiconductor structure according to claim 3, wherein: The first plasma dry etching process parameters include: the etching gas also includes at least three gases of carbon tetrafluoride gas, nitrogen trifluoride gas, argon gas, hydrogen fluoride and ammonia gas; the RF power range is 200 watts to 1200 watts; the reaction temperature range is -50 degrees Celsius to 200 degrees Celsius.

5. The method for forming a semiconductor structure according to claim 3, wherein: The second plasma dry etching process parameters include: the etching gas also includes one or more of carbon tetrafluoride gas, nitrogen trifluoride gas and argon gas; the RF power range is 200 watts to 1200 watts; the reaction temperature range is -50 degrees Celsius to 200 degrees Celsius.

6. The method for forming a semiconductor structure according to claim 1, wherein: After the second plasma dry etching treatment, it also includes: forming a gate on a portion of the surface of the isolation structure, the gate spanning the first fin and the second fin, and the gate is located on a portion of the sidewalls and top surface of the first channel region, and the gate is located on a portion of the sidewalls and top surface of the second channel region.

7. The method for forming a semiconductor structure according to claim 6, wherein: After the second plasma dry etching process and before forming the gate, the method further includes: forming a second protection layer on surfaces of the first channel region and the second channel region.

8. The method for forming a semiconductor structure according to claim 7, wherein: The material of the second protection layer includes silicon.

9. The method for forming a semiconductor structure according to claim 6, wherein: The gate is made of polysilicon.

10. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the isolation structure includes: forming a dielectric material layer on the surface of the substrate, wherein the top surface of the dielectric material layer is higher than the top surfaces of the first fin and the second fin; planarizing the dielectric material layer; and after the planarization process, etching back the dielectric material layer until the side walls of the first channel region and the second channel region are exposed, thereby forming an isolation structure with the dielectric material layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: The dielectric material layer includes a first dielectric layer and a second dielectric layer located on the first dielectric layer. The top surface of the first dielectric layer is higher than the top surfaces of the first fin and the second fin. The density of the second dielectric layer is higher than that of the first dielectric layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: The forming process of the first dielectric layer includes a fluid chemical vapor deposition process; the forming process of the second dielectric layer includes a plasma enhanced chemical vapor deposition process.

13. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the isolation structure, a first protection layer is formed on the surfaces of the first fin and the second fin.

14. The method for forming a semiconductor structure according to claim 13, wherein: The material of the first protection layer includes silicon or silicon nitride.

15. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first channel region includes silicon germanium; the material of the second channel region includes silicon.

16. The method for forming a semiconductor structure according to claim 1, wherein: The first fin also includes a first bottom region located between the substrate and the first channel region; the second fin also includes a second bottom region located between the substrate and the second channel region; the isolation structure is located on the sidewalls of the first bottom region and the second bottom region.

17. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the substrate includes: providing an initial substrate; etching the initial substrate to form a groove in the initial substrate; forming a channel material layer in the groove; forming a hard mask layer on a portion of the initial substrate and the channel material layer; etching the initial substrate and the channel material layer using the hard mask layer as a mask, forming the first channel region with the channel material layer, and forming the base and the second channel region with the initial substrate.

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