Thin film transistor and preparation method of thin film transistor
By forming a second trench on the substrate layer and setting a partial gate, combined with the design of the gate isolation layer and the active layer, the problem of low open state mobility of the IGZO material is solved, and a high storage density without increasing the device area is achieved.
Patent Information
- Application Number
- CN202311378090.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-23
- Publication Date
- 2025-04-25
AI Technical Summary
The existing IGZO materials have low open state mobility in dynamic random memory, resulting in low on-current, limiting the increase in storage density.
By forming a second trench on the substrate layer and providing a partial gate therein, a narrow trench three-dimensional channel device is formed to improve the open state current density and conduction current.
Without increasing the horizontal area of the device, the open-state current density and conduction current of the device are improved, thereby increasing the storage density.
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Figure CN119894053A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present application relate to the field of semiconductor technology, and in particular, to a thin film transistor and a method for preparing the thin film transistor. Background Art
[0002] Dynamic random access memory (DRAM) is the most widely used random access memory in the industry. Its mainstream structure is a combination of transistors and capacitors, namely 1T+1C. The oxide semiconductor IGZO has excellent off-state current, leading to the rise of 2T0C technology. However, the on-state mobility of IGZO is relatively low, only 3 to 15 cm 2 / Vs, the on-state (drive) current is low. Summary of the invention
[0003] The present invention aims to solve at least one of the technical problems existing in the prior art or related art.
[0004] To this end, a first aspect of the present invention provides a thin film transistor.
[0005] A second aspect of the present invention provides a method for preparing a thin film transistor.
[0006] In view of this, according to a first aspect of an embodiment of the present application, a thin film transistor is provided, comprising:
[0007] Substrate layer, source, drain, gate, active layer and gate isolation layer;
[0008] Wherein, the gate isolation layer is arranged on the substrate layer, the active layer is arranged on the gate isolation layer, the source electrode and the drain electrode are arranged on the active layer, and a first trench is formed between the source electrode and the drain electrode;
[0009] A second trench is formed on the substrate layer, at least a portion of the gate is disposed in the second trench, and the gate is connected to a side of the gate isolation layer away from the active layer.
[0010] In a feasible implementation manner, the gate includes:
[0011] a buried gate, the buried gate being disposed in the second trench and connected to the gate isolation layer;
[0012] A lead-out electrode is connected to the buried gate and is disposed on the substrate layer.
[0013] According to a second aspect of an embodiment of the present application, a method for preparing a thin film transistor is provided, which is used to prepare a thin film transistor as described in any of the above technical solutions, and the preparation method comprises:
[0014] Providing a substrate, and forming a first isolation layer on the substrate;
[0015] Etching the first isolation layer to form a second trench;
[0016] preparing the gate through the second trench;
[0017] Preparing a gate isolation layer and an active layer on the gate;
[0018] forming a metal layer on the active layer;
[0019] The metal layer is etched to form the first groove to obtain the source electrode and the drain electrode arranged at intervals.
[0020] In a feasible implementation manner, the step of etching the first isolation layer to form the second trench includes:
[0021] forming a first amorphous silicon layer, a second isolation layer, and a second amorphous silicon layer in sequence on the first isolation layer;
[0022] Etching the second amorphous silicon layer to form a first basic structure;
[0023] forming a first sidewall on the first basic structure, removing the first basic structure and a portion of the first sidewall, and retaining a portion of the first sidewall;
[0024] The second trench is formed by using the first sidewall as a mask.
[0025] In a feasible implementation manner, the step of forming the second trench by using the first sidewall as a mask includes:
[0026] Using the first sidewall spacer as a mask, etching the second isolation layer and the first amorphous silicon layer; removing the first sidewall spacer and the remaining second isolation layer;
[0027] Filling a third isolation layer around the remaining first amorphous silicon layer;
[0028] The remaining first amorphous silicon layer is removed to form the second trench on the third isolation layer.
[0029] In a feasible implementation manner, the step of preparing the gate through the second trench includes:
[0030] forming a buried gate in the second trench;
[0031] A lead-out electrode is formed on the substrate, and the lead-out electrode is connected to the buried gate.
[0032] In a feasible implementation manner, the step of etching the metal layer to form the first groove to obtain the source and the drain arranged at intervals includes:
[0033] Filling a fourth isolation layer around the metal layer;
[0034] forming a third amorphous silicon layer, a fifth isolation layer and a fourth amorphous silicon layer in sequence on the fourth isolation layer;
[0035] Etching the fourth amorphous silicon layer to form a second basic structure;
[0036] forming a second sidewall on the second base structure, removing the second base structure and a portion of the second sidewall, and retaining a portion of the second sidewall;
[0037] The first trench is formed by using the second sidewall as a mask.
[0038] In a feasible implementation manner, the step of forming the first trench by using the second sidewall as a mask includes:
[0039] Using the second sidewall spacer as a mask, etching the fifth isolation layer and the third amorphous silicon layer; removing the second sidewall spacer and the remaining fifth isolation layer;
[0040] Filling a sixth isolation layer around the remaining third amorphous silicon layer;
[0041] removing the remaining third amorphous silicon layer to form an etching groove;
[0042] The metal layer is etched based on the etched grooves to obtain the source and the drain arranged at intervals.
[0043] In a feasible implementation manner, the step of obtaining the source and the drain arranged at intervals includes:
[0044] forming a seventh isolation layer on the metal layer;
[0045] The seventh isolation layer is etched to expose the source and the drain, and the first trench is formed between the source and the drain.
[0046] In one possible implementation,
[0047] The materials for preparing the first isolation layer, the second isolation layer, the third isolation layer, the fourth isolation layer, the fifth isolation layer, the sixth isolation layer and the seventh isolation layer include: at least one of SiO2, SiN, SiNO and SiCO; and / or
[0048] The material for preparing the gate isolation layer includes: at least one of Al2O3, HfO2, HfAlO and HfZrO;
[0049] The material for preparing the metal layer includes: at least one of W, Ta, Mo, TiN, TaN, Au and Pt;
[0050] The material for preparing the active layer includes at least one of IGZO, Si, SiGe, Ge, GaN, GaAs and InP.
[0051] Compared with the prior art, the present invention has at least the following beneficial effects:
[0052] The thin film transistor provided in the embodiment of the present application includes a substrate layer, a source, a drain, a gate, an active layer and a gate isolation layer. A second groove is formed on the substrate layer, at least a portion of the gate is arranged in the second groove, and the gate is connected to the side of the gate isolation layer away from the active layer. Based on this, the thin film transistor provided in the embodiment of the present application effectively shortens the channel and forms a groove-shaped gate, a narrow groove three-dimensional channel device, thereby improving the on-state current density of the device without increasing the horizontal area (foot print) of the device, and improving the conduction current and storage density. BRIEF DESCRIPTION OF THE DRAWINGS
[0053] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:
[0054] Figure 1 A schematic structural diagram of a thin film transistor according to an embodiment of the present application at one angle;
[0055] Figure 2 A schematic structural diagram of a thin film transistor according to an embodiment of the present application from another angle;
[0056] Figure 3 A schematic flowchart of a method for preparing a thin film transistor according to an embodiment of the present application;
[0057] Figure 4a A schematic structural diagram of a first processing step of a thin film transistor according to an embodiment of the present application;
[0058] Figure 4b A schematic structural diagram of a first processing step of a thin film transistor according to an embodiment of the present application;
[0059] Figure 5a A schematic structural diagram of a second processing step of a thin film transistor according to an embodiment of the present application;
[0060] Figure 5bA schematic structural diagram of a second processing step of a thin film transistor according to an embodiment of the present application;
[0061] Figure 6a A schematic structural diagram of a third processing step of a thin film transistor according to an embodiment of the present application;
[0062] Figure 6b A schematic structural diagram of a third processing step of a thin film transistor according to an embodiment of the present application;
[0063] Figure 7a A schematic structural diagram of a fourth processing step of a thin film transistor according to an embodiment of the present application;
[0064] Figure 7b A schematic structural diagram of a fourth processing step of a thin film transistor according to an embodiment of the present application;
[0065] Figure 8a A schematic structural diagram of a fifth processing step of a thin film transistor according to an embodiment of the present application;
[0066] Figure 8b A schematic structural diagram of a fifth processing step of a thin film transistor according to an embodiment of the present application;
[0067] Figure 9a A schematic structural diagram of a sixth processing step of a thin film transistor according to an embodiment of the present application;
[0068] Figure 9b A schematic structural diagram of a sixth processing step of a thin film transistor according to an embodiment of the present application;
[0069] Fig.10a A schematic structural diagram of a seventh processing step of a thin film transistor according to an embodiment of the present application;
[0070] Fig.10b A schematic structural diagram of a seventh processing step of a thin film transistor according to an embodiment of the present application;
[0071] Fig.11a A schematic structural diagram of an eighth processing step of a thin film transistor according to an embodiment of the present application;
[0072] Fig.11b A schematic structural diagram of an eighth processing step of a thin film transistor according to an embodiment of the present application;
[0073] Fig.12a A schematic structural diagram of a ninth processing step of a thin film transistor according to an embodiment of the present application;
[0074] Figure 12b A schematic structural diagram of a ninth processing step of a thin film transistor according to an embodiment of the present application;
[0075] Fig.13a A schematic structural diagram of the tenth processing step of a thin film transistor according to an embodiment of the present application;
[0076] Fig.13b A schematic structural diagram of the tenth processing step of a thin film transistor according to an embodiment of the present application;
[0077] Fig.14a A schematic structural diagram of the eleventh processing step of a thin film transistor according to an embodiment of the present application;
[0078] Fig.14b A schematic structural diagram of the eleventh processing step of a thin film transistor according to an embodiment of the present application;
[0079] Fig.15a A schematic structural diagram of the twelfth processing step of a thin film transistor according to an embodiment of the present application;
[0080] Fig.15b A schematic structural diagram of the twelfth processing step of a thin film transistor according to an embodiment of the present application;
[0081] Fig.16a A schematic structural diagram of a thirteenth processing step of a thin film transistor according to an embodiment of the present application;
[0082] Fig.16b A schematic structural diagram of a thirteenth processing step of a thin film transistor according to an embodiment of the present application;
[0083] Fig.17a A schematic structural diagram of a fourteenth processing step of a thin film transistor according to an embodiment of the present application;
[0084] Fig.17b A schematic structural diagram of a fourteenth processing step of a thin film transistor according to an embodiment of the present application;
[0085] Fig.18a A schematic structural diagram of a fifteenth processing step of a thin film transistor according to an embodiment of the present application;
[0086] Fig.18b A schematic structural diagram of a fifteenth processing step of a thin film transistor according to an embodiment of the present application;
[0087] Fig.19aA schematic structural diagram of a sixteenth processing step of a thin film transistor according to an embodiment of the present application;
[0088] Fig.19b A schematic structural diagram of a sixteenth processing step of a thin film transistor according to an embodiment of the present application;
[0089] Fig.20a A schematic structural diagram of the seventeenth processing step of a thin film transistor according to an embodiment of the present application;
[0090] Fig.20b A schematic structural diagram of the seventeenth processing step of a thin film transistor according to an embodiment of the present application;
[0091] Fig.21a A schematic structural diagram of the eighteenth processing step of a thin film transistor according to an embodiment of the present application;
[0092] Figure 21b A schematic structural diagram of the eighteenth processing step of a thin film transistor according to an embodiment of the present application;
[0093] Fig.22a A schematic structural diagram of a nineteenth processing step of a thin film transistor according to an embodiment of the present application;
[0094] Figure 22b A schematic structural diagram of a nineteenth processing step of a thin film transistor according to an embodiment of the present application;
[0095] Fig.23a A schematic structural diagram of the twentieth processing step of a thin film transistor according to an embodiment of the present application;
[0096] Figure 23b A schematic structural diagram of the twentieth processing step of a thin film transistor according to an embodiment of the present application;
[0097] Fig.24a A schematic structural diagram of the twenty-first processing step of a thin film transistor according to an embodiment of the present application;
[0098] Figure 24b A schematic structural diagram of the twenty-first processing step of a thin film transistor according to an embodiment of the present application;
[0099] Fig.25a A schematic structural diagram of the 22nd processing step of a thin film transistor according to an embodiment of the present application;
[0100] Fig.25b A schematic structural diagram of the 22nd processing step of a thin film transistor according to an embodiment of the present application;
[0101] Fig.26a A schematic structural diagram of the twenty-third processing step of a thin film transistor according to an embodiment of the present application;
[0102] Figure 26b A schematic structural diagram of the twenty-third processing step of a thin film transistor according to an embodiment of the present application;
[0103] Fig.27a A schematic structural diagram of the twenty-fourth processing step of a thin film transistor according to an embodiment of the present application;
[0104] Figure 27b A schematic structural diagram of the twenty-fourth processing step of a thin film transistor according to an embodiment of the present application;
[0105] Fig.28a A schematic structural diagram of the twenty-fifth processing step of a thin film transistor according to an embodiment of the present application;
[0106] Fig.28b A schematic structural diagram of the twenty-fifth processing step of a thin film transistor according to an embodiment of the present application.
[0107] in, Figure 1 , Figure 2 and Figures 4a to 28b The corresponding relationship between the reference numerals and the component names is as follows:
[0108] 110 substrate layer, 120 source electrode, 130 drain electrode, 140 gate electrode, 150 active layer, 160 gate isolation layer;
[0109] 141 buried gate, 142 lead-out pole;
[0110] 211 first isolation layer, 212 second trench, 213 metal layer, 214 first trench, 215 first amorphous silicon layer, 216 second isolation layer, 217 second amorphous silicon layer, 218 first basic structure, 219 first side wall, 220 third isolation layer, 230 fourth isolation layer, 240 third amorphous silicon layer, 250 fifth isolation layer, 260 fourth amorphous silicon layer, 270 second basic structure, 280 second side wall, 290 sixth isolation layer, 300 seventh isolation layer. DETAILED DESCRIPTION
[0111] In order to better understand the above-mentioned technical scheme, the technical scheme of the embodiments of the present application is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present application and the specific features in the embodiments are detailed descriptions of the technical scheme of the embodiments of the present application, rather than limitations on the technical scheme of the present application. In the absence of conflict, the embodiments of the present application and the technical features in the embodiments may be combined with each other.
[0112] like Figure 1 and Figure 2 As shown, according to the first aspect of an embodiment of the present application, a thin film transistor is proposed, comprising: a substrate layer 110, a source 120, a drain 130, a gate 140, an active layer 150 and a gate isolation layer 160; wherein the gate isolation layer 160 is arranged on the substrate layer 110, the active layer 150 is arranged on the gate isolation layer 160, the source 120 and the drain 130 are arranged on the active layer 150, and a first groove 214 is formed between the source 120 and the drain 130; wherein a second groove 212 is formed on the substrate layer 110, at least a portion of the gate 140 is arranged in the second groove 212, and the gate 140 is connected to the side of the gate isolation layer 160 that is away from the active layer 150.
[0113] The thin film transistor provided in the embodiment of the present application includes a substrate layer 110, a source electrode 120, a drain electrode 130, a gate electrode 140, an active layer 150 and a gate isolation layer 160. A second groove 212 is formed on the substrate layer 110, and at least a portion of the gate electrode 140 is arranged in the second groove 212. The gate electrode 140 is connected to the side of the gate isolation layer 160 that is away from the active layer 150. Based on this, the thin film transistor provided in the embodiment of the present application effectively shortens the channel and forms a groove-shaped gate electrode 140, a narrow groove three-dimensional channel device, thereby improving the on-state current density of the device without increasing the horizontal area (foot print) of the device, and improving the conduction current and storage density.
[0114] The thin-film transistor provided in the embodiment of the present application has a channel distance between the source 120 and the drain 130 that is equal to the width of the bottom of the second trench 212. The thin-film transistor preparation method provided in the embodiment of the present application can effectively shorten the carrier channel distance, thereby reducing the on-resistance and increasing the on-current. The contact between the source, drain and channel materials is close to the side wall so that no additional horizontal area is added, which is beneficial to reducing the footprint of a single device, thereby facilitating an increase in the number of devices per unit area, thereby improving storage density.
[0115] It can be understood that by forming the first trench 214 between the source 120 and the drain 130 , the first trench 214 can play a role of separating the source 120 and the drain 130 .
[0116] It can be understood that the thin film transistor provided in the embodiment of the present application includes a source 120, a drain 130, a gate 140 and an active layer 150. The gate 140 can control the on or off of the source 120 and the drain 130, thereby realizing the function of the thin film transistor.
[0117] like Figure 1 and Figure 2 As shown, in a feasible implementation, the gate 140 includes: a buried gate 141 , which is disposed in the second trench 212 and connected to the gate isolation layer 160 ; and a lead-out electrode 142 , which is connected to the buried gate 141 and disposed on the substrate layer 110 .
[0118] In this technical solution, a structural composition of a gate 140 is further provided. The gate 140 may include a buried gate 141 and a lead-out electrode 142. By arranging the buried gate 141 in the second trench 212 so that the channel distance is equal to the width of the bottom of the second trench 212, the carrier channel distance can be effectively shortened, thereby reducing the on-resistance and increasing the on-current. The contact between the source and drain and the channel material is close to the side wall so as not to increase the additional horizontal area, which is beneficial to reducing the footprint of a single device, thereby facilitating an increase in the number of devices per unit area, thereby improving the storage density.
[0119] In this technical solution, the signal input of the gate 140 is facilitated by the provision of the lead-out electrode 142 .
[0120] like Figure 3 As shown, according to the second aspect of the embodiment of the present application, a method for preparing a thin film transistor is proposed, which is used to prepare a thin film transistor as any of the above technical solutions, and the preparation method includes:
[0121] Step 201: providing a substrate, and forming a first isolation layer on the substrate;
[0122] Step 202: etching the first isolation layer to form a second trench;
[0123] Step 203: preparing a gate through a second trench;
[0124] Step 204: Prepare a gate isolation layer and an active layer on the gate; it is understandable that HK can be grown in sequence as a gate isolation layer, a semiconductor channel material, HK is preferably Al2O3, with a thickness of 0.1 to 10 nm, preferably 2 nm, the material of the active layer can be IGZO, grown using PVD or ALD technology with a thickness of 1 to 100 nm, preferably 5 nm, and the active area is defined by lithography and etching.
[0125] Step 205: forming a metal layer on the active layer; it is understandable that metal can be grown, preferably W or Mo or TiN, and the growth method can be PVD or ALD, preferably 50nm, and conventional photolithography is used to define the source and drain regions.
[0126] Step 206: Etching the metal layer to form a first trench to obtain a source electrode and a drain electrode that are arranged at intervals.
[0127] It can be understood that the preparation method provided in the embodiment of the present application is used to prepare a thin film transistor such as any of the above technical solutions, and therefore the preparation method of the thin film transistor has all the beneficial effects of the thin film transistor of the above technical solutions.
[0128] like Figures 4a to 28b As shown, the method for preparing a thin film transistor provided in an embodiment of the present application is to etch the first isolation layer 211 to form a second groove 212, and to etch the metal layer 213 to form a first groove 214. The second groove 212 facilitates the arrangement of the gate 140, and the arrangement of the first groove 214 facilitates the separation of the source 120 and the drain 130, thereby improving the on-state current density of the device without increasing the horizontal area (foot print) of the device, and improving the conduction current and storage density.
[0129] like Fig.12a and Figure 12b As shown, in a feasible implementation manner, the step of etching the first isolation layer 211 to form the second trench 212 includes:
[0130] like Figure 4a and Figure 4b As shown, a first amorphous silicon layer 215, a second isolation layer 216 and a second amorphous silicon layer 217 are sequentially formed on the first isolation layer 211;
[0131] like Figure 5a and Figure 5b As shown, the second amorphous silicon layer 217 is etched to form a first basic structure 218 ; it is understandable that the second amorphous silicon layer can be etched by photolithography and RIE to form an amorphous pattern, stopping at the surface of the second isolation layer 216 to form the first basic structure 218 .
[0132] like Figures 5a to 8bAs shown, a first sidewall 219 is formed on the first base structure 218, and the first base structure 218 and part of the first sidewall 219 are removed, leaving part of the first sidewall 219; it is understood that another medium, such as SiN, can be conformally grown around the first base structure 218, with a thickness of 1nm to 100nm, preferably 20nm, and RIE anisotropic etching is used to form the first sidewall 219. It is understood that the first base structure 218 can be selectively removed, preferably TMAH solution. It is understood that part of the first sidewall 219 can be removed by photolithography masking and RIE selective etching.
[0133] like Figures 9a to 12b As shown, the second trench 212 is formed by using the first spacer 219 as a mask.
[0134] In this technical solution, specific steps for forming the second groove 212 are further provided. A first amorphous silicon layer 215, a second isolation layer 216 and a second amorphous silicon layer 217 are sequentially formed on the first isolation layer 211, and then the second amorphous silicon layer 217 is etched to form a first basic structure 218. Then, a second side wall 280 can be formed on the first basic structure 218, and finally, the second groove 212 can be formed by etching the second side wall 280. Such a configuration facilitates the processing of the second groove 212 without relying on a high-precision lithography machine.
[0135] In a feasible implementation manner, the step of forming the second trench 212 by using the first sidewall 219 as a mask includes:
[0136] like Figure 9a and Figure 9b As shown, the second isolation layer 216 and the first amorphous silicon layer 215 are etched with the first sidewall 219 as a mask; the first sidewall 219 and the remaining second isolation layer 216 are removed; it is understood that the pattern can be transferred to the amorphous silicon by RIE anisotropic etching, and stop on the bottom first isolation layer 211. It is understood that the first sidewall 219 can be removed by wet selective etching, preferably hot phosphoric acid 250°C.
[0137] like Fig.11a and Fig.11b As shown, the third isolation layer 220 is filled around the remaining first amorphous silicon layer 215 ; it can be understood that the first amorphous silicon layer 215 can be exposed by depositing dielectric SiO 2 and selectively etching back (BOE).
[0138] like Fig.12a and Figure 12bAs shown, the remaining first amorphous silicon layer 215 is removed to form a second trench 212 on the third isolation layer 220. It is understood that the first amorphous silicon layer 215 can be selectively removed to prepare a micro-groove structure, which is the second trench 212.
[0139] In this technical solution, specific steps for etching the second groove 212 are further provided. Such a configuration can reduce the requirements on process equipment and does not require reliance on a high-precision lithography machine, thus facilitating implementation.
[0140] In a feasible implementation manner, the step of preparing the gate 140 through the second trench 212 includes:
[0141] like Fig.13a and Fig.13b As shown, a buried gate 141 is formed in the second trench 212 ; it is understandable that the buried gate 141 can be formed by filling metal W or Mo in the second trench 212 and then performing CMP planarization.
[0142] like Fig.14a and Fig.14b As shown, a lead-out electrode 142 is formed on the substrate, and the lead-out electrode 142 is connected to the buried gate 141. It is understood that the lead-out electrode 142 can be formed laterally by sputtering metal W or Mo with a thickness of 1 nm to 1000 nm, preferably 50 nm.
[0143] In this technical solution, a method for preparing the gate 140 is further provided. A buried gate 141 is first formed in the second trench 212, and then a lead-out electrode 142 connected to the buried gate 141 is formed on the substrate. By setting the buried gate 141 in the second trench 212 so that the channel distance is equal to the width of the bottom of the second trench 212, the carrier channel distance can be effectively shortened, thereby reducing the on-resistance and increasing the on-current. The contact between the source and drain and the channel material is close to the side wall so as not to increase the additional horizontal area, which is beneficial to reducing the footprint of a single device, thereby facilitating an increase in the number of devices per unit area, thereby improving the storage density.
[0144] In a feasible implementation manner, the step of etching the metal layer 213 to form the first groove 214 to obtain the source 120 and the drain 130 arranged at intervals includes:
[0145] As 17a to Fig.17b As shown, a fourth isolation layer 230 is filled around the metal layer 213 ; a medium such as SiO 2 may be grown and planarized to form the fourth isolation layer 230 , and the top metal is exposed after planarization.
[0146] As 18a to Fig.18bAs shown, a third amorphous silicon layer 240, a fifth isolation layer 250 and a fourth amorphous silicon layer 260 are sequentially formed on the fourth isolation layer 230; it can be understood that a-Si 50nm, SiO2 5nm, a-Si50nm can be grown by PECVD to serve as the third amorphous silicon layer 240, the fifth isolation layer 250 and the fourth amorphous silicon layer 260.
[0147] As 19a to Fig.19b As shown, the fourth amorphous silicon layer 260 is etched to form a second basic structure 270 ; it is understandable that the pattern of the fourth amorphous silicon layer 260 can be defined by photolithography and RIE etching to serve as the second basic structure 270 .
[0148] As 20a to Figure 22b As shown, a second sidewall 280 is formed on the second base structure 270, and the second base structure 270 and part of the second sidewall 280 are removed, leaving part of the second sidewall 280; it is understood that another medium, such as SiN, can be conformally grown around the second base structure 270, with a thickness of 1nm to 100nm, preferably 25nm, and RIE anisotropic etching is used to form the second sidewall 280. It is understood that the second base structure 270 can be selectively removed, preferably by TMAH solution. It is understood that the second sidewall 280 can be removed by photolithography masking and RIE selective etching.
[0149] As 23a to Fig.25b As shown, the first trench 214 is formed by using the second spacer 280 as a mask.
[0150] In this technical solution, specific steps for forming the first groove 214 are further provided. First, the fourth isolation layer 230 is filled on the peripheral side of the metal layer 213, and then a third amorphous silicon layer 240, a fifth isolation layer 250 and a fourth amorphous silicon layer 260 are formed in sequence on the fourth isolation layer 230. Thereafter, a second basic structure 270 and a second side wall 280 are formed. Finally, the first groove 214 is formed using the second side wall 280. This arrangement facilitates the processing of the first groove 214 without relying on a high-precision lithography machine.
[0151] In a feasible implementation manner, the step of forming the first trench 214 by using the second sidewall 280 as a mask includes:
[0152] Such as 23a and Figure 23bAs shown, the fifth isolation layer 250 and the third amorphous silicon layer 240 are etched with the second spacer 280 as a mask; the second spacer 280 and the remaining fifth isolation layer 250 are removed; it is understood that the pattern can be transferred to the third amorphous silicon layer 240 by RIE etching, and stop on the metal. It is understood that the selective removal of the top fifth isolation layer 250 peels off the second spacer 280, leaving part of the third amorphous silicon layer 240.
[0153] Such as 25a and Fig.25b As shown, a sixth isolation layer 290 is filled around the remaining third amorphous silicon layer 240;
[0154] Such as 25a and Fig.25b As shown, the remaining third amorphous silicon layer 240 is removed to form an etched trench; it can be understood that the third amorphous silicon layer 240 can be selectively removed, preferably TMAH.
[0155] Such as 26a and Figure 26b As shown, the metal layer 213 is etched based on the etched groove to obtain the source 120 and the drain 130 arranged at intervals, and a first groove 214 is formed between the source 120 and the drain 130. It can be understood that RIE etches metal anisotropically to isolate the source and drain metals.
[0156] In this technical solution, specific steps for etching the first groove 214 are further provided. Such a configuration can reduce the requirements on process equipment and does not require reliance on high-precision photolithography machines, making it easier to implement.
[0157] In a feasible implementation, the step of obtaining the source 120 and the drain 130 arranged at intervals includes:
[0158] Such as 27a and Figure 27b As shown, a seventh isolation layer 300 is formed on the metal layer 213 ; it is understandable that a dielectric may be filled and then planarized to form the seventh isolation layer 300 .
[0159] Such as 28a and Fig.28b As shown, the seventh isolation layer 300 is etched to expose the source 120 and the drain 130. It is understood that the seventh isolation layer 300 can be opened by photolithography and RIE etching to expose the source 120 and the drain 130 lead-out electrodes.
[0160] In this technical solution, a method for preparing the source electrode 120 and the drain electrode 130 is further provided, and such a configuration can make the structure of the thin film transistor more stable.
[0161] In a feasible embodiment, the material for preparing the first isolation layer 211, the second isolation layer 216, the third isolation layer 220, the fourth isolation layer 230, the fifth isolation layer 250, the sixth isolation layer 290 and the seventh isolation layer 300 includes: at least one of SiO2, SiN, SiNO and SiCO; and / or the material for preparing the gate isolation layer 160 includes: at least one of Al2O3, HfO2, HfAlO and HfZrO; the material for preparing the metal layer 213 includes: at least one of W, Ta, Mo, TiN, TaN, Au and Pt; the material for preparing the active layer 150 includes at least one of IGZO, Si, SiGe, Ge, GaN, GaAs and InP.
[0162] In this technical solution, materials for preparing the first isolation layer 211, the second isolation layer 216, the third isolation layer 220, the fourth isolation layer 230, the fifth isolation layer 250, the sixth isolation layer 290 and the seventh isolation layer 300, the gate isolation layer 160, the metal layer 213 and the active layer 150 are further provided. Such a configuration facilitates the material acquisition of thin film transistors, can reduce the cost of thin film transistors, and improve the performance of thin film transistors.
[0163] In the present invention, the terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance; the term "plurality" refers to two or more, unless otherwise clearly defined. The terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; "connected" can be a direct connection or an indirect connection through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0164] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by terms such as “upper”, “lower”, “left”, “right”, “front” and “back” are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or unit referred to must have a specific direction, be constructed and operated in a specific orientation, and therefore, cannot be understood as a limitation on the present invention.
[0165] In the description of this specification, the description of the terms "one embodiment", "some embodiments", "specific embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.
[0166] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A thin film transistor, characterized in that: include: Substrate layer, source, drain, gate, active layer and gate isolation layer; Wherein, the gate isolation layer is arranged on the substrate layer, the active layer is arranged on the gate isolation layer, the source electrode and the drain electrode are arranged on the active layer, and a first trench is formed between the source electrode and the drain electrode; A second trench is formed on the substrate layer, at least a portion of the gate is disposed in the second trench, and the gate is connected to a side of the gate isolation layer away from the active layer.
2. The thin film transistor according to claim 1, characterized in that: The gate comprises: a buried gate, the buried gate being disposed in the second trench and connected to the gate isolation layer; A lead-out electrode is connected to the buried gate and is disposed on the substrate layer.
3. A method for preparing a thin film transistor, characterized in that: For preparing the thin film transistor according to claim 1 or 2, the preparation method comprises: Providing a substrate, and forming a first isolation layer on the substrate; Etching the first isolation layer to form a second trench; preparing the gate through the second trench; Preparing a gate isolation layer and an active layer on the gate; forming a metal layer on the active layer; The metal layer is etched to form the first groove to obtain the source electrode and the drain electrode arranged at intervals.
4. The preparation method according to claim 3, characterized in that: The step of etching the first isolation layer to form a second trench comprises: forming a first amorphous silicon layer, a second isolation layer, and a second amorphous silicon layer in sequence on the first isolation layer; Etching the second amorphous silicon layer to form a first basic structure; forming a first sidewall on the first basic structure, removing the first basic structure and a portion of the first sidewall, and retaining a portion of the first sidewall; The second trench is formed by using the first sidewall as a mask.
5. The preparation method according to claim 4, characterized in that: The step of forming the second trench by using the first sidewall as a mask comprises: Using the first sidewall spacer as a mask, etching the second isolation layer and the first amorphous silicon layer; removing the first sidewall spacer and the remaining second isolation layer; Filling a third isolation layer around the remaining first amorphous silicon layer; The remaining first amorphous silicon layer is removed to form the second trench on the third isolation layer.
6. The preparation method according to claim 3, characterized in that: The step of preparing the gate through the second trench comprises: forming a buried gate in the second trench; A lead-out electrode is formed on the substrate, and the lead-out electrode is connected to the buried gate.
7. The preparation method according to claim 3, characterized in that: The step of etching the metal layer to form the first groove to obtain the source and the drain arranged at intervals comprises: Filling a fourth isolation layer around the metal layer; forming a third amorphous silicon layer, a fifth isolation layer and a fourth amorphous silicon layer in sequence on the fourth isolation layer; Etching the fourth amorphous silicon layer to form a second basic structure; forming a second sidewall on the second base structure, removing the second base structure and a portion of the second sidewall, and retaining a portion of the second sidewall; The first trench is formed by using the second sidewall as a mask.
8. The preparation method according to claim 7, characterized in that: The step of forming the first trench by using the second sidewall as a mask comprises: Using the second sidewall spacer as a mask, etching the fifth isolation layer and the third amorphous silicon layer; removing the second sidewall spacer and the remaining fifth isolation layer; Filling a sixth isolation layer around the remaining third amorphous silicon layer; removing the remaining third amorphous silicon layer to form an etching groove; The metal layer is etched based on the etched groove to obtain the source electrode and the drain electrode arranged at intervals, and the first groove is formed between the source electrode and the drain electrode.
9. The preparation method according to claim 8, characterized in that: The step of obtaining the source and the drain arranged at intervals comprises: forming a seventh isolation layer on the metal layer; The seventh isolation layer is etched to expose the source and the drain.
10. The preparation method according to any one of claims 3 to 9, characterized in that: The materials for preparing the first isolation layer, the second isolation layer, the third isolation layer, the fourth isolation layer, the fifth isolation layer, the sixth isolation layer and the seventh isolation layer include: at least one of SiO2, SiN, SiNO and SiCO; and / or The material for preparing the gate isolation layer includes: at least one of Al2O3, HfO2, HfAlO and HfZrO; The material for preparing the metal layer includes: at least one of W, Ta, Mo, TiN, TaN, Au and Pt; The material for preparing the active layer includes at least one of IGZO, Si, SiGe, Ge, GaN, GaAs and InP.