Method for producing a bottom oxide
By depositing polysilicon, oxides and nitrides on the SiC substrate and forming spacers by dry etching, the problems of uneven oxidation rate and high process complexity when producing thick bottom oxide structures on the SiC substrate are solved, and high quality and manufacturable TBO structure production is achieved.
Patent Information
- Application Number
- CN202411458130.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-24
- Filing Date
- 2024-10-18
- Publication Date
- 2025-04-25
AI Technical Summary
When producing thick bottom oxide (TBO) structures on SiC substrates, the prior art faces problems of uneven oxidation rates, high process complexity and lithography resolution limitations, resulting in insufficient production quality and manufacturability.
By depositing the selection sequence of polycrystalline silicon, oxides and nitrides, and combined with dry etching of the nitride layer, a spacer is formed to prevent side wall oxidation and promote oxidation of the substrate surface and bottom, thereby forming a thick bottom oxide. This method combines the self-alignment process of LOCOS technology to simplify the lithography process of TBO structure.
It realizes efficient production of thick bottom oxides on SiC substrates, solves the problems of uneven oxidation rates and high process complexity, improves production quality and manufacturability, and reduces the requirements of lithography resolution and adjustment accuracy through self-alignment processes.
Smart Images
Figure CN119894064A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the invention relate to a method for producing a (thick) bottom oxide. Further embodiments relate to the resulting product. In general, embodiments of the invention belong to the field of MOSFET transistors or trench MOSFET transistors. Preferred embodiments relate to a process for producing a gate oxide in a trench MOSFET (metal-oxide semiconductor field effect transistor), which is a silicon carbide-based (SiC) power semiconductor component. Background Art
[0002] SiC-based trench MOSFETs have the potential to reduce on-resistance, which is mainly attributed to the higher cell density without the JFET region. In addition, trench MOSFETs may have improved channel mobility on the trench side, especially when compared with planar MOSFETs. This feature leads to high cell integration density, thereby reducing chip area and ultimately reducing unit cost.
[0003] In embodiments of the present invention, it has been recognized that the gate oxide plays an important role in determining the channel mobility along the trench sidewalls. This is strongly exposed to the electric field at the bottom of the trench, so it has been recognized that optimization needs to be performed here.
[0004] In the prior art, there are several methods to improve the properties and manufacturability of gate oxides.
[0005] To address the problem of premature gate oxide breakdown, different extended shielding configurations have been proposed. Among these configurations, the TBO (thick bottom oxide) structure is promising. This approach involves inserting a gate trench with a thick oxide layer on the bottom of the trench, effectively increasing the electric field strength of the gate oxide layer.
[0006] The prior art for making TBO gate oxide in silicon (Si) is local oxidation of silicon (LOCOS), in which Si is locally oxidized during thermal oxidation of the substrate by using an oxidation-resistant mask, typically silicon nitride (Si3N4). After forming the TBO on the bottom of the trench and removing the mask, the trench sidewalls can be equally oxidized (US2020243679A1, 2020).
[0007] Due to the dependence of the plane direction on the oxidation rate, it is more difficult to produce TBO in SiC trench structures on SiC because the oxidation rate of the trench sidewalls is higher. One approach is to use a similar LOCOS method, in which during the thermal oxidation of the SiC substrate, the trench sidewalls are covered with a thin oxide layer and a Si3N4 mask so that only the bottom and the terrace of the trench are oxidized. After removing the mask by wet etching, the thin oxide layer remains on the trench sidewalls, while a thick oxide has been formed on the terrace and bottom of the trench, which can be oxidized again to form the gate oxide (US5915180A, 1990). Here, due to the higher oxidation rate, the difference in thickness of the bottom oxide and the sidewall oxide depends on the expected thickness of the sidewall oxide.
[0008] Another method of forming TBO in the gate trench is to fill the trench by oxide deposition and then perform an etch-back process so that the SiC mesa is exposed. Afterwards, the gate oxide can be formed by thermal oxidation or CVD process (US2018366569A1, 2018). In this method, the selectivity must be sufficient in the oxide etch-back process to prevent etching into the SiC substrate. Summary of the invention
[0009] As indicated above, the prior art has several disadvantages, the recognition of which forms part of the subject matter of the present invention.
[0010] Starting from the perceived disadvantages, it is an object of the present invention to provide a concept for producing a bottom oxide, in particular for semiconductor devices such as MOSFETs or trench MOSFETs, which offers a better compromise between production quality and manufacturability.
[0011] This object is achieved by the subject-matter of the independent claims.
[0012] An embodiment of the present invention provides a method for producing a (thick) bottom oxide in a trench structure (e.g., a trench structure of a semiconductor substrate). The method comprises the following steps:
[0013] - providing a substrate having at least one trench structure or a plurality of trenches, wherein the at least one trench structure comprises a bottom and sidewalls;
[0014] - depositing a polysilicon layer on the surface, bottom and sidewalls of the substrate;
[0015] - depositing an oxide layer, for example a silicon dioxide layer, on the polysilicon layer, i.e. for example along the bottom and the side walls;
[0016] - depositing a nitride layer, for example silicon nitride (Si3N4), on the oxide layer, i.e., for example again along the bottom and the side walls;
[0017] - Anisotropic dry etching of the nitride layer;
[0018] - initiating thermal oxidation of the polysilicon and polysilicon layers to locally produce a thick oxide layer;
[0019] - For example, isotropic wet etching of nitride layers, oxide layers and polysilicon on the sidewalls in trench structures;
[0020] - Depositing a further oxide layer on the remaining oxide at least along the bottom and the surface, or depositing a further oxide layer on the remaining oxide along the bottom and the surface and on the side walls.
[0021] According to some embodiments, the substrate may be a substrate made of a silicon material such as silicon carbide (SiC).
[0022] Embodiments of the invention are based on the discovery that, according to the embodiment, by the selective sequence of depositing polysilicon, oxide and nitride, in combination with the dry etching of the nitride through the nitride layer, so-called spacers are formed along the side walls. In the subsequent oxidation step, the spacers prevent oxidation of the polysilicon along the side walls. Thus, oxidation of the substrate surface and the substrate bottom is promoted, thereby forming a thick bottom oxide, for example with a protrusion. During the subsequent isotropic etching (wet etching) of the trench structure, the oxide layer is also etched back, but most importantly, the exposure of the side walls is achieved, so that in the last elementary step of depositing a further oxide layer, a thin oxide layer is formed on the side walls and a thick oxide layer is formed on the bottom (thick oxide layer thus produced). This is a self-aligned process.
[0023] The proposed solution is based on simplifying the lithographic aspects of the TBO (bottom oxide) structure by implementing a self-aligned process using LOCOS technology. Using this self-aligned method, the TBO structure can be developed without limitations in terms of lithographic resolution and adjustment accuracy. The use of this self-aligned process is a compensating measure for the increased technological complexity required to produce a stable TBO structure.
[0024] According to some embodiments, during dry etching, the nitride of the nitride layer on the bottom and the surface is removed, so that, for example, the oxide of the oxide layer on the bottom and the surface is exposed during dry etching. Due to the anisotropy of the dry etching process, a spacer consisting of the nitride of the nitride layer is formed along the sidewall by the nitride that remains there and is not etched. According to some embodiments, the nitride or spacer protects the exposed oxide and the polysilicon below from oxidation in the subsequent oxidation process. According to some embodiments, oxidation occurs at the exposed bottom and the exposed surface. This means that according to further embodiments, oxidation does not occur along the sidewall and / or oxidation does not occur in the area of the spacer consisting of the nitride of the nitride layer along the sidewall. For example, oxidation can be triggered at a temperature that allows oxidation of polysilicon without causing oxidation of the substrate material (e.g., silicon carbide). According to some embodiments, during the oxidation process, polysilicon can be combined with oxide to form a thick oxide region at the bottom and / or surface.
[0025] In a subsequent isotropic etch (wet etch), the spacer consisting of nitride is removed along the sidewalls. According to some embodiments, a portion of the oxide layer and / or polysilicon layer may also be removed, such as a portion previously covered by the nitride layer of the spacer. According to some embodiments, the oxide layer at the bottom and / or the surface may also be etched back. According to some embodiments, the wet etch is characterized by a high selectivity to polysilicon and / or nitride. According to some embodiments, the wet etch may also be performed so that a buffered etch process is used to remove the oxide along the sidewalls. According to a preferred embodiment, the wet etch process is performed in several wet etch steps.
[0026] There is an additional advantage to producing the gate oxide layer on the trench sidewalls, which is independent of whether the oxide is deposited or thermally grown. In other common manufacturing processes for TBO structures, the application of thermal oxide can be challenging due to the large oxide thickness only at the bottom of the trench. When using thermal oxidation, a very thin oxide layer is produced on the SiC mesas while trying to achieve the required oxide thickness on the trench sidewalls. This is because the oxidation rate of the SiC trench sidewalls is significantly higher compared to the SiC mesas. By using a self-aligned process to produce a thick oxide layer at the bottom of the trench and on the SiC mesas, an oxide layer with the desired properties can be provided by either deposition or thermal oxidation.
[0027] According to some embodiments, LPCVD techniques may be used for depositing the oxide layer and / or for depositing the nitride layer. This is advantageous because the sidewalls in the trench structure are also uniformly coated in this way.
[0028] According to some embodiments, the method can be extended by introducing a gate also in a trench structure, ie a trench structure with a thick bottom oxide, after applying a further oxide layer (according to some embodiments, this can again be done by LPCVD).
[0029] Further embodiments relate to a semiconductor device, in particular a MOSFET or trench MOSFET having a thick oxide produced by the above method. According to one embodiment, the semiconductor device comprises a SiC substrate having one or more trenches and oxidized polysilicon at the bottom of the one or more trenches and at the surface of the substrate. The semiconductor device may include one or more trench MOSFETs arranged in the one or more trenches. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Embodiments of the present invention will be explained below with reference to the accompanying drawings, in which:
[0031] Figure 1 shows a schematic flow chart of a basic method for producing a (deep) trench according to an embodiment;
[0032] 2a-d are schematic diagrams showing various process steps for producing a semiconductor device having a trench structure according to an embodiment;
[0033] 3a-c show schematic diagrams of intermediate products for producing semiconductor devices according to embodiments. DETAILED DESCRIPTION
[0034] Before the embodiments of the present invention will be described with reference to the accompanying drawings, it should be noted that the same components and structures are denoted by the same reference numerals so that their descriptions may be mutually applicable or interchangeable.
[0035] Figure 1 A method 100 is shown for producing a semiconductor device 10 as shown in Figures 2a-d and 3a-c. The method 100 shows basic steps, wherein optional steps are shown as dashed boxes in the flow chart.
[0036] In an initial step, a substrate 12 is provided having at least one trench structure, but preferably a plurality of trenches 14. This step is marked with reference numeral 110. In this step 110, optional steps of processing the substrate 10 may be performed first, for example by etching the trenches 14 or by growing a SiC layer 12s. These steps are not shown.
[0037] As shown in FIG. 2a, substrate 12 includes at least one trench structure 14 having sidewalls 14s and a bottom 14b. The surface of the substrate is marked with reference numeral 12o. Polysilicon layer 16 is deposited on surface 12o, sidewalls 14s and bottom 14b. Figure 114b. In the figure of FIG. 14, the deposition is indicated by reference number 120. According to some embodiments, the deposition can be performed by LPCVD. After this step, a step of depositing an oxide layer 18 on the polysilicon layer 16 is performed. This step has the reference number 130. In a subsequent step, a nitride layer 20 is deposited on the oxide layer 18. As shown in reference FIG. 2a, the oxide layer 18 (e.g., silicon dioxide (SiO2)) and / or the nitride layer 20 (e.g., silicon nitride (Si3N4)) is deposited so that the sheet extends along the surface 12o, the sidewalls 14s and the bottom 14b. According to some embodiments, this can also be referred to as full-surface deposition at least in a local area of the trench 14. After the step 140 of depositing the nitride layer 20, the individual areas are opened again. This is achieved by dry etching in step 150. Due to the dry etching, the nitride layer 20 is removed in the area of the bottom 14b and also on the surface 12o, wherein the nitride or silicon nitride of the sheet 20 is retained along the sidewalls 14s. The so-called spacer has the reference number 24. Spacers 24 cover the oxide layer 18 and the polysilicon layer 16 along the sidewalls 14s.
[0038] In a subsequent step, oxidation takes place. This is triggered, for example, by a corresponding temperature. During the oxidation, the polysilicon 16 of the polysilicon layer is oxidized. This step has the reference number 160 and is shown in FIG. 2 c. By oxidation, silicon dioxide is formed in the region of the surface 12 o and on the bottom 14 b, thereby forming a thick oxide bottom 28 b and a corresponding surface 28 o. The bottom 28 b may include a protrusion in the region of the spacer 24. By means of the spacer 24, oxidation of the polysilicon 16 along the sidewalls 14 s and connection with the oxide 18 along the sidewalls 14 s do not occur.
[0039] In the subsequent step 170, at least the spacer 24 is removed, but according to some embodiments, the polysilicon 16 and the oxide 18 in the region of the sidewall 14s are also removed. This step is marked with reference number 170 in the flow chart and may have multiple wet etching sub-steps. In particular, due to the high selectivity, the nitride of the spacer 24 and the polysilicon 16 can be easily removed, while the wet chemical removal of the oxide 18 between the elements 16 and 24 in the region of the sidewall 14s is based on the precise control of the wet etching process. For example, a BOE (buffered oxide etching) process can be used. During the wet etching 170, parts of the regions 28o and 28b can also be removed, for example, the surfaces of the regions 28o and 28b are removed. However, due to the previous oxidation in step 160, the regions 28o and 28b become thicker, leaving residual oxide.
[0040] Starting from this prerequisite, a further oxide layer can then be produced in step 180. This is achieved, for example, by LPCVD, so that the sidewalls 14s exposed in the previous step are covered with oxide again. As a result, the oxide layer in the regions 28o and 28b becomes thicker, while the layer thickness in these regions along the sidewalls 14s decreases. The result is shown in FIG. 2d. The layer produced by LPCVD along the sidewalls 14s is also referred to as a TEOS layer.
[0041] The method for producing a TBO (thick bottom oxide) structure will be explained below with reference to Figures 2a to 2d. Figures 2a-2d show a semiconductor device as an intermediate product, which is marked as 10* in steps 2a to 2c and as a final intermediate product 10 in Figure 2d. As mentioned above, after the state 10 of Figure 2d, further processing in one or more steps may also be performed.
[0042] The semiconductor device 10* or 10 comprises one or more trench structures 14 introduced into a substrate 12. The substrate 12 is, for example, a silicon substrate, or in particular a silicon carbide (SiC) substrate, so that a SiC trench MOSFET can be produced by the production method. Due to the method steps, in particular the deposition of the spacer 24 and the subsequent wet etching, the resulting wall region 30s (see FIG. 2d ) as well as the thick bottom region 28b and the thick surface region 28o are self-aligned. In this respect, this is a self-aligned process, which includes the LOCOS technology (LOCOS=local oxidation of silicon). The LOCOS process is commonly used for isolation in CMOS production in order to produce individual regions on a silicon substrate.
[0043] 2a-d show step-by-step the production process of a gate oxide 30s having a TBO structure 28b. As shown in FIG2a, the process starts with the preparation of an n-type epitaxial 4H-SiC wafer 12, followed by trench structuring (see trench structure 14). First, a layer of polysilicon 16 is deposited, and then a thin oxide layer 18 is added. A thin layer 20 consisting of silicon nitride (Si3N4) is then deposited using LPCVD technology. The thin oxide layer 18 serves as an indicator for endpoint detection during dry etching (see 150) of the nitride layer 20. For example, the nitride layer 20 is anisotropically etched to form the spacer 24 shown in FIG2b. In a subsequent step (FIG2c), the polysilicon 16 is oxidized at a specific temperature (see 160), which is selected to promote oxidation of the polysilicon 16 while avoiding oxidation of the SiC 12. The exposed areas consisting of polysilicon that are not covered by the nitride mask 24 undergo oxidation 160, similar to the process used in LOCOS. This results in the formation of thick oxide layers 28b and 28o on the mesas and the bottom of the trench. Due to the presence of the nitride mask 24 (which acts as a barrier), the polysilicon at the trench sidewall 14s remains laterally unoxidized. Finally, the layers at the trench sidewall 24s (including the nitride (spacer) layer 24, the TEOS layer 18s, and the polysilicon layer 16) are completely removed, leaving a blank space at the trench sidewall 14s. Since the trench geometry of the trench 14 is not suitable for anisotropic dry etching, an isotropic etching technique (see 170) is used to remove the material at the trench sidewall 14s. The removal process 170 includes several wet etching steps to remove the layers of Si3N4 24, SiO2 18s, and polysilicon 16. The main challenge is to etch the SiO2 18s at the trench sidewall 14s. While over-etching of Si3N4 24 and polysilicon 16 can be tolerated due to their high selectivity, etching of the oxide layer 18 requires careful control to prevent unnecessary over-removal of the oxide layer at the mesa and trench bottom. A cautious approach is required when using a BOE (buffered oxide etch) process to remove the thin TEOS layer, which is assumed to exist between the spacer and polysilicon layers at the trench sidewalls. After complete removal of the layers at the trench sidewalls, a TEOS layer is deposited using LPCVD technology to create the gate oxide (see Figure 2d).
[0044] 3a, 3b and 3c show the steps of forming a spacer by dry etching 150, triggering oxidation according to step 160 and forming a thick oxide after deposition 180 via microscope images, wherein the microscope images are images of cross-sectional analysis using a focused ion beam (FIB). FIG. 3a shows the spacer 24 and the polysilicon 16 at the bottom and surface 12o. The remaining part of the oxide layer 18 is also shown here. Then, FIG. 3b shows the oxidation in the area of the surface 12o (see reference number 28o) and at the bottom (see reference number 28b). It can be seen that even after oxidation, the polysilicon 16 remains in the area of the sidewall 14s.
[0045] FIG3c shows the state after the spacer 24, the polysilicon 16 and the oxide 18 have been removed along the trench sidewalls 14s. It can be seen that the oxide regions 28o and 28b remain in the trench 14. It can also be seen from the figure that a plurality of adjacent trenches can be manufactured simultaneously. The state shown in FIG2d or 3c represents an intermediate product, from which further steps for manufacturing a SiC trench MOSFET can be carried out. For example, in a subsequent step, a gate region can be formed in the trench 14. Then, after a further isotropic or anisotropic etching process or thinning process, a source or drain region can be optionally formed on the surface.
[0046] Although embodiments of the present invention are described with particular reference to production methods, other embodiments relate to products produced with corresponding production methods, such as trench MOSFETs. The semiconductor product produced in this way is characterized in that it has a thick bottom oxide, and in particular the oxide region is uniformly formed along the sidewalls 14s of the gate oxide and the thickness is reduced. The background here is a self-aligned process using a spacer and a corresponding oxidation and wet etching process. Therefore, the advantage of the product is that the process parameters, in particular the thickness / size of the gate oxide, can be optimally controlled here. The quality of the oxide is different from that of existing products. Here, polysilicon is oxidized (instead of SiC), and in addition, in the last oxidation step (producing gate oxide), thermal oxidation and deposition / LPCVD can be applied in principle. According to some embodiments, the semiconductor product includes SiC as a substrate and oxidized polysilicon located at the bottom 14b and the terrace / surface 12o.
[0047] Even though embodiments of the invention are described with reference to production methods, it should be noted that a description of a corresponding method step is equivalent to a description of a corresponding feature. Conversely, it should be understood that these aspects also represent a description of a corresponding method, and thus, a block or component of an apparatus should also be understood as a corresponding method step or a feature of a method step. Similarly, aspects associated with or described as a method step also represent a description of a corresponding block or detail or feature of a corresponding apparatus.
Claims
1. A method (100) for producing a (thick) bottom oxide (28b) in a trench structure (14), the method (100) comprising the following steps: Providing (110) a substrate (12) having at least one trench structure (14), wherein the trench structure (14) includes a bottom (14b) and a sidewall (14s); Depositing (120) a polysilicon layer (16) on the surface (12o), the bottom (14b) and the sidewall (14s) of the substrate (12); depositing (130) an oxide layer (18) on the polysilicon layer (16); depositing (140) a nitride layer (20) on the oxide layer (18); performing anisotropic dry etching (150) on the nitride layer (20); thermally oxidizing (160) the polysilicon of the polysilicon layer (16) to locally produce a thick oxide layer; Wet etching; A further oxide layer (18) is deposited (180) on the thick oxide layer at least along the bottom (14b) and the surface (12o), or a further oxide layer (18) is deposited (180) on the thick oxide layer along the bottom (14b) and the surface (12o) and on the sidewalls (14s).
2. The method (100) according to claim 1, wherein during the dry etching (150), spacers (24) consisting of the nitride of the nitride layer (20) are retained and / or formed along the sidewalls (14s).
3. The method (100) according to claim 1, wherein the nitride of the nitride layer (20) on the bottom (14b) and the surface (12o) is removed during the dry etching (150), and / or wherein the oxide of the oxide layer (18) on the bottom (14b) and the surface (12o) is exposed during the dry etching (150).
4. The method (100) of claim 1, wherein oxidation of the bottom portion (14b) and the exposed surface (12o) exposed by the nitride occurs during oxidation (160).
5. The method (100) of claim 1, wherein during the oxidation (160) no oxidation occurs along the sidewalls and / or no oxidation occurs in the region of the spacers (24) consisting of the nitride of the nitride layer (20) along the sidewalls.
6. The method (100) of claim 1, wherein the polysilicon combines with the oxide during oxidation (160) to form thick oxide regions at the bottom (14b) and / or the surface (12o); and / or wherein triggering the oxidation (160) occurs at a temperature that allows oxidation of the polysilicon without causing oxidation of the material of the substrate (12).
7. The method (100) of claim 1, wherein a spacer (24) consisting of nitride of the nitride layer (20) is removed along the sidewalls during the wet etching; and / or During the wet etching, a portion of the oxide layer (18) and / or a portion of the polysilicon layer (16) is removed.
8. The method (100) of claim 1, wherein the wet etching is performed with high selectivity; and / or wherein a buffered etching process is performed during the wet etching to remove the oxide along the sidewalls; and / or The wet etching includes multiple wet etching processes.
9. The method (100) according to claim 1, wherein depositing the further oxide layer (18) and / or depositing the nitride layer (20) is performed by means of a LPCVD technique.
10. The method (100) of claim 1, wherein the oxide comprises silicon dioxide and / or SiO2.
11. The method (100) according to claim 1, wherein the substrate (12) comprises a silicon material and / or a silicon carbide material and / or SiC.
12. The method (100) of claim 1, wherein the nitride comprises silicon nitride and / or Si3N4.
13. The method (100) according to claim 1, wherein the method (100) comprises the step of forming a gate in the trench structure (14) having the bottom oxide (28b).
14. A semiconductor device, in particular a MOSFET or a trench MOSFET with a thick oxide produced by a method (100) according to claim 1.
15. A semiconductor device, in particular a MOSFET or trench MOSFET with thick oxide, wherein the semiconductor device comprises a SiC substrate with one or more trenches (14) and oxidized polysilicon located at the bottom (14b) of the one or more trenches (14) and at the surface (12o) of the substrate (12). 16 . The semiconductor device according to claim 14 , comprising one or more trench MOSFETs arranged in the one or more trenches.