Multi-capacitor gate structure, preparation method and application thereof

Abstract

The invention provides a multi-capacitor gate structure which sequentially comprises a first gate dielectric layer, a first metal layer, a second gate dielectric layer and a second metal layer. The second metal layer is connected with a power or circuit output end. According to the invention, the capacitor is connected in series above the first metal layer, so that the input capacitance is reduced without influencing the direct current conduction of the first metal layer, thereby improving the data transmission rate of the device, reducing the parasitic capacitance of the whole device, and improving the linear characteristic of the device; and particularly, when the metal oxide semiconductor field effect transistor is applied to a high-frequency metal oxide semiconductor field effect transistor, the high-voltage anti-breakdown capability is enhanced due to more gate capacitor structures, so that the anti-surge or transient breakdown characteristic of the gate of the device is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor device technology, and specifically relates to a multi-capacitor gate structure and a manufacturing method thereof, and describes its application in fields such as communications. Background Art

[0002] Semiconductor devices with gate structures, such as metal oxide field effect transistors, are widely used in the field of communications, such as 5G radio frequency communications, 6G radio frequency communications, and quantum communications. These communication scenarios have high requirements for data transmission speed, efficiency, stability, and fidelity. However, the gate parasitic parameters caused by the process will increase the signal transmission delay, resulting in limited data transmission rate, such as high-speed 5G and even higher-speed communication scenarios in the future, reducing the signal transmission speed; secondly, it may cause distortion such as waveform distortion, making it difficult for the receiving end to accurately restore the original signal, affecting the communication quality; thirdly, it is easy to cause unstable phenomena such as circuit self-oscillation, interfere with the processing and transmission of normal communication signals, increase the bit error rate, and is not conducive to reliable communication; finally, additional parasitic parameters will bring unnecessary power loss, which will shorten the battery life of communication equipment (such as mobile terminals) with strict requirements on power consumption.

[0003] Taking Si-based N-channel metal oxide field effect transistor (N-MOSFET) as an example, due to the use of ion implantation and high-temperature annealing to form the source and drain regions, the ion diffusion process and process fluctuations lead to parasitic capacitance formed by the gate and the source and drain. The uncertain parasitic capacitance value leads to reduced linearity of the device under high-frequency conditions. The use of complex process integration and optimization, such as adjusting the gate and source and drain photolithography overlap, optimizing the relevant ion implantation doping concentration and dosage, etc., puts forward high requirements on the working conditions of the machine and the coordination of various processes. In particular, in the process of process coordination, more wafer taping processes will be consumed to determine the optimal conditions, consuming more manpower, material resources and time costs. Even so, it is difficult to meet the linearity requirements by directly using core components to form a circuit structure.

[0004] Advanced power amplifier technologies such as power modulation, inverting modulation or Doherty can be used to improve the linearity and efficiency of the amplifier. However, these technologies are often considered expensive solutions because they require additional components such as power modulators or baseband processors, which require the addition of a DC power supply or consume additional area. But it is undeniable that reducing the parasitic parameters of core devices can fundamentally reduce linear challenges. If we can bypass the existing complex process integration and optimization and directly innovate the device structure, it will be of great significance to the overall optimization effect of the device and time cost control. Summary of the invention

[0005] The present application proposes a multi-capacitor gate structure, which greatly reduces the parasitic parameters caused by the gate.

[0006] The present application adopts the following technical solution: a multi-capacitor gate structure, which includes a first gate dielectric layer, a first metal layer, a second gate dielectric layer, and a second metal layer in sequence; the second metal layer is connected to a power supply or a circuit output terminal; the first metal layer, the second gate dielectric layer, and the second metal layer constitute a capacitor. The present invention connects a capacitor in series above the first metal layer, so that the input capacitance is reduced without affecting the DC conduction of the first metal layer.

[0007] The multi-capacitor gate structure is basically applicable to any semiconductor device that requires a gate, including but not limited to silicon-based metal oxide semiconductor (MOSFET), and also includes lateral diffused metal oxide semiconductor (LDMOS), drain extended metal oxide semiconductor (DEMOS), silicon carbide metal oxide semiconductor (SiC MOSFET), etc. Due to the reduction of input capacitance, the data transmission rate of the device can be effectively improved, the parasitic capacitance of the entire device is reduced, and the linear characteristics of the device are improved; further, due to the device having more gate capacitance structures, the anti-breakthrough capability for high voltage is enhanced, thereby improving the device gate surge or instantaneous breakdown characteristics.

[0008] This multi-capacitor gate structure is basically suitable for any application scenario that requires reducing gate parasitic parameters, including but not limited to 5G RF communication, 6G RF communication, quantum communication, etc.

[0009] The present invention also provides a method for preparing the multi-capacitor gate structure, which at least comprises: forming the first gate dielectric layer, the first metal layer, the second gate dielectric layer, and the second metal layer in sequence by deposition. The above preparation process has good compatibility with the traditional metal oxide semiconductor field effect transistor preparation process, and mass production can be achieved with less adjustment of the existing process.

[0010] The present invention also relates to a high-frequency metal oxide semiconductor field effect transistor, which includes the above-mentioned multi-capacitor gate structure. In the high-frequency state, the second metal layer, the second gate dielectric layer and the first metal layer form a smaller capacitor, which is connected in series with the metal oxide semiconductor capacitor, so that the input capacitance is reduced, the data transmission rate of the device is significantly improved, and the adverse effect of the gate parasitic capacitance on the linearity of the power amplifier is reduced.

[0011] In the embodiment of the present invention, in order to balance the contradictory relationship between improving linearity and reducing power efficiency and construct a reasonable capacitance value, the area of ​​the second gate dielectric layer and the second metal layer should be between 0.5 and 1.5 times the area of ​​the first metal layer. In the manufacturing method provided in the embodiment of the present invention, two photolithography plates are used to etch the first gate dielectric layer 2, the first metal layer 3 and the second gate dielectric layer 4 so that they meet the aforementioned area ratio, which can greatly reduce the manufacturing cost caused by adding photolithography plates.

[0012] In the embodiment of the present invention, in order to balance the conflicting relationship between improving linearity and reducing power efficiency and construct a reasonable capacitance value, the thickness of the second gate dielectric layer should be between 0.5 and 1.5 times that of the first gate dielectric layer.

[0013] As is common knowledge in the art, the gate dielectric layer of the present invention can be oxide, nitride or high-K insulating dielectric, which can be obtained by chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, etc., and the deposition temperature generally does not exceed 900 degrees Celsius.

[0014] The beneficial effects of the present invention are as follows: the present invention does not change the DC conduction mode of the device, and under high-frequency conditions, the input capacitance is reduced, thereby improving the data transmission rate of the device; secondly, the parasitic capacitance is reduced to improve the linear characteristics of the device; thirdly, since the device has more gate capacitance structures, the high voltage breakdown resistance is enhanced, thereby improving the device gate surge or transient breakdown resistance characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of the cross-sectional structure of a conventional metal oxide semiconductor field effect transistor device;

[0016] Figure 2 A schematic cross-sectional view of a multi-capacitor gate structure according to an embodiment of the present application;

[0017] Figure 3 A schematic cross-sectional view of a metal oxide semiconductor field effect transistor including a multi-capacitor gate structure according to an embodiment of the present application;

[0018] Figure 4 A small signal schematic diagram of a metal oxide semiconductor field effect transistor including a multi-capacitor gate structure according to an embodiment of the present application;

[0019] Figure 5 A schematic diagram of a process for preparing a metal oxide semiconductor field effect transistor according to the present application;

[0020] Figure 6 A schematic diagram of a process for preparing a metal oxide semiconductor field effect transistor according to the present application;

[0021] Figure 7 A schematic diagram of a process for preparing a metal oxide semiconductor field effect transistor according to the present application;

[0022] Figure 8 A schematic diagram of a process for preparing a metal oxide semiconductor field effect transistor according to the present application;

[0023] Fig. 9A schematic diagram of a process for preparing a metal oxide semiconductor field effect transistor according to the present application;

[0024] Fig.10 A schematic diagram of a process for preparing a metal oxide semiconductor field effect transistor according to the present application;

[0025] Fig.11 This is a schematic diagram of a process of manufacturing a metal oxide semiconductor field effect transistor according to the present application.

[0026] The reference numerals are:

[0027] 1. Source; 2. First gate dielectric layer; 3. First metal layer; 4. Second gate dielectric layer; 5. Gate sidewall; 6. Second metal layer; 7. Drain; 8. Substrate electrode; 9. Source region; 10. Lightly doped drain region; 11. Drain region; 12. Substrate heavily doped region; 13. Substrate. DETAILED DESCRIPTION

[0028] In the description of the present application, it should be understood that the orientations or positional relationships indicated by terms such as “top”, “above”, “extended position”, “upper surface”, etc. are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0029] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0030] In this application, unless otherwise clearly specified and limited, the terms "through", "connected" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0031] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0032] The power amplifier (PA) is one of the most critical RF chips and is considered to be one of the most critical components in a wireless transceiver. Its performance usually determines the overall linearity and energy efficiency of the system composed of various RF chips in the entire wireless transmitter. In order to achieve high data rates, some high-order complex modulation schemes, such as quadrature amplitude modulation (QAM), are used to improve the high peak-to-average power ratio (PAPR) and broadband of the power amplifier. These complex modulation schemes used in these standards require a high degree of linear amplification to maintain signal integrity. In addition, the power amplifier must operate in a power back-off state to accommodate the high signal peak-to-average power ratio.

[0033] CMOS technology is widely used in various RF chip power amplifiers due to its many advantages such as high integration, low cost, low leakage current, good thermal conductivity, and high design flexibility. Si-based N-channel metal oxide field effect transistor (N-MOSFET) is a core device constructed by CMOS technology. Due to the use of ion implantation and high-temperature annealing to form the source and drain regions, the ion diffusion process and process fluctuations lead to parasitic capacitance formed by the gate and the source and drain. The uncertain parasitic capacitance value leads to reduced linearity of the device under high-frequency conditions. The use of complex process integration and optimization, such as adjusting the gate and source and drain lithography overlap, related ion implantation doping concentration and dosage, etc., puts forward high requirements on the working conditions of the machine and the coordination of various processes. In particular, in the process of process coordination, more tape-out processes will be consumed to determine the optimal conditions, consuming more manpower, material resources and time costs. Even so, it is difficult to meet the linearity requirements by directly using core devices to form a circuit structure.

[0034] Advanced PA techniques such as power supply modulation, inverting modulation or Doherty can be used to improve amplifier linearity and efficiency. However, these techniques are often considered expensive solutions because they require additional components such as power supply modulators or baseband processors, which require adding a DC supply or consume additional area.

[0035] However, it is undeniable that reducing the parasitic parameters of core devices can fundamentally reduce linear challenges. If we can bypass the existing complex process integration and optimization and directly innovate the device structure, it will be of great significance to the overall optimization effect of the device and the control of time cost.

[0036] The present invention aims to propose a multi-capacitor gate structure, which can be applied to Si-based MOSFET, which sequentially comprises a first gate dielectric layer 2, a first metal layer 3, a second gate dielectric layer 4, and a second metal layer 6; the second metal layer 6 is connected to a power supply or a circuit output terminal; the first metal layer 3, the second gate dielectric layer 4, and the second metal layer 6 constitute a capacitor (hereinafter referred to as an additional capacitor). Figure 4As shown, the capacitor is connected in series with the native metal oxide semiconductor capacitor to form a multi-capacitor gate structure. Without affecting the DC conduction of the first metal layer 3, in a high-frequency state, it is connected in series with the native metal oxide semiconductor capacitor, so that the total input capacitance is reduced, thereby improving the data transmission rate of the device, reducing the parasitic capacitance of the entire device, and improving the linear characteristics of the device; further, since the device has more gate capacitor structures, the high voltage resistance is enhanced, thereby improving the device gate surge or instantaneous breakdown characteristics.

[0037] according to Figure 4 The principle shown is that the smaller the additional capacitance is, the smaller the parasitic capacitance formed in series with the native capacitance will be, which effectively improves the linear characteristics. In some application scenarios, such as the gate of a power amplifier, if the additional capacitance is too small, it will affect the amplification efficiency of the device. Generally, when the additional capacitance is 0.5~1.5 times the native capacitance, the amplification efficiency and linear characteristics of the power amplifier will be effectively guaranteed.

[0038] Those skilled in the art can adjust the size of the additional capacitance by setting the thickness, area, dielectric constant, etc. of the second gate dielectric layer 4. Generally, the larger the area, the smaller the thickness, and the higher the dielectric constant, the larger the additional capacitance.

[0039] Alternatively, those skilled in the art may determine the parameters of the second gate dielectric layer 4 according to the following formula.

[0040] C=

[0041] r is the relative dielectric constant, k is the electrostatic force constant, S is the area facing the two plates, and d is the distance between the two plates.

[0042] refer to Figure 3 In the gate structure shown, the material of the substrate 13 is silicon, and may also be silicon carbide, silicon germanium, a multi-component semiconductor material composed of III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). The multi-component semiconductor material composed of III-V elements includes InP, GaAs, InAs, InSb, InGaAs or InGaAsP.

[0043] The material of the first gate dielectric layer 2 is silicon oxide, and may also be a high dielectric constant gate dielectric layer material such as silicon nitride and hafnium oxide. Through testing, the native capacitance is 0.67 pF.

[0044] The second gate dielectric layer 4 and the second metal layer 6 are further constructed on the first metal layer 3. The material used for the second gate dielectric layer is silicon oxide, and it can also be a high dielectric constant gate dielectric layer material such as silicon nitride and hafnium oxide. The thickness is 0.5-1 times that of the first gate dielectric layer, and the area is the same as that of the first gate dielectric layer. The material used for the second metal layer 6 is tungsten, and there is no requirement for thickness, and the area is the same as that of the first metal layer. In this embodiment, the additional capacitance used is 1pF. Since the additional capacitance is connected in series with the native capacitance, the total capacitance obtained is 0.4 times that of the native capacitance, thereby reducing the influence of the native capacitance. The above-mentioned equivalent structure is applied to the common source amplifier and the stable feedback network and input-output network matching are performed, and the third-order intermodulation parameters and power growth efficiency of the power amplifier obtained are improved, breaking the traditional design contradiction between the two. Moreover, the device implementation is easier to implement and has lower cost than the circuit implementation because a simple process change is made in the existing machine.

[0045] like Figure 3 As shown, according to one aspect of an embodiment of the present application, an N-MOSFET is provided, including:

[0046] A substrate 13; a heavily doped substrate region 12 located at the top of the substrate; a substrate electrode 8 located above the heavily doped substrate region; a source region 9 and a drain region 11 located at the top of the substrate; a source electrode 1 and a drain electrode 7 located above the source region; a lightly doped drain region 10 located at an extended position of the source region and the drain region; a first gate dielectric layer 2 located above the lightly doped drain region; a first metal layer 3 located above the first gate dielectric layer; a second gate dielectric layer 4 located above the first metal layer; a gate sidewall 5 located around the first gate; a second metal layer 6 located above the second gate dielectric layer; wherein one end of the second metal layer is connected to the second gate dielectric layer, and the other end is connected to the back-end interconnect metal.

[0047] In an N-MOSFET provided in an embodiment of the present invention, a capacitor similar to a metal oxide semiconductor capacitor is connected in series above a first metal layer, such as Figure 4 As shown, in the high frequency state, it is connected in series with the metal oxide semiconductor capacitor to form a smaller capacitor, which reduces the input capacitance and thus improves the data transmission rate of the device; secondly, it reduces the influence of parasitic capacitance on the entire device and improves the linear characteristics of the device.

[0048] Wherein, the N-MOSFET includes a substrate 13, and the substrate 13 can be silicon, silicon carbide, silicon germanium, a multi-element semiconductor material composed of III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Wherein, the multi-element semiconductor material composed of III-V elements includes InP, GaAs, InAs, InSb, InGaAs or InGaAsP. Specifically, in the embodiment of the present application, the substrate 13 is a P-type silicon substrate.

[0049] The area of ​​the second gate dielectric layer is between 0.5 and 1.5 times the area of ​​the first metal layer. The area of ​​the second metal layer is between 0.5 and 1.5 times the area of ​​the first metal layer.

[0050] Wherein, the thickness of the second gate dielectric layer is between 0.5 and 1.5 times of the first gate dielectric layer.

[0051] Another aspect of the present application embodiment is shown in Figures 5 to 11 As shown, a manufacturing method is provided, and the N-MOSFET manufactured by this method has small gate parasitic parameters in the radio frequency scenario, so that the linearity of the circuit composed of the device is improved. In addition, the device constructed by the above preparation process has a higher gate capacitance structure, and its high voltage resistance is enhanced, thereby improving the device gate surge resistance or transient breakdown characteristics; finally, the above preparation process is compatible with the traditional metal oxide semiconductor field effect transistor preparation process, and basically no special adjustment of the existing process is required to achieve mass production. Unless otherwise specified, the processes such as ion implantation, thin film deposition, etching, photolithography, thermal oxidation and high temperature annealing in this application can adopt existing processes, which will not be repeated here.

[0052] join Figure 5-Figure 11 , the manufacturing method comprises:

[0053] Step S101: forming a first gate dielectric layer 2 on the substrate 13, see Figure 5 A thermal oxidation process may be used to form a first gate dielectric layer 2 on a P-type substrate 13, with a gate thickness of 10-120 Å.

[0054] Step S201: A first metal layer 3 is obtained by thin film deposition and growth on the first gate dielectric layer 2. Figure 6 Wherein, the thickness of the first metal layer is 50-600A.

[0055] Step S301: A second gate dielectric layer 4 is formed on the first metal layer 3 by thin film deposition and growth. Figure 7 .

[0056] Step S401: etching the first gate dielectric layer 2, the first metal layer 3 and the second gate dielectric layer 4 simultaneously. Figure 8 .

[0057] Step S501: Etching the second gate dielectric layer 4, see Fig. 9 .

[0058] Step S601: forming a lightly doped drain region 10 near the first gate 3 by ion implantation, and forming a gate sidewall 5 by thermal oxidation, see Fig.10.

[0059] Step S701: forming a source region, a drain region and a heavily doped region of the substrate by ion implantation, see Fig.11 Specifically, the source region and the drain region are implanted with N-type ions, and the heavily doped region of the substrate is implanted with P-type ions.

[0060] Step S801: forming a second metal layer 6, a source electrode 1, a drain electrode 7 and a substrate electrode 8 by dry etching and thin film deposition, see Figure 3 One end of the second metal layer is connected to the second gate, and the other end is connected to the back-end interconnection metal.

[0061] The above is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application. The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and variations can be made without departing from the technical principles of the present application, and these improvements and variations should also be regarded as the protection scope of the present application.

Claims

1. A multi-capacitor gate structure, characterized in that: It includes a first gate dielectric layer, a first metal layer, a second gate dielectric layer, and a second metal layer in sequence; the second metal layer is connected to a power source or a circuit output terminal.

2. The multi-capacitor gate structure according to claim 1, characterized in that: The first metal layer, the second gate dielectric layer and the second metal layer form a capacitor.

3. The method for preparing a multi-capacitor gate structure according to claim 1, wherein: The first gate dielectric layer, the first metal layer, the second gate dielectric layer and the second metal layer are sequentially formed by deposition.

4. The preparation method according to claim 3, characterized in that: The deposition method is chemical vapor deposition, atomic layer deposition or molecular beam epitaxy.

5. The preparation method according to claim 3, characterized in that: The second gate dielectric layer may be oxide, nitride or high-K insulating dielectric.

6. The preparation method according to claim 3, characterized in that: The deposition temperature of the second gate dielectric layer should not exceed 900 degrees Celsius.

7. A semiconductor device, characterized in that: The gate of the device has the multi-capacitor gate structure as claimed in claim 1.

8. Application of the multi-capacitor gate structure of claim 1 as a high-frequency metal oxide semiconductor field effect transistor gate.

9. The use according to claim 4, characterized in that: The areas of the second gate dielectric layer and the second metal layer should be between 0.5 and 1.5 times the area of ​​the first metal layer.

10. The use according to claim 4, characterized in that: The thickness of the second gate dielectric layer should be between 0.5 and 1.5 times that of the first gate dielectric layer.

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