Method for manufacturing electronic device

Abstract

The invention provides a manufacturing method of an electronic device. The manufacturing method comprises the following steps: forming a sacrificial layer on a substrate; forming a semiconductor structure on the sacrificial layer; separating the semiconductor structure from the substrate; detecting defects of the substrate; and classifying the substrate.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing an electronic device. Background Art

[0002] The manufacturing cost of existing electronic devices (such as electronic devices including light emitting diodes) is very high. Therefore, how to reduce the manufacturing cost of electronic devices has become one of the problems that researchers are eager to solve. Summary of the invention

[0003] The present disclosure provides a method for manufacturing an electronic device, which helps to reduce manufacturing costs.

[0004] According to an embodiment of the present disclosure, a method for manufacturing an electronic device includes: forming a sacrificial layer on a substrate; forming a semiconductor structure on the sacrificial layer; separating the semiconductor structure from the substrate; detecting defects of the substrate; and classifying the substrate.

[0005] According to an embodiment of the present disclosure, a method for manufacturing an electronic device includes: forming a semiconductor structure on a recycled substrate; separating the semiconductor structure from the recycled substrate; performing a product inspection on the semiconductor structure; and performing a recycling inspection on the recycled substrate.

[0006] In order to make the above features and advantages of the present disclosure more obvious and understandable, embodiments are given below with reference to the accompanying drawings for detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A as well as Figure 1B is a block diagram of a method for manufacturing an electronic device according to some embodiments of the present disclosure;

[0008] Figure 2 , Figure 3 , Figure 4 as well as Figure 5 are cross-sectional schematic diagrams respectively showing four examples of forming a sacrificial layer on a substrate;

[0009] Figure 6 , Figure 7 as well as Figure 8 are cross-sectional schematic diagrams respectively showing three examples of forming a semiconductor structure on a sacrificial layer;

[0010] Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 as well as Fig.19 are schematic diagrams respectively showing eight examples of separating a semiconductor structure from a substrate;

[0011] FIG. 16A to FIG. 16C is a cross-sectional schematic diagram showing the laser cutting process;

[0012] Fig.17 is a cross-sectional schematic diagram showing laser cutting using an alignment pattern;

[0013] Fig.18 is a schematic cross-sectional view showing laser cutting using a ruler;

[0014] Fig. 20 is a schematic diagram showing the removal of a sacrificial layer or impurities remaining on a substrate;

[0015] Fig.21 is a schematic diagram showing defects and cracks of a detection substrate;

[0016] Fig. 22 is a schematic cross-sectional view showing the reduction in size of a substrate in the presence of defects;

[0017] Fig.23 is a schematic cross-sectional view showing the reduction in size of a substrate in the presence of a crack;

[0018] Fig.24 is a schematic diagram showing chemical mechanical polishing of a substrate;

[0019] Fig.25 is a schematic diagram showing the thickness of a detection substrate;

[0020] Fig.26 is a schematic diagram showing the surface roughness of a detection substrate;

[0021] Fig. 27 is a schematic diagram showing wet chemical cleaning of a substrate;

[0022] Fig.28 is a schematic diagram showing classification of substrates according to their thickness;

[0023] Fig.29A as well as Fig.29B is a block diagram of a method for manufacturing an electronic device according to other embodiments of the present disclosure;

[0024] Fig.30 is a schematic diagram showing chemical mechanical polishing of a buffer layer;

[0025] Fig.31 is a schematic diagram showing the thickness of a buffer layer on a detection substrate;

[0026] Fig.32 is a schematic diagram showing the detection of the surface roughness of the buffer layer on the substrate;

[0027] Fig.33is a schematic diagram showing classification of substrates according to the thickness of the substrate and the surface roughness of a buffer layer on the substrate;

[0028] Fig.34 is a block diagram of a method for manufacturing an electronic device according to some other embodiments of the present disclosure. DETAILED DESCRIPTION

[0029] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0030] Certain words are used throughout the present disclosure and in the appended claims to refer to specific components. It should be understood by those skilled in the art that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following description and claims, the words "including" and "comprising" are open-ended words and should therefore be interpreted as "including but not limited to..."

[0031] Directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are only with reference to the directions of the accompanying drawings. Therefore, the directional terms used are for illustration and not for limiting the present disclosure. In the accompanying drawings, each figure shows the general characteristics of the methods, structures and / or materials used in a particular embodiment. However, these drawings should not be interpreted as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative size, thickness and position of each film layer, region and / or structure may be reduced or enlarged.

[0032] It should be understood that relative terms, such as "lower" or "bottom" or "upper" or "top", may be used in various embodiments to describe the relative relationship of one element of the drawings to another element. It is understood that if the device in the drawings is turned upside down, the element described on the "lower" side will become the element on the "upper" side. The embodiments of the present disclosure can be understood in conjunction with the drawings, and the drawings of the present disclosure are also considered part of the disclosure.

[0033] A structure (or layer, element, substrate) described in the present disclosure is located on / above another structure (or layer, element, substrate), which may refer to the two structures being adjacent and directly connected, or it may refer to the two structures being adjacent but not directly connected. Indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate element, intermediate substrate, intermediate interval) between the two structures, the lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be composed of a single-layer or multi-layer physical structure or a non-physical structure, without limitation. In the present disclosure, when a certain structure is disposed "on" another structure, it may refer to that the certain structure is "directly" on the other structure, or that the certain structure is "indirectly" on the other structure, that is, at least one structure is sandwiched between the certain structure and the other structure.

[0034] The terms "approximately", "substantially" or "substantially" are generally interpreted as within 10% of a given value or range, or as within 5%, 3%, 2%, 1% or 0.5% of a given value or range. In addition, the phrases "a range is from a first value to a second value", "a range is between a first value and a second value" indicate that the range includes the first value, the second value and other values ​​therebetween.

[0035] The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify the elements. They do not imply or represent any previous ordinal numbers of the element (or elements), nor do they represent the order of one element and another element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make the element with a certain name clearly distinguishable from another element with the same name. The claims and the specification may not use the same words. Accordingly, the first component in the specification may be the second component in the claim.

[0036] The electrical connection or coupling described in the present disclosure may refer to direct connection or indirect connection. In the case of direct connection, the endpoints of the components on the two circuits are directly connected or connected to each other by a conductor segment, and in the case of indirect connection, there is a switch, diode, capacitor, inductor, resistor, other suitable components, or a combination of the above components between the endpoints of the components on the two circuits, but it is not limited to these.

[0037] In the present disclosure, the thickness, length and width can be measured by using an optical microscope (OM), and the thickness or width can be measured by a cross-sectional image in an electron microscope, but it is not limited thereto. In addition, any two values ​​or directions used for comparison may have a certain error. In addition, the term "a given range is from a first value to a second value", "a given range falls within the range from a first value to a second value" or "a given range is between a first value and a second value" means that the given range includes the first value, the second value and other values ​​therebetween. If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0038] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art to which the present disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

[0039] In the present disclosure, the electronic device may include a power device, a semiconductor packaging device, a display device, a backlight device, an antenna device, a packaging device, a sensing device or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The display device may be a non-self-luminous display device or a self-luminous display device. The display device may, for example, include liquid crystal, light-emitting diode, fluorescence, phosphor, quantum dot (quantum dot, QD), other suitable display media or a combination of the foregoing. The antenna device may, for example, include a reconfigurable surface (Reconfigurable Intelligent Surface, RIS), a frequency selective surface (Frequency Selective Surface, FSS), a radio frequency filter (RF-Filter), a polarizer (Polarizer), a resonator (Resonator) or an antenna (Antenna), etc. The antenna may be a liquid crystal type antenna or a varactor diode (Varactor Diodes) antenna. The sensing device may be a sensing device that senses capacitance, light, heat energy or ultrasound, but is not limited thereto. In the present disclosure, an electronic device may include an electronic component, and the electronic component may include a passive component and an active component, such as a known good die (KGD), a capacitor, a resistor, an inductor, a diode, a transistor, a varactor diode, a variable capacitor, a filter, a noise canceller, a sensor, a micro-electromechanical system component (MEMS), a liquid crystal chip, a biosensor chip, a structure of a semiconductor-related process, or a structure of a semiconductor-related process disposed on a substrate (such as polyimide, glass, a silicon substrate, a circuit board or other suitable substrate material), but not limited thereto. A diode may include a light-emitting diode, a varactor diode or a photodiode. A light-emitting diode may include, for example, an organic light-emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro light-emitting diode (micro LED), a sub-micro light-emitting diode (sub-micro LED), a nano-rod LED or a quantum dot light-emitting diode (quantum dot LED), but not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any combination of the aforementioned, but is not limited thereto.The packaging device may be a packaging device suitable for wafer-level packaging (WLP) technology or panel-level packaging (PLP) technology, such as a chip first process or a chip last (RDL first) process. In addition, the appearance of the electronic device may be rectangular, circular, polygonal, a shape with curved edges or other suitable shapes. The electronic device may have peripheral systems such as a drive system, a control system, a light source system, etc. to support a display device, an antenna device, a wearable device (for example, including augmented reality or virtual reality), a vehicle-mounted device (for example, including a car windshield), or a splicing device. The following embodiments illustrate some implementation forms of electronic devices with packaging devices as examples, but are not limited to this. According to the embodiments of the present disclosure, the manufacturing method of the provided electronic device can be applied, for example, to a wafer-level packaging process (WLP) or a panel-level packaging process (PLP), and a chip first process or a chip last / RDL first process can be adopted, which will be further described in detail below. According to the embodiments of the present disclosure, the packaging structure of the electronic device may include a system on chip (SoC), a system in package (SiP), an antenna in package (AiP) or a combination thereof, but is not limited thereto.

[0040] Figure 1A as well as Figure 1B is a block diagram of a method for manufacturing an electronic device according to some embodiments of the present disclosure. Figure 2 , Figure 3 , Figure 4 as well as Figure 5 2 are cross-sectional schematic diagrams respectively showing four examples of forming a sacrificial layer on a substrate. Figure 6 , Figure 7 as well as Figure 8 2 are cross-sectional schematic diagrams respectively showing three examples of forming a semiconductor structure on a sacrificial layer. Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 as well as Fig.19 Schematic diagrams showing eight examples of separating a semiconductor structure from a substrate. FIG. 16A to FIG. 16C Schematic cross-section diagram showing the laser cutting process. Fig.17 2 is a schematic cross-sectional view showing laser cutting using an alignment pattern. Fig.18is a schematic cross-sectional view showing laser cutting using a ruler. Fig. 20 is a schematic diagram showing the removal of a sacrificial layer or impurities remaining on a substrate. Fig.21 It is a schematic diagram showing the detection of defects and cracks in a substrate. Fig. 22 is a schematic cross-sectional view showing the reduction in size of a substrate in the presence of defects. Fig.23 is a schematic cross-sectional view showing the reduction in size of a substrate in the presence of a crack. Fig.24 is a schematic diagram showing chemical mechanical polishing of a substrate. Fig.25 Schematic diagram showing the thickness of the detection substrate. Fig.26 Schematic diagram showing the detection of the surface roughness of a substrate. Fig. 27 is a schematic diagram showing wet chemical cleaning of a substrate. Fig.28 is a schematic diagram showing classification of substrates according to their thickness. Fig.29A as well as Fig.29B is a block diagram of a method for manufacturing an electronic device according to other embodiments of the present disclosure. Fig.30 is a schematic diagram showing chemical mechanical polishing of a buffer layer. Fig.31 Schematic diagram showing the thickness of the buffer layer on the detection substrate. Fig.32 Schematic diagram showing the detection of the surface roughness of the buffer layer on the substrate. Fig.33 Schematic diagram showing classification of substrates according to the thickness of the substrate and the surface roughness of a buffer layer on the substrate. Fig.34 is a block diagram of a method for manufacturing an electronic device according to some other embodiments of the present disclosure. It should be noted that the following embodiments can replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. The features of each embodiment can be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

[0041] According to some embodiments of the present disclosure, a method for manufacturing an electronic device may include: forming a sacrificial layer 12 (see Figure 1A Step S10; Figures 2 to 4 ); forming a semiconductor structure 14 on the sacrificial layer 12 (refer to Figure 1A Step S12; Figures 6 to 8 ); Separate the semiconductor structure 14 from the substrate 10 (refer to Figure 1A Step S14; Figures 9 to 19 ); Detecting defects of substrate 10 (refer to Figure 1A Step S18; Fig.21 ); and classifying the substrate 10 (refer to Figure 1B Step S32; Fig.28 or Fig.32), but not limited thereto. According to different requirements, the manufacturing method of the electronic device may also selectively include other steps, such as Figure 1A as well as Figure 1B In other embodiments, the method for manufacturing an electronic device may omit the steps shown in FIG. Figure 1A as well as Figure 1B One or more steps shown may be supplemented with one or more steps not shown.

[0042] In detail, Figure 1A As shown in step S10, the manufacturing method of the electronic device may include forming a sacrificial layer 12 on a substrate 10. The substrate 10 can be used to support a film layer formed thereon. In some embodiments, the substrate 10 can be a silicon substrate, such as a silicon (111) substrate, but is not limited thereto. Compared to using a sapphire substrate, using a silicon substrate as a growth substrate for the semiconductor structure 14 helps to reduce process costs, but the present disclosure is not limited thereto. In other embodiments, the substrate 10 can be a sapphire substrate or other types of substrates, and the process costs can be reduced by recycling and reusing the substrate.

[0043] The sacrificial layer 12 may be used to relieve stress caused by lattice constant mismatch and / or thermal expansion coefficient mismatch, provide defect barrier, enhance mechanical strength, enhance adhesion and / or assist in separation of the semiconductor structure 14 and the substrate 10. In some embodiments, as Figures 2 to 5 As shown, the sacrificial layer 12 may include a buffer layer 122, a peeling layer 120, or a combination thereof. Figure 2 , Figure 4 or Figure 5 For example, the sacrificial layer 12 may include a peeling layer 120 and a buffer layer 122. The material of the peeling layer 120 may include aluminum gallium nitride, graphene, a combination of graphene and aluminum oxide, indium gallium nitride, aluminum indium gallium nitride, aluminum indium gallium arsenide, silicon carbide, other suitable organic materials or other suitable inorganic materials or other suitable metal oxides. The material of the buffer layer 122 may include N-type gallium nitride, graphene, aluminum nitride, silicon dioxide, aluminum oxide, other suitable organic materials or other suitable inorganic materials. On the other hand, as Figure 4 As shown, the sacrificial layer 12 may include the buffer layer 122 and may not include the peeling layer 120. Alternatively, although not shown, the sacrificial layer 12 may include the peeling layer 120 and may not include the buffer layer 122.

[0044] In some embodiments, Figure 2 or Figure 5 As shown, the peeling layer 120 and the buffer layer 122 can be sequentially formed on the substrate 10. In other embodiments, such as Figure 3 As shown, the buffer layer 122 and the peeling layer 120 may be sequentially formed on the substrate 10. Alternatively, as Figure 5 As shown, the substrate 10 may be a silicon substrate, and the method for manufacturing an electronic device may further include: after forming a sacrificial layer 12 on the silicon substrate, cutting the silicon substrate into thin substrates. The method for cutting the silicon substrate may include wire cutting, but is not limited thereto. Figure 5 In the structure of , the sacrificial layer 12 is not limited to the peeling layer 120 and the buffer layer 122 formed sequentially on the substrate 10. Alternatively, Figure 5 The positions of the peeling layer 120 and the buffer layer 122 may be interchanged, or one of the peeling layer 120 and the buffer layer 122 may be omitted.

[0045] like Figure 1A As shown in step S12 , the method for manufacturing an electronic device may further include forming a semiconductor structure 14 on the sacrificial layer 12 . Figures 6 to 8 Shown respectively in Figure 2 (or Figure 5 ), Figure 3 as well as Figure 4 A semiconductor structure 14 is formed on the sacrificial layer 12, and a bonding layer 16 and a carrier 18 are successively formed on the semiconductor structure 14. In some embodiments, the semiconductor structure 14 may include a diode structure, for example, a light emitting diode structure. For example, the semiconductor structure 14 may include a first-type semiconductor layer, an active layer, and a second-type semiconductor layer sequentially formed on the sacrificial layer 12, but is not limited thereto. In some embodiments, the first-type semiconductor layer includes an N-type gallium nitride layer, the active layer may be a multi-quantum well layer and include multiple layers of indium gallium nitride and multiple layers of gallium nitride alternately stacked layers, and the second-type semiconductor layer may include a P-type gallium nitride layer, but is not limited thereto. In other embodiments, the first-type semiconductor layer and the second-type semiconductor layer may be a P-type semiconductor layer and an N-type semiconductor layer, respectively, and the materials or component ratios of the first-type semiconductor layer, the active layer, and the second-type semiconductor layer may be changed according to actual needs.

[0046] The bonding layer 16 may be used to bond the substrate 18 to the semiconductor structure 14. In some embodiments, the material of the bonding layer 16 may include solder, gold-indium alloy (Au / In), aluminum (Al), copper (Cu), tin-copper compound (Cu6Sn5, Cu3Sn, Cu3Sn4), tin-nickel compound (Ni6Sn5, Ni3Sn, Ni3Sn4), tin-copper-nickel compound (Cu 1-x Ni x )6Sn5、(Cu 1-y Ni y )3Sn、(Cu 1-z Ni z)3Sn4) or other suitable conductive bonding materials, wherein 0.01≤x≤0.8, 0.01≤y≤0.8 and 0.1≤z≤0.8. The carrier 18 may include a silicon substrate, such as a silicon (100) substrate, but is not limited thereto.

[0047] like Figure 1A As shown in step S14, the method for manufacturing an electronic device may further include separating the semiconductor structure 14 from the substrate 10. In some embodiments, Fig. 9 and Fig.10 As shown, the method of separating the semiconductor structure 14 from the substrate 10 may include removing the peeling layer 120 by photoelectric chemical etching (PEC etching). Specifically, the structure formed above may be immersed in a chemical solution CS and irradiated with a light beam B to remove the peeling layer 120, thereby separating the semiconductor structure 14 from the substrate 10. In some embodiments, as Fig. 9 and Fig.10 As shown, the material of the buffer layer 122 may be different from the material of the stripping layer 120, so that after the photoelectrochemical etching step, the buffer layer 122 is retained. Alternatively, although not shown, the material of the buffer layer 122 may be the same as the material of the stripping layer 120, so that after the photoelectrochemical etching step, the buffer layer 122 is removed together.

[0048] The composition of the chemical solution CS and the wavelength and energy of the light beam B may be determined according to the film material to be removed (e.g., the material of the peeling layer 120). For example, the composition of the chemical solution CS may include a combination of potassium hydroxide (KOH) and water, or a combination of nitric acid (HNO3), hydrofluoric acid (HF), and acetic acid (CH3COOH), but is not limited thereto. In addition, the light beam B may be a laser beam. When the wavelength of the light beam B is 463 nm, the energy of the light beam B at room temperature is, for example, approximately 180 kW / cm 2 Up to 230kW / cm 2 , and when the wavelength of the light beam B is 475 nm, the energy of the light beam B at room temperature is, for example, about 330 kW / cm 2 Up to 390kW / cm 2 , but it is not limited to this.

[0049] In some embodiments, Fig.11 and Fig.12As shown, the method for separating the semiconductor structure 14 from the substrate 10 may further include removing the peeling layer 120 with an infrared laser IRL. Specifically, the peeling layer 120 may be irradiated with the infrared laser IRL from the side where the substrate 10 is located. An infrared laser IRL that can penetrate the substrate 10 may be selected so that the infrared laser IRL penetrates the substrate 10 and focuses on the peeling layer 120. The energy generated by the infrared laser IRL focusing on the peeling layer 120 is used to melt the peeling layer 120, thereby separating the semiconductor structure 14 from the substrate 10.

[0050] In some embodiments, Fig.13 , Fig.14 as well as FIG. 16A to FIG. 16C As shown, the method for separating the semiconductor structure 14 from the substrate 10 may further include cutting the peeling layer 120 with a laser LS. Specifically, the laser LS may include a carbon dioxide laser or other types of lasers suitable for laser cutting, and the laser LS may be along the Fig.13 or Fig.14 The cutting line CL shown cuts off the peeling layer 120. In some embodiments, as shown in FIG. Fig.16A As shown, when the peeling layer 120 is cut by laser LS, the thickness T120 of the peeling layer 120 may be greater than 1 mm to increase the cutting margin or reduce the damage of the laser LS to the adjacent film layers.

[0051] In some embodiments, FIG. 16A to FIG. 16C As shown, in the process of cutting the peeling layer 120 with the laser LS, the laser LS forms a cutting mark CT from the opposite side edges (e.g., the first side edge SW1 and the second side edge SW2) of the peeling layer 120, and in the process of the cutting mark CT extending from the opposite side edges (e.g., the first side edge SW1 and the second side edge SW2) to the center C of the peeling layer 120, the energy of the laser LS may be high, low, and high in sequence. For example, the energy of the laser LS at the cutting mark CT adjacent to the opposite side edges (e.g., the first side edge SW1 and the second side edge SW2) and the center C may be greater than the energy of the laser LS at the cutting mark CT located between the first side edge SW1 (or the second side edge SW2) and the center C. For ease of identification, FIG. 16A to FIG. 16C In the figure, a thick arrow indicates a laser with high energy, and a thin arrow indicates a laser with low energy. When the cutting mark CT extends to between the first side SW1 (or the second side SW2) and the center C, by lowering the energy of the laser LS, the damage of the laser LS to the film layer adjacent to the peeling layer 120 can be reduced. In addition, when the cutting mark CT extends to the center C, by increasing the energy of the laser LS, the peeling layer 120 can be effectively cut off, reducing the probability of the peeling layer 120 sticking or failing to be completely cut off.

[0052] In some embodiments, Fig.17 as well as Fig.18 As shown, with laser LS (refer to FIG. 16A to FIG. 16C ) Cutting the peeling layer 120 may include aligning the cutting position with an alignment pattern AL, confirming the thickness (thickness of the layer to be cut) with a ruler VK, or a combination thereof. The alignment pattern AL is, for example, a hole or a metal mark formed in the layer to be cut. For example, the alignment pattern AL may be a hole or a metal mark located on the sidewall surface of the peeling layer 120, but is not limited thereto. According to different requirements, the alignment pattern AL may be formed in one or more of the above-mentioned film layers.

[0053] In some embodiments, Fig.15 As shown, the method for separating the semiconductor structure 14 and the substrate 10 may further include using a laser LS (see FIG. 16A to FIG. 16C ) to cut the interface between the buffer layer 122 and the substrate 10. For example, in a structure where the sacrificial layer 12 does not include the peeling layer 120, a laser LS (refer to FIG. 16A to FIG. 16C ) cuts the interface between the buffer layer 122 and the substrate 10 to separate the semiconductor structure 14 from the substrate 10. FIG. 16A to FIG. 16C ) When cutting the interface between the buffer layer 122 and the substrate 10, the thickness T122 of the buffer layer 122 may be greater than 1 mm to increase the cutting margin or reduce the damage of the laser LS to the adjacent film layer. FIG. 16A to FIG. 16C ) The interface between the cutting buffer layer 122 and the substrate 10 may also include an alignment pattern AL (see Fig.17 ) to align the cutting position and use the ruler VK (see Fig.18 ) to confirm the thickness (such as thickness T122) or the above combination. In addition, when cutting the buffer layer 122, the cutting mark CT (refer to FIG. 16A to FIG. 16C and its corresponding description) to adjust the energy of the laser LS.

[0054] In some embodiments, Fig.19 As shown, the method for separating the semiconductor structure 14 from the substrate 10 may also include separating the semiconductor structure 14 from the peeling layer 120 using a thermal release tape (TRT). For example, the semiconductor structure 14 may be peeled off from the peeling layer 120 using the thermal release tape TRT and then the semiconductor structure 14 may be moved to another temporary substrate or carrier. In some embodiments, when the semiconductor structure 14 and the peeling layer 120 are separated using the thermal release tape TRT, the material of the buffer layer 122 includes, for example, C-face aluminum oxide, and the material of the peeling layer 120 includes, for example, graphene, so that the semiconductor structure 14 is easily separated from the peeling layer 120, but the present disclosure is not limited thereto, and other buffer layer materials and peeling layer materials are also intended to be included in the present disclosure.

[0055] In some embodiments, Figure 1AAs shown in step S16, the method for manufacturing an electronic device may further include removing the sacrificial layer 12 or impurities remaining on the substrate 10 after separating the semiconductor structure 14 from the substrate 10 and before detecting defects of the substrate 10. For example, Fig. 20 As shown, the substrate 10 can be cleaned by chemical etching, wherein the etchant ET includes, for example, acetic acid (CH3COOH), hydrochloric acid (HCL), nitric acid (HNO3), phosphoric acid (H3PO4), sulfuric acid (H2SO4), potassium hydroxide (KOH), potassium hydroxide plus water, potassium hydroxide plus ethylene glycol (ethylene glycol), sodium hydroxide (NaOH) plus water, sodium hydroxide plus ethylene glycol or other suitable etchants.

[0056] In some embodiments, Figure 1A As shown in step S18, the method for manufacturing an electronic device may further include detecting a defect of the substrate 10 while detecting a crack of the substrate 10 and confirming whether the substrate 10 can be cut into a size greater than or equal to a threshold size if there is a defect or crack. Fig.21 As shown, the substrate 10 can be inspected by an automated optical inspection (AOI) system S to determine whether there is a defect DF (see Fig. 22 ) and / or cracks CK (refer to Fig.23 ). If it is detected that the substrate 10 has defects DF and / or cracks CK, the defects DF and / or cracks CK are removed by reducing the size of the substrate 10. If it is confirmed that the substrate 10 has defects DF or cracks CK and can be cut into a size greater than or equal to the threshold size, the size of the substrate 10 is reduced, such as Figure 1A Step S20 and Fig. 22 and Fig.23 As shown, if it is confirmed that the substrate 10 has a defect DF or a crack CK and cannot be cut into a size greater than or equal to the threshold size, the substrate 10 is scrapped. Figure 1A As shown in step S22.

[0057] Taking the semiconductor structure 14 as a light emitting diode structure as an example, the substrates currently used to produce LED chips are mainly four inches, so the threshold size can be set to 4 inches. If it is determined that the size of the substrate 10 needs to be reduced to four inches, six inches, or eight inches to remove the defect DF and / or crack CK, then the following steps can be performed: Figure 1A On the other hand, if it is determined that the size of the substrate 10 must be reduced to less than four inches in order to remove the defect DF and / or the crack CK, then the next Figure 1A Step S22.

[0058] In some embodiments, the scrapped substrate 10 can be broken into particles to be used as heat dissipation materials in related processes. In other embodiments, the scrapped substrate 10 can enter the semiconductor recycling process. In still other embodiments, the scrapped substrate 10 can be used for educational training or experiments.

[0059] In some embodiments, Figure 1A As shown in step S24, the method for manufacturing an electronic device may further include performing chemical-mechanical planarization (CMP) on the substrate 10 after detecting defects of the substrate 10 and before classifying the substrate 10. For example, if it is confirmed that the substrate 10 has no defects DF and cracks CK, chemical-mechanical planarization may be performed. Fig.24 As shown, a slurry SL can be used as an abrasive, and a polishing head PH is used to press the substrate 10 down on a polishing pad PP to perform chemical mechanical polishing. During the chemical mechanical polishing process, the polishing head PH and the polishing pad PP can rotate to flatten the surface of the substrate 10.

[0060] In some embodiments, Figure 1A As shown in step S26, the method for manufacturing an electronic device may further include detecting the thickness T10 and surface roughness of the chemically mechanically polished substrate 10. Fig.25 as well as Fig.26 As shown, a non-contact thickness detection method can be used to detect the thickness T10 and surface roughness (eg, arithmetic average roughness Ra, AA) of the substrate 10. For example, Fig.25 As shown, the substrate 10 can be placed on the stage G, and the light can be divided into different focal lengths as a function of wavelength by the optical probe P. The distance measurement is performed according to the wavelength of the reflected light received by the light receiver R, thereby calculating the thickness T10 and the surface roughness of the substrate 10. In some embodiments, the thickness T10 and the surface roughness of the substrate 10 can be measured in different areas.

[0061] In some embodiments, if the thickness T10 and the surface roughness meet the specifications, the chemically mechanically polished substrate 10 is chemically cleaned, such as Figure 1B As shown in step S28, if any one of the thickness T10 and the surface roughness does not meet the specification, chemical mechanical polishing can be performed again, for example, back to Figure 1AIn some embodiments, after determining that any one of the thickness T10 and the surface roughness does not meet the specification (for example, when Ra>10nm) and before performing chemical mechanical polishing again, the number of chemical mechanical polishings that the substrate 10 has undergone may be confirmed. If the number of chemical mechanical polishings that the substrate 10 has undergone does not reach the threshold, chemical mechanical polishing may be performed again, for example, back to Figure 1A On the other hand, if the number of times the substrate 10 has been subjected to chemical mechanical polishing reaches a threshold, the substrate 10 is scrapped, for example, Figure 1A Step S22.

[0062] In some embodiments, Fig. 27 As shown, chemically cleaning the CMP-polished substrate 10 may include immersing the substrate 10 in a chemical solution CS' to remove impurities or dirt remaining on the substrate 10. In some embodiments, the chemical cleaning described in step S28 may also be referred to as RCA cleaning.

[0063] In some embodiments, Figure 1B As shown in step S30, the method for manufacturing an electronic device may further include confirming the number and size of particles on the substrate 10 before classifying the substrate 10. For example, Fig.21 The automatic optical inspection system S shown in the figure is used to confirm the number and size of the particles on the substrate 10. If the number and size of the particles on the substrate 10 meet the specifications, the substrate 10 is classified according to the thickness T10 of the substrate 10, such as Figure 1B As shown in step S32, if any of the number and size of particles on the substrate 10 does not meet the specification, the substrate 10 is scrapped, for example, Figure 1B In some embodiments, if the number of particles on the substrate 10 is greater than 5 and / or the size of the particles is greater than 0.5 nm*0.5 nm, the substrate 10 is scrapped, for example, Figure 1B Step S22.

[0064] In some embodiments, Fig.28As shown, classifying the substrate 10 may include storing the substrate 10 in different lockers for next use according to the thickness T10 of the substrate 10, and / or storing the substrates 10 with different reuse times in different lockers according to the number of reuse times of the substrate 10. For example, a substrate 10 with a thickness T10 greater than or equal to 800nm ​​and less than or equal to 2000nm may be stored in locker ST1, a substrate 10 with a thickness T10 greater than or equal to 300nm and less than 800nm ​​may be stored in locker ST2, and a substrate 10 with a thickness T10 greater than or equal to 50nm and less than 300nm may be stored in locker ST3, but not limited thereto. In some embodiments, the humidity in the locker (such as locker ST1, locker ST2 and / or locker ST3) may be greater than 7% of the ambient humidity and less than 30% of the ambient humidity, but not limited thereto.

[0065] In some embodiments, based on considerations such as warehouse management convenience and substrate service life, when it is desired to reuse the substrate 10 stored in a storage cabinet (such as storage cabinet ST1, storage cabinet ST2 and / or storage cabinet ST3), a substrate 10 with a smaller thickness T10 (such as the substrate 10 in storage cabinet ST3) may be preferentially used to grow the aforementioned semiconductor structure 14, but this is not limited to this.

[0066] Please refer to Fig.29A as well as Fig.29B , a method for manufacturing an electronic device and Figure 1A as well as Figure 1B The main difference in the manufacturing method of the electronic device shown is that Fig.29A The manufacturing method of the electronic device shown omits Figure 1A Step S16, and Fig.29A as well as Fig.29B Steps S24', S26', S28' and S32' shown in FIG. Figure 1A as well as Figure 1B There are differences among step S24, step S26, step S28 and step S32 shown.

[0067] In detail, Fig.29A as well as Fig.29B The manufacturing method of the electronic device shown in the figure omits the step of removing the sacrificial layer 12 remaining on the substrate 10 ( Figure 1A In step S16), the step of forming the sacrificial layer 12 can be omitted or the number of passes for forming the sacrificial layer 12 can be saved when the substrate 10 is reused. Fig.10 , Fig.12 , Fig.14 and / or Fig.19In the step of separating the semiconductor structure 14 from the substrate 10, at least the buffer layer 122 in the sacrificial layer 12 remains on the substrate 10. Therefore, by omitting the step of removing the sacrificial layer 12 remaining on the substrate 10, at least the buffer layer 122 in the sacrificial layer 12 can be retained on the substrate 10 and stored together in a storage cabinet (such as Fig.33 Therefore, when the substrate 10 in the storage cabinet is selected for reuse, the formation of the sacrificial layer 12 can be omitted or at least the formation of the buffer layer 122 can be omitted to save the number of passes for forming the sacrificial layer 12.

[0068] In the structure where the sacrificial layer 12 remaining on the substrate 10 is omitted from removal, Fig.29A At step S24' in the embodiment, after detecting defects of the substrate 10 (such as step S18) and before classifying the substrate 10 (such as step S32), the sacrificial layer 12 remaining on the substrate 10 is chemically mechanically polished. Fig.30 As shown, if the sacrificial layer 12 remaining on the substrate 10 includes a buffer layer 122 , the buffer layer 122 is subjected to chemical mechanical polishing.

[0069] In the structure where the sacrificial layer 12 remaining on the substrate 10 is omitted from removal, Fig.29A In step S26', the thickness and surface roughness of the chemically mechanically polished sacrificial layer 12 are detected. Fig.31 as well as Fig.32 As shown, if the sacrificial layer 12 remaining on the substrate 10 includes a buffer layer 122 , the thickness T122 and the surface roughness of the buffer layer 122 after chemical mechanical polishing are detected.

[0070] In the structure where the sacrificial layer 12 remaining on the substrate 10 is omitted from removal, Fig.29B In step S28' of the method, if the thickness and surface roughness of the sacrificial layer 12 meet the specifications, the sacrificial layer 12 after chemical mechanical polishing is chemically cleaned. In some embodiments, the substrate 10 can be chemically cleaned at the same time. Specifically, the substrate 10 and the sacrificial layer 12 thereon can be immersed in a Fig. 27 The chemical solution CS' is shown.

[0071] In the structure where the sacrificial layer 12 remaining on the substrate 10 is omitted from removal, Fig.29B In step S32', if the number and size of particles on the substrate 10 meet the specification, the substrate 10 can be classified according to the thickness T10 of the substrate 10, the surface roughness of the sacrificial layer 12 remaining on the substrate 10, or a combination thereof. Fig.33For example, classifying the substrates 10 may include storing the substrates 10 in different lockers for next use according to the thickness T10 of the substrates 10, the surface roughness of the sacrificial layer 12 remaining on the substrates 10 (such as the surface roughness of the buffer layer 122), or a combination thereof. Further, as described above, whether the substrates 10 are placed in the locker ST1, the locker ST2, or the locker ST3 may be determined according to the thickness T10 of the substrates 10. In some embodiments, Fig.33 As shown, each locker can be further layered according to the surface roughness of the sacrificial layer 12 (such as the surface roughness of the buffer layer 122). For example, each of the lockers ST1, ST2 and ST3 includes a first layer L1, a second layer L2 and a third layer L3, wherein the first layer L1 is used to place a sacrificial layer 12 with a surface roughness (such as the surface roughness of the buffer layer 122) less than 5nm and a substrate 10 thereunder, the second layer L2 is used to place a sacrificial layer 12 with a surface roughness (such as the surface roughness of the buffer layer 122) greater than or equal to 5nm and less than 10nm and a substrate 10 thereunder, and the third layer L3 is used to place a sacrificial layer 12 with a surface roughness (such as the surface roughness of the buffer layer 122) greater than or equal to 10nm and a substrate 10 thereunder. In other words, the third layer L3 in the locker ST2 is used to place the sacrificial layer 12 with a surface roughness (such as the surface roughness of the buffer layer 122) greater than or equal to 10nm and the substrate 100 with a thickness T10 greater than or equal to 300nm and less than 800nm ​​thereunder.

[0072] In some embodiments, based on considerations such as warehouse management convenience and substrate service life, when it is desired to reuse the substrate 10 stored in a storage cabinet (such as storage cabinet ST1, storage cabinet ST2 and / or storage cabinet ST3), a substrate 10 with a smaller thickness T10 and a sacrificial layer 12 with a larger surface roughness (such as the substrate 10 in the third layer L3 of storage cabinet ST3) may be preferentially selected to grow the aforementioned semiconductor structure 14, but this is not limited to this.

[0073] In some embodiments, Fig.34 As shown, the method for manufacturing an electronic device may include: forming a semiconductor structure on a recycled substrate (step S40); separating the semiconductor structure from the recycled substrate (step S42); performing a product inspection on the semiconductor structure (step S44); and performing a recycling inspection on the recycled substrate (step S46). For example, at step S40, the semiconductor structure may be removed from the aforementioned storage cabinet (see Fig.28 or Fig.33 ) to take out the recovered substrate. At step S42, if there is a sacrificial layer 12 (see Fig.33 ), which can be optionally omitted Figure 1A or Fig.29AStep S10 in the above example and execute Figure 1A or Fig.29A In step S12; on the contrary, if there is no sacrificial layer 12 on the recycled substrate (see Fig.28 ), then they can be executed in sequence Figure 1A or Fig.29A In step S44, product inspection of the semiconductor structure may include performing an electrical test or a lighting test on the semiconductor structure (such as the aforementioned semiconductor structure 14) to confirm that the semiconductor structure can work properly. In step S46, recycling inspection of the recycled substrate may include continuing Figure 1A or Fig.29A Step S18 and subsequent steps in Figure 1A For example, after step S18, step S20, step S22 or step S24 may be followed. After step S20, step S24 may be followed. After step S24, step S26 may be followed. After step S26, step S24 or step S28 may be followed. After step S28, step S30 may be followed. After step S30, step S22 or step S32 may be followed. Fig.29A The same can be said and I will not repeat it here.

[0074] In summary, in the embodiments of the present disclosure, the substrates separated from the semiconductor structure are classified to facilitate subsequent reuse, thereby helping to reduce the manufacturing cost of the electronic device.

[0075] The above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

[0076] Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person skilled in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure, and the features between the embodiments can be arbitrarily mixed and replaced with each other to form other new embodiments. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure content of the present disclosure, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can all be used according to the present disclosure. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present disclosure also includes the combination of each claim and embodiment. The scope of protection of the present disclosure shall be determined by the attached claims.

Claims

1. A method for manufacturing an electronic device, characterized in that: include: forming a sacrificial layer on the substrate; forming a semiconductor structure on the sacrificial layer; separating the semiconductor structure from the substrate; detecting defects of the substrate; as well as The substrates are classified.

2. The method for manufacturing an electronic device according to claim 1, wherein: The substrate is a silicon substrate.

3. The method for manufacturing an electronic device according to claim 1, wherein: The substrate is a silicon substrate, and the method for manufacturing the electronic device further comprises: After forming the sacrificial layer on the silicon substrate, the silicon substrate is cut into thin substrates.

4. The method for manufacturing an electronic device according to claim 1, wherein: The sacrificial layer includes a buffer layer, a peeling layer or a combination thereof.

5. The method for manufacturing an electronic device according to claim 4, characterized in that: The method of separating the semiconductor structure from the substrate comprises: removing the release layer by photoelectrochemical etching; removing the peeling layer by infrared laser; cutting the release layer with a laser; cutting the interface between the buffer layer and the substrate by using the laser; or The semiconductor structure and the release layer are separated by using a thermal adhesive tape.

6. The method for manufacturing an electronic device according to claim 5, characterized in that: Cutting the release layer with the laser or cutting the interface between the buffer layer and the substrate with the laser includes aligning the cutting position with an alignment pattern, confirming the thickness with a ruler, or a combination thereof.

7. The method for manufacturing an electronic device according to claim 1, wherein: Also includes: After separating the semiconductor structure and the substrate and before inspecting the defect of the substrate, the sacrificial layer or impurities remaining on the substrate are removed.

8. The method for manufacturing an electronic device according to claim 1, wherein: Also includes: While detecting the defect of the substrate, cracks of the substrate are detected and it is confirmed whether the substrate can be cut into a size greater than or equal to a threshold size if the defect or crack exists.

9. The method for manufacturing an electronic device according to claim 1, wherein: Also includes: After detecting the defect of the substrate and before classifying the substrate, chemically mechanically polishing the substrate or the sacrificial layer remaining on the substrate; as well as The thickness and surface roughness of the substrate or the sacrificial layer after the chemical mechanical polishing are detected.

10. The method for manufacturing an electronic device according to claim 9, characterized in that: If the thickness and the surface roughness meet the specifications, the chemically mechanically polished substrate or the sacrificial layer is chemically cleaned, and if either the thickness or the surface roughness does not meet the specifications, the chemical mechanical polishing is performed again.

11. The method for manufacturing an electronic device according to claim 1, wherein: Also includes: Before classifying the substrate, the number and size of particles on the substrate are confirmed.

12. The method for manufacturing an electronic device according to claim 1, wherein: Sorting the substrates includes storing the substrates in different lockers for next use according to the thickness of the substrates, the surface roughness of the sacrificial layer remaining on the substrates, or a combination thereof.

13. A method for manufacturing an electronic device, characterized in that: include: forming a semiconductor structure on the recycled substrate; separating the semiconductor structure and the recovered substrate; Performing product inspection on the semiconductor structure; as well as The recycled substrate is subjected to a recycling inspection.

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