Storage capacitor structure and manufacturing method thereof

Abstract

The invention relates to a storage capacitor structure and a manufacturing method thereof. The storage capacitor structure comprises a lower electrode, a capacitor dielectric layer, a first upper electrode, a lower electrode contact structure, a dielectric layer blind hole and an oxidation dielectric layer, the capacitor dielectric layer is positioned on one side of the lower electrode; the first upper electrode is located on one side of the capacitor dielectric layer away from the lower electrode; the lower electrode contact structure is located on the side, away from the capacitor dielectric layer, of the lower electrode and electrically connected with the lower electrode. The dielectric layer blind hole is located right above the lower electrode contact structure in the first direction and penetrates through the first upper electrode and the capacitor dielectric layer in the first direction instead of penetrating through the lower electrode; the oxidation dielectric layer is embedded in the dielectric layer blind hole. The problem of storage capacitor failure caused by capacitor dielectric layer fracture can be effectively solved, and the process yield and the performance stability of the storage capacitor structure are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a storage capacitor structure and a manufacturing method thereof. Background Art

[0002] Ferroelectric Random Access Memory (FRAM) is a memory device that integrates memory cells (CELLs) in the back end of line (BEOL) process, and has the advantages of high speed, high density, low power consumption and radiation resistance. The capacitor structure in the memory cell of the ferroelectric memory is usually composed of an upper electrode, a lower electrode and a capacitor medium (such as a ferroelectric material) located between the upper electrode and the lower electrode; wherein the contact structure (such as a conductive lead) is electrically connected to the upper electrode and the lower electrode respectively.

[0003] However, in practical applications, the manufacture of the capacitor structure is subject to the process limitations of the lower electrode contact structure, which can easily lead to the problem of capacitor dielectric layer fracture. For example: there will inevitably be a void in the center of the lower electrode contact structure, which can easily cause the lower electrode material and the capacitor dielectric layer material to enter the void, thereby causing the capacitor dielectric layer to fracture; and, if a step is formed between the lower electrode contact structure and the interlayer dielectric layer, the capacitor structure will accumulate at the step corner, causing the capacitor dielectric layer to fracture. If the capacitor dielectric layer is fractured, electrical contact will occur between the upper electrode and the lower electrode of the capacitor structure, causing a short circuit, thereby causing the storage unit to fail. Summary of the invention

[0004] Based on this, the embodiments of the present application provide a storage capacitor structure and a manufacturing method thereof, which can effectively solve the problem of storage capacitor failure caused by the breakage of the capacitor dielectric layer, and improve the process yield and performance stability of the storage capacitor structure.

[0005] In order to achieve the above-mentioned purpose, on the one hand, some embodiments of the present application provide a storage capacitor structure. The storage capacitor structure includes a lower electrode, a capacitor dielectric layer, a first upper electrode, a lower electrode contact structure, a dielectric layer blind hole and an oxidized dielectric layer; the capacitor dielectric layer is located on one side of the lower electrode; the first upper electrode is located on the side of the capacitor dielectric layer away from the lower electrode; the lower electrode contact structure is located on the side of the lower electrode away from the capacitor dielectric layer and is electrically connected to the lower electrode; the dielectric layer blind hole is located directly above the lower electrode contact structure in the first direction, and penetrates the first upper electrode and the capacitor dielectric layer in the first direction without penetrating the lower electrode; the oxidized dielectric layer is embedded in the dielectric layer blind hole.

[0006] In some embodiments, the orthographic projection of the lower electrode contact structure in the first direction is located within the orthographic projection of the oxide dielectric layer in the first direction.

[0007] In some embodiments, the storage capacitor structure also includes a first upper electrode contact structure; the first upper electrode contact structure is located on the side of the first upper electrode away from the capacitor dielectric layer and is electrically connected to the first upper electrode; wherein the first upper electrode contact structure is located on one side of the oxide dielectric layer in the second direction; the second direction intersects with the first direction.

[0008] In some embodiments, the distance between the first upper electrode contact structure and the oxidized dielectric layer in the second direction is greater than half of a size of the first upper electrode contact structure in the second direction.

[0009] In some embodiments, the storage capacitor structure further includes a second upper electrode; the second upper electrode is located on a side of the first upper electrode away from the capacitor dielectric layer, and covers the first upper electrode and a surface of the oxidation dielectric layer away from the lower electrode.

[0010] In some embodiments, the storage capacitor structure further includes a second upper electrode contact structure; the second upper electrode contact structure is located on a side of the second upper electrode away from the first upper electrode and is electrically connected to the second upper electrode.

[0011] In some embodiments, a ratio between a size of the oxide medium layer in the second direction and a size of the upper electrode contact structure in the second direction ranges from 1.1 to 2.

[0012] On the other hand, the present application also provides a method for manufacturing a storage capacitor structure according to some embodiments; the method for manufacturing the storage capacitor structure includes: forming a lower electrode contact structure; forming a lower electrode on one side of the lower electrode contact structure; forming a capacitor dielectric layer on the side of the lower electrode away from the lower electrode contact structure; forming a first upper electrode on the side of the capacitor dielectric layer away from the lower electrode; etching the capacitor dielectric layer and the first upper electrode to form a dielectric layer blind hole that penetrates the first upper electrode and the capacitor dielectric layer in a first direction but does not penetrate the lower electrode; and forming an oxidized dielectric layer in the dielectric layer blind hole.

[0013] In some embodiments, after forming an oxidized dielectric layer in a blind hole in the dielectric layer, the manufacturing method further includes: forming a first upper electrode contact structure electrically connected to the first upper electrode on a side of the first upper electrode facing away from the capacitor dielectric layer; wherein the first upper electrode contact structure is located on one side of the oxidized dielectric layer in a second direction; and the second direction intersects with the first direction.

[0014] In some embodiments, after forming an oxidized dielectric layer in a blind hole in the dielectric layer, the manufacturing method further includes: forming a second upper electrode on a side of the first upper electrode facing away from the capacitor dielectric layer; the second upper electrode covers the first upper electrode and a surface of the oxidized dielectric layer facing away from the lower electrode; and forming a second upper electrode contact structure electrically connected to the second upper electrode on a side of the second upper electrode facing away from the first upper electrode.

[0015] The embodiments of the present application may or at least have the following advantages:

[0016] In the embodiment of the present application, a dielectric layer blind hole that penetrates the capacitor dielectric layer and the first upper electrode but does not penetrate the lower electrode is formed directly above the lower electrode contact structure in the first direction, so as to remove the capacitor dielectric layer above the lower electrode contact structure, thereby avoiding the capacitor dielectric layer fracture problem caused by the capacitor dielectric layer material entering the void of the lower electrode contact structure; and, filling the dielectric layer with an oxidized dielectric layer in the dielectric layer blind hole can also support and protect the lower electrode, the capacitor dielectric layer, the first upper electrode and other upper structures, so that the storage capacitor structure is not affected by the void problem of the lower electrode contact structure. In this way, the embodiment of the present application can effectively solve the storage capacitor failure problem caused by the capacitor dielectric layer fracture, and improve the process yield and performance stability of the storage capacitor structure.

[0017] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 A schematic diagram of a storage capacitor structure provided in the related art;

[0020] Figure 2 A schematic diagram of another storage capacitor structure provided in the related art;

[0021] Figure 3 is a three-dimensional schematic diagram of a storage capacitor structure provided in some embodiments;

[0022] Figure 4 is a schematic structural diagram of a storage capacitor structure provided in some embodiments;

[0023] Figure 5 is a three-dimensional schematic diagram of a storage capacitor structure provided in some other embodiments;

[0024] Figure 6 is a schematic structural diagram of a storage capacitor structure provided in some other embodiments;

[0025] Figure 7 is a flow chart of a method for manufacturing a storage capacitor structure provided in some embodiments;

[0026] Figure 8 is a flow chart of another method for manufacturing a storage capacitor structure provided in some embodiments;

[0027] Fig. 9 is a flow chart of a method for manufacturing a storage capacitor structure provided in some other embodiments;

[0028] Fig.10 A schematic diagram of a structure obtained after forming a lower electrode contact structure provided in some embodiments;

[0029] Fig.11 A schematic diagram of a structure obtained after forming a lower electrode provided in some embodiments;

[0030] Fig.12 A schematic diagram of a structure obtained after a capacitor dielectric layer is provided in some embodiments;

[0031] Fig.13 A schematic structural diagram of a structure obtained after forming a first upper electrode provided in some embodiments;

[0032] Fig.14 A schematic diagram of a structure obtained after forming a blind hole in a dielectric layer provided in some embodiments;

[0033] Fig.15 A schematic diagram of a structure obtained after forming an oxidizing medium layer provided in some embodiments;

[0034] Fig.16 A schematic structural diagram of a structure obtained after forming a first upper electrode contact hole provided in some embodiments;

[0035] Fig.17 A schematic structural diagram of a structure obtained after forming a second upper electrode provided in some embodiments;

[0036] Fig.18 A schematic structural diagram of a structure obtained after forming a second upper electrode contact hole provided in some embodiments.

[0037] Description of reference numerals:

[0038] 1-lower electrode, 2-capacitor dielectric layer, 3-upper electrode, 31-first upper electrode, 32-second upper electrode, 4-oxidation dielectric layer, 51-first interlayer dielectric layer, 52-second interlayer dielectric layer, H-dielectric layer blind hole, CT1-lower electrode contact structure, CT2-upper electrode contact structure, G1-first upper electrode contact hole, G2-second upper electrode contact hole, CT21-first upper electrode contact structure, CT22-second upper electrode contact structure. DETAILED DESCRIPTION

[0039] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0041] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0042] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0044] In the ferroelectric random access memory (FRAM), which is a kind of actual manufacturing process in the back end of line (BEOL), the manufacturing of its storage capacitor structure is limited by the process of the lower electrode contact structure, which makes it easy to have the problem of capacitor dielectric layer fracture. For example: Figure 1 As shown, there is inevitably a void in the center of the lower electrode contact structure CT1, which easily causes the material of the lower electrode 1 and the material of the capacitor dielectric layer 2 to enter the void, thereby causing the capacitor dielectric layer 2 to break (such as Figure 1 As shown in A in FIG. 1 ). And, Figure 2 As shown in FIG. 1 , if a step (step high) is formed between the lower electrode contact structure CT1 and the first interlayer dielectric layer 51 , the storage capacitor structure will be accumulated at the corner of the step, thereby causing the capacitor dielectric layer 2 to break (eg, Figure 2 If the capacitor dielectric layer 2 is broken, the upper electrode 3 and the lower electrode 1 of the storage capacitor structure will be in electrical contact, resulting in a short circuit, thereby causing the storage unit to fail.

[0045] In response to the above problems, the embodiments of the present application provide a storage capacitor structure and a manufacturing method thereof, which can effectively solve the problem of storage capacitor failure caused by fracture of the capacitor dielectric layer, and improve the process yield and performance stability of the storage capacitor structure.

[0046] In some embodiments, see Figure 3 and Figure 4 The storage capacitor structure includes a lower electrode 1, a capacitor dielectric layer 2, a first upper electrode 31, a lower electrode contact structure CT1, a dielectric layer blind hole H and an oxidized dielectric layer 4; the capacitor dielectric layer 2 is located on one side of the lower electrode 1; the first upper electrode 31 is located on the side of the capacitor dielectric layer 2 away from the lower electrode 1; the lower electrode contact structure CT1 is located on the side of the lower electrode 1 away from the capacitor dielectric layer 2 and is electrically connected to the lower electrode 1; the dielectric layer blind hole H is located directly above the lower electrode contact structure CT1 in a first direction (for example, the Z direction), and penetrates the first upper electrode 31 and the capacitor dielectric layer 2 in the first direction (for example, the Z direction) but does not penetrate the lower electrode 1; the oxidized dielectric layer 4 is embedded in the dielectric layer blind hole H.

[0047] By way of example, the storage capacitor structure includes but is not limited to a random access memory (Random Access Memory, RAM for short); the storage capacitor structure may be, for example, a ferroelectric random access memory (Ferroelectric Random Access Memory, FRAM for short) or the like.

[0048] By way of example, the material of the lower electrode 1 includes, but is not limited to, a conductive metal; the material of the lower electrode 1 may be, for example, tungsten (W) or the like.

[0049] By way of example, the material of the first upper electrode 31 includes, but is not limited to, a conductive metal; the material of the first upper electrode 31 may be, for example, tungsten (W) or the like.

[0050] By way of example, the material of the capacitor dielectric layer 2 includes ferroelectric material or high dielectric (Hight-K, HK for short) material.

[0051] For example, see Figure 3 and Figure 4 , the lower electrode contact structure CT1 may extend in a first direction (eg, Z direction) in a direction away from the lower electrode 1 .

[0052] By way of example, the material of the lower electrode contact structure CT1 includes, but is not limited to, a conductive metal; the material of the lower electrode contact structure CT1 may be, for example, zinc (Zu) or copper (Cu).

[0053] For example, the shape of the lower electrode contact structure CT1 includes but is not limited to a circular column, a square column or a regular polygonal column, etc.; it should be noted that, Figure 3 Although the shape of the electrode contact structure CT1 is a circular column as an example, the present application is not limited to this.

[0054] By way of example, the dielectric layer blind hole H includes but is not limited to a circular hole, a square hole, a regular polygonal hole, and the like.

[0055] For example, the material of the oxidizing medium layer 4 includes but is not limited to oxide (OX); the material of the oxidizing medium layer 4 may be, for example, silicon monoxide (SiO) or silicon dioxide (SiO 2 ).

[0056] For example, the shape of the oxidizing medium layer 4 includes but is not limited to a circular column, a square column or a regular polygonal column, etc.; it should be noted that, Figure 3 Although the shape of the oxidizing medium layer 4 is illustrated as a circular column, the present application is not limited thereto.

[0057] For some examples, see Figure 4 The surface of the oxide dielectric layer 4 facing away from the lower electrode 1 is flush with the surface of the first upper electrode 31 facing away from the capacitor dielectric layer 2 .

[0058] In the embodiment of the present application, a dielectric layer blind hole H is formed directly above the lower electrode contact structure CT1 in the first direction, which penetrates the capacitor dielectric layer 2 and the first upper electrode 31 but does not penetrate the lower electrode 1, so as to remove the capacitor dielectric layer 2 above the lower electrode contact structure CT1, thereby avoiding the problem of the capacitor dielectric layer 2 breaking caused by the capacitor dielectric layer 2 material entering the void of the lower electrode contact structure CT1; and the oxide dielectric layer 4 is filled in the dielectric layer blind hole H, which can also support and protect the lower electrode 1, the capacitor dielectric layer 2, the first upper electrode 31 and other upper structures, so that the storage capacitor structure is not affected by the void problem of the lower electrode contact structure CT1. In this way, the embodiment of the present application can effectively solve the problem of storage capacitor failure caused by the fracture of the capacitor dielectric layer 2, and improve the process yield and performance stability of the storage capacitor structure.

[0059] In some embodiments, see Figure 4 , the orthographic projection of the lower electrode contact structure CT1 in the first direction (eg, Z direction) is located within the orthographic projection of the oxide dielectric layer 4 in the first direction (eg, Z direction).

[0060] For example, the size of the lower electrode contact structure CT1 in the second direction (eg, the X direction) is smaller than the size of the oxide dielectric layer 4 in the second direction (eg, the X direction).

[0061] For example, the size of the first upper electrode contact structure CT21 in the second direction (eg, X direction) is smaller than the size of the oxide medium layer 4 in the second direction (eg, X direction).

[0062] In the embodiment of the present application, the orthographic projection of the lower electrode contact structure CT1 in the first direction (for example, the Z direction) is located within the orthographic projection of the oxide dielectric layer 4 in the first direction (for example, the Z direction), so that the capacitor dielectric layer 2 above the lower electrode contact structure CT1 can be completely removed, thereby effectively avoiding the problem of the capacitor dielectric layer 2 being broken due to the material of the capacitor dielectric layer 2 entering the void of the lower electrode contact structure CT1, thereby improving the process yield and performance stability of the storage capacitor structure.

[0063] In some embodiments, see Figure 3 and Figure 4 The storage capacitor structure also includes a first upper electrode contact structure CT21; the first upper electrode contact structure CT21 is located on a side of the first upper electrode 31 away from the capacitor dielectric layer 2 and is electrically connected to the first upper electrode 31; wherein the first upper electrode contact structure CT21 is located on one side of the oxide dielectric layer 4 in a second direction (for example, an X direction); the second direction (for example, the X direction) intersects with the first direction (for example, the Z direction).

[0064] By way of example, the first upper electrode contact structure CT21 may extend in a direction away from the first upper electrode 31 in a first direction (eg, the Z direction).

[0065] By way of example, the material of the first upper electrode contact structure CT21 includes, but is not limited to, a conductive metal; the material of the first upper electrode contact structure CT21 may be, for example, zinc (Zu) or copper (Cu).

[0066] For example, the shape of the first upper electrode contact structure CT21 includes but is not limited to a circular column, a square column or a regular polygonal column, etc.; it should be noted that, Figure 3 Although the shape of the first upper electrode contact structure CT21 is a circular column as an example, the present application is not limited to this.

[0067] For some examples, see Figure 4 , the orthographic projection of the first upper electrode contact structure CT21 in the first direction (eg, Z direction) does not overlap with the orthographic projection of the oxide medium layer 4 in the first direction (eg, Z direction).

[0068] It should be noted that in the embodiment of the present application, the lower electrode 1, the capacitor dielectric layer 2 and the first upper electrode 31 are stacked in sequence from bottom to top along a first direction (eg, the Z direction) to form a ferroelectric storage structure layer (FRC for short) of a storage capacitor structure.

[0069] In the embodiment of the present application, the first upper electrode contact structure CT21 is located on one side of the oxidized dielectric layer 4 in the second direction (for example, the X direction), so as to form the oxidized dielectric layer 4 and avoid the problem of the capacitor dielectric layer 2 being broken due to the void problem of the lower electrode contact structure CT1, and then the first upper electrode 31 is electrically connected to the first upper electrode 31 and led out through the first upper electrode 31 structure; in this way, the performance stability of the storage capacitor structure is guaranteed while effectively solving the problem of storage capacitor failure caused by the breakage of the capacitor dielectric layer 2.

[0070] In some embodiments, see Figure 4 , the distance between the first upper electrode contact structure CT21 and the oxide medium layer 4 in the second direction (eg, X direction) is greater than half of the size of the first upper electrode contact structure CT21 in the second direction (eg, X direction).

[0071] For example, please continue to see Figure 4 , the distance between the first upper electrode contact structure CT21 and the oxide medium layer 4 in the second direction (eg, X direction) is d, and the size of the first upper electrode contact structure CT21 in the second direction (eg, X direction) is M; then d>1 / 2M.

[0072] In the embodiment of the present application, there is a certain distance between the first upper electrode contact structure CT21 and the oxidized dielectric layer 4, so that there is no contact between the first upper electrode contact structure CT21 and the oxidized dielectric layer 4, which effectively ensures a reliable electrical connection between the first upper electrode contact structure CT21 and the first upper electrode 31, and avoids damage to the oxidized dielectric layer 4 during the contact hole etching process of the first upper electrode contact structure CT21, thereby ensuring the isolation and support functions of the oxidized dielectric layer 4 and improving the process yield and performance stability of the storage capacitor structure.

[0073] In some embodiments, see Figure 5 and Figure 6 The storage capacitor structure further includes a second upper electrode 32 ; the second upper electrode 32 is located on a side of the first upper electrode 31 away from the capacitor dielectric layer 2 , and covers the first upper electrode 31 and a surface of the oxide dielectric layer 4 away from the lower electrode 1 .

[0074] In some examples, the second upper electrode 32 is electrically connected to the first upper electrode 31 .

[0075] By way of example, the material of the second upper electrode 32 includes, but is not limited to, a conductive metal; the material of the second upper electrode 32 may be, for example, tungsten (W) or the like.

[0076] In some embodiments, see Figure 5 and Figure 6 The storage capacitor structure further includes a second upper electrode contact structure CT22 ; the second upper electrode contact structure CT22 is located at a side of the second upper electrode 32 away from the first upper electrode 31 and is electrically connected to the second upper electrode 32 .

[0077] For some examples, see Figure 6 The second upper electrode contact structure CT22 is directly opposite to the lower electrode contact structure CT1 in the first direction (eg, the Z direction).

[0078] For some examples, see Figure 6 The orthographic projection of the second upper electrode contact structure CT22 in the first direction (for example, the Z direction) is located within the orthographic projection of the oxidation medium layer 4 in the first direction (for example, the Z direction); the orthographic projection of the lower electrode contact structure CT1 in the first direction (for example, the Z direction) is located within the orthographic projection of the oxidation medium layer 4 in the first direction (for example, the Z direction).

[0079] By way of example, the second upper electrode contact structure CT22 may extend in a direction away from the second upper electrode 32 in the first direction (eg, the Z direction).

[0080] By way of example, the material of the second upper electrode contact structure CT22 includes, but is not limited to, a conductive metal; the material of the second upper electrode contact structure CT22 may be, for example, zinc (Zu) or copper (Cu).

[0081] For example, the shape of the second upper electrode contact structure CT22 includes but is not limited to a circular column, a square column or a regular polygonal column, etc.; it should be noted that, Figure 5 Although the shape of the second upper electrode contact structure CT22 is a circular column as an example, the present application is not limited to this.

[0082] It should be noted that the upper electrode in the embodiment of the present application adopts a stacked electrode structure composed of a first upper electrode 31 and a second upper electrode 32, that is, the lower electrode 1, the capacitor dielectric layer 2, the first upper electrode 31 and the second upper electrode 32 are stacked in sequence from bottom to top along a first direction (for example, the Z direction) to form a ferroelectric storage structure layer (FRC for short) of a storage capacitor structure.

[0083] In the embodiment of the present application, a dielectric layer blind hole H is formed directly above the lower electrode contact structure CT1 in the first direction, which penetrates the capacitor dielectric layer 2 and the first upper electrode 31 but does not penetrate the lower electrode 1, so as to remove the capacitor dielectric layer 2 above the lower electrode contact structure CT1, thereby avoiding the problem of the capacitor dielectric layer 2 being broken due to the material of the capacitor dielectric layer 2 entering the cavity of the lower electrode contact structure CT1; and, the oxide dielectric layer 4 is filled in the dielectric layer blind hole H, which can also support and protect the lower electrode 1, the capacitor dielectric layer 2, the first upper electrode 31 and the second upper electrode 32, so that the storage capacitor structure is not affected by the lower electrode. The influence of the void problem of the upper electrode contact structure CT1; in addition, the embodiment of the present application also adopts a stacked electrode structure composed of a first upper electrode 31 and a second upper electrode 32, which can maintain the original ferroelectric storage structure layer under the premise of achieving isolation protection through the oxide dielectric layer 4, so that the second upper electrode contact structure CT22 and the lower electrode contact structure CT1 can be arranged opposite to each other, which is beneficial to wire wiring and improves the connection reliability of the storage capacitor structure; in this way, the embodiment of the present application can effectively solve the problem of storage capacitor failure caused by the breakage of the capacitor dielectric layer 2, and improve the process yield and performance stability of the storage capacitor structure.

[0084] In some embodiments, a ratio between a size of the oxidation medium layer 4 in the second direction (eg, X direction) and a size of the upper electrode contact structure in the second direction (eg, X direction) ranges from 1.1 to 2.

[0085] It should be noted that the upper electrode contact structure includes a first upper electrode contact structure CT21 and a second upper electrode contact structure CT22.

[0086] For some examples, see Figure 4The ratio between the dimension M of the oxide medium layer 4 in the second direction (eg, the X direction) and the dimension x21 of the first upper electrode contact structure CT21 in the second direction (eg, the X direction) is in the range of 1.1-2.

[0087] For example, the ratio between the dimension M of the oxide medium layer 4 in the second direction (eg, X direction) and the dimension x21 of the first upper electrode contact structure CT21 in the second direction (eg, X direction) may be, for example, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2, etc.

[0088] For some examples, see Figure 6 The ratio between the dimension M of the oxide medium layer 4 in the second direction (eg, the X direction) and the dimension x22 of the second upper electrode contact structure CT22 in the second direction (eg, the X direction) is in the range of 1.1-2.

[0089] For example, the ratio between the dimension M of the oxide medium layer 4 in the second direction (e.g., X direction) and the dimension x22 of the second upper electrode contact structure CT22 in the second direction (e.g., X direction) can be, for example, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2, etc.

[0090] In some embodiments, see Figure 4 or Figure 6 The ratio between the dimension M of the oxide medium layer 4 in the second direction (eg, the X direction) and the dimension x1 of the lower electrode contact structure CT1 in the second direction (eg, the X direction) is in the range of 1.1-2.

[0091] For example, the ratio between the dimension M of the oxide medium layer 4 in the second direction (eg, X direction) and the dimension x1 of the lower electrode contact structure CT1 in the second direction (eg, X direction) may be 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2, etc.

[0092] In some embodiments, see Figure 4 or Figure 6 The storage capacitor structure further includes a first interlayer dielectric layer 51 ; the first interlayer dielectric layer 51 is located on a side of the lower electrode 1 away from the capacitor dielectric layer 2 ; wherein the lower electrode contact structure CT1 is embedded in the first interlayer dielectric layer 51 .

[0093] By way of example, the material of the first interlayer dielectric layer 51 includes an insulating material; the material of the first interlayer dielectric layer 51 may be, for example, oxide (OX).

[0094] In some embodiments, the storage capacitor structure further includes a second interlayer dielectric layer 52 .

[0095] By way of example, the material of the second interlayer dielectric layer 52 includes an insulating material; the material of the second interlayer dielectric layer 52 may be, for example, oxide (OX).

[0096] For some examples, see Figure 4 The second interlayer dielectric layer 52 is located at a side of the first upper electrode 31 away from the capacitor dielectric layer 2 ; wherein the first upper electrode contact structure CT21 is embedded in the second interlayer dielectric layer 52 .

[0097] For some examples, see Figure 6 The second interlayer dielectric layer 52 is located at a side of the second upper electrode 32 away from the first upper electrode 31 ; wherein the second upper electrode contact structure CT22 is embedded in the second interlayer dielectric layer 52 .

[0098] The present application also provides a method for manufacturing a storage capacitor structure according to some embodiments, and the method for manufacturing a storage capacitor structure can be used to prepare the storage capacitor structure in some of the above embodiments. The technical advantages of the above storage capacitor structure are also possessed by the method for manufacturing the storage capacitor structure. It should be noted that for the parts that are the same or corresponding to the above embodiments, reference can be made to the corresponding description of the above embodiments, and will not be described in detail below.

[0099] In some embodiments, see Figure 7 , the manufacturing method of the storage capacitor structure includes the following steps S100~S600.

[0100] S100, forming a lower electrode contact structure.

[0101] S200 , forming a lower electrode on one side of the lower electrode contact structure.

[0102] S300, forming a capacitor dielectric layer on a side of the lower electrode away from the lower electrode contact structure.

[0103] S400, forming a first upper electrode on a side of the capacitor dielectric layer away from the lower electrode.

[0104] S500, etching the capacitor dielectric layer and the first upper electrode to form a dielectric layer blind hole that penetrates the first upper electrode and the capacitor dielectric layer in a first direction but does not penetrate the lower electrode.

[0105] S600, forming an oxidized dielectric layer in the blind hole of the dielectric layer.

[0106] In some embodiments, step S100 includes the following steps S110 to S120.

[0107] S110, providing a target layer; one side of the target layer has a first interlayer dielectric layer.

[0108] S110, etching the first interlayer dielectric layer to form a lower electrode contact hole in the first interlayer dielectric layer.

[0109] S120, forming a lower electrode contact structure in the lower electrode contact hole.

[0110] In some embodiments, see Figure 8 , after step S600, the manufacturing method further includes the following step S700.

[0111] S700, forming a first upper electrode contact structure electrically connected to the first upper electrode on a side of the first upper electrode away from the capacitor dielectric layer; wherein the first upper electrode contact structure is located on one side of the oxide dielectric layer in a second direction; and the second direction intersects the first direction.

[0112] In some embodiments, step S700 includes the following steps S710 to S730.

[0113] S710, forming a second interlayer dielectric layer on a side of the first upper electrode away from the capacitor dielectric layer.

[0114] S720, etching the second interlayer dielectric layer to form a first upper electrode contact hole in the second interlayer dielectric layer.

[0115] S730, forming a first upper electrode contact structure in the first upper electrode contact hole.

[0116] In some other embodiments, see Fig. 9 , after step S600, the manufacturing method further includes the following steps S810~S820.

[0117] S810, forming a second upper electrode on a side of the first upper electrode away from the capacitor dielectric layer; the second upper electrode covers the first upper electrode and a surface of the oxidation dielectric layer away from the lower electrode.

[0118] S820, forming a second upper electrode contact structure electrically connected to the second upper electrode on a side of the second upper electrode away from the first upper electrode.

[0119] In some embodiments, step S820 includes the following steps S821 to S823.

[0120] S821, forming a second interlayer dielectric layer on a side of the second upper electrode facing away from the first upper electrode.

[0121] S822, etching the second interlayer dielectric layer to form a second upper electrode contact hole in the second interlayer dielectric layer.

[0122] S823, forming a second upper electrode contact structure in the second upper electrode contact hole.

[0123] It should be understood that although Figure 7~Figure 9 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 7~Figure 9 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0124] In order to more clearly illustrate the manufacturing method of the storage capacitor structure in some of the above embodiments, the following embodiments are combined with Figure 4 , Figure 6 as well as Figure 10~Figure 18 Understand.

[0125] In some embodiments, the method for manufacturing a storage capacitor structure includes the following steps S100 - S600 .

[0126] In step S100 , a lower electrode contact structure CT1 is formed.

[0127] In some embodiments, step S100 includes the following steps S110 to S120.

[0128] In step S110 , a target layer is provided; one side of the target layer has a first interlayer dielectric layer 51 .

[0129] In step S110, refer to Fig.10 , the first interlayer dielectric layer 51 is etched to form a contact hole for the lower electrode 1 in the first interlayer dielectric layer 51 .

[0130] For example, the etching process of the first interlayer dielectric layer 51 includes, but is not limited to, a dry etching process; for example, it may be a photolithography process.

[0131] In step S120, please continue to refer to Fig.10 , a lower electrode contact structure CT1 is formed in the lower electrode 1 contact hole.

[0132] In step S200, refer to Fig.11 , a lower electrode 1 is formed on one side of the lower electrode contact structure CT1.

[0133] By way of example, the lower electrode 1 covers the first interlayer dielectric layer 51 and the lower electrode contact structure CT1 .

[0134] Illustratively, the bottom electrode 1 is electrically connected to the bottom electrode contact structure CT1 .

[0135] In step S300, refer to Fig.12 A capacitor dielectric layer 2 is formed on a side of the lower electrode 1 away from the lower electrode contact structure CT1.

[0136] In step S400, refer to Fig.13 , a first upper electrode 31 is formed on a side of the capacitor dielectric layer 2 away from the lower electrode 1 .

[0137] In step S500, refer to Fig.14 , the capacitor dielectric layer 2 and the first upper electrode 31 are etched to form a dielectric layer blind hole H that penetrates the first upper electrode 31 and the capacitor dielectric layer 2 but does not penetrate the lower electrode 1 in the first direction.

[0138] For example, the etching process of the capacitor dielectric layer 2 and the first upper electrode 31 includes, but is not limited to, a dry etching process; for example, it may be a photolithography process.

[0139] In some examples, the dielectric layer blind hole H is located directly above the lower electrode contact structure CT1 in the first direction (eg, the Z direction).

[0140] For example, please continue to see Fig.14 The dielectric layer blind hole H exposes a portion of the surface of the lower electrode 1 directly above the lower electrode contact structure CT1 in the first direction (eg, Z direction).

[0141] In step S600, refer to Fig.15 , an oxidized dielectric layer 4 is formed in the blind hole H of the dielectric layer.

[0142] For some examples, see Fig.15 The surface of the oxide dielectric layer 4 facing away from the lower electrode 1 is flush with the surface of the first upper electrode 31 facing away from the capacitor dielectric layer 2 .

[0143] For some examples, see Fig.15 , the orthographic projection of the lower electrode contact structure CT1 in the first direction (eg, Z direction) is located within the orthographic projection of the oxide dielectric layer 4 in the first direction (eg, Z direction).

[0144] In some embodiments, after step S600 , the manufacturing method further includes the following step S700 .

[0145] In step S700, a first upper electrode contact structure CT21 electrically connected to the first upper electrode 31 is formed on a side of the first upper electrode 31 away from the capacitor dielectric layer 2; wherein the first upper electrode contact structure CT21 is located on one side of the oxide dielectric layer 4 in a second direction; and the second direction intersects the first direction.

[0146] In some embodiments, step S700 includes the following steps S710 to S730.

[0147] In step S710 , a second interlayer dielectric layer 52 is formed on a side of the first upper electrode 31 away from the capacitor dielectric layer 2 .

[0148] In step S720, refer to Fig.16 , the second interlayer dielectric layer 52 is etched to form a first upper electrode contact hole G1 in the second interlayer dielectric layer 52 .

[0149] For example, the etching process of the second interlayer dielectric layer 52 includes but is not limited to a dry etching process; for example, it may be a photolithography process.

[0150] In step S730, refer to Figure 4 , a first upper electrode contact structure CT21 is formed in the first upper electrode contact hole G1.

[0151] In some examples, the distance between the first upper electrode contact structure CT21 and the oxidized medium layer 4 in the second direction (eg, X direction) is greater than half of the size of the first upper electrode contact structure CT21 in the second direction (eg, X direction).

[0152] Illustratively, the first upper electrode contact structure CT21 is electrically connected to the first upper electrode 31 .

[0153] It should be noted that in some of the above embodiments, the lower electrode 1, the capacitor dielectric layer 2 and the first upper electrode 31 are stacked in sequence from bottom to top along a first direction (eg, Z direction) to form a ferroelectric storage structure layer (FRC for short) of a storage capacitor structure.

[0154] In some other embodiments, after step S600, the manufacturing method further includes the following steps S810-S820.

[0155] In step S810, refer to Fig.17 A second upper electrode 32 is formed on the side of the first upper electrode 31 away from the capacitor dielectric layer 2 ; the second upper electrode 32 covers the first upper electrode 31 and the surface of the oxide dielectric layer 4 away from the lower electrode 1 .

[0156] For example, the second upper electrode 32 is electrically connected to the first upper electrode 31 .

[0157] In step S820 , a second upper electrode contact structure CT22 electrically connected to the second upper electrode 32 is formed on a side of the second upper electrode 32 away from the first upper electrode 31 .

[0158] In some embodiments, step S820 includes the following steps S821 to S823.

[0159] In step S821 , a second interlayer dielectric layer 52 is formed on a side of the second upper electrode 32 away from the first upper electrode 31 .

[0160] In step S822, refer to Fig.18 , the second interlayer dielectric layer 52 is etched to form a second upper electrode contact hole G2 in the second interlayer dielectric layer 52 .

[0161] For example, the etching process of the second interlayer dielectric layer 52 includes but is not limited to a dry etching process; for example, it may be a photolithography process.

[0162] In step S823, refer to Figure 6 , a second upper electrode contact structure CT22 is formed in the second upper electrode contact hole G2.

[0163] By way of example, the second upper electrode contact structure CT22 is directly opposite to the lower electrode contact structure CT1 in the first direction (eg, the Z direction).

[0164] For example, the orthographic projection of the second upper electrode contact structure CT22 in the first direction (e.g., Z direction) is located within the orthographic projection of the oxidized medium layer 4 in the first direction (e.g., Z direction); the orthographic projection of the lower electrode contact structure CT1 in the first direction (e.g., Z direction) is located within the orthographic projection of the oxidized medium layer 4 in the first direction (e.g., Z direction).

[0165] It should be noted that the upper electrode in some of the above embodiments adopts a stacked electrode structure composed of a first upper electrode 31 and a second upper electrode 32, that is, the lower electrode 1, the capacitor dielectric layer 2, the first upper electrode 31 and the second upper electrode 32 are stacked in sequence from bottom to top along a first direction (for example, the Z direction) to form a ferroelectric storage structure layer (FRC for short) of a storage capacitor structure.

[0166] In some embodiments, a ratio between a size of the oxidation medium layer 4 in the second direction (eg, X direction) and a size of the upper electrode contact structure in the second direction (eg, X direction) ranges from 1.1 to 2.

[0167] It should be noted that the upper electrode contact structure includes a first upper electrode contact structure CT21 and a second upper electrode contact structure CT22.

[0168] For some examples, see Figure 4 The ratio between the dimension M of the oxide medium layer 4 in the second direction (eg, the X direction) and the dimension x21 of the first upper electrode contact structure CT21 in the second direction (eg, the X direction) is in the range of 1.1-2.

[0169] For example, the ratio between the dimension M of the oxide medium layer 4 in the second direction (eg, X direction) and the dimension x21 of the first upper electrode contact structure CT21 in the second direction (eg, X direction) may be, for example, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2, etc.

[0170] For some examples, see Figure 6 The ratio between the dimension M of the oxide medium layer 4 in the second direction (eg, the X direction) and the dimension x22 of the second upper electrode contact structure CT22 in the second direction (eg, the X direction) is in the range of 1.1-2.

[0171] For example, the ratio between the dimension M of the oxide medium layer 4 in the second direction (e.g., X direction) and the dimension x22 of the second upper electrode contact structure CT22 in the second direction (e.g., X direction) can be, for example, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2, etc.

[0172] In some embodiments, see Figure 4 or Figure 6 The ratio between the dimension M of the oxide medium layer 4 in the second direction (eg, the X direction) and the dimension x1 of the lower electrode contact structure CT1 in the second direction (eg, the X direction) is in the range of 1.1-2.

[0173] For example, the ratio between the dimension M of the oxide medium layer 4 in the second direction (eg, X direction) and the dimension x1 of the lower electrode contact structure CT1 in the second direction (eg, X direction) may be 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2, etc.

[0174] In the description of this specification, the description with reference to the terms "some embodiments", "some examples", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0175] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0176] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. A storage capacitor structure, characterized in that: include: Lower electrode; A capacitor dielectric layer, located on one side of the lower electrode; A first upper electrode, located on a side of the capacitor dielectric layer away from the lower electrode; A lower electrode contact structure, located at a side of the lower electrode away from the capacitor dielectric layer and electrically connected to the lower electrode; a dielectric layer blind hole, located directly above the lower electrode contact structure in the first direction, and penetrating the first upper electrode and the capacitor dielectric layer in the first direction but not penetrating the lower electrode; The oxidized dielectric layer is embedded in the blind hole of the dielectric layer.

2. The storage capacitor structure according to claim 1, characterized in that: The orthographic projection of the lower electrode contact structure in the first direction is located within the orthographic projection of the oxide medium layer in the first direction.

3. The storage capacitor structure according to claim 2, characterized in that: Also includes: A first upper electrode contact structure, located at a side of the first upper electrode away from the capacitor dielectric layer and electrically connected to the first upper electrode; Wherein, the first upper electrode contact structure is located at one side of the oxidized dielectric layer in a second direction; and the second direction intersects with the first direction.

4. The storage capacitor structure according to claim 3, characterized in that: The distance between the first upper electrode contact structure and the oxide medium layer in the second direction is greater than half of a size of the first upper electrode contact structure in the second direction.

5. The storage capacitor structure according to claim 2, characterized in that: Also includes: The second upper electrode is located at a side of the first upper electrode away from the capacitor dielectric layer, and covers the first upper electrode and a surface of the oxidation dielectric layer away from the lower electrode.

6. The storage capacitor structure according to claim 5, characterized in that: Also includes: The second upper electrode contact structure is located at a side of the second upper electrode away from the first upper electrode and is electrically connected to the second upper electrode.

7. The storage capacitor structure according to any one of claims 3 or 6, characterized in that: The ratio between the size of the oxide medium layer in the second direction and the size of the upper electrode contact structure in the second direction is in the range of 1.1-2.

8. A method for manufacturing a storage capacitor structure, characterized in that: include: forming a lower electrode contact structure; forming a lower electrode on one side of the lower electrode contact structure; forming a capacitor dielectric layer on a side of the lower electrode away from the lower electrode contact structure; forming a first upper electrode on a side of the capacitor dielectric layer away from the lower electrode; Etching the capacitor dielectric layer and the first upper electrode to form a dielectric layer blind hole that penetrates the first upper electrode and the capacitor dielectric layer in a first direction but does not penetrate the lower electrode; An oxidized dielectric layer is formed in the blind hole of the dielectric layer.

9. The method for manufacturing a storage capacitor structure according to claim 8, characterized in that: After forming the oxidized dielectric layer in the blind hole of the dielectric layer, the manufacturing method further includes: A first upper electrode contact structure electrically connected to the first upper electrode is formed on a side of the first upper electrode away from the capacitor dielectric layer; wherein the first upper electrode contact structure is located on one side of the oxidized dielectric layer in a second direction; and the second direction intersects the first direction.

10. The method for manufacturing a storage capacitor structure according to claim 8, characterized in that: After forming the oxidized dielectric layer in the blind hole of the dielectric layer, the manufacturing method further includes: A second upper electrode is formed on a side of the first upper electrode away from the capacitor dielectric layer; the second upper electrode covers the first upper electrode and a surface of the oxidizing dielectric layer away from the lower electrode; A second upper electrode contact structure electrically connected to the second upper electrode is formed on a side of the second upper electrode away from the first upper electrode.

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