Grouping and error correction for non-volatile memory cells

Abstract

Numerous examples of an improved grouping and error correction system for non-volatile memory cells are disclosed. In one example, a system includes a memory array including non-volatile memory cells arranged in rows and columns, where the non-volatile memory cells of the memory array store first bits of a first data packet and second bits of a second data packet, and wherein the first packet is supported by a first ECC block and the second packet is supported by a second ECC block.

Description

[0001] Priority declaration

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 427,406, filed on November 22, 2022 and entitled “Level Assignment and Error Correction for Multilevel Non-Volatile Memory Cells,” and U.S. Patent Application No. 18 / 106,421, filed on February 6, 2023 and entitled “Grouping and Error Correction for Non-volatile Memory Cells.” Technical Field

[0003] Many examples of improved level assignment and error correction systems for multi-level non-volatile memory cells are disclosed. Background Art

[0004] Non-volatile memory is well known. For example, U.S. Pat. No. 5,029,130 ​​("the '130 patent"), which is incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which is a type of flash memory cell. Such memory cells 110 are Figure 1 1. Each memory cell 110 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 14. A word line terminal 22 (which is typically coupled to a word line) has a first portion disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion extending upward and located over the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by a gate oxide. A bit line 24 is coupled to the drain region 16.

[0005] Memory cell 110 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on word line terminal 22, which causes the electrons on floating gate 20 to tunnel through the intervening insulator via Fowler-Nordheim (FN) tunneling from floating gate 20 to word line terminal 22.

[0006] The memory cell 110 is programmed by source side injection (SSI) with hot electrons (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal 22 and a positive voltage on the source region 14. The electron flow will flow from the drain region 16 to the source region 14. When the electrons reach the gap between the word line terminal 22 and the floating gate 20, the electrons will accelerate and become hot. Due to the electrostatic attraction from the floating gate 20, some of the heated electrons will be injected through the gate oxide onto the floating gate 20.

[0007] The memory cell 110 is read by placing a positive read voltage on the drain region 16 and the word line terminal 22 (which turns on the portion of the channel region 18 below the word line terminal). If the floating gate 20 is positively charged (i.e., the electrons are erased), the portion of the channel region 18 below the floating gate 20 is also turned on, and current will flow through the channel region 18, which is sensed as an erased state or a "1" state. If the floating gate 20 is negatively charged (i.e., programmed by electrons), the portion of the channel region below the floating gate 20 is mostly or completely turned off, and current will not (or very little) flow through the channel region 18, which is sensed as a programmed state or a "0" state.

[0008] Table 1 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 110 for performing read operations, erase operations, and program operations:

[0009] Table 1: Figure 1 Operation of the flash memory unit 110

[0010] WL BL SL Read 2V-3V 0.6V-2V 0V Erase About 11V-13V 0V 0V programming 1V-2V 10.5μA-3μA 9V-10V

[0011] Other split gate memory cell configurations are known as other types of flash memory cells. For example, Figure 2 A quad-gate memory cell 210 is depicted, which includes a source region 14, a drain region 16, a floating gate 20 over a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) over a second portion of the channel region 18, a control gate 28 over the floating gate 20, and an erase gate 30 over the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, except for the floating gate 20, all gates are non-floating gates, meaning that they are electrically connected or capable of being electrically connected to a voltage source. Programming is performed by heated electrons from the channel region 18 that inject themselves into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0012] Table 2 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 210 for performing read operations, erase operations, and program operations:

[0013] Table 2: Figure 2 Operation of the flash memory unit 210

[0014] WL / SG BL CG EG SL Read 1.0V-2V 0.6V-2V 0V-2.6V 0V-2.6V 0V Erase -0.5V / 0V 0V 0V / -8V 8V-12V 0V programming 1V 0.1μA-1μA 8V-11V 4.5V-9V 4.5V-5V

[0015] Figure 3 Depicted is a tri-gate memory cell 310, which is another type of flash memory cell. The memory cell 310 is similar to Figure 2 The memory cell 210 is the same as the memory cell 310 except that the memory cell 310 does not have a separate control gate. Except that no control gate bias is applied, the erase operation (thus erasing by using the erase gate) and the read operation are the same as Figure 2 The operation of is similar. The programming operation is also completed without a control gate bias, and therefore, a higher voltage is applied on the source line during the programming operation to compensate for the lack of control gate bias.

[0016] Table 3 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 310 for performing read operations, erase operations, and program operations:

[0017] Table 3: Figure 3 Operation of the flash memory unit 310

[0018] WL / SG BL EG SL Read 0.7V-2.2V 0.6V-2V 0V-2.6V 0V Erase -0.5V / 0V 0V 11.5V 0V programming 1V 0.2μA-3μA 4.5V 7V-9V

[0019] Figure 4 A stacked gate memory cell 410 is depicted, which is another type of flash memory cell. The memory cell 410 is similar to Figure 1 18 is similar to the memory cell 110 of 210, except that the floating gate 20 extends over the entire channel region 18, and the control gate 22 (which here will be coupled to the word line) extends over the floating gate 20, separated by an insulating layer (not shown). Erasing is performed by FN tunneling of electrons from the FG to the substrate, programming is performed by channel hot electron (CHE) injection at the region between the channel 18 and the drain region 16, by electrons flowing from the source region 14 toward the drain region 16, and a read operation similar to the memory cell 210 with a higher control gate voltage.

[0020] Table 4 depicts typical voltage ranges that may be applied to the terminals of the memory cell 410 and the substrate 12 for performing read operations, erase operations, and program operations:

[0021] Table 4: Figure 4 Operation of the flash memory unit 410

[0022] CG BL SL Substrate Read 2V-5V 0.6V-2V 0V 0V Erase -8V to -10V / 0V FLT FLT 8V-10V / 15V-20V programming 8V-12V 3V-5V 0V 0V

[0023] The methods and devices described herein may be applied to other non-volatile memory technologies such as, but not limited to, FINFET split-gate flash or stacked-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trapped in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trapped in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), CT (charge trap) memory, CN (carbon tube) memory, OTP (two-level or multi-level one-time programmable) and CeRAM (correlated electron ram).

[0024] Figure 5 A block diagram of a prior art memory system 500 suitable for analog multi-level cell (MLC) memory storage (e.g., where the spacing between levels is 1 to 2 varying sigmas and is less strict than digital MLC memory storage) or vector-matrix multiplication neural network applications (e.g., where the spacing between levels is 1 to 2 varying sigmas and is less strict than digital MLC memory storage) is depicted.

[0025] The memory system 500 includes an array 501, a row decoder 502, a high voltage decoder 503, a column decoder 504, a bit line driver 505, an input circuit 506, an output circuit 507, a control logic unit 508, and a bias generator 509. The memory system 500 further includes a high voltage generation block 510, which includes a charge pump 511, a charge pump regulator 512, and a high voltage level generator 513. The memory system 500 also includes a (program / erase or weight adjustment) algorithm controller 514, an analog circuit 515, a control engine 516 (which may include special functions such as arithmetic functions, activation functions, embedded microcontroller logic, but not limited thereto), a test control logic unit 517, and an SRAM block 518 to store data such as intermediate data for input circuits (e.g., activation data) or output circuits (neuron output data) or data for programming (such as data for an entire row or multiple rows).

[0026] Array 501 includes rows and columns of nonvolatile memory cells, such as from Figures 1 to 4 Memory cell 110, 210, 310 or 410.

[0027] The input circuit 506 may include various circuits such as a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter, digital-to-time modulated pulse converter), an AAC (analog-to-analog converter, such as a current-to-voltage converter, a logarithmic converter), a PAC (pulse-to-analog level converter), or any other type of converter. The input circuit 506 may implement one or more of normalization, linear or nonlinear up / down scaling functions, or arithmetic functions. The input circuit 506 may implement a temperature compensation function for the input level. The input circuit 506 may implement an activation function such as a ReLU or a sigmoid. The input circuit 506 may store digital activation data to be applied as an input signal or combined with an input signal during a programming or read operation. The digital activation data may be stored in a register. The input circuit 506 may include circuits for driving array terminals, such as CG, WL, EG, and SL lines, which may include sample-and-hold circuits and buffers. The DAC may be used to convert the digital activation data into an analog input voltage to be applied to the array.

[0028] The output circuit 507 may include circuits such as ITV (current voltage circuit), ADC (analog-to-digital converter for converting neuron analog output into digital bits), AAC (analog-to-analog converter, such as current-voltage converter, logarithmic converter), APC (analog-to-pulse converter, analog-to-time modulated pulse converter), or any other type of converter. The output circuit 507 may convert the array output into activation data. The output circuit 507 may implement an activation function, such as a rectified linear activation function (ReLU) or sigmoid. The output circuit 507 may implement one or more of statistical normalization, regularization, up / down scaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, logarithm) for the neuron output. The output circuit 507 may implement a temperature compensation function for the neuron output or the array output (such as the bit line output) to keep the power consumption of the array approximately constant over a temperature range or to improve the accuracy of the array (neuron) output, such as by keeping the IV slope approximately the same over a temperature range. The output circuit 507 may include registers for storing output data. Output circuit 507 may include error correction logic to repair errors from neuron outputs. Error correction such as Hamming code that can perform single error correction and double error detection (SECDED). Errors such as from noise, data retention, interference, etc.

[0029] For digital MLC memory storage (e.g., where the level spacing is typically 12 sigma, and can be 4 to 6 sigma), the input circuit 506 does not need to include analog circuits such as D / A converters, scaling, activation functions, or arithmetic circuits, and the output circuit 507 does not need to include analog circuits such as A / D (analog to digital) converters, scaling, activation functions, or arithmetic circuits. However, the output circuit 507 may require a multi-level sense amplifier circuit that converts the analog output (cell current) from the selected memory cell into a digital output bit. For example, the output of a 4-level cell can be represented by 2 digital output bits, and the output of a 16-level cell can be represented by 4 digital output bits.

[0030] The algorithm controller 514 includes an ECC (Error Correction Code) engine 519 which may generate ECC data as described below.

[0031] refer to Figure 6 It is common in the prior art to store data in words (such as word 601) within array 501 in analog multi-level memory cells (where each memory cell can store two or more levels using a series of analog voltages or currents to represent each level) or as digital multi-level memory cells (where each memory cell can store two or more levels using discrete levels of voltages or currents to represent each level). The array includes multiple rows and multiple columns. For example, a word may include 128 bits. For a single level cell, 128 bits require 128 cells to store information. A row may consist of multiple words. For example, a row of 4096 cells may include 32 words of 128 bits per word. To select a 128-bit word, a row is selected and 128 of the 4096 columns are selected.

[0032] Figure 6 A single exemplary word 601 is depicted, which in this example includes a certain number of non-volatile memory cells in array 501. The prior art also includes various error detection and error correction schemes that may be implemented by ECC engine 519.

[0033] When the memory system 500 follows the NOR memory structure, one error correction scheme that can be applied is an error correction scheme that utilizes a Hamming code, in which for each bit group (such as word 601), a set of error correction data (such as ECC 602) is generated and stored with the bit group. For example, ECC 602 can be generated by performing a Hamming function on word 601. In this way, each bit in word 601 is supported by ECC 602. During a read operation, the memory system 500 reads word 601 and ECC 602. ECC 602 will indicate whether word 601 contains an error when it is read, and ECC 602 can be used to correct up to one single bit error (e.g., a "1" that has been mistakenly read as a "0" or a "0" that has been mistakenly read as a "1"). ECC 602 has limitations. Specifically, in this example, ECC 602 can only be used to correct single bit errors. If two or more bit errors occur, ECC 602 will not be able to correct these errors.

[0034] In the case where the memory system 500 is used for neural network vector-matrix multiplication, the digital output bits from the output circuit 507 (such as from the ADC output) can be error corrected. In this case, multiple words in multiple rows can be selected instead of a single word. Also, in this case, multiple cells in multiple rows in a single column can be selected instead of a single cell in a single row in a single column.

[0035] Table 5 can be used to illustrate examples of single-bit errors and multi-bit errors:

[0036] Table 5: Multi-level unit assignment

[0037] Unit current DIN0 DIN1 1μA 0 0 2μA 0 1 3μA 1 0 4μA 1 1

[0038] In the example of Table 5, each cell can store two data bits, DINO0 and DIN1, meaning that it can store four analog data levels. The value 00 corresponds to a read current of 1 μA, 01 corresponds to 2 μA, 10 corresponds to 3 μA, and 11 corresponds to 4 μA. If the cell is intended to store a 00 value, but the sensed current is incorrectly detected as 2 μA instead of 1 μA (single-level error), the data will be interpreted as 01 instead of 00, which contains a single bit error. In the absence of other errors, ECC 601 can be used to correct 01 to 00. However, if the cell is intended to store a 00 value, but the sensed current is incorrectly detected as 4 μA instead of 1 μA (multi-level error, e.g., >2 levels), the data will be interpreted as 11 instead of 00, which contains two bit errors. ECC 601 will not be able to correct the data.

[0039] There is a need for improved error correction schemes for multi-level memory cells that are capable of correcting more than a single bit error or more than 2 level errors. Summary of the invention

[0040] Many examples of improved level assignment and error correction systems for multi-level non-volatile memory cells are disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A prior art split gate flash memory cell is depicted.

[0042] Figure 2 Another prior art split gate flash memory cell is depicted.

[0043] Figure 3 Another prior art split gate flash memory cell is depicted.

[0044] Figure 4 Another prior art split gate flash memory cell is depicted.

[0045] Figure 5 A prior art memory system is depicted.

[0046] Figure 6 Prior art data words and associated ECC data are described.

[0047] Fig. 7A , Figure 7B and Figure 7C An improved error correction system is depicted.

[0048] Figure 8 An ECC engine for implementing an improved error correction system is depicted.

[0049] Fig. 9 Describes the use Figure 8 An example of an ECC engine. DETAILED DESCRIPTION

[0050] Fig. 7A , Figure 7B and Figure 7C An improved error correction scheme for multi-level non-volatile memory cells is described.

[0051] exist Fig. 7A and Figure 7B In the example, data to be stored in the array 501 is divided into sub-words, such as half-words, rather than whole words, and two ECC blocks are generated and stored rather than one ECC block. The example depicts half-word 701, half-word 702, ECC block 703 associated with half-word 701, and ECC block 704 associated with half-word 702.

[0052] Figure 7C Describes the Fig. 7A and Figure 7B 703, and one bit in the other halfword in unit n is supported by the ECC code in ECC 704. One physical unit contains one bit for halfword 701 and another bit for halfword 702. For example, unit n contains d bits of halfword 701. n and half word 702 d n If the cell is intended to store a 00 value, but the sensed current is erroneously detected as 4 μA instead of 1 μA, the data will be interpreted as 11 instead of 00, which contains two bit errors. ECC 703 will be used to correct the error in the first bit, and ECC 704 will be used to correct the error in the second bit, with the end result that the erroneous value of 11 will be corrected back to the intended 00 value. This is a significant improvement over the prior art.

[0053] For the 2-bit cell example (where one cell can store 4 levels), a physical cell storing an ECC bit can be combined in the same manner as one physical cell storing one bit for ECC 703 and another bit for ECC 704.

[0054] 7A to 7C The example describes a multi-level cell that can store two bits representing four different levels. One of ordinary skill in the art will appreciate that the same principles can be applied to multi-level cells that store more than two bits by using additional ECC blocks.

[0055] Alternatively, a word may be divided into more than two sub-words, for example four sub-words, wherein ECC is implemented for each sub-word.One physical unit will contain bits for all sub-words.

[0056] Alternatively, multiple words may be combined into a super-word, which is a structure containing two or more words, where ECC is implemented for each word.One physical unit will contain bits for two or more words.

[0057] Figure 8 These concepts are illustrated in Figure 8, the system stores data represented by data packet 801. Data packet 801 is a collection of bits and can be a word, a superword, a subword, or any other data packet. Data packet 801 is provided to ECC engine 800 (which is an example of ECC engine 519 that implements the ECC algorithm described herein), and ECC engine 800 separates data packet 801 into data packets 802-n, ..., 802-1. For example, if n = 2, two data packets 802-2 and 802-1 are generated. If n = 3, three data packets 802-3, 803-3, and 803-1 are generated. If n = 4, four data packets 802-4, 803-3, 803-2, and 803-1 are generated. In one example, n is also equal to the number of bits stored in each memory cell. The ECC engine 800 also generates ECC blocks 803-n, ..., 803-1, wherein a corresponding bit stored in a memory cell is supported by one of the ECC blocks 803-n, ..., 803-1, so that the entirety of the corresponding memory cell is jointly supported by the ECC blocks 803-n, ..., 803-1, wherein a corresponding ECC block in the ECC blocks supports a bit of the corresponding memory cell.

[0058] For example, if data group 801 is a word and n=4, four quarter-word groups (which are sub-word groups) will be generated: data group 802-4 (first quarter-word or first sub-word), 802-3 (second quarter-word or second sub-word), 802-2 (third quarter-word or third sub-word) and 802-1 (fourth quarter-word or fourth sub-word), where the memory cells store bits from the corresponding data groups 802-4, 802-3, 802-2 and 802-1. The ECC engine 800 will also generate ECC blocks 803-4, 803-3, 803-2 and 803-1, where the corresponding bit stored in the memory cell is supported by one of the ECC blocks 803-4, 803-3, 803-2 and 803-1, so that the entirety of the corresponding memory cell is jointly supported by the ECC blocks 803-4, 803-3, 803-2 and 803-1, where the corresponding ECC block in the ECC blocks supports one bit of the corresponding memory cell.

[0059] Fig. 9This example is illustrated where memory cell 901 stores bits from data packet 802-4 (labeled d(802-4)), bits from data packet 802-3 (labeled d(802-3)), bits from data packet 802-2 (labeled d(802-2)), and bits from data packet 802-1 (labeled d(802-1)) supported by ECC blocks 803-4, 803-3, 803-3, and 803-1, respectively. Under this scheme, up to four bit errors (i.e., a first error, a second error, a third error, and a fourth error) in cell 901 can be corrected by ECC blocks 803-4, 803-3, 803-3, and 803-1.

[0060] It should be noted that, as used herein, the terms "above" and "on" both inclusively include "directly on" (no intervening materials, elements, or spaces are provided in between) and "indirectly on" (intervening materials, elements, or spaces are provided in between). Similarly, the term "adjacent" includes "directly adjacent" (no intervening materials, elements, or spaces are provided in between) and "indirectly adjacent" (intervening materials, elements, or spaces are provided in between), "mounted to" includes "directly mounted to" (no intervening materials, elements, or spaces are provided in between) and "indirectly mounted to" (intervening materials, elements, or spaces are provided in between), and "electrically coupled to" includes "directly electrically coupled to" (no intervening materials or elements electrically connecting the elements together) and "indirectly electrically coupled to" (intervening materials or elements electrically connecting the elements together). For example, forming an element "above" a substrate may include directly forming the element on the substrate without intervening materials / elements in between, and indirectly forming the element on the substrate with one or more intervening materials / elements in between.

Claims

1. A system, comprising: A memory array comprising non-volatile memory cells arranged in rows and columns, wherein the non-volatile memory cells of the memory array store a first bit of a first data packet and a second bit of a second data packet, and wherein the first data packet is supported by a first ECC block and the second data packet is supported by a second ECC block.

2. The system of claim 1, wherein the first data grouping is a first halfword and the second data grouping is a second halfword, the first halfword and the second halfword forming a word.

3. The system of claim 1, wherein the first data packet is a first word and the second data packet is a second word, the first word and the second word forming a superword.

4. The system of claim 1, wherein the first ECC block is capable of correcting a first single bit error in the nonvolatile memory cell and the second ECC block is capable of correcting a second single bit error in the nonvolatile memory cell.

5. The system of claim 1, wherein corresponding non-volatile memory cells of the memory array further store third bits of a third data packet supported by a third ECC block and fourth bits of a fourth data packet supported by a fourth ECC block.

6. The system of claim 5, wherein the first grouping is a first quarter-word, the second grouping is a second quarter-word, the third grouping is a third quarter-word, and the fourth grouping is a fourth quarter-word, the first quarter-word, the second quarter-word, the third quarter-word, and the fourth quarter-word forming a word.

7. The system of claim 1, wherein the non-volatile memory cell is a digital multi-level memory cell.

8. The system of claim 1, wherein the non-volatile memory cell is an analog multi-level memory cell.

9. The system of claim 1, wherein the memory array is a vector-matrix multiplication array in a neural network.

10. The system of claim 1, wherein the non-volatile memory cells are split-gate flash memory cells.

11. The system of claim 1 , wherein the non-volatile memory cells are stacked gate flash memory cells.

12. A system, comprising: A memory array comprising non-volatile memory cells arranged in rows and columns, wherein the array stores a plurality of words, wherein respective words are divided into a plurality of sub-words, and respective non-volatile memory cells in the memory array store digital bits belonging to different ones of the plurality of sub-words.

13. The system of claim 12, wherein corresponding non-volatile memory cells of the memory array store a first bit of a first sub-word of the plurality of sub-words and a second bit of a second sub-word of the plurality of sub-words, wherein the first sub-word is supported by a first ECC block and the second sub-word is supported by a second ECC block.

14. The system of claim 13, wherein the first ECC block is capable of correcting a first single bit error in the nonvolatile memory cell and the second ECC block is capable of correcting a second single bit error in the nonvolatile memory cell.

15. The system of claim 13, wherein the corresponding nonvolatile memory cell further stores a third bit of a third sub-word of the plurality of sub-words and a fourth bit of a fourth sub-word of the plurality of sub-words, wherein the third sub-word is supported by a third ECC block and the fourth sub-word is supported by a fourth ECC block.

16. The system of claim 12, wherein the corresponding non-volatile memory cells are digital multi-level memory cells.

17. The system of claim 12, wherein the corresponding non-volatile memory cells are analog multi-level memory cells.

18. The system of claim 12, wherein the array is a vector-matrix multiplication array in a neural network.

19. The system of claim 12, wherein the respective non-volatile memory cells are split-gate flash memory cells.

20. The system of claim 12, wherein the respective non-volatile memory cells are stacked gate flash memory cells.

21. A method comprising: storing a first bit of a first data packet in a nonvolatile memory cell in the array; storing a second bit of a second data packet in the nonvolatile memory unit; storing ECC data for the first bit in a first ECC block in the array; as well as The ECC data for the second bit is stored in a second ECC block in the array.

22. The method of claim 21, wherein the first grouping is a first halfword and the second grouping is a second halfword, the first halfword and the second halfword forming a word.

23. The method of claim 21, wherein the first grouping is a first word and the second grouping is a second word, the first word and the second word forming a superword.

24. The method of claim 21, wherein the first ECC block is capable of correcting a first single bit error in the nonvolatile memory cell and the second ECC block is capable of correcting a second single bit error in the nonvolatile memory cell.

25. The method according to claim 21, comprising: storing a third bit of a third data packet in the non-volatile memory unit; storing a fourth bit of a fourth data packet in the nonvolatile memory unit; storing the ECC data for the third bit in a third ECC block in the array; as well as The ECC data for the fourth bit is stored in a fourth ECC block in the array.

26. The method of claim 25, wherein the first data grouping is a first quarter word, the second data grouping is a second quarter word, the third data grouping is a third quarter word, and the fourth data grouping is a fourth quarter word, the first quarter word, the second quarter word, the third quarter word, and the fourth quarter word forming a word.

27. The method of claim 21, wherein the non-volatile memory cell is a digital multi-level memory cell.

28. The method of claim 21, wherein the non-volatile memory cell is an analog multi-level memory cell.

29. The method of claim 21, wherein the array is a vector-matrix multiplication array in a neural network.

30. The method of claim 21, wherein the non-volatile memory cells are split gate flash memory cells.

31. The method of claim 21, wherein the non-volatile memory cell is a stacked gate flash memory cell.

32. A method comprising: A plurality of words are stored in a memory array comprising nonvolatile memory cells arranged in rows and columns, the plurality of words being respectively divided into a plurality of sub-words, and corresponding ones of the nonvolatile memory cells storing a plurality of digital bits belonging to different sub-words.

33. The method of claim 32, comprising: storing ECC data for a first one of the plurality of digital bits in a first ECC block in the array; as well as ECC data for a second bit of the plurality of digital bits is stored in a second ECC block in the array.

34. The method of claim 33, comprising: using the first ECC block to correct a first error in a bit among the plurality of digital bits; as well as A second error of a bit among the plurality of digital bits in the nonvolatile memory cell is corrected using the second ECC block.

35. The method of claim 33, comprising: storing ECC data for a third bit of the plurality of digital bits in a third ECC block in the array; as well as ECC data for a fourth bit of the plurality of digital bits is stored in a fourth ECC block in the array.

36. The method of claim 35, comprising: using the third ECC block to correct a third error of a bit among the plurality of digital bits; as well as A fourth error of a bit among the plurality of digital bits in the nonvolatile memory cell is corrected using the fourth ECC block.

37. The method of claim 32, wherein the non-volatile memory cell is a digital multi-level memory cell.

38. The method of claim 32, wherein the non-volatile memory cell is an analog multi-level memory cell.

39. The method of claim 32, wherein the array is a vector-matrix multiplication array in a neural network.

40. The method of claim 32, wherein the non-volatile memory cells are split gate flash memory cells.

41. The method of claim 32, wherein the non-volatile memory cell is a stacked gate flash memory cell.

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