Controller and method for copying data from processing unit to memory system

Abstract

A controller for copying data from a processing unit to a memory system, where the processing unit comprises volatile memory, the memory system comprises persistent memory, where the controller comprises a memory address decode module for receiving a first address from the processing unit, the first address is a physical address of data to be copied used by the processing unit. The memory address decoding module is also configured to translate the first address to a second address while taking into account an interleaving setting and a granularity of the persistent memory, where the second address is a shifted version of the first address and for the persistent memory, and where the second address is a shifted version of the first address. And providing the second address to a memory controller of the memory system. The disclosed controller reduces latency during migration of data from the processing unit to the persistent memory device.

Description

Technical Field

[0001] The present invention relates generally to the field of data management, and more particularly to a controller and method for copying data from a processing unit to a memory system. Background Art

[0002] Typically, copying data from a central processing unit (CPU) to a memory subsystem is handled internally by the CPU, including cache mechanisms and memory controller modules. Each CPU socket can contain multiple memory controllers, each of which can have multiple memory channels and are arranged with memory devices attached to the memory controllers. In this setup of CPUs and memory devices, the physical memory address range of each memory device is combined in an interleave set (IS) and processed with the source address decoder (SAD) and target address decoder (TAD) registers of the CPU. The interleave set granularity depends on the built-in addressing scheme of the CPU. The values ​​of the built-in addressing scheme in modern CPUs include 4kB / 16kB sizes. This addressing scheme causes all objects smaller than the interleave set granularity (e.g., 4kB in a page-aligned scenario) to be stored on a single memory device. Data is spread across multiple memory devices only when the size of the object is larger than the interleave set granularity. Persistent storage of objects smaller than the interleave set granularity results in underutilization of the number of memory devices, which further leads to performance degradation. This is due to the nature of non-volatile dual in-line memory module (NVDIMM) devices operating at an error correction code (ECC) block size granularity (typically 256 bytes). Therefore, storing a 2kB object results in 8 write cycles to the memory device (i.e., medium). This limitation is not observed in regular dynamic random-access memory (DRAM) because all writes are buffered on the CPU cache side or within the memory controller (MC) buffer. In the case of persistent memory, these writes cannot be buffered. The reason is that the application relies on the safe storage of data on the medium (i.e., storage medium) and waits until the appropriate memory barrier is released.

[0003] Currently, certain efforts are made to ensure data persistence while migrating data from the CPU to a persistent memory device, such as executing certain instructions in the proper order. For example, an application that uses persistent memory (PMEM / NVDIMM / SCM) for secure object storage is required to ensure reliable data transfer to a persistent domain (sometimes referred to as a power failure safety domain). This is performed using a memory copy operation followed by a cache refresh operation and a memory barrier. The code is executed only after the memory barrier instruction is executed. For small objects, this approach is subject to the bottleneck of the performance of a single persistent memory device. The execution of a 2kB write is performed using the bandwidth and latency profile of a single persistent memory device, either due to the large granularity of the CPU addressing scheme or due to the granularity mismatch between the CPU interleaving set and the ECC block size of the memory device. Therefore, there is a technical problem that the mismatch between the granularity of the CPU addressing scheme and the persistent memory device further leads to increased latency during data migration from the CPU to the persistent memory device.

[0004] Therefore, in light of the above discussion, there exists a need to overcome the above-mentioned shortcomings associated with conventional methods of ensuring data persistence when migrating data from a CPU to a persistent memory device. Summary of the invention

[0005] The present invention provides a controller and method for copying data from a processing unit to a memory system. The present invention provides a solution to the existing problem that the mismatch between the CPU addressing scheme and the granularity of the persistent memory device further leads to increased latency during the migration of data from the CPU to the persistent memory device. The purpose of the present invention is to provide a solution that at least partially solves the problems encountered in the prior art, and to provide an improved controller and an improved method for copying data from a processing unit to a memory system.

[0006] The objects of the invention are achieved by what is presented in the attached independent claim. Advantageous implementations of the invention are further defined in the dependent claims.

[0007] In one aspect, the present invention provides a controller for copying data from a processing unit to a memory system, wherein the processing unit includes a volatile memory, and wherein the memory system includes a persistent memory, wherein the controller includes a memory address decoding module for receiving a first address from the processing unit, the first address being a physical address of the data to be copied used by the processing unit. The memory address decoding module is also used to convert the first address to a second address while taking into account an interleaving setting and a granularity (ECC) of the persistent memory, wherein the second address is a shifted version of the first address and is used for the persistent memory, and the second address is provided to a memory controller of the memory system.

[0008] The disclosed controller bridges the gap between the addressing capability of a processing unit (e.g., a CPU) and the granularity of a persistent memory device, which further reduces latency during migration of data from the processing unit to the persistent memory device. The controller is used to decode the physical address of data copied from the processing unit to the persistent memory of the memory system into a shifted physical address. Thus, the controller ensures persistent storage of the data and propagates the data between multiple persistent memory devices. This further speeds up the distribution of data to multiple persistent memory devices.

[0009] In one implementation, the first address is based on a first interleaving, wherein the conversion of the first address to the second address includes a second interleaving.

[0010] Using the second interleaving during translation of the first address to the second address results in compatibility of addressing schemes of the volatile memory and the persistent memory.

[0011] In another implementation, the interleaving setting includes a granularity (IS) and a number of devices (N).

[0012] By including the granularity and number of devices in the interleaving setting, data can be distributed across multiple persistent memory devices.

[0013] In another implementation, the memory address decoding module is further configured to convert the first address (X) into the second address (f(X)) according to the following formula:

[0014] f(X)=(X mod ECC)+((X / ECC)mod N)*IS+(X / (ECC*N))*ECC

[0015] This facilitates converting the first address to the second address according to the above mathematical formula in order to achieve accuracy.

[0016] In another implementation, the size of the data to be copied is smaller than the interleaving granularity.

[0017] In another implementation, the granularity of the volatile memory is different from the granularity of the persistent memory.

[0018] In another implementation, the memory addressing scheme of the volatile memory is different than the memory addressing scheme of the persistent memory.

[0019] The controller bridges the gap between the memory addressing schemes of volatile memory and persistent memory.

[0020] In another implementation, the controller is included in a Cache and Homing Agent (CPU CHA).

[0021] In another implementation, the controller is included in a core memory controller.

[0022] In another aspect, the present invention provides a method for copying data from a processing unit to a memory system, wherein the processing unit comprises a volatile memory, and wherein the memory system comprises a persistent memory, wherein the method comprises:

[0023] A first address is received from the processing unit, wherein the first address is a physical address used by the processing unit to copy data. The method also includes converting the first address to a second address while taking into account an interleaving setting and a granularity (ECC) of the persistent memory, wherein the second address is a shifted version of the first address and is for the persistent memory. The method also includes providing the second address to a memory controller of the memory system.

[0024] The method realizes all the advantages and technical effects of the controller of the present invention.

[0025] In yet another aspect, the invention provides a computer program product comprising program instructions for performing the method when executed by one or more processors in a controller.

[0026] One or more processors in the controller realize all advantages and effects of the method after executing the method.

[0027] It should be understood that all of the above implementations may be combined.

[0028] It should be noted that all equipment, elements, circuits, units and devices described in this application can be implemented in software or hardware elements or any type of combination thereof. All steps performed by various entities described in this application and the functions to be performed by various entities described are intended to refer to the corresponding entities for performing the corresponding steps and functions. Although in the description of the following specific embodiments, the specific functions or steps to be performed by external entities are not reflected in the description of the specific detailed elements of the entities performing the specific steps or functions, it should be clear to the technician that these methods and functions can be implemented by corresponding hardware or software elements or any combination thereof. It should be understood that the features of the present invention are easy to be combined in various combinations without departing from the scope of the present invention defined by the appended claims.

[0029] Additional aspects, advantages, features and objects of the present invention will become apparent from the accompanying drawings and detailed description of illustrative implementations interpreted in conjunction with the following appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above summary of the invention and the following detailed description of illustrative embodiments may be better understood when read in conjunction with the accompanying drawings. In order to illustrate the present invention, exemplary structures of the present invention are shown in the accompanying drawings. However, the present invention is not limited to the specific methods and tools disclosed herein. In addition, it should be understood by those skilled in the art that the accompanying drawings are not drawn to scale. Where possible, identical elements are represented by identical numerals.

[0031] Embodiments of the present invention will now be described by way of example only with reference to the following figures, in which:

[0032] Figure 1 is a block diagram illustrating migration of data from a processing unit to a memory system by using a controller according to an embodiment of the present invention;

[0033] Figure 2 is an implementation scenario of a controller according to an embodiment of the present invention;

[0034] Figure 3A is a diagrammatic representation of data migration from a processing unit to a plurality of persistent memory devices according to an embodiment of the present invention;

[0035] Figure 3B is a diagram of data migration from a processing unit to a plurality of persistent memory devices according to another embodiment of the present invention;

[0036] Figure 3C is a diagram of data migration from a processing unit to a plurality of persistent memory devices according to yet another embodiment of the present invention;

[0037] Figure 4 This is an implementation scenario of data address conversion according to an embodiment of the present invention;

[0038] Figure 5 is a graphical representation depicting variations in data write latency to a persistent memory device in accordance with an embodiment of the present invention;

[0039] Figure 6 is a representation of a system including a processing unit and a plurality of persistent memory devices according to an embodiment of the present invention;

[0040] Figure 7 is a flow chart of a method for copying data from a processing unit to a memory system according to an embodiment of the present invention.

[0041] In the drawings, underlined numbers are used to indicate the item in which the underlined number is located or an item adjacent to the underlined number. Non-underlined numbers are associated with the item identified by the line that associates the non-underlined number with the item. When a number is not underlined and has an associated arrow, the non-underlined number is used to identify the general item that the arrow points to. DETAILED DESCRIPTION

[0042] The following detailed description describes embodiments of the invention and ways in which these embodiments may be implemented. Although some modes of implementing the invention have been disclosed, those skilled in the art will recognize that there may be other embodiments for implementing or practicing the invention.

[0043] Figure 1 is a block diagram illustrating migration of data from a processing unit to a memory system by using a controller according to an embodiment of the present invention. Figure 1 , a block diagram 100 is shown showing a controller 102 for copying data from a processing unit 104 to a memory system 106. The processing unit 104 includes a volatile memory 108, and the memory system includes a persistent memory 110 and a memory controller 112. The controller 102 includes a memory address decoding module 114.

[0044] Controller 102 may include appropriate logic, circuits, and / or interfaces for copying data from processing unit 104 to memory system 106. In one implementation, controller 102 may be used to execute instructions stored in memory system 106. Examples of controller 102 may include, but are not limited to, microcontrollers, microprocessors, complex instruction set computing (CISC) processors, application-specific integrated circuits (ASIC) processors, reduced instruction set (RISC) processors, very long instruction word (VLIW) processors, data processing units, and other processors or control circuits. In addition, controller 102 may refer to one or more separate processors according to the application scenario. In one implementation, controller 102 may be included in processing unit 104.

[0045] The processing unit 104 may include suitable logic, circuitry, and / or interfaces for having, for example, Figure 2 A. The processing unit 104 may also be referred to as a central processing unit (CPU). In one implementation, the processing unit 104 may refer to one or more processing devices.

[0046] The memory system 106 may include suitable logic, circuitry, and / or interfaces that may be operable to store data and instructions executable by the controller 102 or processing unit 104 .

[0047] The volatile memory 108 may include suitable logic, circuitry, and / or interfaces for storing data and instructions executable by the processing unit 104. Examples of implementations of the volatile memory 108 include, but are not limited to, electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), read only memory (ROM), hard disk drive (HDD), flash memory, solid-state drive (SSD), or CPU cache. The volatile memory 108 may store an operating system or other program product (including one or more operating algorithms) to operate the computing device.

[0048] Persistent memory 110 may include appropriate logic, circuitry, and / or interfaces for storing data structures so that the stored data structures may continue to be accessed using memory instructions or memory application programming interfaces (APIs) even after the process that created or last modified the data structures has ended. Persistent memory 110 is similar to conventional memory, but the persistent memory is persistent across server crashes, such as a hard drive or solid-state drive (SSD). However, persistent memory 110 is byte addressable like conventional memory and may be accessed using remote direct memory access (RDMA). The use of persistent memory 110 provides fast access to data stored therein.

[0049] In operation, controller 102 is used to copy data from processing unit 104 to memory system 106, wherein processing unit 104 includes volatile memory 108, and wherein memory system 106 includes persistent memory 110, wherein controller 102 includes memory address decoding module 114 for receiving a first address from processing unit 104, the first address being a physical address of the data to be copied used by processing unit 104. Memory address decoding module 114 is used to receive a first address of data to be copied from processing unit 104 to persistent memory 110 of memory system 106. The first address is a physical address of the data in volatile memory 108 of processing unit 104.

[0050] The memory address decoding module 114 is also used to convert the first address to a second address, taking into account the interleaving setting and the granularity (ECC) of the persistent memory 110, wherein the second address is a shifted version of the first address and is used for the persistent memory 110. The memory address decoding module 114 is used to receive information about the interleaving setting of the processing unit 104 and the granularity of the persistent memory 110 (e.g., error correction code (ECC) block size) to convert the first address to the second address. The second address is a shifted (or decoded) version of the first address. In addition, the second address may correspond to a physical address of data copied from the processing unit 104 to the persistent memory 110 of the memory system 106.

[0051] The memory address decoding module 114 is further configured to provide the second address to the memory controller 112 of the memory system 106. The second address of the data is provided to the memory controller 112 of the memory system 106 for copying the data to the persistent memory 110 of the memory system 106.

[0052] According to one embodiment, the first address is based on a first interleave, wherein the translation of the first address to the second address includes a second interleave. The first address is based on the first interleave corresponding to an interleave set of processing unit 104. More specifically, the first interleave corresponds to an interleave set (or granularity) of volatile memory 108 of processing unit 104. Moreover, the translation of the first address to the second address includes a second interleave corresponding to an interleave set of persistent memory 110.

[0053] According to an embodiment, the granularity of the volatile memory 108 is different from the granularity of the persistent memory 110. The memory address decoding module 114 is used to distinguish the granularity of the volatile memory 108 (i.e., the volatile memory 108 region) from the granularity (or ECC block size) of the persistent memory 110 (i.e., the persistent memory 110 region). Alternatively, the memory address decoding module is used to resolve the granularity mismatch between the volatile memory 108 of the processing unit 104 and the persistent memory 110 of the memory system 106 by introducing an additional memory interleaving layer that bridges the gap between the addressing capability of the processing unit 104 and the granularity of the persistent memory 110.

[0054] According to an embodiment, the memory addressing scheme of the volatile memory 108 is different from the memory addressing scheme of the persistent memory 110. The memory addressing scheme of the volatile memory 108 is different from the memory addressing scheme of the persistent memory 110. Therefore, the memory address decoding module 114 is used to fill the gap between the memory addressing schemes of the volatile memory 108 and the persistent memory 110.

[0055] According to an embodiment, the interleave setting includes a granularity (IS) and a number of devices (N). The interleave setting (ie, a first interleave and a second interleave) includes a granularity of the volatile memory 108 and the persistent memory 110 and a number of devices (N).

[0056] According to one embodiment, the size of the data to be copied is smaller than the interleaving granularity. The size of the data to be copied from the volatile memory 108 to the persistent memory 110 is smaller than the interleaving granularity of the persistent memory 110 (ie, the ECC block size).

[0057] According to an embodiment, the controller 102 is included in a Cache and Homing Agent (CPUCHA). In one implementation, the controller 102 may be included in a Cache and Homing Agent. Typically, a cache and homing agent (CHA) is defined as a unit found within a core tile (i.e., the tile of the controller 102) that maintains cache consistency between tiles. The CHA is also used to interface with a converged / commonmesh stop (CMS). A CMS is typically defined as a mesh stop station that facilitates the interface between tiles and a switch fabric.

[0058] According to an embodiment, the controller 102 is included in a core memory controller. In another implementation, the controller 102 may be included in a core memory controller.

[0059] Thus, the controller 102 bridges the gap between the addressing capability of the processing unit 104 (i.e., the CPU) and the granularity of the persistent memory device (e.g., the persistent memory 110), which further reduces the latency during the migration of data from the processing unit 104 to the persistent memory device (e.g., the persistent memory 110). The controller 102 is used to decode the physical address of the data copied from the processing unit 104 to the persistent memory 110 of the memory system 106 into the shifted physical address. Thus, the controller 102 ensures the persistent storage of the data and spreads the data among the multiple persistent memory devices. This further speeds up the distribution of the data to the multiple persistent memory devices.

[0060] Figure 2 This is an implementation scenario of a controller according to an embodiment of the present invention. Figure 1 Component Description Figure 2 . refer to Figure 2 , showing the controller 102 ( Figure 1 Implementation scenario 200 of ).

[0061] In the implementation scenario 200, the controller 102 is included in a cache and homing agent (CPU CHA). The memory address decoding module 114 is used to distinguish the functions of the volatile memory 108 and the persistent memory 110. The memory address decoding module 114 is used to receive a first address of data to be copied from the processing unit 104 to the persistent memory 110. The first address of the data corresponds to a physical address in the processing unit 104. The memory address decoding module 114 is used to decode the first address of the data into a second address, and the second address is a shifted physical address of the data copied to the persistent memory 110.

[0062] According to an embodiment, the memory address decoding module 114 is further configured to convert the first address (X) into a second address (f(X)) according to equation (1):

[0063] f(X)= (X mod ECC) + ((X / ECC) mod N)*IS + (X / (ECC*N))*ECC (1)

[0064] Among them, X——physical address

[0065] ECC - device write granularity (usually ECC block size)

[0066] N——Number of devices belonging to the interleaving set

[0067] IS - Interleaving Set Granularity

[0068] mod——modulus operation; / -division without remainder operation

[0069] To convert the first address to the second address, the memory address decoding module 114 accepts various inputs, such as the interleaving granularity (i.e., ECC block size) of the persistent memory 110, the interleaving set setting of the processing unit 104, and the address range of the persistent memory 110. The second address of the data (i.e., the shifted physical address) is provided to the memory controller 112 of the memory system 106. In this way, each access to the persistent memory 110 passes through the memory address decoding module 114, which is used to propagate the input data to the available persistent memory modules.

[0070] Figure 3A is a diagram of data migration from a processing unit to multiple persistent memory devices according to an embodiment of the present invention. Figure 1 and Figure 2 Component Description Figure 3A . refer to Figure 3A, a diagram 300A is shown depicting a processing unit 104 including a plurality of cores 302. Also shown are a controller 102, a memory controller 112 (also denoted as MC), and a plurality of persistent memory devices 304 (also denoted as PMEM).

[0071] Each persistent memory device in the plurality of persistent memory devices 304 corresponds to ( Figure 1 The processing unit 104 including the plurality of cores 302 may also be referred to as a central processing unit (CPU) including the plurality of cores 302. Each of the plurality of cores 302 may have a volatile memory (e.g., Figure 1 In diagram 300A, controller 102 is associated with multiple cores 302 of processing unit 104. In addition, controller 102 is used to copy data from multiple cores 302 to memory controller 112 and then to multiple persistent memory devices 304. To copy the data, memory address decoding module 114 ( Figure 3A 304) is used to map the physical addresses of the data to be copied from the plurality of cores 302 to the plurality of persistent memory devices 304 into the shifted physical addresses. The shifted physical addresses correspond to the addresses of the data to be copied from the plurality of cores 302.

[0072] In another implementation, instead of controller 102 , memory address decoding module 114 may be associated with multiple cores 302 of processing unit 104 and may copy data from multiple cores 302 to multiple persistent memory devices 304 by mapping physical addresses of the data.

[0073] Figure 3B is a diagram of data migration from a processing unit to multiple persistent memory devices according to another embodiment of the present invention. Figure 1 , Figure 2 and Figure 3A Component Description Figure 3B . refer to Figure 3B , diagram 300B is shown, which depicts a processing unit 104 including multiple cores 302.

[0074] In diagram 300B, controller 102 is associated with each of the plurality of cores 302 of processing unit 104. In addition, controller 102 is operable to copy data from each of the plurality of cores 302 to the plurality of persistent memory devices 304 by decoding the physical address of the data to be copied from each of the plurality of cores 302 to the plurality of persistent memory devices 304.

[0075] Figure 3CFIG. 1 is a diagram of data migration from a processing unit to multiple persistent memory devices according to another embodiment of the present invention. Figure 1 , Figure 2 , Figure 3A and Figure 3B Component Description Figure 3C . refer to Figure 3C , a diagram 300C is shown depicting a processing unit 104 including a plurality of cores 302. There is also an exclusive write section (EWS) 306 associated with the processing unit 104, each of the plurality of cores 302, and the memory controller 112.

[0076] In diagram 300C, EWS 306 is associated with each of the plurality of cores 302 of processing unit 104. In addition, EWS 306 is used to copy data from each of the plurality of cores 302 to the plurality of persistent memory devices 304 by decoding the physical address of the data to be copied from each of the plurality of cores 302 to the plurality of persistent memory devices 304.

[0077] Figure 4 This is an implementation scenario of data address conversion according to an embodiment of the present invention. Figure 1 , Figure 2 , Figure 3A , Figure 3B and Figure 3C Component Description Figure 4 . refer to Figure 4 , illustrates an implementation scenario 400 of address translation of data to be copied from processing unit 104 to memory system 106. Implementation scenario 400 includes operations 402 to 408.

[0078] At operation 402, the application saves one or more objects of size 2kB.

[0079] At operation 404, one or more objects of size 2kB are copied using a memory copy instruction (ie, memset / mm256_xx / ...).

[0080] At operation 406, one or more objects of size 2kB are copied from the refresh domain to the persistent domain according to the definition of the power fail safe domain (eg, using instructions clflush, clflushopt).

[0081] At operation 408, a memory barrier instruction (ie, sfence, mfence, ...) is used.

[0082] Conventionally, operations 402 to 408 are performed using sequential writes of ECC-sized blocks (typically 256B). In the case of a 2kB write, the conventional approach requires 8 writes, each of which takes approximately 600ns using existing Optane persistent memory devices. In contrast to conventional approaches, the proposed approach (i.e., using controller 102 to copy data from processing unit 104 to memory system 106) distributes writes of one or more objects of size 2kB across all available persistent memory (PMEM) devices. The same 2kB object write can be implemented in 2 device write cycles using "x6" interleaving, resulting in a 4x acceleration. In this way, by using the memory address decoding function, the persistent storage of data is spread across multiple persistent memory devices. Therefore, the memory addressing decoding function is suitable for systems equipped with persistent memory (e.g., persistent memory 110) and enables these systems to improve the performance of writes to the medium. Memory reads may also be positively affected.

[0083] Figure 5 is a graphical representation of a variation in data write latency to a persistent memory device according to an embodiment of the present invention. Figure 1 , Figure 2 , FIG. 3A to FIG. 3C as well as Figure 4 Component Description Figure 5 . refer to Figure 5 , shows a graphical representation 500 that depicts a persistent memory device (e.g., Figure 1 1. The graphical representation 500 shows the variation of data write latency for persistent storage 110. The graphical representation 500 includes an X-axis 502 representing the size of a data object in bytes (B). The graphical representation 500 also includes a Y-axis 504 representing the number of sequential writes required.

[0084] In graphical representation 500, first curve 506 represents conventional performance, where no controller is used to copy data from a processing unit to a memory system. A second curve 508 is also shown, which represents the performance of the proposed method, where controller 102 is used to copy data from processing unit 104 to memory system 106 by mapping the physical address of the data to be copied from volatile memory 108 of processing unit 104 to persistent memory 110 of memory system 106. Second curve 508 has lower data write latency (i.e., improved latency) compared to first curve 506. Graphical representation 500 is obtained by considering a persistent memory topology consisting of six persistent memory devices, 256B ECC block size, 4kB interleaved set granularity.

[0085] Figure 6is a system representation including a processing unit and a plurality of persistent memory devices according to an embodiment of the present invention. Figure 1 , Figure 2 , FIG. 3A to FIG. 3C , Figure 4 as well as Figure 5 Component Description Figure 6 . refer to Figure 6 , a system 600 is shown including a processing unit 104 and an input / output (I / O) unit 604, the processing unit including a source address decoder (SAD) / target address decoder (TAD) register 602. The processing unit 104 has a memory controller (MC) 112 attached, which is also connected to a plurality of persistent memory devices 304 via a compute express link (CXL) switch 606. An application 608 and a persistent memory middleware library 610 are also shown.

[0086] Application 608 provides consecutive blocks of data.

[0087] The persistent storage middleware library 610 is responsible for providing persistent guarantees for data transmission. The persistent storage middleware library 610 can be implemented in a separate application. The persistent storage middleware library 610 will cause additional overhead for address calculation.

[0088] The presence of the SAD / TAD registers 602 and logic within the cache homing agent (CHA) provides potential for improved performance gains.

[0089] System 600 is applicable only to a single CPU (i.e., processing unit 104), wherein multiple persistent memory devices 304 are connected via memory controller 112. Multiple persistent memory devices 304 can also be connected to processing unit 104 via CXL switch 606 or via double data rate (DDR) memory. Implementation scenarios with multiple interconnected CPU sockets are also theoretically feasible. Nevertheless, due to other negative effects of crossing CPU boundaries, implementation scenarios with multiple interconnected CPU sockets are not applicable in practice. For application scenarios, any application that relies on ensuring data persistence can use system 600. Typically, in order to work with persistent memory devices, many applications use middleware software, such as a persistent memory development kit (PMDK). Such applications can use system 600. Another application of system 600 is a logging function within a database.

[0090] Figure 7 is a flow chart of a method for copying data from a processing unit to a memory system according to an embodiment of the present invention. Figure 1 , Figure 2 , FIG. 3A to FIG. 3C , Figure 4 , Figure 5 as well as Figure 6 Component Description Figure 7 . refer to Figure 7 , a method 700 for copying data from a processing unit 104 to a memory system 106 is shown. The method 700 includes steps 702, 704, and 706. Step 704 includes two sub-steps 704A and 704B.

[0091] A method 700 is provided for copying data from a processing unit 104 to a memory system 106. The processing unit 104 includes a volatile memory 108 and the memory system 106 includes a persistent memory 110. The method 700 is provided to bridge the gap between the addressing capability of the processing unit 104 and the granularity of the persistent memory device (i.e., the persistent memory 110). The volatile memory 108 has a granularity that is different from the granularity of the persistent memory 110. The method 700 is provided to bridge the gap between the granularity of the volatile memory 108 and the persistent memory 110 in the following manner.

[0092] At step 702, method 700 includes receiving a first address from processing unit 104, the first address being a physical address of data to be copied used by processing unit 104. The first address corresponds to a physical address of data to be copied from volatile memory 108 of processing unit 104 to persistent memory 110 of memory system 106.

[0093] In sub-step 704A of step 704, method 700 further includes converting the first address to a second address while taking into account the interleaving setting. Figure 2 The first address is converted to the second address according to equation (1) described in detail in . The conversion of the first address to the second address includes an interleaving arrangement of the volatile memory 108 and the persistent memory 110 .

[0094] In sub-step 704B of step 704, method 700 further includes converting the first address to a second address, taking into account the granularity (ECC) of persistent memory 110, wherein the second address is a shifted version of the first address and is for persistent memory 110. The second address is a shifted (or decoded) version of the first address. In addition, the second address may correspond to a physical address of data copied from processing unit 104 to persistent memory 110 of memory system 106.

[0095] At step 706 , the method 700 further includes providing the second address to the memory controller 112 of the memory system 106 . The second address of the data is provided to the memory controller 112 of the memory system 106 for copying the data to the persistent memory 110 of the memory system 106 .

[0096] Steps 702 to 706 are merely illustrative, and other alternatives may be provided in which one or more steps are added, one or more steps are deleted, or one or more steps are provided in a different order without departing from the scope of the claims herein.

[0097] In one aspect, a computer program is provided, the computer program product including program instructions for performing method 700 when executed by one or more processors in controller 102. In another aspect, a computer system is provided, including one or more processors in a controller (e.g., controller 102) and one or more memories (e.g., volatile memory 108 and persistent memory 110), the one or more memories (i.e., volatile memory 108 and persistent memory 110) storing program instructions, which, when executed by one or more processors in the controller (i.e., controller 102), cause the one or more processors in the controller (i.e., controller 102) to perform method 700. In yet another aspect, the present invention provides a non-transitory computer-readable medium having computer-implemented instructions stored thereon, which, when executed by a computer, cause the computer to perform the operations of method 700.

[0098] Without departing from the scope of the invention as defined by the appended claims, the embodiments of the invention described above may be modified. Expressions such as "including", "comprising", "incorporating", "being / being" etc. used to describe and claim the present invention are intended to be interpreted in a non-exclusive manner, i.e., allowing items, components or elements that are not explicitly described to also exist. References to the singular should also be interpreted as involving the plural. The word "exemplary" used herein means "as an example, instance or illustration". Any embodiment described as "exemplary" is not necessarily interpreted as being more preferred or more advantageous than other embodiments, and / or excluding the combination of the features of other embodiments. The word "optionally" used herein means "provided in some embodiments and not provided in other embodiments". It should be understood that certain features of the present invention described in the context of a single embodiment for the sake of clarity may also be provided in a single embodiment by combination. On the contrary, the various features of the present invention described in the context of a single embodiment for the sake of clarity may also be provided individually or in any suitable combination or as any other described embodiment of the present invention.

Claims

1. A controller (102) for copying data from a processing unit (104) to a memory system (106), characterized in that The processing unit (104) includes a volatile memory (108), the memory system (106) includes a persistent memory (110), wherein the controller (102) includes a memory address decoding module (114), the memory address decoding module being configured to: receiving a first address from the processing unit (104), wherein the first address is a physical address used by the processing unit (104) to copy data; Convert the first address to a second address, taking into account Interweaving settings, a granularity of the persistent memory (110), wherein the second address is a shifted version of the first address and is used for the persistent memory (110); The second address is provided to a memory controller (112) of the memory system (106).

2. The controller (102) according to claim 1, characterized in that The first address is based on a first interleave, wherein the conversion of the first address to the second address comprises a second interleave.

3. The controller (102) according to claim 1 or 2, characterized in that: The interleaving settings include granularity and number of devices.

4. The controller (102) according to any one of the preceding claims, characterized in that The memory address decoding module (114) is also used for: The first address is converted to the second address according to the following formula: f(X)=(X mod ECC)+((X / ECC)mod N)*IS+(X / (ECC*N))*ECC 5. The controller (102) according to any one of the preceding claims, characterized in that The size of the data to be copied is smaller than the interleaving granularity.

6. The controller (102) according to any one of the preceding claims, characterized in that The granularity of the volatile memory (108) is different from the granularity of the persistent memory (110).

7. The controller (102) according to any one of the preceding claims, characterized in that The memory addressing scheme of the volatile memory (108) is different from the memory addressing scheme of the persistent memory (110).

8. The controller (102) according to any one of the preceding claims, characterized in that The controller (102) is included in a cache and homing agent (CPU CHA).

9. The controller (102) according to any one of claims 1 to 7, characterized in that: The controller (102) is included in a core memory controller.

10. A method (700) for copying data from a processing unit (104) to a memory system (106), characterized in that: The processing unit (104) includes a volatile memory (108), the memory system (106) includes a persistent memory (110), wherein the method (700) includes: receiving a first address from the processing unit (104), wherein the first address is a physical address used by the processing unit (104) to copy data; Convert the first address to a second address, taking into account Interweaving settings, a granularity of the persistent memory (110), wherein the second address is a shifted version of the first address and is used for the persistent memory (110); The second address is provided to a memory controller (112) of the memory system (106).

11. A computer program product, characterized in that The computer program product comprises program instructions for performing the method (700) according to claim 10 when executed by one or more processors in the controller (102).

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