Time efficient implementation of cache replacement policies

Abstract

A cache includes: a plurality of groups, wherein each group has a plurality of respective ways; and replacement logic configured to implement a two-stage least recently used (LRU) replacement calculation. The two-stage LRU replacement computation causes the cache to perform a first stage during which the cache computes the LRU path of the group and a second stage during which the cache updates the LRU data structure with information of the transactional access path.

Description

Background Art

[0001] The present description relates to systems having integrated circuit devices.

[0002] A cache is a device that stores data retrieved from memory or data to be written to memory for one or more different hardware devices in the system. The hardware devices can be different components integrated into a system on a chip (SOC). In this specification, the device that provides read requests and write requests through a cache will be referred to as a client device. Some caches serve memory requests of multiple different client devices integrated into a single system.

[0003] Caches can be used to reduce power consumption by reducing overall requests to main memory. Additionally, as long as client devices can access the data they need in cache, further power savings can be achieved by placing main memory and the data path to main memory into a low power state. Thus, cache usage is related to overall power consumption, and increasing cache usage results in a reduction in overall power consumption. Thus, devices that rely on battery power, such as mobile computing devices, can extend their battery life by increasing cache usage of integrated client devices.

[0004] The cache placement policy determines how memory blocks are placed in the cache. For a set-associative cache, a least recently used (LRU) replacement policy may be used. In a conventional LRU replacement implementation, the system schedules all cache replacement operations for a transaction in the same clock cycle. However, because the execution time of most operations in the LRU replacement policy increases with the number of cache lines in a cache set, it may be challenging to schedule all operations of a transaction into a single clock cycle for a set-associative cache with high associativity. Summary of the invention

[0005] This specification describes a cache system that includes multiple sets of cache lines and replacement logic that is configured to implement a two-phase least recently used (LRU) replacement strategy. By performing LRU replacement in two phases, the cache system overcomes some limitations of conventional LRU replacement implementations and improves the time efficiency of executing multiple cache transactions.

[0006] In one particular aspect of the specification, a cache system is provided. The cache system includes: a plurality of groups, each group having a plurality of corresponding ways; and replacement logic, the replacement logic being configured to implement a two-stage least recently used (LRU) replacement calculation. The two-stage LRU replacement calculation causes the cache to perform a first stage during which the cache calculates the LRU way of the group and a second stage during which the cache updates the LRU data structure with information of the transaction access way.

[0007] In some implementations of a cache system, the cache is configured to perform a two-stage LRU replacement calculation in consecutive clock cycles.

[0008] In some implementations of a cache system, the cache is configured to implement an LRU replacement policy using the calculated LRU way.

[0009] In some implementations of the cache system, the replacement logic includes a plurality of nodes storing respective way values ​​for each group, and wherein performing the second phase includes shifting the stored way values ​​between the nodes for the groups.

[0010] In some implementations of the cache system, to perform the second phase, the cache system is configured to update each node with data that it already stores for the group or data that was displaced from another node.

[0011] In some implementations of the cache system, when executing the first phase of the current transaction, in response to a risk condition caused by the second phase of the previous transaction being executed on the same specific group, the cache system executes the risk

[0012] In some implementations of the cache system, performing risk resolution for the current transaction includes: in response to determining that all corresponding ways in the particular group are eligible for replacement, determining an LRU way for the current transaction based on the LRU data structure after the LRU data structure has been updated for a previous transaction.

[0013] In some implementations of the cache system, the replacement logic is configured to, in response to determining that not all corresponding ways in the corresponding ways in a particular group are eligible for replacement: determine an eligible node for which risk has been resolved from a plurality of nodes; select an eligible node from the eligible nodes for which risk has been resolved; and determine the LRU way using a way value stored in the selected eligible node.

[0014] In some implementations of the cache system, the replacement logic is configured to begin determining the eligible node for which the risk has been resolved from the plurality of nodes before the second phase of the previous transaction has completed.

[0015] In some implementations of the cache system, determining a qualified node with resolved risk from a plurality of nodes includes: generating unresolved node data identifying the qualified node from a plurality of nodes based on qualified ways and the LRU data structure before the LRU data structure has been updated by the second phase of a previous transaction; and shifting the unresolved node data using shift information generated during the second phase of the previous transaction to generate resolved risk node data identifying the qualified node with resolved risk.

[0016] In another aspect of the present specification, a method for performing LRU replacement calculation is provided. The method is performed by the above cache system and includes the above operations.

[0017] The subject matter described in this specification can be implemented in a specific implementation to achieve one or more advantages. For example, in some implementations, by executing a two-stage LRU replacement strategy in two consecutive clock cycles, the cache system improves the time efficiency of executing multiple cache transactions. In addition, in some implementations, when a risk arises between a current transaction and a previous transaction, the system can start a risk resolution process for the current transaction before the LRU update of the previous transaction has been completed to minimize the time impact of risk resolution. The increased timing efficiency can help implement an advanced LRU replacement strategy for a set-associative cache with a high associativity number.

[0018] The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 An example of a cache system is shown.

[0020] Figure 2 is a flow diagram illustrating an example process for performing a cache transaction.

[0021] Figure 3 An example process for performing multiple cache transactions is shown.

[0022] Figure 4A An example data structure of LRU data for a group is shown.

[0023] Figure 4B An example process for updating LRU data is shown.

[0024] Figure 5 is a flow chart illustrating an example process for performing risk resolution for cache transactions.

[0025] Figure 6 An example hardware implementation of an LRU cache replacement policy is shown.

[0026] Figure 7 An example hardware implementation of cache risk resolution is shown.

[0027] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0028] A cache placement policy determines how memory blocks are placed in a cache. This description focuses on a set-associative cache placement policy, where the cache is divided into multiple sets, and each set includes multiple cache lines.

[0029] Figure 1 Cache system 100 is shown. Cache system 100 may be part of a processing system such as a system on a chip (SOC) communicatively coupled to a memory device. Specifically, cache system 100 is a set associative cache and includes a plurality of sets 110. Each set 110 includes a plurality of corresponding cache lines 114.

[0030] A cache line, also called a way, is a unit of data transfer between a cache and another memory device, such as the main memory of a processing system. All cache lines in a group have a fixed size, for example, 64 bytes. When reading or writing anywhere in a 64-byte region, the processor reads or writes the entire cache line.

[0031] The cache system 100 also includes a cache transaction controller 120 that manages cache transactions of the cache system 100. In this specification, a cache transaction refers to a process of accessing the cache system using a request for a specific memory block. Figure 2An example cache transaction process is described. Typically, the cache transaction controller 120 uses index bits derived from the address of the memory block to map the requested memory block to a particular group 110. The cache transaction controller 120 then performs a tag check to determine whether the requested memory block has already been placed in one of the cache lines 110. The tag check is performed based on tag data 130 that stores tags for all cache lines 114 of the memory device. Specifically, the cache transaction controller 120 compares the tag bits of the address of the memory block with the tags of the cache lines 114 in the mapped group 110. If the memory block tag matches any of the cache lines in the mapped group, the tag check returns a "cache hit". Otherwise, the tag check returns a "cache miss".

[0032] In the case of a "cache miss", the cache transaction controller 120 requests a memory block from another memory device, such as from the main memory of the processing system or from a next level cache of the processing system, and places the memory block in the selected cache line 114 of the mapped group 110. If all cache lines 114 in the mapped group 110 have been allocated (i.e., previously placed with corresponding memory blocks), the cache transaction controller 120 replaces the block stored in the cache line identified by the replacement policy with the new data read from the external memory device.

[0033] Specifically, the system 100 uses the cache replacement logic 125 to implement a least recently used (LRU) replacement policy that The least recently used cache line 114 is selected for replacement in each way. This process requires keeping track of the recency of use of each cache line 114 relative to all other cache lines in a particular group 110. Therefore, the system 100 maintains LRU data 140 that specifies recency information for each cache line 114 in each group 110 of the system 100.

[0034] The cache replacement logic 125 implements the LRU replacement calculation in two phases. During the first phase, the cache system 100 determines the least recently used cache line (referred to as the LRU way in this application) based at least on the current LRU data 140. The LRU way is selected for replacement. During the second phase, the cache system 100 updates the LRU data 140 based on the information of the transaction access way so that the LRU data 140 is up to date for the next transaction.

[0035] Figure 2An example process 200 for performing a cache transaction is shown. For convenience, process 200 will be described as being performed by a process such as Figure 1 The cache system 100 performs a cache system execution.

[0036] Prior to executing process 200, the system has determined the set for a cache transaction. The output of process 200 specifies a particular cache line in the set (referred to in this specification as an "access way") for accessing the memory block specified in the cache transaction request.

[0037] After receiving a cache transaction request specifying a memory block, the system performs a tag check in step 210. Specifically, the system compares the tag bits associated with the address of the memory block with the tags of the cache lines in the group.

[0038] In step 220, the system determines whether the tag check result is a cache HIT or a MISS. That is, if the tag bits associated with the address of the memory block match the tag of one of the cache lines in the group, the system determines that the tag check result is a cache HIT. For convenience, the cache line with a tag that matches the memory block tag is referred to as a "HIT way". If the tag bits associated with the address of the memory block do not match any of the tags of the cache lines in the group, the system determines that the tag check result is a MISS.

[0039] If the system determines that the tag check result is a cache HIT, the system uses the HIT way for the transaction and therefore assigns the access way to the HIT way in step 230 .

[0040] If the system determines that the tag check result is a cache MISS, this means that the data in the specified memory block has not been loaded into any of the cache lines in the group, and the system needs to request the data from the next level of the memory hierarchy and load the data into the selected cache line in the group.

[0041] In step 240, the system checks for cache lines in the group that are not occupied. For convenience, unoccupied cache lines are referred to as "free ways". If the system determines in step 250 that a free way is available, then for a cache miss scenario, the system uses the free way to execute the transaction. That is, in step 260, the system assigns the access way to the free way.

[0042] If the system determines in step 250 that a free way is not available, this means that all cache lines in the set are already occupied, and the system needs to identify a cache line for replacement through a replacement policy and place data in the cache line identified for replacement.

[0043] Because the system implements an LRU replacement policy, the system calculates the LRU way in step 270. In step 280, the system assigns the access way to the LRU way.

[0044] Once the access way is determined (by steps 230, 260, or 280), the system updates the LRU data in step 290. The LRU data tracks the recency of cache lines in a group, i.e., specifies how recently a particular cache line has been accessed for a transaction compared to other cache lines in the group. FIG. 4A to FIG. 6 Describe the update process in more detail.

[0045] In the conventional LRU replacement implementation, the system replaces the transaction Figure 2 All operations shown are scheduled in the same clock cycle. In this case, the time required to complete these operations can be estimated as:

[0046] here, represents the timing depth used to complete <operation>, and C is the constant time delay of the operation, such as selecting Figure 2 One of the HIT way / free way / compute LRU way branches shown.

[0047] Note that as the total number of cache lines in the set increases, the three entries , and The time taken to determine the access way increases with each entry in the cache. That is, the time taken to determine the access way increases with the cache associativity. When the cache associativity is significant (e.g., when the total number of cache lines in a group exceeds a threshold), it may be challenging to schedule all operations of a transaction into a single clock cycle.

[0048] In order to overcome the limitations of conventional LRU replacement implementations, the system described in this specification uses a 2-phase solution to perform LRU replacement. That is, the system implements a two-phase LRU replacement strategy in consecutive clock cycles.

[0049] In the first phase, the system determines the access way. In the second phase, the system updates the LRU data.

[0050] Therefore, the time required for the first clock cycle is:

[0051] The time required for the second clock cycle is:

[0052] By splitting the time required to perform the operation of a transaction into two clock cycles, the system can generally improve the time efficiency of performing cache transactions. For example, after the system has determined the access path in the first phase of a particular transaction, the system can start the first phase of the next cache transaction, that is, start determining the access path of the next cache transaction, while performing the second phase of the particular cache transaction, instead of waiting for the LRU data update of the particular transaction to be completed in the second phase. Therefore, the second phase of the current transaction and the first phase of the next transaction can be performed in parallel. This scheme generally shortens the total time required to perform multiple cache transactions.

[0053] Figure 3 The clock cycles for cache operations to perform 3 cache transactions are shown. The first transaction (txt1) is performed on the first group (group A) in the cache. The second transaction (txt 2) is performed on the second group (group B) in the cache. The third transaction (txt 3) is also performed on the second group (group B)

[0054] like Figure 3 As shown, in At , the system executes the first phase of the first transaction. At , the system executes the second phase of the first transaction and the first phase of the second transaction. At , the system executes the second phase of the second transaction and the first phase of the third transaction.

[0055] Note that At , the system executes two phases in parallel, i.e., the second phase of the first transaction and the first phase of the second transaction. This timing overlap does not result in a risk because the first transaction and the second transaction are executed on different banks of the cache, i.e., the first transaction is executed on bank A and the second transaction is executed on bank B. In this specification, a risk refers to a problem that occurs in the instruction pipeline when the next instruction cannot be executed correctly in the next clock cycle, for example, because the instruction exhibits a data dependency on modified data in different stages of the pipeline. Because the first transaction and the second transaction are executed on different banks, there is no data dependency between the two transactions and no risk occurs.

[0056] In contrast, At , the timing overlap of the two phases may cause risks because both the second transaction and the third transaction are executed on the same group (group B). In the cycle of , the first phase of the third transaction may need to use the LRU data of the group to determine the access way (e.g., for calculating the LRU way), while the LRU data of the same group is being updated in the second phase of the second transaction. This leads to a risk. Therefore, in order to correctly calculate the LRU way of the third transaction, the risk needs to be resolved. Figure 5 and Figure 7 Describe example processes and implementations for addressing risks.

[0057] Figure 4A An example data structure 400 for storing LRU data is shown. The data structure includes One-to-one correspondence between cache lines Each node 410 stores a way value 412 that identifies a corresponding cache line. Each node 410 is associated with a corresponding node index, such as The corresponding node index of node 410 Specifies the recency of the cache line identified by way value 412 of node 410. For example, the cache line identified by the way value stored in node 0 is the least recently accessed cache line in the group, and the cache line identified by the way value stored in node 1 is the least recently accessed cache line in the group. The cache line identified by the way value in the node is the most recently accessed cache line in the group.

[0058] During the process of updating the LRU data, ie, during the second phase of the cache transaction, the system updates the LRU data by shifting the way values ​​412 stored in the sequence of nodes 410 .

[0059] Figure 4B shows a method for updating a data structure stored in a data structure—for example, stored in Figure 4A An example process of LRU data in the node sequence shown. Figure 4B In the example, the top row of nodes stores the way value before the LRU data is updated. The bottom row of nodes stores the way value after the LRU data is updated. Both rows of nodes are arranged from left to right in descending order of recency. That is, the leftmost node of each row stores the way value of the most recently used (MRU) cache line, and the rightmost node of each row stores the way value of the least recently used (LRU) cache line.

[0060] exist Figure 4B In the example shown, the access route for the transaction is identified by the way value "2" stored in the 4th node from the left in the top row. The system updates the LRU data to reflect the change in recency by moving the way value "2" to the MRU node and shifting the way values ​​stored in the 1st to 3rd nodes by one node from left to right, resulting in the way values ​​shown in the bottom row.

[0061] Figure 5 An example process 500 for performing risk resolution in LRU calculations is shown. For convenience, the process 500 will be described as being performed by a process such as Figure 1 The cache system 100 performs a cache system execution.

[0062] When the system starts calculating the LRU way for the current transaction, if the current transaction is mapped to the same group as the previous transaction, and the previous transaction has started one clock cycle before the current transaction, a data risk may occur, and the system performs process 500 to resolve the risk.

[0063] As an illustrative example, refer to Figure 3 , when transaction #3 (txn3) is the current transaction executed on group B, data risk may be caused between calculating the LRU way of txn3 (T1 phase) and updating the LRU data of the previous transaction (txn2) also executed on group B (T2 phase).

[0064] Return to reference Figure 5 , in step 510 of the risk resolution process 500, the system determines whether all cache lines in the group are eligible for replacement. This step is required because in some scenarios, the cache system can be accessed by multiple client devices. In this specification, a client device is a device that issues read requests and write requests to the cache system to access data of the cache system. When the cache system is being accessed by multiple client devices, each client device can use only a subset of the cache lines in the current group for replacement. Therefore, for the current transaction associated with a particular client device, only a subset of the cache lines are eligible for replacement, and the system can calculate the LRU way only from the eligible cache lines.

[0065] If the system determines that all cache lines in the group are eligible for replacement, the system can simply execute step 520 to wait for the LRU update to complete, and then execute step 525 to determine the LRU way for the current transaction based on the updated LRU data (which has been updated for the previous transaction). For example, in step 525, the system can simply determine the LRU way stored in the cache line storage such as Figure 4A The way value 412 in the LRU node (node ​​0) of the illustrated LRU data 400 specifies an LRU way in which all LRU data nodes 410 have been updated for the previous transaction. Since the LRU way is selected based on the latest LRU data about the previous transaction, the selected LRU way is risk-resolved.

[0066] As an illustrative example, refer to Figure 3To resolve the risk between the current transaction (txn3) and the previous transaction (txn2), the system can simply wait for all cache lines in group B to meet the replacement conditions. The LRU data of txn2 in is updated, and then the calculation of the LRU path for txn3 begins.

[0067] Return to reference Figure 5 If the system determines that not all cache lines in the group are eligible for replacement, that is, for the current transaction, only a subgroup of cache lines in the group are eligible for replacement, the system needs to identify the eligible subgroup of cache lines and then determine the LRU way from the eligible cache lines. Since the recency information of the cache lines can be stored in the corresponding LRU data node (e.g., Figure 4A ), the system may determine a qualifying cache line by determining a qualifying LRU data node group and identifying a qualifying cache line using the corresponding stored way values ​​412 stored in the qualifying LRU data nodes. Here, a qualifying LRU data node refers to an LRU data node storing a way value that identifies a qualifying cache line.

[0068] Since process 500 is executed for the current transaction during the same clock cycle when the previous transaction is updating the LRU data, in order to correctly identify the eligible way, the system needs to determine the eligible node that has resolved the risk in step 530. Here, the eligible node that has resolved the risk refers to the LRU data node that stores the latest way value that identifies the eligible cache line. The latest way value refers to the way value that is consistent with the updated LRU data from the previous transaction.

[0069] In some implementations, to improve time efficiency, the system begins the step of determining eligible nodes for resolved risks for the current transaction before the LRU data update of the previous transaction is completed. This can be achieved by directly using the node shift information of the LRU data updated in the previous transaction. For each node of the LRU data of the current group, the node shift information specifies whether the node has been shifted (or will be shifted) by the LRU data update process of the previous transaction. Figure 7 Example implementations for determining eligible nodes for resolved risks in a time-efficient manner are described.

[0070] After the eligible nodes for which the risk has been resolved have been determined in step 530, the system selects an LRU node from the eligible nodes for which the risk has been resolved in step 540. The selected LRU node is the least recently used node among the group of eligible nodes for which the risk has been resolved. In step 550, the system determines the LRU way using the way value stored in the selected LRU node.

[0071] Figure 6 An example hardware implementation 600 of an LRU cache replacement strategy applied to LRU data (i.e., corresponding way values ​​of cache lines in a group) stored in a sequence of nodes 640 is shown. Similar to the data structure shown in FIG. 4 , The sequence of nodes 610 is arranged according to the recency of the cache lines identified by the corresponding way values ​​stored in the nodes (with recency decreasing from left to right). Figure 6 In the example shown, the leftmost node, node , stores the way value of the MRU cache line, and the rightmost node, that is, node , stores the way value of the LRU cache line.

[0072] The circuit 600 includes a plurality of comparators 640, a plurality of OR gates 650, and a plurality of multiplexers 660. The circuit receives as input an access way 605 determined by the first stage of a cache transaction, and uses a corresponding comparator 640 to compare the access way 605 with each of the way values ​​stored in the node 610. The output of the comparator 650 is connected to a first input of the corresponding logical OR gate 650.

[0073] For the convenience of description and without loss of generality, the A comparator 640 is used to store the The path value in is compared with the access path 605, where For the nodes, there is an OR gate, where .for , No. The output of the first comparator 640 is connected to the The first input of the OR gate, and the The second input of the OR gate is connected to the The output of the OR gate. , No. The output of the first comparator 640 is connected to the The first input of the OR gate, and the The second input of the OR gate is connected to the The output of the comparator. In other words, the OR gate is ) and all previous nodes (nodes 0, 1, ..., ) to perform an OR operation on the comparison result. If nodes 0, 1, ..., A node in stores a path value that matches the access path 605, then The OR gate outputs "1". If nodes 0, 1, ..., No node in the access path 605 stores a path value that matches the access path 605. The OR gate outputs "0".

[0074] No. The output of each OR gate is connected to the corresponding multiplexer 660 (MUX ) control input. Here, The rightmost multiplexer (MUX )'s control input is connected to the node The data input of MUX k is connected to the current node (node ) and the next node (node ),in The leftmost multiplexer (MUX ) are connected to the data input of the node Therefore, the multiplexer 660 outputs the updated LRU data 630 , ie, the way values ​​that have been shifted according to the control input of the multiplexer 660 .

[0075] The circuit 600 also outputs the control input of the multiplexer 660 as a shift flag signal 620. The shift flag signal 620 includes a corresponding flag value for each specific LRU data node 610, which is used to indicate whether a shift operation has been performed (or is about to be performed) on the way value stored in the specific LRU data node 610. Figure 7 As described, the system may use the shift flag signal 620 to perform risk resolution between two transactions.

[0076] Figure 7 An example hardware implementation 700 for cache risk resolution between a current cache transaction and a previous cache transaction is shown. Specifically, when the second phase (for LRU data update) of the previous cache transaction and the first phase (for LRU way calculation) of the current cache transaction are executed in the same clock cycle, the circuit 700 performs risk resolution, such as Figure 3 The clk = 3 cycle is shown, during which the previous transaction (txn2) performs an LRU data update and the current transaction (txn3) performs an LRU way calculation.

[0077] Return to reference Figure 7, the circuit 700 receives several input signals, including: (1) eligible ways 730, which identify cache lines eligible for replacement in the group for the current transaction; (2) access ways 705 of the previous transaction; (3) shift flags 720, which are output by the previous transaction and specify the shift information of the LRU data node updated by the LRU data in the previous transaction; (4) updated LRU data 740, which specifies the way value that has been updated by the previous transaction; (5) unupdated LRU data 710, which specifies the way value that has not been updated by the previous transaction; and (6) risk flags 760, which indicate whether to perform risk resolution between the previous transaction and the current transaction. The circuit 700 outputs the LRU way 770 calculated for the current transaction.

[0078] Note that input signals 705, 720 and 730 are available for the current transaction before the LRU data update process of the previous transaction has been completed. Therefore, data processing using these input signals of the current transaction can be started before the LRU data update process of the previous transaction has been completed.

[0079] Circuit 700 includes multiple Multiplexer 702 includes MUX 0, MUX 1, ..., MUX K. Each Multiplexer 702 receives qualified paths 730 as input. Qualified paths 730 may be encoded as cache lines A flag "1" or "0" in the length vector, where a flag "1" indicates that the corresponding way meets the replacement condition, and a flag "0" indicates that the corresponding way does not meet the replacement condition. MUX 0, ..., MUX Each of MUX 0, MUX 1, MUX 2, MUX 3, MUX 4, MUX 5 also obtains the way value from the corresponding LRU data node 710 as a control input. The received way value is an outdated way value, that is, a way value that has not been updated by the second phase (T2) of the previous transaction. An access way 705 is received as a second input. The output of multiplexer 702 specifies an unresolved eligible LRU data node for which a risk has not yet been resolved. That is, the output of multiplexer 702 specifies whether the corresponding node stores an outdated way value that identifies one of the eligible cache lines. An outdated way value refers to a way value that has not been updated by the LRU data update process of a previous transaction.

[0080] The circuit 700 includes a plurality of multiplexers 704 that receive a shift flag signal 720 as a control signal. The data input of each multiplexer 704 is connected to two adjacent The output of multiplexer 702. Therefore, when there is a risk, multiplexer 704 performs data shifting on the unresolved eligible LRU data nodes based on shift flag 720. Risk signal 760 indicates that two transactions are executed to the same group, that is, there is a risk. Since shift flag 720 has been output by the previous transaction and specifies the shift information of the LRU data node of the previous transaction, multiplexer 704 performs the same data shift on the unresolved eligible LRU data nodes as the data shift performed on the LRU data nodes by the previous transaction. Therefore, the output of multiplexer 704 specifies the LRU data nodes for which the risk has been resolved.

[0081] Circuit 700 includes a fixed priority arbitrator 790 that performs fixed priority arbitration among eligible nodes for which risk has been resolved and selects an LRU node 780, i.e., a least recently used node as indicated by a node index, among eligible nodes for which risk has been resolved. Circuit 700 may use another The multiplexer 708 receives the selected LRU node 780 as a control signal to select the LRU way 770 from the updated LRU data 740 or the non-updated LRU data 710 according to the risk signal 760 .

[0082] As described above, the circuit 700 is configured to perform risk resolution on the eligible LRU data nodes of the current transaction at least partially in parallel with the LRU data update process of the previous transaction. Therefore, in the case of risk resolution, the time required to determine the access path in the first stage can be estimated as: Where C2 is a constant small time delay for performing additional operations such as data shifts on unresolved eligible nodes.

[0083] Compared to the conventional implementation of the LRU replacement strategy, the above implementation provides the following time savings:

[0084] Since the time to update LRU data increases with cache associativity, the time savings shown in equation (5) can be significant for set-associative caches with a large number of cache lines in each set.

[0085] As shown in the above analysis, by using the reference Figure 2 , Figure 3 and Figure 6 The cache replacement process described and referenced Figure 5 and Figure 7The risk resolution process described and the described cache system can overcome certain limitations of conventional LRU replacement implementations and improve the time efficiency of executing multiple cache transactions.

[0086] Embodiments of the subject matter and functional operations described in this specification may be implemented in digital electronic circuit systems, in tangibly embodied computer software or firmware, in computer hardware including the structures disclosed in this specification and their structural equivalents, or in a combination of one or more of them. Embodiments of the subject matter described in this specification may be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory storage medium for execution by a data processing device or for controlling the operation of a data processing device. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them. Alternatively or additionally, program instructions may be encoded on an artificially generated propagation signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, generating an artificially generated propagation signal to encode information for transmission to a suitable receiver device for execution by a data processing device.

[0087] This specification uses the term "configured" in conjunction with system and computer program components. For a system of one or more computers to be configured to perform a specific operation or action, it means that the system has installed thereon software, firmware, hardware, or a combination thereof that causes the system to perform these operations or actions in operation. For one or more computer programs to be configured to perform a specific operation or action, it means that one or more programs include instructions that cause the device to perform the operation or action when executed by a data processing device. The embodiments of the subject matter and functional operations described in this specification can be implemented in a digital electronic circuit system, in a tangibly embodied computer software or firmware, in a computer hardware including the structure disclosed in this specification and its structural equivalents, or in a combination of one or more of them. The embodiments of the subject matter described in this specification can be implemented as one or more computer programs, that is, one or more modules of computer program instructions encoded on a tangible non-temporary storage medium for execution by a data processing device or control of the operation of a data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them. Alternatively or additionally, program instructions may be encoded on an artificially generated propagated signal, e.g., a machine-generated electrical, optical or electromagnetic signal, which is generated to encode the information for transmission to appropriate receiver apparatus for execution by the data processing apparatus.

[0088] The term "data processing equipment" refers to data processing hardware and encompasses all kinds of equipment, devices and machines for processing data, including, for example, a programmable processor, a computer or a plurality of processors or computers. The equipment may also be or include a dedicated logic circuit system, for example, an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). In addition to hardware, the equipment may optionally include code that creates an execution environment for a computer program, for example, code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0089] A computer program, which may also be referred to or described as a program, software, software application, app, module, software module, script, or code, may be written in any form of programming language including compiled or interpreted languages ​​or declarative or procedural languages, and it may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A program may, but need not, correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data—for example, one or more scripts stored in a markup language document—in a single file dedicated to the program in question, or in multiple coordinated files—for example, files that store portions of one or more modules, subroutines, or code. A computer program may be deployed to execute on one computer or on multiple computers located at one site or distributed over multiple sites and interconnected by a data communications network.

[0090] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by a dedicated logic circuit system (e.g., an FPGA or ASIC) or by a combination of a dedicated logic circuit system and one or more programmed computers.

[0091] A computer suitable for executing a computer program can be based on a general or special microprocessor or both, or any other kind of central processing unit. Generally, the central processing unit will receive instructions and data from a read-only memory or a random access memory or both. The basic elements of a computer are a central processing unit for fulfilling or executing instructions and one or more memory devices for storing instructions and data. The central processing unit and the memory can be supplemented by a special logic circuit system or incorporated into the special logic circuit system. Generally, the computer will also include one or more large-capacity storage devices for storing data, such as a magnetic disk, a magneto-optical disk or an optical disk, or be operably coupled to receive data from one or more large-capacity storage devices or transfer data to one or more large-capacity storage devices or both. However, the computer does not have to have such a device. In addition, the computer can be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver or a portable storage device, such as a universal serial bus (USB) flash drive, to name a few.

[0092] Computer-readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media, and memory devices, including, by way of example: semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices); magnetic disks (e.g., internal hard disks or removable disks); magneto-optical disks; and CD ROM and DVD-ROM disks.

[0093] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope of any invention or the scope that may be claimed, but should be interpreted as descriptions of features that may be peculiar to a particular embodiment of a particular invention. Certain features described in the context of separate embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may involve a sub-combination or a variant of a sub-combination.

[0094] Similarly, although operations are depicted in the drawings and described in the claims in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in a continuous order, or that all of the operations shown be performed to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0095] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying drawings do not necessarily require the particular order or sequential order shown to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous.

Claims

1. A cache comprising: a plurality of groups, wherein each group has a plurality of corresponding paths; as well as replacement logic configured to implement a two-stage least recently used (LRU) replacement calculation, wherein the two-stage LRU replacement calculation causes the cache to perform operations comprising: A first phase, during which the cache computes the LRU way of the group, and A second phase, during which the cache updates the LRU data structure with information of the transaction access way. 2 . The cache of claim 1 , wherein the cache is configured to perform the two-stage LRU replacement calculation in consecutive clock cycles. 3 . The cache of claim 1 , wherein the cache is configured to implement an LRU replacement policy using the calculated LRU way.

4. The cache of claim 1, wherein the replacement logic includes a plurality of nodes storing respective way values ​​for each group, and wherein performing the second stage includes shifting the stored way values ​​between the nodes for the groups.

5. The cache of claim 4, wherein performing the second stage comprises updating each node of a group with data already stored by the node or data displaced from another node.

6. The cache of claim 5, wherein performing the first phase of the current transaction comprises: In response to a risk condition resulting from the second phase of a previous transaction being executed on the same specific group, risk resolution for the current transaction is performed.

7. The cache of claim 6, wherein performing the risk resolution for the current transaction comprises: In response to determining that all of the corresponding ways in the particular group are eligible for replacement, the LRU way for the current transaction is determined based on the LRU data structure after the LRU data structure has been updated for the previous transaction.

8. The cache of claim 6, wherein the replacement logic is configured to, in response to determining that not all of the corresponding ways in the particular set are eligible for replacement: determining, from the plurality of nodes, eligible nodes for which risks have been resolved; Selecting a qualified node from the qualified nodes of the resolved risk; as well as The LRU way is determined using the way value stored in the selected eligible node.

9. The cache of claim 8, wherein the replacement logic is configured to begin determining eligible nodes for the resolved risk from the plurality of nodes before the second phase of the previous transaction has completed.

10. The cache of claim 9, wherein determining eligible nodes for the resolved risk from the plurality of nodes comprises: before the LRU data structure has been updated by the second phase of the previous transaction, generating unresolved node data identifying a qualifying node from the plurality of nodes based on the qualifying way and the LRU data structure; as well as The unresolved node data is shifted using the shift information generated during the second phase of the previous transaction to generate node data for resolved risks identifying eligible nodes for the resolved risks.

11. A method for performing an LRU replacement calculation for a cache comprising a plurality of sets, wherein each set has a plurality of corresponding ways: During the first phase, the LRU way of the group is calculated; and During the second phase the LRU data structure is updated with information about the transaction access ways.

12. The method of claim 11, wherein the first stage and the second stage are performed in consecutive clock cycles.

13. The method of claim 11, wherein the cache is configured to implement an LRU replacement policy using the calculated LRU way.

14. The method according to claim 11, wherein: The method further includes: storing a corresponding way value for each group in a plurality of nodes; and Executing the second phase includes shifting the stored way values ​​between the nodes for the group.

15. The method of claim 14, wherein performing the second phase comprises updating each node of the group with data already stored by the node or data displaced from another node.

16. The method of claim 15, wherein executing the first phase of the current transaction comprises: In response to a risk condition resulting from the second phase of a previous transaction being executed on the same specific group, risk resolution for the current transaction is performed.

17. The method of claim 16, wherein performing the risk resolution for the current transaction comprises: In response to determining that all of the corresponding ways in the particular group are eligible for replacement, the LRU way for the current transaction is determined based on the LRU data structure after the LRU data structure has been updated for the previous transaction.

18. The method of claim 16, wherein performing the risk resolution for the current transaction comprises, in response to determining that not all of the corresponding ways in the particular group meet a replacement condition: determining, from the plurality of nodes, eligible nodes for which risks have been resolved; Selecting a qualified node from the qualified nodes of the resolved risk; as well as The LRU way is determined using the way value stored in the selected eligible node.

19. The method of claim 18, wherein determining eligible nodes for which risks have been resolved comprises: Determining eligible nodes for the resolved risk from among the plurality of nodes begins before the second phase of the previous transaction has been completed.

20. The method of claim 19, wherein determining eligible nodes for the resolved risk comprises: before the LRU data structure has been updated by the second phase of the previous transaction, generating unresolved node data identifying a qualifying node from the plurality of nodes based on the qualifying way and the LRU data structure; as well as The unresolved node data is shifted using the shift information generated during the second phase of the previous transaction to generate node data for resolved risks identifying eligible nodes for the resolved risks.

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