Detecting and mitigating memory attacks

Abstract

The present disclosure relates to systems and methods implemented on a memory controller for detecting and mitigating memory attacks (e.g., raking attacks). For example, a memory controller may enable a count mode in which an activation count of memory sub-banks is tracked. For example, a memory controller may enable a count mode in which an activation count of memory rows of a memory sub-bank is maintained. In some conditions, a memory controller may transition from a count mode to a sampling mode to mitigate potential hammer attacks. The memory controller may account for various conditions when determining whether to continue to detect and mitigate potential hammer attacks in the sampling mode and / or transition back to the counting mode. By selectively transitioning between different operating modes, the memory controller may reduce the time period during which memory hardware is susceptible to attacks.

Description

Background Art

[0001] Recent years have seen an increase in the use of computing devices (e.g., mobile devices, personal computers, server devices, cloud computing systems) to receive, store, edit, transmit, process, or otherwise utilize digital data for various processing applications and services. Indeed, cloud computing architectures and the use of computing resources on various computing devices are now commonly adopted by individuals and businesses. As the demand for memory resources grows, memory resources continue to expand in terms of availability and complexity on various computing platforms.

[0002] In some memory systems, many security vulnerabilities have been used to exploit unintended and / or undesirable side effects in dynamic random access memory (DRAM) hardware. For example, some malicious actors have found ways to corrupt data in memory cells by using row hammer attacks. These attacks typically involve rapidly activating one or more memory rows multiple times in rapid succession to cause charge from nearby memory cells to leak and ultimately corrupt the data on them. Furthermore, as DRAM manufacturing processes continue to shrink, row hammer attacks have the potential to affect a greater number of memory cells.

[0003] Detecting and mitigating row hammer attacks presents significant challenges to memory systems. For example, conventional approaches often involve expending significant processing resources (e.g., memory hardware) to accurately identify specific attacking rows (i.e., rows with high activation rates) or victim rows (i.e., rows that are under attack). Alternatively, where conventional systems do not dedicate significant hardware resources to identifying and stopping row hammer attacks, these systems can easily become overwhelmed, especially where the hardware is operated outside of normal operating conditions or where the hardware is accessed in an unconventional manner.

[0004] These and other problems are related to detecting and mitigating memory attacks, and in particular to detecting and mitigating row hammer attacks. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 An example computing device environment is shown that includes a memory system having a memory controller including a row hammer detection system implemented thereon.

[0006] Figure 2 An example implementation of activation count recording is shown, demonstrating the recording of activation counts and overflow counts for row addresses across multiple memory sub-banks.

[0007] Figure 3 Example activation count tables for memory sub-banks are shown in accordance with one or more embodiments.

[0008] Figure 4An example series of actions is shown while in a counting mode for determining whether there is a possible attack row for a given memory sub-bank.

[0009] Figure 5 An example series of behaviors when in operation to mitigate a possible attack on a given memory sub-bank is shown.

[0010] Figure 6 An example countdown record including a sampling mode countdown is shown in accordance with one or more embodiments.

[0011] Figure 7 An example timeline showing a series of refresh windows is shown in which the row hammer detection system transitions between operating modes.

[0012] Figure 8 A series of actions associated with determining whether to transition between modes of operation in detecting and mitigating a hammer attack are shown.

[0013] Fig. 9 Another series of actions associated with transitioning between operating modes for detecting and mitigating a hammer attack is shown.

[0014] Fig.10 Some components that may be included in a computer system are shown. DETAILED DESCRIPTION

[0015] The present disclosure generally relates to detecting and mitigating memory attacks (e.g., row hammer attacks) on memory systems. Specifically, one or more embodiments described herein relate to a hybrid approach using multiple operating modes to detect potential attack rows (e.g., row addresses) within memory hardware (e.g., dynamic random access memory (DRAM)). For example, as will be discussed in further detail below, a memory controller may enable a counting mode in which an activation count of memory rows of memory subbanks is maintained. Under certain conditions, the memory controller may transition from the counting mode to a sampling mode to mitigate potential row hammer attacks. In addition, one or more embodiments described herein relate to determining whether to continue detecting and mitigating potential row hammer attacks in the sampling mode and / or transition back to the counting mode.

[0016] As an illustrative example, a row hammer detection system can enable a counting mode for a memory subbank by maintaining a row activation count for a memory row within the memory subbank and an overflow count based on memory row activations that are not included in the multiple counts. Based on determining that the overflow count exceeds a threshold, the row hammer detection system can enable a sampling mode for the memory subbank. When in the sampling mode, the row hammer detection system can determine whether to report a row address as an attacking row based on a comparison of a random number and a sampling threshold, and maintain a countdown for the sampling mode that determines the duration that the memory controller remains in the sampling mode. Additional details related to the counting and sampling modes will be discussed in more detail below.

[0017] After the countdown has iterated (e.g., increased or decreased) to the threshold, the row hammer detection system can re-enable the counting mode. In one or more embodiments, the row hammer detection system can determine whether to enable (e.g., re-enable) the counting mode based on the countdown value and one or more additional factors. For example, when used in sampling mode, the row hammer detection system can continue to maintain an activation count for a row of a memory sub-bank and consider the number of times the overflow count has exceeded a threshold for a certain duration before determining whether to re-enable the counting mode.

[0018] The present disclosure includes many practical applications that provide advantages and / or solve problems associated with detecting and mitigating row hammer attacks occurring on memory sub-banks of memory hardware. Examples of some of these applications and advantages are discussed below.

[0019] For example, by transitioning between an activation counting mode (or simply "counting mode") and a sampling mode, a row hammer detection system can provide a low computational cost alternative to maintaining an expensive and robust record of activations for a memory bank or multiple memory banks. Indeed, where conventional approaches typically involve maintaining a large record of activation examples for one or more entire memory banks to ensure that a specific instance of a row hammer attack is detected, the row hammer detection system uses a hybrid scheme to transition between counting mode and sampling mode to predict that a row hammer attack may be occurring and allow the row hammer detection system to identify the location of the attack within an acceptable amount of time.

[0020] Furthermore, rather than tracking activation counts for an entire memory system or entire memory bank, the hybrid approach enables the row hammer detection system to track activations at a sub-memory bank level while effectively detecting and mitigating row hammer attacks. This smaller scale tracking approach allows the row hammer detection system to maintain activation counts using smaller count tables maintained for corresponding memory sub-banks. Tracking and detecting row hammer attacks at the sub-memory bank level allows the row hammer detection system to activate a sampling mode for the relevant sub-memory bank, which becomes overwhelmed, while allowing the use of a counting mode to monitor other sub-memory banks. Furthermore, features of the system described herein reduce the associativity of the table from potentially thousands to a much smaller amount (e.g., 16, 32) while reducing the total number of counters (e.g., by a factor of 20 or 30). This reduced associativity additionally enables the system described herein to meet performance requirements of memory controllers, which are difficult or impossible with conventional approaches.

[0021] As described above, and as will be discussed in further detail below, one or more embodiments described herein relate to implementations of a hybrid scheme in which a memory controller transitions between a counting mode and a sampling mode when detecting a potential row hammer attack. This hybrid approach enables the memory controller to maintain an activation count table without consuming or occupying the large amounts of memory resources required by conventional approaches. For example, where conventional approaches that rely exclusively on a thump count mode would require 10s of megabytes (MB) of static random access memory (SRAM) to reliably detect instances of a row hammer attack, the approach described herein involves a much smaller scale of SRAM resources to track activation counts across multiple memory sub-banks. In fact, features of a row hammer detection system that implements a hybrid detection scheme at the sub-bank level can reduce the amount of SRAM required to detect and mitigate row hammer attacks on memory banks of similar size by a factor of 1 / 100 or 1 / 1000 as compared to conventional approaches. In fact, as described above, implementing the hybrid scheme described herein can reduce the number of counters by a factor of 20, 30, or more as compared to conventional approaches.

[0022] In addition, features of the row hammer detection system reduce computational and hardware overhead on the memory controller while still maintaining a very low probability that a row hammer attack will go undetected. For example, by identifying specific memory sub-banks that may be affected by a row hammer attack and then selectively activating a sampling mode for the memory sub-banks, the row hammer detection system can implement the sampling mode at the sub-bank level without interrupting operation of other sub-banks of the memory hardware. This allows the row hammer detection system to implement the sampling mode on a smaller portion of the memory hardware using a sampling threshold that almost guarantees that a row hammer attack will be found and prevented before causing data corruption on nearby memory cells.

[0023] In one or more embodiments, the row hammer detection system includes features and capabilities that allow detection and mitigation of row hammer attacks without requiring memory hardware to share or making all hardware and topology information available to the memory controller. For example, by identifying specific rows of memory (and / or impact ranges) that are predicted to be attack rows in a row hammer attack, the row hammer detection system can issue commands to the memory hardware that allow the memory hardware to take steps locally and mitigate the identified row hammer attack. As described above, the command can be issued without requiring the hardware to share certain information with the memory controller that certain hardware vendors wish to avoid sharing. This allows the row hammer detection system to be implemented on memory controllers across a variety of hardware architectures to detect and mitigate a variety of memory attacks across different computing devices.

[0024] In addition to the advantages described above, the row hammer detection system can implement an efficient method for switching between various operating modes. For example, while the sampling mode provides an efficient method for detecting and mitigating potential or ongoing row hammer attacks, it may be an undesirable approach to enable the sampling mode indefinitely when a row hammer attack is not currently ongoing or when the row hammer attack has been effectively mitigated. As will be discussed in further detail below, the row hammer detection system utilizes various features to selectively determine whether to re-enable the counting mode after a previous transition from the counting mode to the sampling mode. For example, the row hammer detection system can implement a countdown measurement or track the number of activation counts over a series of refresh windows to determine the number of times the countdown mode will become overwhelmed when the memory controller has enabled the sampling mode.

[0025] In practice, by selectively managing the frequency with which the row hammer detection system causes the memory controller to transition between operating modes, the row hammer detection system can limit the amount of time (e.g., the number of refresh windows) that the memory hardware is vulnerable to a row hammer attack. In particular, because the act of transitioning between operating modes (e.g., from a counting mode to a sampling mode) may render the memory hardware vulnerable for a brief period of time (e.g., one refresh window), the row hammer detection system can benefit from reducing the number of refresh windows that the memory hardware transitions between operating modes. By implementing a countdown, the row hammer detection system can control the number of refresh windows that the memory hardware is vulnerable to, thereby reducing the probability that a memory attack (e.g., a row hammer attack) will successfully destroy data on the memory hardware.

[0026] The row hammer detection system may additionally include features and functionality to prevent deterministic methods of attacking memory hardware. For example, as will be discussed in further detail below, the row hammer detection system may implement a measure of randomness in setting or otherwise initializing a countdown or duration for the row hammer detection system to enable a sampling mode. For example, where the row hammer detection system implements a countdown that determines the length of time that a memory controller implements a sampling mode, the row hammer detection system may initialize the countdown with some randomness to prevent sophisticated attacks from anticipating the countdown length and configuring the row hammer attack accordingly.

[0027] As indicated in the foregoing discussion, the present disclosure utilizes various terms to describe the features and advantages of the systems herein. Additional details are now provided regarding the meaning of some exemplary terms.

[0028] For example, a "computing device" may refer to a computing node, a server node, a host device, or any electronic device having (or accessible to) memory hardware thereon. In one or more embodiments described herein, a computing device may refer to a server device on a network of connected network devices (e.g., a cloud computing system). Alternatively, a computing device may refer to a mobile or non-mobile device, such as a portable computer, a desktop computer, a phone, a tablet computer, or other device capable of accessing the memory resources of one or more memory devices. In one or more embodiments described herein, a computing device refers to a device or system on which memory hardware and (multiple) associated memory controllers are implemented. This will be described below in conjunction with Fig.10 Additional details regarding some general features and functions of computing devices are discussed.

[0029] As used herein, "memory hardware" or "memory resource(s)" may refer to accessible memory across one or more computing devices. For example, memory hardware may refer to local memory having memory blocks accessible by an application or operating system on a computing device. Memory hardware may refer to memory managed by one or more integrated memory controllers (or simply "memory controllers") that are co-located on a memory system or otherwise implemented on a computing device. A memory device may refer to any memory resource managed by a memory controller, including local, external, remote, or pooled memory accessible to one or more computing devices. In fact, memory hardware may refer to any memory device managed by a memory controller.

[0030] Memory hardware may refer to memory resources of various memory types. In one or more embodiments described herein, a memory device may refer to a dynamic access memory (DRAM), a static random access memory (SRAM), a flash memory, or other non-persistent memory source. A memory system may include a dual in-line memory module (DIMM) device (or other device type) that provides an accessible memory source. In one or more embodiments, a memory device may include multiple memory banks that provide portions of memory resources to various applications or processes.

[0031] As used herein, a "memory bank" may refer to a memory unit on memory hardware. For example, a memory bank may refer to a logical partition of memory partitioned across multiple chips on a memory system. In one or more specific examples described herein, a memory bank refers to a memory bank among a plurality of similarly sized memory banks representing corresponding portions of memory hardware. As an illustrative example consistent with one or more embodiments described herein, the memory hardware may include sixty-four (64) memory banks, each of which includes eight (8) sub-banks. As used herein, a memory sub-bank may refer to a portion (e.g., a subset) of a memory resource from a corresponding memory bank. It should be understood that while one or more embodiments are described herein in conjunction with memory hardware having a specific number (e.g., 64) of memory banks each including eight memory sub-banks, other implementations may include any number of memory banks, wherein one or more of the memory banks include a variable number of multiple memory sub-banks. It should also be understood that a memory bank and a corresponding sub-bank may refer to memory resources of various sizes.

[0032] As will be discussed in conjunction with the following examples, a memory controller may track activation (e.g., row activation) counts across multiple memory sub-banks. In one or more embodiments, the memory controller may perform tracking of activation counts while operating in a counting mode. As used herein, "activation" or "row activation" may refer to an example in which (multiple) memory cells (e.g., row addresses) are activated and become readable or otherwise accessible within a period of time (e.g., a refresh interval). Row addresses can be activated without having to be read or accessed. In one or more embodiments, a memory system may have different strategies for managing the number of times a row can be accessed during an activation cycle. In one or more embodiments, only one row can be accessed per activation. Other implementations may involve multiple accesses during a single activation.

[0033] As used herein, "counting mode" refers to an operating mode of a memory controller relative to a corresponding memory sub-bank, wherein the memory controller tracks row activation counts of the memory sub-bank. For example, as described below, a row hammer detection system can maintain an activation count table that includes a plurality of counts for corresponding memory addresses (e.g., memory row addresses). The activation count table can also include an overflow count.

[0034] In one or more embodiments described herein, the counting mode specifically refers to a row activation counting mechanism that involves maintaining an estimate of activation for a row while maintaining an overflow count value, and determining whether the counting mode is overwhelmed based on the overflow count value. Other implementations may involve other counting mechanisms, including other means for determining whether the counting mode has become overwhelmed. For example, a counting Bloom filter or a variant thereof may be used, in which a counter array is maintained and the row address is hashed x times, the count is looked up at different increments, and the count is compared to a threshold to determine whether the counting mode is overwhelmed. In fact, any of the various variations of the data structure may be used to determine whether the counting mode is overwhelmed and whether the sampling mode should be enabled.

[0035] In one or more embodiments, the row hammer detection system may cause the memory controller to transition to a sampling mode or otherwise activate a sampling mode. As used herein, "sampling mode" refers to an operating mode of the memory controller relative to a corresponding memory sub-bank, wherein the memory controller generates a random number for an activated row and compares the random number to a sampling threshold. Based on the comparison, the memory controller may report an address / row by generating and issuing a refresh command indicating a memory address as a predicted attack row for a row hammer attack. After resolving the row hammer attack, the memory controller may return to sampling mode for the corresponding memory sub-bank.

[0036] In one or more embodiments described herein, reference is made to features of a row hammer detection system using different time periods, such as an activation time period (e.g., a duration associated with a row activation) or multiple intervals over which the duration of activation is tracked or over which a countdown is measured. As an example, a "refresh window" may refer to a duration that includes multiple "refresh intervals." While the specific lengths of refresh windows and refresh intervals may vary between different examples, the durations of refresh windows and refresh intervals may be determined based on hardware specifications (e.g., DRAM specifications). To illustrate, in one or more implementations described herein, the refresh windows are approximately thirty-two (32) milliseconds, with each refresh window including a predetermined number (e.g., eight thousand and ninety-two (8092)) of refresh intervals having a predetermined length (e.g., 3.9 microseconds).

[0037] Additional details will now be provided regarding example features and functionality of the hammer detection system in relation to the illustrative figures depicting example implementations. Specifically, Figure 1 An example implementation of computing device(s) 102 having an operating system 104 thereon is shown. Computing device(s) 102 may refer to any of the various computing devices described above. Additionally, operating system 104 may refer to a system for managing software and hardware on computing device 102. In addition to features of conventional operating systems, one or more embodiments of operating system 104 may facilitate transitioning between a memory controller operating in a counting mode or a sampling mode, which mode (as discussed below) may be based on data maintained on the memory controller. Further details regarding transitioning a memory controller between operating modes will be discussed below.

[0038] like Figure 1 As further shown in FIG. 1 , the computing device(s) 102 include a memory system 106. The memory system includes a memory controller 108 and memory hardware 122. In addition to the features that will be discussed in conjunction with detecting and mitigating row hammer attacks, the memory controller 108 can generally control the flow of data to and from the memory hardware 122. For example, the memory controller 108 can manage read and write operations to the memory hardware 122. The memory controller 108 can also track and manage data associated with reads and writes to the memory hardware 122. The memory controller 108 further implements error detection and correction features with respect to memory resources on the memory hardware 122.

[0039] As described above, and as will be discussed in further detail below, the memory controller 108 may provide features related to detecting and mitigating row hammer attacks on the memory hardware 122. For example, Figure 1 As shown, the memory controller 108 includes a hammer detection system 110. As will be discussed in further detail below, the hammer detection system 110 can implement features and functions related to detecting and mitigating hammer attacks. As described above, the hammer detection system 110 can implement various operating modes when detecting and mitigating hammer attacks.

[0040] like Figure 1 As shown, the row hammer detection system 110 may include a counting mode manager 112. The counting mode manager 112 may implement a counting mode in which a count of addresses (e.g., row addresses) is maintained within an activation count table for a plurality of memory sub-banks on the memory hardware 122. Specifically, the counting mode manager 112 may determine an estimated count of a plurality of row addresses of a corresponding memory sub-bank and determine whether a particular sub-bank is being overwhelmed by a potential row hammer attack based on the estimated activation counts and the corresponding overflow account. Additional details regarding the counting mode will be discussed in detail below.

[0041] like Figure 1 As further shown, the row hammer detection system 110 may include a sampling pattern manager 114. The sampling pattern manager 114 may implement a sampling pattern for one or more memory sub-banks that become overwhelmed while maintaining activation counts within a corresponding activation count table. Specifically, upon detecting a potential row hammer attack on an address (e.g., a row address) of an associated memory sub-bank, the sampling pattern manager 114 may apply a sampling pattern in which a random number is generated for each memory row activation and compared to a sampling threshold. Based on the comparison, the sampling pattern manager 114 may estimate that a row hammer attack has occurred on the associated memory address and generate a refresh command to send to the memory hardware 122. Additional details regarding the sampling pattern will be discussed in detail below.

[0042] like Figure 1 As shown, the row hammer detection system 110 may include a plurality of sub-bank count tables 116. The sub-bank count tables 116 may include records of memory addresses (e.g., row addresses) and corresponding row activation counts for associated time periods (e.g., refresh windows). The sub-bank count tables 116 may additionally include overflow counts for each of the corresponding sub-banks. As will be discussed in further detail below, the row hammer detection system 110 (e.g., the count pattern manager 112) may consider the counts of the corresponding row addresses in conjunction with the overflow counts to determine whether an address from a particular sub-bank has an attacking memory address (e.g., an attacking row) as part of a row hammer attack.

[0043] like Figure 1 As shown, the row hammer detection system 110 may include a countdown manager 118. The countdown manager 118 may maintain a countdown that iterates a countdown value (e.g., increments or decrements the countdown value) at periodic intervals to indicate a period of time that the row hammer detection system 110 has enabled a particular operating mode. Specifically, when in a sampling mode, the row hammer detection system 110 may maintain a countdown for the sampling mode (e.g., a countdown indicating the duration that the row hammer detection system 110 has been in the sampling mode) by iterating the countdown value at periodic intervals (e.g., each refresh window). As described below, the countdown provides a mechanism whereby the row hammer detection system 110 can facilitate re-enabling the counting mode after a period of time. In addition, the countdown provides a mechanism to reduce the number of refresh intervals during which the memory hardware 122 is vulnerable to a row hammer attack.

[0044] like Figure 1As shown, the hammer detection system 110 additionally includes an operating mode transition manager 120. The operating mode transition manager 120 can determine or provide information that enables the operating system 104 to determine when to transition between various operating modes. For example, the operating mode transition manager 120 can include conditions or instructions that indicate when the hammer detection system 110 should exit the counting mode and transition to the sampling mode. Conversely, the operating mode transition manager 120 can include conditions or instructions that indicate when the hammer detection system 110 should re-enable the counting mode after operating in the sampling mode for a period of time. Additional information related to transitions between operating modes will be discussed below.

[0045] As described above, the memory system 106 includes memory hardware 122 that provides memory resources to any of the various applications managed by the operating system 104. As described above, the memory controller 108 may provide access to and control of data flow between the operating system 104 and the memory hardware 122. Figure 1 As shown, the memory hardware 122 may include a plurality of memory banks 124 , each memory bank including a plurality of memory sub-banks 126 .

[0046] Although one or more embodiments described herein refer to an implementation of memory hardware 122 including a specific number of memory banks 124 and corresponding sub-banks 126, it should be understood that memory hardware 122 may include any number of memory banks and associated sub-banks. As described above, a memory bank may refer to a logical partition of memory resources from memory hardware 122, wherein a memory sub-bank references a subset of memory resources of a corresponding memory bank. In one or more embodiments described herein, memory hardware 122 includes sixty-four memory banks, wherein each memory bank has an associated set of eight memory sub-banks. These memory banks and associated sub-banks may represent resources of similar size, or alternatively, may be of different sizes within memory hardware 122. In one or more embodiments, a memory bank may refer to a physically adjacent row of memory cells. Alternatively, a memory bank 124 and a corresponding memory sub-bank 126 may include rows spaced apart across memory hardware 122.

[0047] Although Figure 1An example implementation of a computing device 102 is shown in accordance with one or more embodiments, but it will be appreciated that other implementations described herein may be implemented on different environments of computing device(s). For example, in one or more embodiments, computing device(s) 102 may include multiple memory systems implemented on different memory devices (e.g., pooled memory systems) that are accessible by one or more applications or virtual machines hosted by the computing device(s). In one or more embodiments, an environment may include multiple computing devices that can access memory resources on a single memory system. In each implementation, the memory hardware 122 may be managed by a corresponding memory controller 108 on which the hammer detection system 110 is implemented.

[0048] As described above, the row hammer detection system 110 (eg, the count mode manager 112 ) may implement a count mode to track activation counts from corresponding sub-banks 126 of a plurality of memory banks 124 on the memory hardware 122 . Figure 2 An example implementation showing an activation count record 202 within which activation counts are maintained for row addresses on the memory hardware 122 is shown.

[0049] like Figure 2 As shown, the activation count record 202 includes a record of entries including row addresses and corresponding activation counts. For example, the activation count record 202 includes a plurality of entry columns 204a-n, which include M rows. As will be discussed in further detail below, each row of a different column is associated with a corresponding memory sub-bank. In addition, each entry column in the plurality of entry columns 204a-n corresponds to a parallel manner of memory structure within the memory controller 108.

[0050] For example, in one or more embodiments, the number of entry columns 204a-n are based on a number of parallel modes that enable parallel reading of all address values ​​(e.g., all 16 address values). In one or more embodiments described herein, the activation count record 202 is maintained within a static random access memory (SRAM) structure having sixteen parallel access points (e.g., sixteen parallel modes). In one or more embodiments, the size of the activation count table is determined based on the parallel capabilities of the SRAM structure. Therefore, although one or more embodiments describe a row with sixteen entries representing estimated activation counts of corresponding memory sub-banks, other implementations may have fewer or additional entries based on an SRAM structure with additional parallel modes.

[0051] like Figure 2As shown, multiple entry columns 204a-n include memory address columns 206a-n and corresponding activation counts 208a-n. For example, the first entry column 204a may include a first set of addresses 206a and a corresponding first set of activation counts 208a. The first set of addresses 206a may include row addresses from different sub-memory banks and associated activation counts 208b, which associated activation counts 208b indicate estimated activation counts for the corresponding row addresses. Similarly, the second access column 204b may include a second set of addresses 206b and a corresponding second set of activation counts 208b. The access columns 204a-n may include any number of addresses and corresponding activation counts, up to an Nth set of addresses 206n and a corresponding Nth set of activation counts 208n.

[0052] In addition to the addresses 206a-n and the corresponding activation counts 208a-n, the activation count record 202 may include an overflow column 210 that indicates the overflow count for each row of the activation count record 202 corresponding to the corresponding memory sub-bank. For example, the first row of the activation count record 202 may include a first overflow count, the second row of the activation count record 202 may include a second overflow count, and so on. As described above, in the case where the memory hardware 122 includes sixty-four memory banks, each memory bank including eight memory sub-banks, the activation count record 202 may include five hundred and twelve rows, each row representing a corresponding memory sub-bank. It should also be noted that each entry of the corresponding sub-bank is associated with a different entry column 204a-n that is accessible in different parallel ways via the memory controller hardware. This parallelism allows for rapid access and updating of the various entries within the activation count record 202.

[0053] Figure 2 Also shown is an example row activation command 201 according to one or more embodiments. In the illustrated example, the row activation command 201 includes a row address 203 and a sub-bank identifier 205. When accessing a row, the memory controller 108 sends the row activation command 201. In the illustrated example, the sub-bank identifier 205 corresponds to the three least significant bits of the row activation command 201, which are used to identify the corresponding sub-bank. As described above, each row of the activation count record 202 corresponds to a sub-bank. Therefore, the three least significant bits can be used to identify a specific row of the activation count record 202. The row address 203 can then be evaluated and considered when updating one or more entries within the corresponding row of the activation count record 202. This will be described below in conjunction with Figure 3 Additional information related to updating or alternatively iterating entries of the overflow count is discussed with reference to the example activation count table for the corresponding sub-bank illustrated in FIG.

[0054] As mentioned above, and as Figure 2As shown, each row of the activation count record 202 relates to an activation count table for an associated memory sub-bank. Additionally, as described above, upon receiving a row activation command 201, the row hammer detection system 110 may update a corresponding row of the activation count record 202 (e.g., based on a sub-bank identifier 205 included in the row activation command 201). To further illustrate the process for updating a row from the activation count record 202, additional information will be discussed in conjunction with an example row 212 of the activation count record 202 corresponding to a first sub-bank represented within the activation count record 202. As an example, in Figure 3 An example row 212 of entries is further shown in the example activation count table shown.

[0055] Figure 3 2 shows an example activation count table 302 according to one or more embodiments described herein. As described above, the activation count table 302 can refer to an example of a row (e.g., the example row 212) from the activation count record 202. In particular, the activation count table 302 can include multiple entries, each entry corresponding to a respective way from an associated row of the activation count record. Thus, as Figure 3 As shown, the activation count table 302 may include a first row including the address and count of the first row from the first way (way 0), a second row including the address and count of the first row from the second way (way 1), and so on, until the Nth entry including the address and count of the first row from the Nth way (way N).

[0056] like Figure 3 As shown, the activation count table 302 may include a plurality of entries including a first column address 304 and a second column count 306. Additionally, the activation count table 302 may include an overflow entry 308 indicating an overflow count of the activation count table 302.

[0057] Although Figure 3 An example activation count table 302 is shown including a table with sixteen entries and an overflow count, but the activation count table 302 may include any number of entries to track estimates of activation counts associated with corresponding addresses. In the example shown, the number of entries in the activation count table 302 may correspond to the number of parallel ways from the SRAM structure on the memory controller 108. In other implementations, the activation count table 302 may include additional or fewer entries based on the hardware specifications of the memory controller 108 (e.g., the size of the SRAM structure).

[0058] It will also be noted that the counts of the corresponding addresses represent estimates of the counts of the associated addresses. For example, because the activation count table 302 may include a much smaller number of entries than the number of row addresses of the corresponding sub-memory bank, when an activation command (e.g., the activation command 201) is detected, the activation count table 302 may dump certain addresses from the activation count table 302. Figure 4 Additional details discussing how to update the activation count table 302 are provided in further detail.

[0059] Specifically, Figure 4 An exemplary series of actions 400 for updating respective entries of a corresponding activation count table is shown. More specifically, Figure 4 An example implementation is shown in which the row hammer detection system 110 maintains an activation count of a corresponding memory sub-bank when in a counting mode. In one or more embodiments, the row hammer detection system 110 enables the counting mode by default for each memory sub-bank. The row hammer detection system 110 can implement a series of actions 400 for each row activation command received while in the counting mode.

[0060] like Figure 4 As shown, the row hammer detection system 110 may perform an act 402 of detecting activation of a next address. For example, in one or more embodiments, the row hammer detection system 110 may receive, detect, or otherwise identify a row activation command indicating a sub-bank and an associated address (e.g., a row address). In one or more embodiments, the row hammer detection system 110 may identify a specific activation table (e.g., activation count table 302) to be updated (e.g., a specific row of activation count record 202) based on a sub-bank identifier included in the row activation command.

[0061] Upon detecting activation of the next address, the row hammer detection system 110 may first perform an action 404 of determining whether the address in the memory subbank is available in the associated activation table. For example, the row hammer detection system 110 may compare the address portion of the row activation command to a set of addresses in the first column of the activation count table and determine whether one of the addresses matches the address from the row activation command. In the event that the address matches an existing address in the activation count table (e.g., "yes" at action 404), the row hammer detection system 110 may perform an action 410 of incrementing or otherwise iterating the count of the row entry (of the matching address). In other words, the row hammer detection system 110 may increment the count estimate of the matching address within the activation count table. Figure 4 As shown, after incrementing the count for the row entry, the row hammer detection system 110 may return to perform action 402 regarding the next row activation.

[0062] Alternatively, in the event that the hammer detection system 110 determines that the address does not match an existing address in the activation count table (e.g., "No" at act 404), the hammer detection system 110 may perform additional steps related to updating the activation count table. Figure 4 As shown, the row hammer detection system 110 may perform an action 406 to determine whether any count within a table entry of the activation count table is equal to the overflow count. More specifically, the row hammer detection system 110 may query the counts of the table, and if any count of the corresponding address is equal to the overflow count, the row hammer detection system 110 may perform an action 408 of inserting the address of the detected row activation into the address field of the corresponding entry (or one of the address fields having a count that matches the overflow count). The row hammer detection system 110 may then proceed to perform an action 410 of incrementing the count for the new row entry. Figure 4 As shown, after incrementing the count for the row entry, the row hammer detection system 110 may return to perform action 402 regarding the next row activation.

[0063] Returning to act 406, in the event that the row hammer detection system 110 determines that there is no table entry equal to the overflow count, the row hammer detection system 110 may perform an act 412 of incrementing or otherwise iterating the overflow count. As is apparent from the illustrated series of acts 400, the overflow count should generally be the lowest count (or equal to the lowest count) of any of the entries within the activation table. Furthermore, it should be noted that one of the entries (e.g., the address count or the overflow count) should be incremented with each row activation. Furthermore, while the entries within the activation count table may be replaced with any address of the corresponding sub-memory bank (e.g., as illustrated at act 408), it should be understood that the particular count of the corresponding address in the activation count table reflects an upper limit estimate of the address represented within the activation count table at any time. Thus, while the activation count does not necessarily reflect the exact number of activations for a particular row address, the activation count does represent an upper limit estimate for the corresponding row address.

[0064] like Figure 4 As shown, the row hammer detection system 110 may perform an action 414 of determining whether the overflow count of the activation count table is greater than (or equal to) the threshold count. In the event that the overflow count does not exceed the threshold count, the row hammer detection system 110 may return to perform action 402 regarding the next row activation. Conversely, in the event that the overflow count is greater than (or equal to) the threshold count, the row hammer detection system 110 may perform an action 416 of activating the sampling mode. Additional information related to implementing the sampling mode is discussed below.

[0065] It should be noted that the overflow count may be considered a metric for determining whether the counting method is being overwhelmed by a potential row hammer attack. In one or more embodiments, an overflow count being equal to or above a threshold count may not mean that a row hammer attack has necessarily occurred, but rather that a row hammer attack may have occurred (or be predicted to be occurring) based on abnormal read or write behavior that the counting mode is not fully equipped to handle. This may be caused by row hammering, or alternatively, may be caused by other read and / or write behavior with respect to row addresses of a particular sub-memory bank.

[0066] Although not in Figure 4 , it should be understood that the series of actions 400 may be performed relative to a certain time interval. For example, in one or more embodiments, the activation count table may be cleared at periodic intervals (e.g., at each refresh window), which may include resetting the activation count and the overflow count to zero. The hammer detection system 110 may determine the specific time interval based on the specifications of the memory hardware 122 and / or the hardware (e.g., SRAM structure) of the memory controller 108.

[0067] Although the clearing interval may vary from system to system, in one or more embodiments described herein, the row hammer detection system 110 resets the count of the activation count table for each refresh window based on the specification or generation of the DRAM hardware (e.g., 32 milliseconds in DDR5 and 64 milliseconds in DDR4). In one or more implementations, the row hammer detection system 110 resets the activation count for the associated memory sub-bank based on determining that the row hammer detection system 110 is used in the counting mode of the corresponding sub-memory bank after a predetermined interval has passed. Therefore, in one or more examples described herein, after 32 milliseconds have passed and the overflow count misses or exceeds the threshold and triggers activation of the sampling mode, the row hammer detection system 110 may assume that a row hammer attack is not currently occurring for the associated memory sub-bank and reset the count and continue to track the count, as described above in conjunction with Figure 4 In one or more embodiments, the row hammer detection system 110 uses a counter invalidation register (CIR) on the memory controller 108 to clear the counter of the activation count table.

[0068] In addition, it should be understood that the activation counter may not be cleared simultaneously for each of the sub-banks. For example, refresh windows may be interleaved between different sub-banks. Some sub-banks may have refresh windows of different lengths than other sub-banks. In addition, as described above, in the event that the row hammer detection system 110 has activated the sampling mode for a given sub-bank, the row hammer detection system 110 may not reset the count of the associated sub-bank at the end of the predetermined interval. In one or more implementations, the row hammer detection system 110 may wait to receive a specific instruction (e.g., from the memory hardware 122 or the operating system 104) to transition back to the counting mode for the memory sub-banks. Additional details related to determining whether (and when) to re-enable the counting mode will be discussed in more detail below.

[0069] Figure 5 5 shows a series of example actions 500 that the hammer detection system 110 may perform in response to detecting a trigger condition associated with transitioning from the counting mode to the enabled sampling mode. For example, the hammer detection system 110 may perform an action based on detecting that the overflow count equals or exceeds a threshold for a given time interval (e.g., Figure 4 ) to perform a series of actions 500 on a specific sub-memory storage body.

[0070] like Figure 5 As shown, the row hammer detection system 110 may perform an act 510 of activating or otherwise enabling a sampling mode. In one or more embodiments, activating the sampling mode includes determining one or more thresholds and parameters associated with implementing the sampling mode. For example, the row hammer detection system 110 may define a sampling threshold that is compared to a random number. In one or more embodiments, the sampling threshold is determined based on a maximum activation count (MAC) that the memory hardware 122 is configured to tolerate before a bit value changes due to a row hammer attack. For example, as mentioned above, a MAC may refer to a metric that measures the number of activations that a row can maintain until a bit in an adjacent row (or within a certain range of impact) flips (e.g., from 0 to 1 or from 1 to 0).

[0071] As described above, the sampling threshold can vary based on the specifications of the memory hardware 122 and / or the memory controller 108. As described above, the MAC value can be considered in determining a particular threshold and the probability that a given random number will fall within the sampling threshold. In one or more embodiments, the threshold is set based on the assumption that a row hammer attack may affect up to four rows. Other implementations may determine slightly different thresholds based on similar (or different) considerations specific to the memory hardware 122. As described above, the MAC value can vary from device to device. However, despite the variable MAC value, sampling threshold, and sampling probability register value, it should be understood that one or more embodiments described herein can achieve a row hammer failure rate of less than 1e-10 during the five-year life of the memory hardware 122.

[0072] In addition to setting the sampling threshold, the hammer detection system 110 can also activate the sampling mode by setting the total sampling register (ASR) to an "on" value. Figure 4 and Figure 5 , but in one or more embodiments, the hammer detection system 110 may first check the ASR bit to determine whether to implement an action according to the counting mode (e.g., Figure 4 ) or implement actions according to the sampling mode (e.g., Figure 5 ). Thus, where the row hammer detection system 110 can be configured to check the ASR bit in response to each detected row activation, the ASR bit can act as a signal or trigger to implement one of the corresponding operating modes (i.e., counting mode or sampling mode). Thus, in this example, setting the ASR value to "on" will trigger the sampling mode for each subsequently detected activated row until the row hammer detection system 110 receives an instruction to re-enable the counting mode.

[0073] Although not in Figure 5 , but as an alternative to setting the ASR bit to "ON" to enable sampling mode, the hammer detection system 110 may additionally implement features for selectively determining when to re-enable counting mode (or remain in sampling mode). Additional details regarding conditions and triggers for transitioning from sampling mode (or remaining in sampling mode) will be discussed in further detail below.

[0074] As described above, in one or more embodiments, a sampling mode is activated for a particular memory sub-bank. In fact, in one or more examples described herein, the decision to transition between a counting mode and a sampling mode will be performed on a sub-bank-by-sub-bank basis. Therefore, in the case where the sampling mode is activated for a first sub-bank, the hammer detection system 110 may continue to maintain activation counts for other memory sub-banks of the same memory bank (and other memory banks) while implementing the sampling mode for the first memory sub-bank. In one or more embodiments, the hammer detection system 110 may simultaneously execute the sampling mode on multiple sub-memory banks while implementing the counting mode on other (multiple) memory sub-banks.

[0075] When the sampling mode is activated and the relevant parameters, sampling thresholds and other values ​​are set, the row hammer detection system 110 can perform an action 520 of detecting activation of the next address. For example, similar to one or more embodiments described above, the row hammer detection system 110 can identify an activation command including a corresponding address and a sub-bank identifier. As discussed above, the row hammer detection system 110 can identify the relevant sub-bank based on the sub-bank identifier from the activation command.

[0076] like Figure 5 As shown, the hammer detection system 110 may perform an act of generating a random number 530. In one or more embodiments, the hammer detection system 110 generates the random number using a linear feedback shift register (LFSR) (or other more robust mechanism) on the memory controller 108. As described above, when the sampling mode is activated and various thresholds and parameters for the sampling mode are determined, a range of potential random numbers may be determined.

[0077] As further shown, the hammer detection system 110 can perform an action 540 of determining whether the random number is within a sampling threshold. As described above, the sampling threshold can be determined when the sampling mode is activated. In at least one example described herein, the random number is compared to a sampling probability register (SPR) value. The implementation of the random source can specify a specific value for the sampling threshold (e.g., how large the SPR value needs to be).

[0078] As described above, the specific value(s) and threshold of the SPR may be determined based on the hardware specifications of the memory controller 108 and the acceptable probability that a given row hammer attack may not be mitigated before causing data to be corrupted. In particular, the sampling threshold(s) may be determined to achieve a failure rate equal to or below a threshold. In one or more embodiments described herein, the sampling threshold may be determined based on a maximum activation count (MAC) metric that measures the number of activations that a row may maintain until bits in an adjacent (or nearby) row begin to flip. The MAC value may represent the minimum recorded number of activations for a given row that flips bits in a nearby row (e.g., an adjacent row). In one or more embodiments described herein, the MAC value may refer to approximately one thousand (1000). However, other memory hardware 122 may have different MAC values, which will result in different sampling thresholds (e.g., as shown in the table above).

[0079] like Figure 5 As shown, if the random number is not within the sampling threshold, the row hammer detection system 110 may return to act 520 and detect the activation of the next row address. In this case, the row hammer detection system 110 may not issue a refresh command for the given row address. Conversely, if the row hammer detection system 110 determines that the random number is within the sampling threshold, the row hammer detection system 110 may perform act 550 of generating a refresh command.

[0080] A refresh command may include any command sent from the memory controller 108 to the memory hardware 122 to facilitate refreshing one or more rows of memory corresponding to a suspected row hammer attack. For example, in one or more embodiments, the refresh command includes a command indicating a specific row or range of rows and instructions that enable the memory hardware 122 to locally execute the refresh command on the specific row of memory. In one or more embodiments, the refresh command is a directed refresh management (DRFM) command with a hardware specific scheme (e.g., a double data rate (DDR) scheme, such as DDR5), in which the memory controller reports the identity of the attack row and requests the memory hardware 122 (e.g., DRAM device) to refresh all victims affected by a given attack row.

[0081] In one or more embodiments, the refresh command includes an indication of an impact range. For example, the row hammer detection system 110 may generate and issue a refresh command indicating a row suspected of being an attack row in combination with an impact range that defines a predetermined number of rows (e.g., two rows) at a threshold distance from the attack row. The impact range may indicate both the attack row and the row(s) on either side of the attack row within the threshold distance as row addresses that should be refreshed in response to the refresh command. In one or more embodiments, the row hammer detection system 110 simply identifies the attack row and the associated impact range (or the impact range is determined locally by the memory hardware 122). Alternatively, the row hammer detection system 110 may simply send a refresh command (e.g., a DRFM command) for each affected row, including the attack row and one or more rows on each side of the attack row (e.g., depending on the impact range).

[0082] As described above, in one or more embodiments, the hammer detection system 110 can limit the number of refresh commands issued within a given time period. For example, in one or more embodiments, the hammer detection system 110 can be limited to issuing a limited number of commands per memory bank within a given time interval. In one or more embodiments described herein, the hammer detection system 110 can be limited to a single refresh command every 7.8 microseconds (or other interval determined by the hardware specification).

[0083] To prevent the hammer detection system 110 from violating this limitation of the memory system 106, the hammer detection system 110 may track the refresh commands issued over a predetermined interval (e.g., a 7.8 microsecond interval) to ensure that the hammer detection system 110 does not issue more than a threshold number of commands over a predetermined interval (for a particular memory bank). In one or more embodiments, the hammer detection system 110 may issue only one refresh command for a given memory bank or sub-memory bank within a predetermined interval. The predetermined number of commands and the predetermined interval may be known or determined based on the specifications of the memory hardware 122.

[0084] In addition to determining whether to report a row address as an attacking row by issuing a refresh command, the row hammer detection system 110 may also track or otherwise maintain various data while in the sampling mode. For example, as described above, the row hammer detection system 110 may track a number of signals that may be used to determine whether to re-enable the counting mode after the sampling mode has been enabled for a period of time (e.g., a number of refresh windows).

[0085] As an example, Figure 6 2 shows an example count record 602 that may be maintained when the hammer detection system 110 is in sampling mode. Figure 6 As shown, the count record 602 may include one or more sampling mode countdowns 604, one or more overflow counts 606 (e.g., overflow countdowns), one or more clear bits 608, and additional values ​​previously discussed in connection with implementing the count mode. Figure 6 As shown, count record 602 may include overflow count(s) 610 and row address and count pairs 612a-n for one or more memory subbanks. Count record 602 may be maintained within an SRAM structure on memory controller 108 similar to other records and entries described herein.

[0086] like Figure 6 As shown, the count record 602 may include any number of rows, referred to as countdown entries. In this example, the count record 602 may include M entries (e.g., M - number of entries). Each countdown entry may include a corresponding countdown and other tracking values ​​associated with a corresponding memory sub-bank. In one example, the count record 602 contains 512 entries corresponding to an associated number of sub-banks of a plurality of memory banks. In one or more implementations, the count record 602 includes only as many rows as there are sub-banks in sampling mode. For example, the row hammer detection system 110 may generate or populate rows of the count record 602 based on enabling sampling mode for an associated memory sub-bank. As shown in FIG. Figure 6 As shown, each row of count record 602 may include some or all of the values ​​of the corresponding entry.

[0087] As described above, the count record 602 includes a set of sampling mode countdowns 604. The sampling mode countdown can refer to a value from which the row hammer detection system 110 counts down when determining the length of time that the associated memory sub-bank remains in the sampling mode. As described above, when there is a high probability or possible row hammer attack (e.g., causing the counting mode to become overwhelmed), the sampling mode represents a safer operating mode than the counting mode. As such, in the case of a potential vulnerability, it may be beneficial to remain in the sampling mode for a period of time before re-enabling the counting mode.

[0088] When the sampling mode countdown is started, the hammer detection system 110 can iterate the value of the countdown field at regular intervals. For example, in one or more embodiments, the set of sampling mode countdowns 604 decrements the value at each refresh window. In the case where each memory sub-storage bank has an associated refresh window, each of the sampling mode countdown values ​​can be decremented while in sampling mode. In one or more embodiments, this decrement action is triggered by the value of the clear bit 608.

[0089] In one or more embodiments, the sampling mode countdown is initialized to a starting value and iterates (e.g., counts down) with each refresh window. For example, the row hammer detection system 110 can set the sampling mode countdown to a predetermined initial value associated with an expected or preconfigured length of time that the memory controller 108 should enable the sampling mode for the corresponding memory sub-bank. In practice, the row hammer detection system 110 can determine (or receive instructions indicating) that the sampling mode should be enabled for a fixed duration when transitioning from the counting mode to ensure that an expected or desired row hammer attack has sufficient time to resolve.

[0090] The initial value of the sampling mode countdown 604 can be based on a number of factors. For example, as described above, the sampling mode countdown bits can be initially set based on the expected time period that the memory controller 108 is configured to remain in the sampling mode to prevent or mitigate potential row hammer attacks. In one or more embodiments, the sampling mode countdown value is initialized based on minimizing the number of refresh intervals for which the memory subbank is considered vulnerable. In practice, the row hammer detection system 110 can reduce the total number of vulnerable refresh windows by reducing the total number of instances that the memory controller 108 transitions between the counting mode and the sampling mode.

[0091] In one or more embodiments, the initial value of the sampling mode countdown(s) is determined based on a maximum amount of time (e.g., one hour) over a longer duration (e.g., one month) that a given memory sub-bank should be vulnerable to a row hammer attack. Specifically, the row hammer detection system 110 can establish an initial countdown value that ensures a maximum number of refresh windows that the memory sub-bank may be vulnerable to due to transitioning between operating modes (e.g., in a worst-case scenario, such as when the count mode is quickly overwhelmed at each refresh window after re-enabling the count mode).

[0092] In one or more embodiments, the initial countdown value is set to a high flag or high threshold that causes or otherwise signals the memory controller 108 to enter a sampling mode for an undetermined period of time. For example, in the event that a row hammer attack is determined to be highly likely or in the event that a system-wide row hammer attack is confirmed, the row hammer detection system 110 may cause the memory controller 108 to enable a sampling mode for some or all memory sub-banks for the entire duration of the suspected or confirmed row hammer attack. In this example, the row hammer detection system 110 may fix the countdown value at the high threshold and cause the memory controller 108 to remain in the sampling mode until the row hammer attack is mitigated.

[0093] One or more of the sampling countdown values ​​may be initialized to semi-randomized values. For example, to reduce the predictability of the countdown values ​​and prevent a potentially deterministic approach to implementing a row hammer attack, the row hammer detection system 110 may randomize one or more bits represented in the sampling mode countdown. As an illustrative example, when initializing the sampling mode countdown value when enabling sampling mode, the row hammer detection system 110 may randomize the three least significant bits (LSBs) of the sampling mode countdown value. Such randomness may prevent a certain deterministic approach to a row hammer attack without causing the memory controller 108 to remain in sampling mode for an unreasonable number of refresh windows.

[0094] like Figure 6 As further shown in FIG. 6 , the count record 602 may include a set of overflow override counts 606. As described herein, the overflow override count for a given entry may include a value indicating the number of refresh windows during which the memory subbank was occupied in the sampling mode where the overflow count exceeded a threshold. As described above, the row hammer detection system 110 may continue to track various values ​​associated with the count mode without issuing any refresh commands in response to the count mode condition.

[0095] For example, the hammer detection system 110 may continue to track the addresses and count values ​​612a-n of the corresponding memory sub-banks, except for the overflow count 610 indicating the case where the memory sub-bank is already in the counting mode, and the memory controller 108 will be in the sampling mode of the associated memory sub-bank. Figure 2-Figure 4 The row hammer detection system 110 may maintain the overflow count 606 for each refresh window for the entire duration that the memory controller 108 has enabled the sampling mode for the corresponding memory sub-bank.

[0096] Although some examples described herein refer to the overflow count 606 as a count value indicating the number of refresh windows when the corresponding overflow count 610 exceeds a threshold, in one or more embodiments, the overflow count 606 is a countdown value that counts down from an initial value. For example, the overflow count can be initialized to a predetermined value when the sampling mode is enabled. As will be discussed in further detail below, the overflow count can be decremented until it reaches zero, which can be used as a signal when determining whether to re-enable the counting mode (e.g., after the corresponding sampling mode countdown has also been decremented to zero).

[0097] In addition to general telemetry and tracking instances where the counting mode would be overridden if the counting mode was used, tracking the overflow count provides the following advantages: the hammer detection system 110 can selectively determine whether to re-enable the counting mode based on a combination of the sampling mode countdown value and the corresponding overflow count value. For example, if the overflow count is greater than a threshold, or equal to any non-zero number, the hammer detection system 110 can determine that the memory controller 108 will likely revert to the sampling mode in a short period of time. Based on this determination, the hammer detection system 110 can determine to remain in the sampling mode even after the sampling mode countdown has reached a minimum value (e.g., zero).

[0098] In one or more embodiments, rather than establishing a static or predetermined threshold overflow count that is applicable to all memory sub-banks across the memory hardware, the row hammer detection system 110 initializes the value of the overflow count for a given memory sub-bank to be a function of the initial value of the sampling mode countdown value. For example, the row hammer detection system 110 may set the overflow count to a ratio of the initial sampling mode countdown value. In the case where the sampling countdown value has a randomness measure, this may additionally introduce a measure of randomness in the overflow count, thereby further increasing the difficulty of planning a row hammer attack on the memory hardware.

[0099] In this example where the overflow count is initialized to a non-zero value (e.g., a ratio of the initial sampling mode countdown value), the row hammer detection system 110 can determine whether to iterate (e.g., decrement) the overflow count value at each refresh interval. For example, similar to one or more examples described herein, the row hammer detection system 110 can iterate the overflow count at the beginning or end of a refresh interval based on the overflow count exceeding a threshold (or simply upon detecting that the overflow count exceeds a threshold).

[0100] The row hammer detection system 110 may consider the overflow count value in conjunction with the sampling mode countdown value when determining whether to re-enable the counting mode or continue to enable the sampling mode. For example, when the sampling mode countdown reaches zero (or other minimum threshold), the row hammer detection system 110 may re-enable the counting mode only if the overflow count is greater than zero. Otherwise, the row hammer detection system 110 may remain in the sampling mode. Similar to the other examples herein, this further limits the number of times the row hammer detection system 110 will transition between operating modes, particularly when the memory controller 108 is likely to re-enable the sampling mode only after a few refresh intervals.

[0101] As mentioned above, and as Figure 6 As shown, the count record 602 includes a set of clear bits 608 for each entry (e.g., row) of the count record 602. The clear bits 608 can be toggled or set to signal that the sampling mode countdown should be decremented at each refresh interval. In one or more of the above-described possible or confirmed examples of a row hammer attack being conducted, each of the clear bits 608 can be set to an off or on mode associated with stopping the sampling mode countdown for a period of time (and maintaining the memory controller 108 in the sampling mode indefinitely).

[0102] Figure 7 An exemplary timeline 702 is shown, which shows the memory controller 108 enabling the operating mode over the series refresh window. Figure 7 As shown in FIG. 1 , the memory controller 108 may enable a counting mode (CM) 710 at a first counting mode stage 704 and transition to enabling a sampling mode (SM) 712 at a second sampling mode stage 706. Figure 7 As shown, the counting mode phase 704 can extend multiple refresh windows. Similarly, the sampling mode phase 706 can extend multiple refresh windows.

[0103] like Figure 7 As further shown in , during the indicated refresh window, the memory sub-bank may be secure (or not vulnerable to a row hammer attack). In this example, in the event that the counting mode becomes overwhelmed and causes the memory controller 108 to transition from the counting mode to the sampling mode, the memory sub-bank associated with the timeline 702 may experience a transition window 708 in which the memory sub-bank is vulnerable to a row hammer attack. This is because the counting mode has become overwhelmed, and between making this determination and transitioning to the safer sampling mode, the memory sub-bank may be vulnerable. As described above, the row hammer detection system 110 can limit the number of transition windows between operating modes by setting the initial value of the countdown to a particular value or establishing certain conditions that limit going back and forth between operating modes (e.g., requiring the overflow count to be greater than zero or other predetermined value).

[0104] Figure 7 Additionally shown is a sampling workflow of events between enabling counting mode (CM) 710, enabling sampling mode (SM) 711, and enabling sampling mode (SM) 712. For example, the memory controller 108 can remain in counting mode as long as the overflow count is less than a threshold. When the counter is overwhelmed, the hammer detection system 110 can initialize the sampling mode (SM) 711 by enabling one or more countdown values. This can include enabling the sampling mode countdown and the overflow count values, as discussed in one or more embodiments above. The hammer detection system 110 can then enter the sampling mode (SM) 712. The memory controller can remain in sampling mode as long as the sampling mode countdown is above a minimum value (e.g., zero). The memory controller can also consider the overflow count when determining whether to remain in sampling mode.

[0105] To illustrate, in Figure 7 In the example shown, in the case where the sampling mode countdown is greater than zero, the hammer detection system 110 may continue to enable the sampling mode (SM) 712. In the case where the sampling mode countdown reaches zero and the overflow count is equal to or less than zero, the hammer detection system 110 may start the sampling mode again by setting the values ​​of the sampling mode countdown and the overflow count to the initial values, and then re-enable the sampling mode. Alternatively, in the case where the sampling mode countdown reaches zero and the overflow count is greater than zero (or other predetermined minimum value), the hammer detection system 110 may re-enable the counting mode (CM) 710.

[0106] Figure 8 A series of example actions 800 are shown in connection with transitioning back and forth between a counting mode and a sampling mode in various situations and based on various strategies. Figure 8 The actions shown may be implemented in conjunction with any of the above examples described herein. In addition, any of the features and functions of the hammer detection system 110 described in conjunction with the previous examples may be combined with the series of actions 800 described below. In one or more embodiments, the series of actions 800 is performed by the memory controller 108 coupled to the memory hardware 122. In addition, according to one or more embodiments described herein, Figure 8 The actions may be suitable for facilitating transitions between operating modes in one or across multiple memory sub-banks.

[0107] like Figure 8As shown, the series of actions 800 includes an action 802 of enabling a sampling mode. As described above, enabling the sampling mode may involve transitioning from the counting mode based on the counting mode becoming overwhelmed for a given refresh window (e.g., based on an overflow count value exceeding a predetermined threshold). Also as discussed above, enabling the sampling mode may involve a transition window in which a memory sub-bank is in a vulnerable state for the duration of the refresh window (e.g., thirty-two milliseconds). In one or more embodiments, the action 802 of enabling the sampling mode includes starting the sampling mode of the memory sub-bank that previously enabled the counting mode. Other implementations may simply involve continued enabling of the sampling mode for subsequent refresh windows (e.g., as discussed below in conjunction with action 820).

[0108] When the sampling mode is enabled, the row hammer detection system 110 may perform an action of clearing the overflow count 804. As described above, the row hammer detection system 110 may cause the overflow counts of one or more memory subbanks to be cleared at each refresh window. In this example, the row hammer detection system 110 may clear the overflow counts based on initiating the sampling mode or, alternatively, based on detecting the beginning of a new refresh window (or the end of a previous refresh window).

[0109] In addition to clearing the overflow count, the hammer detection system 110 may perform an iterative countdown action 806. Figure 8 , but the row hammer detection system 110 can set the countdown to an initial value based on an estimated, minimum, or otherwise predetermined period of time that the memory controller 108 should be enabled in the sampling mode. Once enabled, the row hammer detection system 110 can repeatedly count down by decrementing (or incrementing) the countdown value with each refresh interval.

[0110] like Figure 8 As shown, the hammer detection system 110 may perform an action 808 of determining whether the countdown has hit zero. Other implementations may include determining that the countdown has fallen below an arbitrary threshold. If the countdown is less than (or equal to) a minimum threshold (e.g., zero), the hammer detection system 110 may perform an action 810 of determining whether the overflow count has hit zero (e.g., when the overflow count is a countdown). In one or more embodiments, the hammer detection system 110 may determine that the overflow count is less than a minimum threshold count associated with allowing the memory controller 108 to re-enable the counting mode.

[0111] It should be noted that although the sampling mode countdown and overflow count are interchangeably referred to herein as a count or countdown compared to a threshold, it should be understood that one or more embodiments of the memory controller include hardware limitations that require a specific value to be the countdown value. Figure 8As shown, the sampling mode countdown is monitored to determine when the countdown values ​​of the sampling mode countdown and the overflow count (countdown) are equal to zero.

[0112] like Figure 8 As shown, in the event that the overflow count is greater than zero (e.g., in the event that the overflow count has iterated or decremented less than some predetermined number of times), the hammer detection system 110 may perform an action 812 of enabling (or re-enabling) the counting mode. Thus, in the example shown, based on the countdown hitting zero and the overflow count being greater than zero (e.g., failing to decrement to zero), the hammer detection system 110 may transition from the sampling mode to the countdown mode until the countdown mode becomes overwhelmed again or the hammer detection system 110 receives an indication of a possible hammer attack.

[0113] like Figure 8 As shown, when the hammer detection system 110 determines that the countdown has not reached zero and / or the overflow count is not greater than zero (e.g., when the overflow count is equal to or less than the minimum value), the hammer detection system 110 can perform action 814 of maintaining the activation count for the refresh window and maintaining the sampling mode. As described above, even when the hammer detection system 110 is not in the counting mode, the hammer detection system 110 can still maintain the activation count and the overflow value of the memory sub-bank.

[0114] At each activation, the hammer detection system 110 may perform an act of determining whether the overflow count is greater than a threshold 816. For example, consistent with one or more embodiments described above, the hammer detection system 110 may determine whether the overflow count for a refresh interval is greater than a threshold overflow count that triggers a transition from a counting mode to a sampling mode.

[0115] In the event that the hammer detection system 110 determines that the overflow count is greater than (or equal to) the threshold overflow count, the hammer detection system 110 may perform an action 818 of iterating the overflow count (eg, decrementing the overflow count by one). Figure 8 As shown, this may occur once per refresh window. In the case where the overflow count is not greater than the threshold, or in the case where the overflow count has been iterated for the current refresh window, the row hammer detection system 110 may perform action 820 of determining whether the refresh window has ended. In the case where the refresh window is still in progress, the row hammer detection system 110 may continue to perform the above-mentioned action 814. Alternatively, in the case where the refresh window has ended, the row hammer detection system 110 may perform action 802 again by continuing to enable the sampling mode for the corresponding memory sub-bank.

[0116] In one or more embodiments, the hammer detection system 110 can also implement integrity protection for memory hardware by checking for various errors and performing appropriate actions based on the type of error detected. For example, in the event that an error is detected but cannot be corrected, the hammer detection system 110 can perform one of various actions based on various strategies.

[0117] For example, where the detected error is a count (e.g., a row activation count), the row hammer detection system 110 may set the count to one less than a row hammer attack threshold (e.g., a threshold associated with the likelihood of a row hammer attack). As another example, when an error is detected in the overflow count while in the counting mode, the row hammer detection system 110 may set the overflow count to zero. When an error is detected in the address while in the sampling mode, the row hammer detection system 110 may set the overflow count to the row hammer attack threshold.

[0118] Other errors may cause the hammer detection system 110 to determine whether to enable a particular mode of operation. For example, in the case of other errors detected in the counting mode (e.g., errors other than those described above), the hammer detection system 110 may enable the sampling mode. In the case of other errors detected in the sampling mode, the hammer detection system 110 may re-enter the sampling mode.

[0119] The row hammer detection system 110 may implement integrity protection at a certain frequency on a per memory sub-bank basis. For example, in one or more embodiments, the row hammer detection system 110 may perform error checking on each row activation before running the above algorithm.

[0120] Now go to Fig. 9 , which shows an exemplary flow chart including a series of actions for detecting and mitigating suspected row hammer attacks on row addresses of memory hardware (e.g., DRAM devices) and tracking transitions between activation modes of memory rows on the memory hardware. Fig. 9 Actions according to one or more embodiments are shown, but alternative embodiments may omit, add to, reorder, and / or modify Fig. 9 Any action shown. Fig. 9 The actions of may be performed as part of a method. Alternatively, the non-transitory computer-readable medium may include a computer device (eg, a server device) that, when executed by one or more processors, causes the computer device to perform Fig. 9 In a further embodiment, the system may execute Fig. 9 action.

[0121] Fig. 9An example series of actions 900 are described in connection with detecting and mitigating a row hammer attack on a DRAM device and determining whether to transition between various operating modes associated with determining whether a row hammer attack is occurring on a row address. Fig. 9 As shown in , the series of actions of action 900 includes action 910 of enabling a counting mode for a memory sub-bank by maintaining a row activation count and an overflow count. In one or more embodiments, action 910 involves enabling a counting mode for a memory sub-bank by maintaining a count of multiple row activations for memory rows within the memory sub-bank and an overflow count based on memory row activations for at least one memory row not included in the multiple counts.

[0122] like Fig. 9 As further shown in , series of acts 900 includes act 920 of determining that the overflow count exceeds a threshold count associated with a possible attacking row. In one or more embodiments, act 920 includes determining that the overflow count exceeds a threshold count associated with a likelihood of an attacking row from a memory subbank.

[0123] like Fig. 9 As further shown in , the series of actions 900 includes an action 930 of enabling a sampling mode based on an overflow count exceeding a threshold count, wherein enabling the sampling mode includes maintaining a sampling mode countdown. In one or more embodiments, action 930 includes enabling a sampling mode for a memory sub-storage body based on an overflow count exceeding a threshold count. In one or more implementations, enabling the sampling mode includes determining whether to report a row address as an attack row based on a comparison of a random number with a sampling threshold. In one or more embodiments, enabling the sampling mode includes maintaining a countdown for the sampling mode by iterating a sampling mode countdown value at a refresh window. In one or more embodiments, the sampling mode countdown is initialized to a first value based on a threshold number of refresh windows within a time period in which the memory sub-storage body is not protected against possible attack rows.

[0124] like Fig. 9 As further shown in , series of actions 900 includes action 940 of re-enabling counting mode based on sampling mode iterating to a threshold value (e.g., zero). In one or more embodiments, action 940 includes re-enabling counting mode from sampling mode based on sampling mode countdown value iterating to a threshold countdown value.

[0125] In one or more embodiments, enabling a sampling mode includes maintaining a row activation count and an associated overflow count for a memory sub-bank across multiple refresh windows. Enabling the sampling mode may also include maintaining an overflow count indicating the number of refresh windows when a sampling mode is enabled in which an overflow count is determined to exceed a threshold count. In one or more embodiments, re-enabling the counting mode is also based on the overflow count being less than an overflow count threshold. In one or more embodiments, the overflow count is a countdown value, and re-enabling the counting mode is also based on the countdown reaching zero of the overflow count equal to zero. In one or more embodiments, the row activation count and the associated overflow count of the memory sub-bank are cleared at each refresh window in the multiple refresh windows.

[0126] In one or more embodiments, the series of actions 900 includes determining a vulnerable condition of a memory sub-bank associated with one or more attack rows on a DRAM device. The series of actions 900 may further include: based on determining the vulnerable condition of the memory sub-bank, fixing the operation mode for the memory sub-bank to a sampling mode by setting a sampling mode countdown value to a high threshold countdown value.

[0127] In one or more embodiments, enabling the sampling mode includes initializing a sampling mode countdown value to an initial value that is a randomized value within a predetermined range of the initial sampling mode countdown value. In one or more embodiments, the memory subbank is one of a plurality of memory subbanks of memory banks from a DRAM device, wherein enabling the sampling mode includes selectively enabling the sampling mode for the memory subbank without enabling the sampling mode for one or more additional memory subbanks of the plurality of memory subbanks.

[0128] In one or more embodiments, determining whether to report an attack row includes determining that the random number falls within a sampling threshold and issuing a refresh command for the row address, the refresh command indicating that the row address is a predicted attack row. In one or more embodiments, a table having a plurality of row activation counts and overflow counts thereon is maintained in an SRAM structure on a memory controller coupled to the DRAM device.

[0129] In one or more embodiments, the series of actions 900 includes actions configured to be performed by a memory controller coupled to a DRAM device, wherein the DRAM device includes a plurality of memory banks, each memory bank of the plurality of memory banks including a plurality of memory sub-banks.

[0130] In one or more embodiments, the memory controller may perform an action of enabling a sampling mode for a memory sub-bank, wherein enabling the sampling mode includes determining whether to report a row address as an attack row based on a comparison of a random number to a sampling threshold, and maintaining a countdown of the sampling mode by iterating a sampling mode countdown value at a refresh window. In one or more embodiments, the memory controller may perform an action of enabling a counting mode for a memory sub-bank based on a sampling mode countdown value iterated to a threshold, wherein enabling the counting mode for the memory sub-bank includes maintaining a count of a plurality of row activations for memory rows within the memory sub-bank, and an overflow count based on memory row activations for at least one memory row not included in the plurality of counts. In one or more embodiments, the memory controller may perform an action of determining whether to re-enable the sampling mode for the memory sub-bank based on whether the overflow count exceeds a threshold count associated with a likelihood of an attack row for the memory sub-bank.

[0131] Similar to one or more embodiments described above, the memory controller may enable a sampling mode by maintaining a row activation count and an associated overflow count for a memory sub-storage body over multiple refresh windows, and maintaining an overflow count indicating the number of refresh intervals when a sampling mode in which an overflow count is determined to exceed a threshold count is enabled. In one or more embodiments, enabling the counting mode is also based on the overflow count being less than or equal to the overflow count threshold. In addition, in one or more embodiments, enabling the sampling mode includes initializing a sampling mode countdown value to an initial value that is a randomized value within a predetermined range of the initial sampling mode countdown value.

[0132] Fig.10 Illustrated are certain components that may be included within computer system 1000. One or more computer systems 1000 may be used to implement the various devices, components, and systems described herein.

[0133] The computer system 1000 includes a processor 1001. The processor 1001 may be a general-purpose single-chip or multi-chip microprocessor (e.g., an Advanced RISC (Reduced Instruction Set Computer) Machine (ARM)), a special-purpose microprocessor (e.g., a digital signal processor (DSP)), a microcontroller, a programmable gate array, etc. The processor 1001 may be referred to as a central processing unit (CPU). Fig.10 Only a single processor 1001 is shown in the computer system 1000 , but in an alternative configuration, a combination of processors (eg, an ARM and DSP) could be used.

[0134] The computer system 1000 also includes a memory 1003 in electronic communication with the processor 1001. The memory 1003 can be any electronic component capable of storing electronic information. For example, the memory 1003 can be implemented as a random access memory (RAM), a read-only memory (ROM), a magnetic disk storage medium, an optical storage medium, a flash memory device in a RAM, an on-board memory included in the processor, an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM) memory, a register, etc., including combinations thereof.

[0135] Instructions 1005 and data 1007 may be stored in memory 1003. Instructions 1005 may be executed by processor 1001 to implement some or all of the functionality disclosed herein. Executing instructions 1005 may include using data 1007 stored in memory 1003. Any of the various examples of modules and components described herein may be implemented in part or in whole as instructions 1005 stored in memory 1003 and executed by processor 1001. Any of the various examples of data described herein may be data 1007 stored in memory 1003 and used during execution of instructions 1005 by processor 1001.

[0136] The computer system 1000 may also include one or more communication interfaces 1009 for communicating with other electronic devices. The communication interface(s) 1009 may be based on wired communication technology, wireless communication technology, or both. Some examples of the communication interface 1009 include a universal serial bus (USB) Ethernet adapter, a wireless adapter operating according to the Institute of Electrical and Electronics Engineers (IEEE) 802.11 wireless communication protocol, Wireless communication adapter, and infrared (IR) communication port.

[0137] The computer system 1000 may also include one or more input devices 1011 and one or more output devices 1013. Some examples of input devices 1011 include keyboards, mice, microphones, remote control devices, buttons, joysticks, trackballs, touchpads, and light pens. Some examples of output devices 1013 include speakers and printers. One specific type of output device that is often included in the computer system 1000 is a display device 1015. The display device 1015 used with the embodiments disclosed herein may utilize any suitable image projection technology, such as a liquid crystal display (LCD), a light emitting diode (LED), gas plasma, electroluminescence, etc. A display controller 1017 may also be provided for converting data 1007 stored in the memory 1003 into text, graphics, and / or moving images (as appropriate) displayed on the display device 1015.

[0138] The various components of the computer system 1000 may be coupled together via one or more buses, which may include a power bus, a control signal bus, a status signal bus, a data bus, etc. For clarity, Fig.10 The individual buses are shown as bus system 1019.

[0139] The techniques described herein may be implemented in hardware, software, firmware, or any combination thereof, unless explicitly described as being implemented in a particular manner. Any features described as modules, components, etc. may also be implemented together in an integrated logic device, or separately as separate but interoperable logic devices. If implemented in software, the techniques may be implemented at least in part by a non-transitory processor-readable storage medium containing instructions that, when executed by at least one processor, perform one or more of the methods described herein. Instructions may be organized into routines, programs, objects, components, data structures, etc., which may perform specific tasks and / or implement specific data types, and which may be combined or distributed as desired in various embodiments.

[0140] Computer-readable media can be any available media that can be accessed by a general or special purpose computer system. A computer-readable medium that stores computer-executable instructions is a non-transitory computer-readable storage medium (device). A computer-readable medium that carries computer-executable instructions is a transmission medium. Therefore, by way of example and not limitation, embodiments of the present disclosure may include at least two distinct types of computer-readable media: a non-transitory computer-readable storage medium (device) and a transmission medium.

[0141] As used herein, non-transitory computer-readable storage media (devices) may include RAM, ROM, EEPROM, CD-ROM, solid-state drives (“SSD”) (e.g., RAM-based), flash memory, phase change memory (“PCM”), other types of memory, other optical disk storage, magnetic disk storage or other magnetic storage devices, and any other media that can be used to store desired program code means in the form of computer-executable instructions or data structures and that can be accessed by a general or special purpose computer.

[0142] The steps and / or actions of the methods described herein may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is required for the proper operation of the described method, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0143] The term "determining" encompasses a variety of actions, and thus, "determining" may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a data store, or another data structure), ascertaining, etc. In addition, "determining" may include receiving (e.g., receiving information, accessing (e.g., accessing data in a memory), etc. Furthermore, "determining" may include resolving, selecting, choosing, establishing, etc.

[0144] The terms "comprising," "including," and "having" are intended to be inclusive, and mean that there may be additional elements in addition to the listed elements. Additionally, it should be understood that reference to "one embodiment" or "an embodiment" of the present disclosure is not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the described features. For example, any element or feature described with respect to an embodiment herein may be combined with any element or feature of any other embodiment described herein where compatible.

[0145] The present disclosure may be embodied in other specific forms without departing from its essence or characteristics. The described embodiments should be considered illustrative rather than restrictive. Therefore, the scope of the present disclosure is indicated by the appended claims rather than by the preceding description. Changes within the meaning and scope of the equivalents of the claims will be included within their scope.

Claims

1. A method implemented by a memory controller, the memory controller being coupled to a dynamic random access memory (DRAM) device, the method comprising: enabling a counting mode for the memory sub-bank by maintaining a plurality of row activation counts for memory rows within the memory sub-bank and an overflow count of memory row activations based on at least one memory row not included in the plurality of counts; determining that the overflow count exceeds a threshold count associated with a likelihood of an attack row from the memory subbank; as well as Based on the overflow count exceeding the threshold count, enabling a sampling mode for the memory sub-bank, wherein enabling the sampling mode comprises: determining whether to report the row address as an attack row based on a comparison of the random number and a sampling threshold; and maintaining a countdown for the sampling mode by iterating a sampling mode countdown value at a refresh window; and The counting mode is re-enabled from the sampling mode based on the sampling mode countdown value iterating to a threshold countdown value.

2. The method of claim 1, wherein the sampling mode countdown value is initialized to a first value based on a threshold number of refresh windows during a time period when the memory sub-bank is not protected against a possible attack row.

3. The method according to any one of claims 1 to 2, wherein enabling the sampling mode further comprises: maintaining a row activation count and an associated overflow count for the memory subbank over a plurality of refresh windows; as well as When the sampling mode is enabled when the overflow count is determined to exceed the threshold count, an overflow count indicating a number of refresh windows is maintained. 4 . The method of claim 3 , wherein re-enabling the counting mode is further based on the overflow count being less than an overflow count threshold.

5. The method of any one of claims 3 to 4, wherein the row activation count and associated overflow count for the memory sub-bank are cleared at each refresh window of the plurality of refresh windows.

6. The method according to any one of claims 1 to 5, further comprising: determining a vulnerable condition of the memory sub-bank associated with one or more attack rows on the DRAM device; as well as Based on determining the vulnerable condition of the memory sub-bank, an operation mode for the memory sub-bank is fixed to the sampling mode by setting an initial value of the sampling mode countdown value to a high threshold countdown value.

7. The method of any one of claims 1 to 6, wherein enabling the sampling mode comprises initializing the sampling mode countdown value to an initial value, the initial value being a randomized value within a predetermined range of an initial sampling mode countdown value.

8. The method of any one of claims 1 to 7, wherein the memory sub-bank is one of a plurality of memory sub-banks of memory banks from the DRAM device, and wherein enabling the sampling mode comprises: The sampling mode is selectively enabled for the memory sub-bank without enabling sampling mode for one or more additional memory sub-banks of the plurality of memory sub-banks.

9. The method according to any one of claims 1 to 8, wherein determining whether to report an attack row comprises: Determining that the random number falls within the sampling threshold; as well as A refresh command is issued for the row address, indicating that the row address is the predicted attack row.

10. The method of any one of claims 1 to 9, wherein the plurality of row activation counts and a table thereon of the overflow counts are maintained in an SRAM structure on a memory controller coupled to the DRAM device.

11. A method implemented by a memory controller, the memory controller being coupled to a dynamic random access memory (DRAM) device, the method comprising: enabling a counting mode for a memory sub-bank by maintaining a plurality of row activation counts for memory rows within the memory sub-bank; determining that the count pattern for the memory subbank has become overwhelmed; as well as Based on the counting mode for the memory sub-bank having become overwhelmed, enabling a sampling mode for the memory sub-bank, wherein enabling the sampling mode comprises: determining whether to report the row address as an attack row based on a comparison of the random number and a sampling threshold; and maintaining a countdown for the sampling mode by iterating a sampling mode countdown value at a refresh window; and The counting mode is re-enabled from the sampling mode based on the sampling mode countdown value iterating to a threshold countdown value.

12. The method of claim 11, wherein determining that the counting mode for the memory sub-bank has become overwhelmed is based on determining that an overflow count tracked while enabled in the counting mode has exceeded a threshold count.

13. The method according to any one of claims 11 to 12, wherein enabling the sampling mode renders the memory sub-bank vulnerable to possible attacks against a refresh window, and During a time period when the memory sub-bank is not protected against possible attack rows, the sampling mode countdown value is initialized to an initial value based on a threshold number of refresh windows.

14. The method of any one of claims 11 to 13, wherein enabling the sampling mode comprises initializing the sampling mode countdown value to an initial value, the initial value being a randomized value within a predetermined range of an initial sampling mode countdown value.

15. A computer program, which, when executed on a process of a computing system, is configured to perform the method of any one of claims 1 to 14.

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