Electronic device and manufacturing method for electronic device

Abstract

The electronic device includes a substrate, a first via penetrating the substrate, a capacitive element over the substrate, and a first conductive film. A first portion of the first conductive film passes through the substrate along a sidewall of the first via, and a second portion of the first conductive film is in contact with the capacitive element.

Description

[0001] Related Applications

[0002] This application claims the benefit of Japanese Priority Patent Application JP2022-149708 filed on Sep. 21, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present technology relates to an electronic device and a method for manufacturing the electronic device. Specifically, the present technology relates to an electronic device provided with a capacitive element and a method for manufacturing the electronic device. Background Art

[0004] In order to absorb the current change of the load and suppress the fluctuation of the power supply voltage and the generation of noise, there is a situation where a capacitor element is formed in a semiconductor device, a circuit board, etc. For example, a semiconductor device in which a capacitor element is formed on an insulating film covering the first main surface of a wiring substrate is proposed, and the wiring substrate can also be a wiring provided with a through electrode (for example, refer to PTL1). In addition, a semiconductor device in which a capacitor element is formed on the inner peripheral surface of a through hole provided in an insulating substrate is proposed (for example, refer to PTL2).

[0005] [Citation List]

[0006] [Patent Document]

[0007] PTL 1: JP-2012-227266A

[0008] PTL 2: JP-2020-141090A Summary of the invention

[0009] [Technical issues]

[0010] However, with the above-described prior art, since the capacitance element is formed on the inner peripheral surface of the through hole, there is a possibility that the element area at the position of the through hole may be reduced.

[0011] The present technology has been proposed in view of the above circumstances, and it is desirable to form a capacitance element connected to a through-electrode while suppressing a reduction in the element area.

[0012] [Solution to the problem]

[0013] According to an embodiment of the present disclosure, an electronic device is provided, comprising: a substrate; a first through hole penetrating the substrate; a capacitor element above the substrate; and a first conductor film. The first portion of the first conductor film passes through the substrate along the side wall of the first through hole, and the second portion of the first conductor film contacts the capacitor element. The substrate comprises one or both of a semiconductor substrate comprising a semiconductor element and a wiring substrate comprising wiring. The capacitor element comprises an upper electrode, a lower electrode, and a dielectric film between the upper electrode and the lower electrode, the second portion of the first conductor film contacts the upper electrode, and the electronic device further comprises a second conductor film and a second through hole penetrating the substrate. The first portion of the second conductor film passes through the substrate along the side wall of the second through hole, and the second portion of the second conductor film contacts the lower electrode. The upper electrode and the lower electrode each comprise one or more of TiN, TaN, and WN. The dielectric film comprises one or more of SiO2, Si3N4, HfO2, Al2O3, ZrO2, and HfAlO. The dielectric film and the lower electrode have substantially equal planar dimensions to each other, and the upper electrode has a planar dimension smaller than the planar dimension of each of the dielectric film and the lower electrode. The electronic device also includes a sealing film on the capacitive element. The sealing film includes one or more of Si3N4 and Al2O3. The third portion of the second conductor film is separated from the upper electrode by the sealing film. The parasitic capacitance between the substrate and the lower electrode is equal to or less than one tenth of the capacitance of the capacitive element. The electronic device further includes: an insulating film on the capacitive element; and one or more of the wiring and external connection terminals above the capacitive element, with the insulating film interposed therebetween. The electronic device further includes a photosensitive insulating resin film covering the opening of the first through hole. The substrate includes a groove in which the capacitive element is embedded. The electronic device further includes a cavity arranged in the groove. The electronic device further includes an insulating film arranged above the cavity. The capacitive element includes capacitive electrodes having polarities different from each other and having sides opposite to each other. The first conductor film includes a plurality of through holes connected to the capacitive electrodes of the capacitive element. The capacitive element includes a plurality of capacitive elements having planar dimensions different from each other. The capacitive element includes a plurality of upper electrodes above the lower electrode, wherein the plurality of upper electrodes have planar dimensions different from each other. The electronic device further includes a via connected to the lower electrode through a gap between the upper electrodes. The first through hole penetrates the capacitor element. The electronic device further includes a wiring layer located on the bottom surface of the substrate and in contact with the first portion of the first conductor film. The bottom surface of the substrate is opposite to the top surface of the substrate. The electronic device further includes a semiconductor chip connected to the wiring layer. The semiconductor chip includes a solid-state imaging device. According to one aspect of the present disclosure, an electronic device is provided, comprising: a substrate; a capacitor element located above the substrate; and a through electrode penetrating the substrate and the capacitor element. The through electrode includes a first portion of the first conductor film, and wherein a second portion of the first conductor film is in contact with the capacitor element.

[0014] According to one aspect of the present disclosure, an electronic device is provided, comprising: a semiconductor substrate; a wiring layer located on the front side of the semiconductor substrate; a through electrode penetrating the semiconductor substrate and connected to the wiring layer; a groove in the back of the semiconductor substrate; a capacitor element embedded in the groove; and a wiring connecting the through electrode to the capacitor element. The wiring includes a conductor film, wherein the through electrode includes a portion of the conductor film. At least a portion of the capacitor element extends along the sidewall of the groove, and the sidewall of the groove includes a textured surface. The electronic device further includes a cavity in the groove. According to one aspect of the present disclosure, a method for manufacturing an electronic device is provided, the method comprising: forming a capacitor element on a substrate; forming a through hole in the substrate; and forming a through electrode along the sidewall of the through hole. The through electrode is electrically connected to the capacitor element. The through electrode includes a portion of the conductor film. The through electrode is electrically connected to the capacitor element. The method for manufacturing the electronic device further includes forming an insulating film covering the sidewall of the through hole and the capacitor element and removing the insulating film from the bottom surface of the through hole to form an opening in the insulating film. The method for manufacturing the electronic device further includes forming a sealing film on the capacitor element. Part of the insulating film is removed by etching the insulating film using the sealing film as an etching stopper.

[0015] According to the first mode of the present technology, an electronic device is provided, comprising: a substrate; a through hole penetrating the substrate; a through electrode formed on the side wall of the through hole; a capacitor element formed on (or above) the substrate; and a line formed by extending a conductor film for the through electrode (or a portion of the conductor film passing through the substrate along the side wall of the through hole) and connected to (or contacting) the capacitor element. For example, the through electrode may include a portion of the conductor film, which may pass through the substrate along the side wall of the through hole. This brings about the beneficial effect that the line connected to the capacitor element and the through electrode are composed of the same layer of conductor film.

[0016] In addition, in the first mode, the substrate may include a semiconductor substrate on which a semiconductor element is formed or a wiring substrate on which a line is formed. This brings about an advantageous effect of forming a through electrode on the substrate on which a capacitive element is formed.

[0017] In addition, in the first mode, the capacitor element may include an upper electrode, a lower electrode, and a dielectric film located between the upper electrode and the lower electrode, the through electrode may include a first through electrode, and a second through electrode, and the line may include a first line and a second line, the first line is formed by extending a conductor film for the first through electrode, and is connected to the upper electrode or in contact with the upper electrode, for example, a portion of the conductor film may be connected to or in contact with the upper electrode, and the second line is formed by extending a conductor film for the second through electrode, and is connected to or in contact with the lower electrode, for example, the second conductor film may pass through the substrate along the side wall of the second through hole and is connected to or in contact with the lower electrode. This brings about the beneficial effect of configuring the through electrode near the capacitor element formed on the substrate.

[0018] Furthermore, in the first mode, the upper electrode and the lower electrode may each contain at least one of TiN, TaN, and WN. This brings about an advantageous effect of ensuring the reliability of the capacitance element.

[0019] Furthermore, in the first mode, the dielectric film may contain at least any one of SiO2, Si3N4, HfO2, Al2O3, ZrO2, and HfAlO. This brings about an advantageous effect of ensuring the reliability of the capacitance element.

[0020] In addition, in the first mode, the dielectric film and the lower electrode may have substantially equal planar dimensions, and the upper electrode may have a planar dimension smaller than the planar dimensions of the dielectric film and the lower electrode. This brings about the beneficial effect of ensuring contact with the lower electrode.

[0021] Furthermore, in the first mode, the electronic device may further include a sealing film formed on the capacitive element and including at least any one of Si 3 N 4 and Al 2 O 3. This brings about an advantageous effect that the capacitive element is sealed.

[0022] In addition, in the first mode, the electronic device may further include a capacitor electrode formed on the upper electrode, the sealing film is interposed between the capacitor electrode and the upper electrode, and is configured by a conductor film for the second line. Thus, it has the following effects: the increase in the plane size of the capacitor element can be suppressed, and the capacitance of the capacitor element is increased, and the line connected to the capacitor element and the through electrode are composed of the conductor film of the same layer.

[0023] In addition, in the first mode, the electronic device may further include an insulating film formed on the capacitor element, and at least one of a line (or wiring) and an external connection terminal formed above the capacitor element, and the insulating film is interposed between at least one of the line and the external connection terminal and the capacitor element. This brings about the beneficial effect that the line and the external connection terminal and the capacitor element are arranged in an overlapping relationship.

[0024] Furthermore, in the first mode, the parasitic capacitance between the substrate and the lower electrode can be equal to or less than 1 / 10 of the capacitance of the capacitance element. This brings about a beneficial effect of suppressing noise.

[0025] In addition, in the first mode, the electronic device may further include a photosensitive insulating resin film covering the through hole, for example, by covering the opening of the through hole. This brings about the advantageous effect of forming a cavity (or concave portion, hollow) in the through hole while simplifying the patterning of the photosensitive insulating resin film.

[0026] Furthermore, in the first mode, the substrate may further include a groove in which the capacitive element is formed (or embedded). This brings about the advantageous effect of increasing the capacitance of the capacitive element formed on the substrate while suppressing a reduction in the element area.

[0027] Furthermore, in the first mode, the electronic device may further include a cavity provided in the groove. This brings about the advantageous effect that warping of the substrate caused by the capacitive element formed in the groove can be prevented.

[0028] Furthermore, in the first mode, the electronic device may further include an insulating film disposed on (or over) the cavity. This brings about the advantageous effect that the capacitive element in the trench in which the cavity is disposed is sealed.

[0029] Furthermore, in the first mode, the capacitance element may include capacitance electrodes having polarities different from each other and having sides opposite to each other. This brings about the advantageous effect of increasing the capacitance of the capacitance element while suppressing an increase in the planar size.

[0030] Furthermore, in the first mode, the line may include a plurality of through holes connected to the capacitive electrodes of the capacitive element. This brings about a beneficial effect that the potential of the capacitive element is stabilized.

[0031] Furthermore, in the first mode, the capacitive element may include a plurality of capacitive elements having planar dimensions different from each other. This brings about an advantageous effect that capacitive elements having characteristics different from each other are formed on the substrate.

[0032] Furthermore, in the first mode, the capacitive element may include a plurality of upper electrodes arranged on the lower electrode and having planar dimensions different from each other. This brings about the advantageous effect of forming capacitive elements having characteristics different from each other without separating the lower electrodes.

[0033] Furthermore, in the first mode, the electronic device may further include a through hole connected to the lower electrode through the gap between the upper electrodes. This brings about the advantageous effect of stabilizing the potential of the lower electrode while forming capacitance elements having different characteristics from each other.

[0034] Furthermore, in the first mode, the through-electrode can penetrate the capacitor element. This brings about the advantageous effect of reducing the space required for arranging the through-electrode outside the capacitor element.

[0035] In addition, in the first mode, the electronic device may further include a wiring layer and a semiconductor chip, the wiring layer is formed on the surface of the substrate opposite to the formation surface of the capacitor element (such as the bottom surface, the bottom surface is opposite to the top surface of the substrate) and is connected to the through electrode or in contact with the through electrode (such as a part of the conductor film), and the semiconductor chip is connected to the wiring layer, and a solid-state imaging device is formed therein. This brings about the beneficial effect of stabilizing the operation of the packaged solid-state imaging element.

[0036] Meanwhile, according to the second mode, the electronic device may include a substrate, a capacitor formed on (or above) the substrate, and a through electrode penetrating the substrate and the capacitor. This brings the following beneficial effect: reducing the space required for arranging the through electrode outside the capacitor.

[0037] In the second mode, the electronic device may further include a line formed by extending the conductor film for the through electrode and connected to the capacitor element. This brings about the advantageous effect that the line connected to the capacitor element and the through electrode are composed of the same layer of conductor film.

[0038] In addition, in the third mode, the electronic device may include: a semiconductor substrate; a wiring layer formed on the front side of the semiconductor substrate; a through electrode (or through hole) penetrating the semiconductor substrate and connected to the wiring layer; a groove formed on the back side (or back side) of the semiconductor substrate; a capacitor element formed in the groove; and a line connecting the through electrode and the capacitor element to each other. This brings the following beneficial effects: the capacitance of the capacitor element formed on the substrate is increased, while the reduction of the element area is suppressed.

[0039] In the third mode, the wiring can be configured by extending the conductor film for the through-electrode. This brings about the advantageous effect that the wiring connected to the capacitance element and the through-electrode are formed of the conductor film of the same layer.

[0040] In addition, in the third mode, the capacitor element can be formed (or can extend) along the sidewall of the groove, and the groove can have an irregular (or textured) surface formed on its sidewall. This brings the following beneficial effects: while suppressing the increase in the depth of the groove, the capacitance of the capacitor element formed on the substrate is increased, and at the same time.

[0041] Furthermore, in the third mode, the electronic device may further include a void provided in the groove. This brings about the following advantageous effect: warping of the substrate caused by formation of a capacitor element in the inner groove can be prevented.

[0042] In addition, in a fourth mode, a method for manufacturing an electronic device (or for manufacturing) may include: forming a capacitor element on a substrate; forming a through hole in the substrate having the capacitor element formed therein; and forming a through electrode electrically connected to the capacitor element on the side wall of the through hole (such as along the side wall of the through hole). This brings the following beneficial effect: while forming the capacitor element on the substrate, preventing the capacitor element from being formed in the through hole.

[0043] In addition, in the fourth mode, the conductor film for the through electrode can be extended and electrically connected to the capacitor element. For example, the through electrode may include a portion of the conductor film, and a portion of the conductor film may be electrically connected to the capacitor element or in contact with the capacitor element. This brings the following beneficial effect: the line connected to the capacitor element and the through electrode are formed by the same process.

[0044] In addition, in the fourth mode, the manufacturing method may further include forming an insulating film covering the side wall of the through hole and the capacitor element, removing the insulating film from the bottom surface of the through hole, and forming an opening in the insulating film on the capacitor element. This brings the following beneficial effect: the same insulating film is used for the insulation of the through electrode and the substrate and the insulation of the line connected to the capacitor element.

[0045] In addition, in the fourth mode, the manufacturing method may further include forming a sealing film on the capacitor element formed on the substrate, and when an opening is formed in the insulating film on the capacitor element, the sealing film can be used as an etching stopper. For example, a part of the insulating film can be removed by etching the insulating film using the sealing film as an etching stopper. This brings the following beneficial effect: while forming an opening in the insulating film on the capacitor element, over-etching is suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 is a cross-sectional view showing an example of the configuration of the semiconductor device according to the first embodiment.

[0047] Figure 2 is a first cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0048] Figure 3 is a second cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0049] Figure 4 is a third cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0050] Figure 5 is a fourth cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0051] Figure 6is a fifth cross-sectional view illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0052] Figure 7 is a sixth cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0053] Figure 8 is a seventh cross-sectional view illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0054] Fig. 9 is an eighth cross-sectional view illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0055] Fig.10 is a top view showing an embodiment of a configuration of a semiconductor device according to a second embodiment.

[0056] Fig.11 is a cross-sectional view showing a configuration example of a semiconductor device according to a third embodiment.

[0057] Fig.12 is a plan view showing a configuration example of a semiconductor device according to a third embodiment.

[0058] Fig.13 is a cross-sectional view showing an example of the configuration of a capacitance element according to the fourth embodiment.

[0059] Fig.14 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a fifth embodiment.

[0060] Fig.15 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a sixth embodiment.

[0061] Fig.16 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a seventh embodiment.

[0062] Fig.17 is a cross-sectional view showing an example of the configuration of a semiconductor device according to an eighth embodiment.

[0063] Fig.18 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a ninth embodiment.

[0064] Fig.19 10 are plan views each illustrating an example of a configuration of a capacitive element according to a tenth embodiment.

[0065] Fig. 20 is a cross-sectional view showing an example of the configuration of a semiconductor device according to an eleventh embodiment.

[0066] Fig.21 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0067] Fig. 22 : is an explanatory diagram showing an example of the installation position of the imaging section. DETAILED DESCRIPTION

[0068] Hereinafter, a mode for carrying out the present technology (hereinafter referred to as an embodiment) is described. The description is given according to the following order.

[0069] 1. First Embodiment (Example of connecting a capacitor provided on a semiconductor substrate and a through-electrode provided on the semiconductor substrate via a wiring extending from a conductor film used for the through-electrode)

[0070] 2. Second Embodiment (Example of Forming a Wiring and a Bump Electrode Connected to a Through-Electrode Provided in a Semiconductor Substrate on a Capacitive Element Provided on a Semiconductor Substrate)

[0071] 3. Third Embodiment (Example in which a through electrode penetrating a capacitor element provided on a semiconductor substrate is connected to the capacitor element through the semiconductor substrate)

[0072] 4. Fourth Embodiment (Example in which a plurality of upper electrodes are provided on one lower electrode and a plurality of vias are connected to each of the lower electrode and the upper electrode)

[0073] 5. Fifth Embodiment (Example in which a capacitor element and a through electrode provided in a semiconductor substrate are connected to each other through a wiring configured by extending a conductor film for the through electrode and the wiring is also used as a capacitor electrode)

[0074] 6. Sixth Embodiment (Example in which a capacitor is formed along an irregular surface of a side wall of a trench formed on the back side of a semiconductor substrate provided with a through electrode)

[0075] 7. Seventh Embodiment (Example in which a capacitor is formed along the side wall of a trench formed on the back side of a semiconductor substrate having a through electrode, a cavity is provided in the trench, and an insulating film covering the capacitor is formed on the cavity)

[0076] 8. Eighth Embodiment (an example in which a capacitor is formed along the side wall of a groove formed on the back side of a semiconductor substrate provided with a through electrode, a cavity is provided in the groove, and a sealing film for sealing the capacitor is formed on the cavity);

[0077] 9. Ninth Embodiment (Example in which a lower electrode provided on the back side of a semiconductor substrate is patterned so that the lower electrode and an upper electrode also provided on the back side of the semiconductor substrate have side surfaces facing each other)

[0078] 10. Tenth Embodiment (Example in which a lower electrode provided on the back side of a semiconductor substrate is patterned to have opposite side surfaces and an upper electrode provided on the lower electrode is patterned to have opposite side surfaces)

[0079] 11. Eleventh Embodiment (Example in which a semiconductor chip having a solid-state imaging element formed thereon is stacked on a semiconductor substrate having a capacitor element connected to a through electrode formed thereon)

[0080] <1. First Embodiment>

[0081] In the following description, a semiconductor device provided with a through electrode and a capacitor element is taken as an example of an electronic device. The present technology can also be applied to a circuit board provided with a through electrode and a capacitor element, and can also be applied to a semiconductor package provided with a through electrode and a capacitor element.

[0082] Figure 1 is a cross-sectional view depicting an example of the configuration of the semiconductor device according to the first embodiment.

[0083] Reference Figure 1 , the semiconductor device 100 includes a semiconductor chip 110. In the semiconductor chip 110, a semiconductor element is formed. The semiconductor chip 110 may have a semiconductor memory formed therein, such as a static random access memory (SRAM) or a dynamic random access memory (DRAM). In addition, the semiconductor device 100 may have a processor formed therein, such as a central processing unit (CPU) or a graphics processing unit (GPU). In addition, the semiconductor device 100 may have a hardware circuit formed therein, such as a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). The semiconductor chip 110 may have a signal processing circuit formed therein, may have a data processing circuit formed therein, may have an interface circuit formed therein, or may have an optical element formed therein.

[0084] The semiconductor chip 110 includes a semiconductor substrate 101. A semiconductor element such as a transistor or a diode may be formed on the front side of the semiconductor substrate 101. The semiconductor element may be integrated. As a material of the semiconductor substrate 101, a semiconductor such as Si, SiC, GaN, GaAs, or InGaAsP may be used.

[0085] On the semiconductor substrate 101 on which the semiconductor element is formed, a gate electrode 132 is formed, and a wiring layer 102 is formed in such a manner as to cover the gate electrode 132. A pad electrode 122 and a wiring 112 (or a conductor film) are formed in the wiring layer 102. The gate electrode 132, the pad electrode 122, and the wiring 112 are embedded in an insulating film that insulates the wiring layer 102. In addition, the wiring layer 102 has an opening 142 formed therein that exposes the pad electrode 122 on the back side of the semiconductor substrate 101.

[0086] As a material of the gate electrode 132, for example, polysilicon, silicide, etc. can be used. As a material of the pad electrode 122 and the wiring 112, for example, a metal such as Cu or Al can be used.

[0087] Capacitor 103 is formed on the back side of semiconductor substrate 101, with back insulating film 104 between the two. In some embodiments, capacitor 103 may be arranged on semiconductor substrate 101 or embedded in semiconductor substrate 101. Capacitor 103 includes lower electrode 113, dielectric film 123 and upper electrode 133. Lower electrode 113 is formed on back insulating film 104, and upper electrode 133 is formed on lower electrode 113, and dielectric film 123 is between upper electrode and lower electrode. The planar dimensions of dielectric film 123 and lower electrode 113 may be made substantially equal (or equal). Substantially equal may be equal or may be a deviation within about a few percent. By making the planar dimensions of dielectric film 123 and lower electrode 113 substantially equal to each other, the distance between upper electrode 133 and lower electrode 113 may be increased, and reliability may be improved. The planar dimensions of upper electrode 133 may be made smaller than the planar dimensions of dielectric film 123 and lower electrode 113. Here, by making the planar size of the upper electrode 133 smaller than the planar sizes of the dielectric film 123 and the lower electrode 113 , a contact area with the lower electrode 113 can be ensured.

[0088] As the material of the back insulating film 104, for example, an inorganic material such as SiO2, SiON, SiOC, Si3N4, SiCO, etc., an organic material such as polyimide, acrylic acid, silicone, or a material having an epoxy skeleton, or a laminated structure of multiple materials can be used. The film thickness of the back insulating film 104 can be set so that the parasitic capacitance between the semiconductor substrate 101 and the lower electrode 113 is equal to or less than one tenth of the capacitance of the capacitor 103, and can be equal to or less than one twentieth of the capacitance of the capacitor 103. By setting the parasitic capacitance between the semiconductor substrate 101 and the lower electrode 113 to one tenth or less of the capacitance of the capacitor 103, the noise suppression effect can be improved.

[0089] For the material of the upper electrode 133 and the lower electrode 113, for example, TiN, TaN, WN, W, Al, Ti, Ta, Cu, Ru and Co can be used, and a stacked structure of multiple materials can be used. In some embodiments, the material of the upper electrode 133 and the lower electrode 113 may include at least any one of TiN, TaN and WN. For the material of the dielectric film 123, for example, SiO2, SiON, Si3N4, hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO), tantalum oxide (Ta2O5), titanium oxide (TiO2), lanthanum oxide (LaO3), yttrium oxide (Y2O3), aluminum nitride (AlN), hafnium oxynitride (HfON), and aluminum oxynitride (AlON) can be used, and a stacked structure of multiple materials can be used. In some embodiments, the material of the dielectric film 123 includes at least any one of SiO2, Si3N4, HfO2, Al2O3, ZrO2 and HfAlO. By configuring the capacitor 103 using the above-mentioned material, the reliability of the capacitor 103 can be ensured.

[0090] On the back insulating film 104, a sealing film 114 is formed in a manner covering the capacitor element 103. As the material of the sealing film 114, for example, SiO2, SiON, Si3N4, SiCN, SiC, Al2O3, HfO2 can be used, and a stacked structure of multiple materials can also be used. In some embodiments, the material of the sealing film 114 includes at least one of Si3N4 and Al2O3. By forming the sealing film 114 on the capacitor element 103, the moisture resistance and dust resistance of the capacitor element 103 can be improved, and the reliability of the capacitor element 103 formed on the back side of the semiconductor substrate 101 can be improved.

[0091] Through holes 111 and 121 are formed on the semiconductor substrate 101. At this time, the through holes 111 and 121 can penetrate the back insulating film 104, the sealing film 114 and the semiconductor substrate 101, and enter the wiring layer 102. The through holes 111 and 121 can each be arranged near the capacitor element 103 and can be arranged adjacent to the capacitor element 103. Each bottom surface of the through holes 111 and 121 is arranged at a position opposite to the pad electrode 122. The aspect ratio of each of the through holes 111 and 121 can be set in the range of 1 to 10.

[0092] On the sidewall of each through hole 111 and 121, an insulating film 105 is formed, and the insulating film 115 is formed on the sealing film 114 in a way that covers the capacitor element 103. The insulating films 105 and 115 can be formed continuously by the same material. The film thickness of the insulating films 105 and 115 can also be different, or the film formation is also different. As the material of the insulating films 105 and 115, for example, inorganic materials such as SiO2, SiON, SiOC, Si3N4, SiCO, organic materials such as polyimide, acrylic acid, silicone or materials with epoxy skeletons, or materials of the laminated structure of multiple materials can be adopted.

[0093] Openings 145 are formed in the insulating film 115, the sealing film 114, and the dielectric film 123 so that the openings 145 expose the lower electrode 113. Also, openings 155 are formed in the insulating film 115 and the sealing film 114 so that the openings 155 expose the upper electrode 133.

[0094] Through electrodes 106 and 116 are formed on sidewalls of the through holes 111 and 121, respectively, with the insulating film 105 interposed therebetween. At this time, cavities 131 and 141 may be formed in the through holes 111 and 121 in which the through electrodes 106 and 116 are formed, respectively.

[0095] The conductor film for each through electrode 106 and 116 extends and is connected to the capacitor element 103. At this time, the conductor film for each through electrode 106 and 116 may extend onto the insulating film 115 so as to cover the openings 145 and 155, respectively. Here, the back wiring 126, 136, 166 and 176 and the vias 146 and 156 may include a conductor film for each of the through electrodes 106 and 116. The via 146 may be provided in the back wiring 126. The via 156 may be provided in the back wiring 136. At this time, the through electrodes 106 and 116, the back wiring 126, 136, 166 and 176 and the vias 146 and 156 may include a layer of conductor film. The via 146 is connected to the lower electrode 113 through the opening 145, and the via 156 is connected to the upper electrode 133 through the opening 155. In addition, the through electrode 106 is connected to the via 146 through the back line 126, and is connected to the bump electrode 107 through the back line 166. The through electrode 116 is connected to the via 156 through the back line 136, and is connected to the bump electrode 117 through the back line 176. For the materials of the through electrodes 106 and 116, the back lines 126, 136, 166 and 176, and the vias 146 and 156, for example, Cu, Ti, Ta, Al, W, Ni, Ru, Co, TiN, TaN and WN can be used, or a stacked structure of multiple materials can be used. The distance between the via 146 and the upper electrode 133 can be set to be more than 0.2μm. The distance between each through electrode 106, 116 and the lower electrode 113 can be set to be more than 0.2μm.

[0096] A protective film 118 is formed on the insulating film 115. At this time, the protective film 118 may be located on the cavities 131 and 141. As a material for the protective film 118, an organic material such as polyimide, acrylic, silicone, or a material having an epoxy skeleton, a material containing an inorganic filler such as SiO2, Al2O3, AlN, BN, etc. may be used. In order to form the protective film 118 on the gaps 131 and 141 so that it is not filled in the cavities 131 and 141, a coating film may be used. The coating film may be a photosensitive insulating resin film.

[0097] Bump electrodes 107 and 117 are formed on a protective film 118. Bump electrodes 107, 117 are connected to backside wirings 166, 176 respectively through protective film 118. At this time, protective film 118 may have an opening formed therein so that it exposes a portion of each backside wiring 166 and 176 passing therethrough at the position of each bump electrode 107 and 117. Backside wirings 166 and 176 may have pad electrodes disposed thereon, and bump electrodes 107 and 117 are connected to the pad electrodes respectively. Each of bump electrodes 107 and 117 may be a solder ball or may be a columnar electrode. In addition, bump electrodes 107, 117 are examples of external connection terminals described in the claims.

[0098] Figures 2 to 9 is a cross-sectional view depicting an example of a method for manufacturing the semiconductor device according to the first embodiment.

[0099] refer to Figure 2 , semiconductor elements are formed on the front side of the semiconductor wafer 101 ′. Note that the semiconductor wafer 101 ′ may be divided for each semiconductor chip 110 . A dicing line may be provided on a boundary between divided regions of the semiconductor chips 110 .

[0100] In the case where a metal oxide semiconductor (MOS) transistor is formed as a semiconductor element, an impurity diffusion layer and an element separation layer may be formed in the semiconductor wafer 101', and a gate electrode 132 may be formed on the semiconductor wafer 101'. In addition, a wiring layer 102 is formed on the semiconductor wafer 101' to cover the gate electrode 132. A pad electrode 122 and a line 112 embedded in an insulating film may be formed in the wiring layer 102. It should be noted that the semiconductor wafer 101' may be thinned to a desired thickness from the back side of the semiconductor wafer 101' by a method such as chemical mechanical polishing (CMP).

[0101] Then, if Figure 3 As shown, a back insulating film 104 is formed on the back side of the semiconductor wafer 101' by a plasma enhanced chemical vapor deposition (PE-CVD) method. Then, a lower electrode 113, a dielectric film 123, and an upper electrode 133 are sequentially formed on the back insulating film 104. For the film formation of electrodes such as the lower electrode 113 and the upper electrode 133, PE-CVD, plasma enhanced physical vapor deposition (PE-PVD), metal organic chemical vapor deposition (MO-CVD), or atomic layer deposition (ALD) can be used. For the film formation of the dielectric film 123, PE-CVD or ALD can be used.

[0102] Then, if Figure 4As shown, the lower electrode 113 and the dielectric film 123 are patterned by photolithography or dry etching, and then, the upper electrode 133 is patterned to form the capacitor 103 on the back insulating film 104. In the etching of the upper electrode 133, selectivity can be set so that the dielectric film 123 remains on the lower electrode 113. At this time, as an etching gas, for example, Cl2 or HBr gas can be used. If the pattern is not a fine pattern, patterning can be performed by wet etching. A hard mask can be formed on the upper electrode 133.

[0103] Then, if Figure 5 As shown, the sealing film 114 is formed on the back insulating film 104 by a method such as PE-CVD or ALD to cover the capacitor element 103 .

[0104] Then, if Figure 6 As shown, the sealing film 114, the back insulating film 104 and the semiconductor wafer 101' are patterned by photolithography and dry etching to form through holes 111 and 121 in the sealing film 114, the back insulating film 104 and the semiconductor wafer 101'. The through holes 111 and 121 can be respectively provided near the capacitor element 103.

[0105] Then, if Figure 7 As shown, an insulating film 105 is formed on the sidewall of each through hole 111 and 121, and an insulating film 115 is formed on the sealing film 114. The insulating films 105 and 115 can also be formed by the same film forming method. Then, the insulating films 105 and 115 are patterned, the insulating film 105 on the bottom surface of the through holes 111 and 121 is removed, and openings 145 and 155 are formed in the insulating film 115. At this time, a photosensitive insulating resin film can be formed as the insulating films 105 and 115 by coating or lamination, and then patterned by photolithography. Alternatively, after the insulating films 105 and 115 are formed on the entire area of ​​the back side of the semiconductor wafer 101' by PE-CVD, they can be patterned by photolithography and dry etching. Here, different materials can be used for the sealing film 114 and the insulating film 115. At this time, the etching rate of the sealing film 114 can be made lower than the etching rate of the insulating film 115, so that the sealing film 114 is used as an etching stopper. This makes it possible to suppress characteristic changes due to excessive overetching of the semiconductor element on the front side of the semiconductor wafer 101' and the capacitor element 103 on the back side of the semiconductor wafer 101'. When the sealing film 114 is used as an etching stopper, the material of the sealing film 114 and the material of the insulating film 115 may be, for example, a combination of SiO2 and Si3N4, or may be a combination of an inorganic film and an organic film.

[0106] Then, if Figure 8As shown, the wiring layer 102 is patterned through the through holes 111 and 121 by dry etching to form an opening 142 through which the pad electrode 122 is exposed. At this time, the sealing film 114 and the dielectric film 123 are patterned through the opening 145 so that the lower electrode 113 is exposed therethrough, and the sealing film 114 is patterned through the opening 155 so that the upper electrode 133 is exposed therethrough. The patterning of the wiring layer 102, the sealing film 114, and the dielectric film 123 can be self-aligned through the through holes 111 and 121 and the openings 145 and 155.

[0107] Then, if Fig. 9 As shown, for example, through electrodes 106 and 116, back lines 126, 136, 166 and 176, and vias 146 and 156 are formed at one time by a semi-additive method or the like. As an example of a semi-active method, after forming a barrier metal film and a seed metal film, a resist pattern is formed by a photolithography method. In the resist pattern, hollow patterns can be formed at the formation positions of the through electrodes 106, 116, back lines 126, 136, 166, 176, and vias 146, 156, respectively. Then, the through electrodes 106, 116, back lines 126, 136, 166, 176, and vias 146, 156 can be formed by electroplating through the resist pattern at the same time. Then, the resist pattern is removed, and the barrier metal film and the seed metal film are removed by etching back the entire surface of these films.

[0108] Then, if Figure 1 As shown, a protective film 118 is formed on the insulating film 115. At this time, by adjusting the embedding property of the protective film 118 into the through holes 111 and 121, cavities 131 and 141 can be formed in the through holes 111 and 121, respectively. In order to adjust the embedding property of the protective film 118 into the through holes 111 and 121, a coating film can be used as the protective film 118. At this time, by adjusting the viscosity of the coating film, the embedding property of the protective film 118 into the through holes 111 and 121 can be adjusted. Next, openings are formed in the protective film 118 so that the bump electrodes 107 and 117 are connected to the back lines 166 and 176, respectively. At this time, as the protective film 118, after a photosensitive insulating resin is formed by coating or lamination, the photosensitive insulating resin can be patterned by photolithography. Then, the bump electrodes 107 and 117 are connected to the back lines 166 and 176, respectively, through the openings formed in the protective film 118. Thereafter, the semiconductor wafer 101 ′ is cut by such a method as blade dicing to separate the semiconductor wafer 101 ′ into individual semiconductor chips 110 .

[0109] In this manner, in the first embodiment, the through electrodes 106 and 116, the back wirings 126, 136, 166 and 176, and the vias 146 and 156 are formed by a conductor film in one layer. Thus, a contact for connecting the through electrode 106 and the via 146, and a contact for connecting the through electrode 116 and the via 156 are not required, and the line resistance can be reduced, the manufacturing process can be simplified, and the reliability can be improved.

[0110] Furthermore, the insulating film 105 on the side wall of each of the through holes 111 and 121 and the insulating film 115 on the capacitor 103 are continuously formed of the same material, and the through electrodes 106 and 116 are formed on the insulating film 105 and the back side wirings 126 and 136 are formed on the insulating film 115. As a result, the line length of the back side wirings 126, 136 can be reduced, and the line resistance can be reduced.

[0111] In addition, the capacitor element 103 is formed on the back side of the semiconductor substrate 101. Therefore, there is no need to reduce the element formation area on the front side of the semiconductor substrate 101, and the capacitor element 103 can be arranged near each of the through electrodes 106 and 116. Therefore, without increasing the chip size, the fluctuation of the power supply voltage and the generation of noise can be suppressed without involving.

[0112] It should be noted that in the above-mentioned first embodiment, an example is shown in which the through electrodes 106, 116, the back wirings 126, 136, 166, 176, and the vias 146, 156 are formed of a single conductor film. On the contrary, the through electrodes 106 and 116, the back wirings 126 and 166, and the via 146 may be formed of a single conductor film, while the back wirings 136 and 176 and the via 156 are formed of another conductor film. Alternatively, the through electrodes 106, 116, the back wirings 136, 176, and the via 156 may be formed of a single conductor film, while the back wirings 126, 166, and the via 146 are formed of another conductor film.

[0113] In addition, although the above-mentioned first embodiment describes an example in which one capacitor element 103 is provided on the back surface side of the semiconductor substrate 101 , a plurality of capacitor elements 103 may be provided on the back surface side of the semiconductor substrate 101 .

[0114] <2. Second Embodiment>

[0115] In the first embodiment, the bump electrodes 107 and 117 are arranged outside the capacitor 103 formed on the back side of the semiconductor substrate 101. In the second embodiment, the bump electrodes are arranged on the capacitor 103 formed on the back side of the semiconductor substrate 101, and a line not connected to the capacitor 103 is formed on the capacitor 103.

[0116] Fig.10 is a top view illustrating an embodiment of a configuration of a semiconductor device according to a second embodiment.

[0117] refer to Fig.10 The semiconductor device 200 includes a semiconductor substrate 201. The semiconductor substrate 201 has a semiconductor element and a wiring layer on its front side. A capacitor 203, back wirings 226, 236, 266, 276, 286, vias 246, 256, and bump electrodes 207, 217, 227 are formed on the back side of the semiconductor substrate 201. In addition, through electrodes 206, 216, 296 are formed on the semiconductor substrate 201.

[0118] The capacitor 203 includes a lower electrode 213 and an upper electrode 233. The lower electrode 213 is formed on the back side of the semiconductor substrate 201 with a back insulating film interposed therebetween, and the upper electrode 233 is formed on the lower electrode 213 with a dielectric film interposed therebetween.

[0119] At least a portion of each of the bump electrodes 207 and 217 may be formed on the capacitor 203. The through electrodes 206, 216, and 296 may be provided at any position on the semiconductor substrate 201. For example, the through electrode 216 may penetrate the capacitor 203 with the semiconductor substrate 201 interposed therebetween. At this time, the lower electrode 213 and the upper electrode 233 may be provided to be spaced apart from the through electrode 216 in a manner surrounding the through electrode 216. This reduces the distance between the capacitor 203 and the through electrode 216, so that the line resistance can be reduced.

[0120] The conductor film for each through-electrode 206 and 216 extends and is connected to the capacitor element 203. At this time, the back wiring 226, 236, 266 and 276 and the vias 246 and 256 can be configured by the conductor film for each through-electrode 206 and 216. The via 246 is connected to the lower electrode 213, and the via 256 is connected to the upper electrode 233. The via 246 is provided on the exposed surface of the lower electrode 213. The via 246 can be arranged in plurality on the exposed surface of the lower electrode 213. The via 256 can be arranged at any position on the upper electrode 233. The via 256 can be arranged in plurality on the upper electrode 233.

[0121] The through electrode 206 is connected to the via 246 through the back line 226, and is connected to the bump electrode 207 through the back line 266. The through electrode 216 is connected to the via 256 through the back line 236, and is connected to the bump electrode 217 through the back line 276. The through electrode 296 is connected to the bump electrode 227 through the back line 286. The back line 286 may extend across the capacitor element 203.

[0122] In this manner, in the second embodiment described above, the bump electrodes 207 and 217 are arranged on the capacitor element 103 formed on the back side of the semiconductor substrate 101. As a result, the length of the back wiring 266 connecting the bump electrode 207 and the via 246 can be shortened, the length of the back wiring 276 connecting the bump electrode 217 and the via 256 can be shortened, and the wiring resistance of the back wirings 266 and 276 can be reduced.

[0123] In addition, the backside wiring 286 that connects the bump electrode 227 and the through electrode 296 to each other is provided on the capacitor element 203. As a result, it is not necessary to form the backside wiring 286 bypassing the capacitor element 203 in order to connect the bump electrode 227 and the through electrode 296, so that the length of the backside wiring 276 can be shortened. Therefore, the line resistance of the backside wiring 286 can be reduced.

[0124] <3. Third Embodiment>

[0125] In the first embodiment, the through electrodes 106 and 116 are respectively arranged adjacent to the capacitor 103 formed on the back side of the semiconductor substrate 101. In the third embodiment, a through electrode is provided in the semiconductor device, and the through electrode penetrates the semiconductor substrate and penetrates the capacitor.

[0126] Fig.11 is a cross-sectional view depicting an example of a configuration of a semiconductor device according to a third embodiment, and Fig.12 is a top view depicting an example of the configuration of a semiconductor device according to the third embodiment.

[0127] refer to Fig.11 and Fig.12 , the semiconductor device 300 includes a semiconductor chip 310. The semiconductor chip 310 has a semiconductor element formed therein. The semiconductor chip 310 includes a semiconductor substrate 301. On the front side of the semiconductor substrate 301, a semiconductor element such as a transistor or a diode may be formed.

[0128] A gate electrode 332 is formed on the semiconductor substrate 301 on which the semiconductor element is formed, and a wiring layer 302 is formed so that the wiring layer 302 covers the gate electrode 332. A pad electrode 322 and a line 312 are formed in the wiring layer 302. In addition, an opening 342 is formed in the wiring layer 302, and the opening 342 exposes the pad electrode 322.

[0129] A capacitor 303 is formed on the back side of the semiconductor substrate 301, with a back insulating film 304 interposed therebetween. The capacitor 303 includes a lower electrode 313, a dielectric film 323, and an upper electrode 333. The lower electrode 313 is formed on the back insulating film 304, and the upper electrode 333 is formed on the lower electrode 313, with the dielectric film 323 interposed therebetween. A sealing film 314 covering the capacitor 303 is formed on the back insulating film 304.

[0130] The semiconductor substrate 301 has a through hole 311 formed therein. The through hole 311 penetrates the capacitor 303, the back insulating film 304, the sealing film 314, and the semiconductor substrate 301 and enters the wiring layer 302. The bottom surface of the through hole 311 is disposed at a position opposite to the pad electrode 332.

[0131] The through hole 311 has an insulating film 305 formed on the side wall thereof, and the sealing film 314 has an insulating film 315 formed thereon in such a manner as to cover the capacitive element 303. The insulating films 305 and 315 may be continuously formed of the same material.

[0132] The insulating film 315, the sealing film 314, and the dielectric film 323 have openings 345 formed therein so that the openings 345 expose the lower electrode 313. Furthermore, the insulating film 315 and the sealing film 314 have openings 355 formed therein so that the upper electrode 333 is exposed.

[0133] The through hole 311 has a through electrode 306 formed on its sidewall with an insulating film 305 interposed therebetween. At this time, the lower electrode 313 and the upper electrode 333 may be disposed to be spaced apart from the through electrode 306 so as to surround the through electrode 306. A cavity 331 may be formed in the through hole 311 having the through electrode 306 formed therein.

[0134] The conductor film for the through electrode 306 extends and is connected to the capacitor element 303. At this time, the conductor film for the through electrode 306 can extend on the insulating film 315 in a manner covering the opening 345. Here, the back wiring 326, 336 and 366 and the vias 346 and 356 can be configured by the conductor film for the through electrode 306. At this time, the through electrode 306, the back wiring 326, 336 and 366 and the vias 346 and 356 can be formed by a layer of conductor film. The via 346 is connected to the lower electrode 313 through the opening 355, and the via 356 is connected to the upper electrode 333 through the opening 345. In addition, the through electrode 306 is connected to the via 356 through the back wiring 336 and is connected to the bump electrode 307 through the back wiring 366. The via 346 is connected to the back wiring 326.

[0135] A protective film 318 is formed on the insulating film 315. At this time, the protective film 318 may be located on the cavity 331. Bump electrodes 307 and 317 are formed on the protective film 318. The bump electrode 307 is connected to the back line 366, and the protective film 318 is interposed therebetween. The bump electrode 317 is connected to the back line 326, and the protective film 318 is interposed therebetween. At this time, the protective film 318 may have an opening formed therein so that the opening exposes a portion of the back line 366 at the position of the bump electrode 307, and may have an opening formed therein so that the opening exposes a portion of the back line 326 at the position of the bump electrode 317.

[0136] Thus, in the third embodiment described above, the through electrode 306 is provided in the semiconductor device 300, and the through electrode 306 allows the capacitor 303 to penetrate the semiconductor substrate 301. Thus, it is not necessary to arrange the through electrode 306 outside the capacitor 303, and the line length of the back line 326 connecting the through electrode 306 and the via 346 can be reduced, and the line length of the back line 336 connecting the through electrode 306 and the via 356 can be further shortened. Therefore, the line resistance of each of the back lines 326 and 336 can be reduced, so that the fluctuation of the power supply voltage and the generation of noise can be reduced.

[0137] <4. Fourth Embodiment>

[0138] In the above-described first embodiment, a single upper electrode 133 is disposed on a single lower electrode 113, vias 146 are connected to the lower electrode 113, and vias 156 are connected to the upper electrode 133. In the fourth embodiment, a plurality of upper electrodes are disposed on a single lower electrode, and a plurality of vias are connected to each of the lower and upper electrodes.

[0139] Fig.13 is a cross-sectional view describing an example of a configuration of a capacitive element according to a fourth embodiment.

[0140] Reference Fig.13 , the capacitor element 370 includes a lower electrode 371, a dielectric film, and upper electrodes 372 to 374. The upper electrodes 372 to 374 are formed on the lower electrode 371, and the dielectric film is interposed between the upper electrode and the lower electrode. The upper electrodes 372 to 374 may have different planar dimensions from each other. A plurality of vias 381 are connected to the lower electrode 371. A plurality of vias 382 are connected to the upper electrode 372. A plurality of vias 383 are connected to the upper electrode 373. A plurality of vias 384 are connected to the upper electrode 374. The vias 381 connected to the lower electrode 371 may be provided between the upper electrodes 372 to 374.

[0141] In this way, in the fourth embodiment described above, by providing a plurality of upper electrodes 372 to 374 on a single lower electrode 371, the number of vias 381 and the number of lines connected to the lower electrode 371 can be reduced. In addition, the lower electrode 371 can be used to block noise and shield light. In addition, by connecting a plurality of vias to each of the lower electrode 371 and the upper electrodes 372 to 374, the potential at the lower electrode 371 and the upper electrodes 372 to 374 can be stabilized. In addition, by making the planar dimensions of the upper electrodes 372 to 374 different from each other, the characteristics such as the cutoff frequency of each electrode can be made different.

[0142] <5. Fifth embodiment>

[0143] In the first embodiment described above, the lower electrode 113 and the upper electrode 133 are stacked on the semiconductor substrate 101 via the dielectric film 123 to form the capacitor 103 on the back side of the semiconductor substrate 101. In the fifth embodiment, the capacitor and the through electrode are connected to each other by a line formed by extending a conductor film for the through electrode provided on the semiconductor substrate, and the line also serves as a capacitor electrode.

[0144] Fig.14 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a fifth embodiment.

[0145] Reference Fig.14 , the semiconductor device 400 includes a semiconductor chip 410 instead of the semiconductor chip 110 in the first embodiment described above. The semiconductor chip 410 includes a capacitor element 403 and an insulating film 415 instead of the capacitor element 103 and the insulating film 105 in the first embodiment described above. The configuration of other parts of the semiconductor device 400 of the fifth embodiment is similar to the configuration of the semiconductor device 100 of the first embodiment described above.

[0146] Capacitor element 403 is formed on the back side of semiconductor substrate 101, with back insulating film 104 in between. Capacitor element 403 includes lower electrode 113, dielectric film 123, upper electrode 133, sealing film 114 and back wiring 416. Lower electrode 113 is formed on back insulating film 104, and upper electrode 133 is formed on lower electrode 113, with dielectric film 123 in between. Back wiring 416 is formed on upper electrode 133, with sealing film 114 in between. Back wiring 416 on upper electrode 133 can be used as capacitor electrode. In addition, sealing film 114 between upper electrode 133 and back wiring 416 can be used as dielectric film of capacitor element 403.

[0147] The insulating film 105 is formed on the side walls of the respective through holes 111 and 121, and the insulating film 415 is formed on the sealing film 114 so that the capacitive element 403 is covered therewith. The insulating films 105 and 415 may be continuously formed of the same material.

[0148] An opening 445 is formed in the insulating film 415, the sealing film 114, and the dielectric film 123 so that the opening 445 exposes the lower electrode 113. An opening 155 is formed in the insulating film 415 and the sealing film 114 so that the opening 155 exposes the upper electrode 133. An opening portion 446 is formed in the insulating film 415 so that the sealing film 114 on the upper electrode 133 is exposed.

[0149] The conductor film for each of the through electrodes 106 and 116 extends and is connected to the capacitor element 403. At this time, the conductor film for each of the through electrodes 106 and 116 can extend onto the insulating film 415 and the sealing film 114 so as to cover the openings 155, 445 and 446. Here, the back wiring 126, 136, 166, 176 and 416 and the vias 146 and 156 can be configured by the conductor film for each of the through electrodes 106 and 116. At this time, the through electrodes 106 and 116, the back wiring 126, 136, 166, 176 and 416 and the vias 146 and 156 can be formed by a layer of conductor film. The via 146 is connected to the lower electrode 113 through the opening 446, and the via 156 is connected to the upper electrode 133 through the opening 155. The through electrode 106 is connected to the via 146 through the back line 126, is connected to the back line 416, and is connected to the bump electrode 107 through the back line 166. The through electrode 116 is connected to the via 156 through the back line 136, and is connected to the bump electrode 117 through the back line 176.

[0150] A protection film 118 is formed on the insulating film 415. At this time, the protection film 118 may be located on the cavities 131 and 141.

[0151] In this manner, in the fifth embodiment described above, the back wiring 416 formed by extending the conductor film used for the through electrode 106 provided on the semiconductor substrate 101 is used as a capacitor electrode. As a result, the through electrode 106 and the back wiring 416 used as the capacitor electrode of the capacitor element 403 can be formed of the conductor of the same layer, and the capacitance per unit area of ​​the capacitor element 403 can be increased while suppressing an increase in manufacturing cost.

[0152] <Sixth Implementation Method>

[0153] In the first embodiment, the capacitor 103 connected to each through-electrode 106, 116 is provided on the back surface of the semiconductor substrate 101. In the sixth embodiment, the capacitors connected to the through-electrodes 106, 116 are formed along the uneven surface of the sidewall of the trench of the semiconductor substrate 101.

[0154] Fig.15 is a cross-sectional view depicting an example of the configuration of a semiconductor device according to a sixth embodiment.

[0155] Reference Fig.15 , the semiconductor device 500 includes a semiconductor chip 510 instead of the semiconductor chip 110 in the above-mentioned first embodiment. The semiconductor chip 510 has a capacitor element 503 instead of the capacitor element 103 in the above-mentioned first embodiment. The configuration of other parts of the semiconductor device 500 of the sixth embodiment is similar to the configuration of the semiconductor device 100 of the above-mentioned first embodiment.

[0156] A groove 511 is formed on the back side of the semiconductor substrate 101. It should be noted that in order to facilitate the formation of the capacitor 503 in the groove 511, the groove 511 may have a tapered shape. An irregular surface 512 is formed on the side wall of the groove 511. At this time, the side roughness of the groove 511 may be greater than the side roughness of each of the through holes 111 and 121. In order to form the irregular surface 512 on the side wall of the groove 511, the groove 511 can be formed by repeating dry etching and deposition of the semiconductor substrate 101.

[0157] The capacitor element 503 includes a lower electrode 513, a dielectric film 523, and an upper electrode 533. The lower electrode 513 is formed on the side wall of the groove 511 to the back insulating film 104, and the upper electrode 533 is formed on the lower electrode 513, and the dielectric film 523 is between the upper electrode 533 and the lower electrode 513. At this time, the lower electrode 513, the dielectric film 523, and the upper electrode 533 are formed with irregular surface structures thereon, and the irregular surface 512 of the side wall of the groove 511 is reflected on the irregular surface structure. An insulating film 115 is formed on the capacitor element 503, and a sealing film 114 is between the two.

[0158] The insulating film 115, the sealing film 114, and the dielectric film 123 have openings 145 formed therein so that the openings 145 expose the lower electrode 513. In addition, the insulating film 115 and the sealing film 114 have openings 155 formed therein so that the openings 155 expose the upper electrode 533. The via 146 is connected to the lower electrode 513 through the opening 145, and the via 156 is connected to the upper electrode 533 through the opening 155.

[0159] In the above manner, in the sixth embodiment, the capacitor element 503 connected to the through electrodes 106 and 116 is formed along the irregular surface 512 of the side wall of the groove 511 of the semiconductor substrate 101. As a result, the capacitance per unit area of ​​the capacitor element 503 can be increased without reducing the element formation area on the front side of the semiconductor substrate 101.

[0160] <7. Seventh Implementation Method>

[0161] In the first embodiment described above, the capacitor element 103 connected to the through electrodes 106 and 116 is provided on the back side of the semiconductor substrate 101. In the seventh embodiment, the capacitor element is formed along the side wall of a groove formed on the back side of the semiconductor substrate 101, wherein the through electrode is provided in the semiconductor substrate 101, a cavity is provided in the groove, and an insulating film covering the capacitor element is formed on the cavity.

[0162] Fig.16 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a seventh embodiment.

[0163] Reference Fig.16 , the semiconductor device 600 includes a semiconductor chip 610 instead of the semiconductor chip 110 in the first embodiment described above. The semiconductor chip 610 includes a capacitor 603, a back insulating film 604, and a sealing film 614 instead of the capacitor 103, the back insulating film 104, and the sealing film 114 in the above-mentioned first embodiment. The configuration of another part of the semiconductor device 600 of the seventh embodiment is similar to the configuration of the semiconductor device 100 of the above-mentioned first embodiment.

[0164] A groove 611 is formed on the back side of the semiconductor substrate 101. It should be noted that the groove 611 may have a tapered shape in order to facilitate the formation of the capacitor 603 in the groove 611. In addition, an irregular surface may be formed on the side wall of the groove 611. The back insulating film 604 is formed on the side wall of the groove 611 to the back side of the semiconductor substrate 101.

[0165] Capacitor element 603 includes lower electrode 613, dielectric film 623 and upper electrode 633. Lower electrode 613 is formed on the back insulating film 604 in groove 611 to the back insulating film 604 on the back side of semiconductor substrate 101, and upper electrode 633 is formed on lower electrode 613, with dielectric film 623 between the two. At this time, upper electrode 633 is formed in groove 611 in the form of a thin film. Sealing film 614 is formed so as to cover the groove 611 on the upper electrode 633 of capacitor element 603 to the back side of semiconductor substrate 101 on the back insulating film 604. At this time, sealing film 614 is formed in groove 611 in the form of a thin film, and cavity 612 is formed in groove 611. Insulating film 115 is formed on cavity 612.

[0166] The opening 145 is formed in the insulating film 115, the sealing film 614, and the dielectric film 623, so that the opening 145 exposes the lower electrode 613. In addition, the opening 155 is formed in the insulating film 115 and the sealing film 614, so that the opening 155 exposes the upper electrode 633. The via 146 is connected to the lower electrode 613 through the opening 145, and the via 156 is connected to the upper electrode 633 through the opening 155.

[0167] In this way, in the seventh embodiment described above, the capacitor element 603 is formed along the side wall of the groove 611 formed on the back side of the semiconductor substrate 101, wherein the through electrodes 106 and 116 are provided in the semiconductor substrate 101, and the insulating film 115 is formed on the cavity 612 in the groove 611. Therefore, the warping of the semiconductor substrate 101 caused by the mechanical stress of the upper electrode 633 can be prevented, and while the capacitance per unit area of ​​the capacitor element 603 is increased, the deterioration of the mountability and the deterioration of the reliability of the semiconductor chip 610 can be suppressed.

[0168] <8. Eighth Implementation Method>

[0169] In the seventh embodiment described above, the capacitor element 603 is formed along the side wall of the groove 611 formed on the back side of the semiconductor substrate 101, wherein the through electrodes 106 and 116 are provided in the semiconductor substrate 101, and the insulating film 115 is formed on the cavity 612 in the groove 611. In the eighth embodiment, the capacitor element 603 is formed along the side wall of the groove 611 formed on the back side of the semiconductor substrate 101, wherein the through electrodes 106 and 116 are provided in the semiconductor substrate 101, and a sealing film is formed on the cavity 612 in the groove 611.

[0170] Fig.17 is a cross-sectional view showing an example of the configuration of a semiconductor device according to an eighth embodiment.

[0171] Reference Fig.17The semiconductor device 700 includes a semiconductor chip 710 instead of the semiconductor chip 610 in the seventh embodiment described above. The semiconductor chip 710 includes a capacitor element 703 and a sealing film 714 instead of the capacitor element 603 and the sealing film 614 in the seventh embodiment described above. The configuration of another part of the semiconductor device 700 of the eighth embodiment is similar to the configuration of the semiconductor device 600 of the seventh embodiment described above.

[0172] The capacitor element 703 is sealed by a sealing film 714. At this time, the sealing film 714 is formed to cover the capacitor element 703 on the upper electrode 633 in the groove 611 to the back insulating film 604 on the back side of the semiconductor substrate 101. The sealing film 714 is formed in the form of a thin film so as to close the upper part of the cavity 612 in the groove 611. The film thickness of the sealing film 714 at a position away from the bottom of the groove 611 can be made greater than the film thickness at a position closer to the bottom of the groove 611. At this time, for example, the cavity 612 can be formed in a pointed top shape.

[0173] In order to suppress the warping of the semiconductor substrate 101 in which the groove 611 is formed, a compressive stress film may be used as the sealing film 714. For example, in the case of using Si3N4 as the material of the sealing film 714, compressive stress may be applied based on the film forming conditions of Si3N4. The film forming conditions are, for example, the gas flow rate when the Si3N4 film is formed. At this time, the compressive stress may be adjusted based on the amount of nitrogen to be introduced into the sealing film 714.

[0174] In this way, in the eighth embodiment described above, the capacitor element 703 is formed along the side wall of the groove 611 formed on the back side of the semiconductor substrate 101, in which the through electrodes 106 and 116 are formed, and the sealing film 714 is formed to close the upper portion of the cavity 612 in the groove 611. At this time, compressive stress can be applied to the sealing film 714. This can prevent the warping of the semiconductor substrate 101 caused by the mechanical stress of the upper electrode 633, and while increasing the capacitance per unit area of ​​the capacitor element 703, it is possible to suppress the deterioration of the mountability and the deterioration of the reliability of the semiconductor chip 710.

[0175] Note that in order to prevent the semiconductor substrate 101 in which the trench 611 is formed from being warped, a film different from the sealing film 714 may be added.

[0176] <9. Ninth Implementation Method>

[0177] In the first embodiment described above, the capacitor 103 is formed on the back side of the semiconductor substrate 101 using the lower electrode 113 and the upper electrode 133 stacked on the semiconductor substrate 101 and the dielectric film 123 interposed between the lower electrode and the upper electrode. In the ninth embodiment, the lower electrode provided on the back side of the semiconductor substrate 101 is patterned so that the lower electrode and the upper electrode also provided on the back side of the semiconductor substrate 101 have side surfaces facing each other.

[0178] Fig.18 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a ninth embodiment.

[0179] Reference Fig.18 , the semiconductor device 800 includes a semiconductor chip 810 instead of the semiconductor chip 110 in the above-mentioned first embodiment. The semiconductor chip 810 includes a capacitor element 803 instead of the capacitor element 103 in the above-mentioned first embodiment. The configuration of another part of the semiconductor device 800 of the ninth embodiment is similar to the configuration of the semiconductor device 100 of the above-mentioned first embodiment.

[0180] The capacitor 803 is formed on the back side of the semiconductor substrate 101 with the back insulating film 104 interposed therebetween. The capacitor 803 includes a lower electrode 813, a dielectric film 823, and an upper electrode 833. The lower electrode 813 is formed on the back insulating film 104, and the upper electrode 833 is formed on the lower electrode 813 with the dielectric film 823 interposed therebetween.

[0181] The lower electrode 813 is patterned to expose its side. The pattern of the lower electrode 813 can be, for example, a comb shape or a spiral shape. At this time, the upper electrode 833 is stacked on the lower electrode 813 in a manner opposite to the side and top of the lower electrode 813. An insulating film 115 is formed on the capacitor 803, and a sealing film 114 is between the two.

[0182] The opening 145 is formed in the insulating film 115, the sealing film 114, and the dielectric film 823, so that the opening 145 exposes the lower electrode 813. In addition, the opening 155 is formed in the insulating film 115 and the sealing film 114, so that the opening 155 exposes the upper electrode 833. The via 146 is connected to the lower electrode 813 through the opening 145, and the via 156 is connected to the upper electrode 833 through the opening 155.

[0183] In this manner, in the above-described ninth embodiment, the lower electrode 813 provided on the back side of the semiconductor substrate 101 is patterned so that the side surfaces of the lower electrode 813 and the upper electrode 833 provided on the back side of the semiconductor substrate 101 are opposed to each other. As a result, capacitance can be provided between the side surfaces of the lower electrode 613 and the upper electrode 833, and the capacitance of the capacitor 803 can be increased without increasing the planar size of the capacitor 803.

[0184] It should be noted that in the ninth embodiment described above, a hollow pattern is formed in the plane pattern in order to expose the side of the lower electrode 813. By forming the hollow pattern in the plane pattern, the area of ​​the upper surface of the lower electrode 813 is reduced, and the capacitance corresponding to the reduced area of ​​the upper surface of the lower electrode 813 is reduced. Therefore, the lower electrode 813 may have an irregular surface formed on its upper surface. In order to form an irregular surface on the upper surface of the lower electrode 813 without forming a hollow pattern for the lower electrode 813, the lower electrode 813 may be formed as a stacked structure having conductor layers of different materials from each other, so that the lowermost conductor layer serves as an etching stopper.

[0185] <10. Tenth Implementation Method>

[0186] In the first embodiment described above, the capacitor 103 is formed on the back side of the semiconductor substrate 101 using the lower electrode 113 and the upper electrode 133 stacked on the semiconductor substrate 101 and the dielectric film 123 interposed between the lower electrode and the upper electrode. In this embodiment, the lower electrode provided on the back side of the semiconductor substrate 101 is patterned to have opposing side surfaces, and the upper electrode provided on the lower electrode is patterned to have opposing side surfaces.

[0187] Fig.19 10 are top plan views each depicting an example of a configuration of a capacitor element according to the tenth embodiment. Note that, Fig.19 Sub-figure a of FIG. 1 is a top view depicting the lower electrode of the capacitor element, and Fig.19 Sub-figure b is a top plan view depicting the upper electrode of the capacitor element.

[0188] Reference Fig.19 , the capacitor element includes a lower electrode 910 and an upper electrode 920. Fig.19 As shown in sub-figure a of , the lower electrode 910 includes base electrodes 911 and 914 and convex sheet electrodes 912 and 915. The convex sheet electrode 912 is connected to the base electrode 911 to protrude from the base electrode 911. The electrode 915 is connected to the base electrode 914 to protrude from the base electrode 914.

[0189] The base electrode 911 and the convex sheet electrode 912 are arranged to be spaced apart from the base electrode 914 and the convex sheet electrode 915. At this time, the side of the convex sheet electrode 912 and the side of the convex sheet electrode 915 can be arranged to be opposite to each other. At this time, the upper electrode 920 can be configured as a cross comb electrode, for example. At the same time, the base electrode 911 can be arranged to surround the base electrode 914 and the convex sheet electrodes 912 and 915.

[0190] A contact 913 is formed in the base electrode 911, and a contact 916 is formed in the base electrode 914. A plurality of contacts 913 may be formed in the base electrode 911 at equal intervals, and a plurality of contacts 916 may be formed in the base electrode 914 at equal intervals.

[0191] In addition, if Fig.19 As shown in sub-figure b of FIG. 1 , the upper electrode 920 includes base electrodes 921 and 924 and convex sheet electrodes 922 and 925. The convex sheet electrode 922 is connected to the base electrode 921 in a manner protruding from the base electrode 921. Each convex sheet electrode 925 is connected to the base electrode 924 in a manner protruding from the base electrode 924.

[0192] The base electrode 921 and the convex sheet electrode 922 are arranged to be spaced apart from the base electrode 924 and the convex sheet electrode 925. At this time, the side of the convex sheet electrode 922 and the side of the convex sheet electrode 925 may be arranged to be opposite to each other. Here, the convex sheet electrode 922 may be arranged to be opposite to the convex sheet electrode 915 in the upward direction and the downward direction, and the convex sheet electrode 925 may be arranged to be opposite to the convex sheet electrode 912 in the upward direction and the downward direction. At this time, the upper electrode 920 may be configured as, for example, a cross-comb electrode. In addition, the base electrode 921 may be arranged to surround the base electrode 924 and the convex sheet electrodes 922 and 915.

[0193] The base electrode 921 is formed with a contact 923, and the base electrode 924 is formed with a contact 926. A plurality of contacts 923 may be formed at equal intervals in the base electrode 921, and a plurality of contacts 926 may be formed at equal intervals in the base electrode 924.

[0194] The base electrode 911 is connected to the base electrode 921 through the contacts 913 and 923. The base electrode 914 is connected to the base electrode 924 through the contacts 916 and 926. At this time, the protruding sheet electrode 925 is stacked on the protruding sheet electrode 912, and the protruding sheet electrode 922 is stacked on the protruding sheet electrode 915.

[0195] Here, the base electrodes 911, 921 have the same polarity as the protruding sheet electrodes 912, 922. The base electrodes 914 and 924 and the protruding sheet electrodes 912 and 915 are provided to have the same polarity as each other. The polarity of the base electrodes 911, 921 and the base electrodes 912, 922 is different from the polarity of the base electrodes 914, 924 and the protruding sheet electrodes 912, 915.

[0196] At this time, between the protruding sheet electrodes 912 and 915, a capacitor is formed between their upper and lower surfaces, and between the protruding sheet electrodes 915 and 922, a capacitor is formed between their upper and lower surfaces. Between the protruding sheet electrodes 912 and 915, a capacitor is formed between their side surfaces, and between the protruding sheet electrodes 922 and 925, a capacitor is formed between their side surfaces.

[0197] In this manner, in the above-described tenth embodiment, the lower electrode 910 and the upper electrode 920 are patterned so that a capacitor is formed between the upper and lower surfaces of the lower electrode 910 and the upper electrode 920, and a capacitor is formed between the side surfaces of the lower electrode 910 and the upper electrode 920. As a result, the capacitance of the capacitance element can be increased without increasing the planar size of the capacitance element.

[0198] In addition, the base electrode 911 is arranged in a manner surrounding the base electrode 914 and the protruding sheet-shaped electrodes 912 and 915, and the base electrode 921 is arranged in a manner surrounding the base electrode 924 and the protruding sheet-shaped electrodes 922 and 925. In addition, the base electrodes 911 and 921 are connected to each other through the contacts 913 and 923. As a result, the capacitor formed in the capacitance element can be shielded.

[0199] <11. Eleventh Implementation Method>

[0200] In the first embodiment described above, the semiconductor chip 110 is formed so that the capacitor element 103 and the through electrodes 106 and 116 are connected to each other through a line formed by extending the conductor film of each through electrode 106 and 116 provided in the semiconductor substrate 101. In the eleventh embodiment, a semiconductor chip formed with a solid-state imaging element is stacked on the semiconductor chip 110, and in the semiconductor chip 110, the capacitor element 103 connected to the through electrodes 106 and 116 is formed on the back side of the semiconductor substrate 101.

[0201] Fig. 20 is a cross-sectional view showing an example of the configuration of a semiconductor device according to an eleventh embodiment.

[0202] Reference Fig. 20, the semiconductor device 900 includes a semiconductor chip 950 additionally provided in the semiconductor device 100 of the above-described first embodiment. The configuration of another portion of the semiconductor device 900 of the eleventh embodiment is similar to that of the semiconductor device 100 of the above-described first embodiment.

[0203] The semiconductor chip 950 is stacked on the semiconductor chip 110. A semiconductor element is formed in the semiconductor chip 950. The semiconductor element may be a solid-state imaging element such as a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS). The light received by the solid-state imaging element may be visible, or may be near infrared (NIR) light, short wavelength infrared light (SWIR), ultraviolet light, or X-rays. The semiconductor element may be a light receiving element such as a photodiode (PD), or a light emitting element such as a laser diode (LD), a light emitting diode (LED), or a vertical cavity surface emitting laser (VCSEL). It should be noted that in the following description, an example in which a back-illuminated solid-state imaging element is formed in the semiconductor chip 950 is described.

[0204] The semiconductor chip 950 includes a semiconductor layer 951 and a wiring layer 952. An imaging region and a non-imaging region are provided in the semiconductor layer 951. In the imaging region, pixels and pixel transistors are arranged in a matrix form along the row direction and the column direction. In the non-imaging region, a peripheral circuit for driving the pixel transistor and outputting the signal read out from the pixel is provided.

[0205] On the back side of the semiconductor layer 951, an on-chip lens 953 is formed for each pixel. As a material for the on-chip lens 953, a transparent resin such as acrylic resin or polycarbonate can be used. Note that a color filter may be provided for each pixel between the semiconductor layer 951 and the on-chip lens 953. In this case, the color filter may be configured in a Bayer array, for example.

[0206] A gate electrode 972 is formed over the semiconductor layer 951 having the semiconductor element formed therein, and a wiring layer 952 is formed so as to cover the gate electrode 972. A wiring 962 is formed in the wiring layer 952. The gate electrode 972 and the wiring 962 are embedded in an insulating film that insulates the wiring layer 952.

[0207] The wiring layer 952 is bonded to the wiring layer 102. At this time, the line 962 of the wiring layer 952 can be electrically connected to the line 112 of the wiring layer 102. In order to bond the wiring layer 952 to the wiring layer 102, direct bonding can be used. As direct bonding, hybrid bonding can be used. In order to bond the lines 112 and 962 to each other, Cu-Cu bonding can be used.

[0208] In this manner, in the above-described eleventh embodiment, the semiconductor chip 950 formed with the solid-state imaging element is stacked on the semiconductor chip 110, and the capacitance element 103 connected to the through electrodes 106 and 116 in the semiconductor chip 110 is formed on the back side of the semiconductor substrate 101. Therefore, the noise resistance performance of the signal transmission interface circuit used in the solid-state imaging element, for example, can be improved, and enhanced signal noise control performance can be achieved.

[0209] <15. Application examples of mobile objects>

[0210] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device incorporated into any type of mobile body, such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0211] Fig.21 : is a block diagram depicting an example of a schematic configuration of a vehicle control system as an example of a moving body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0212] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.21 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as the functional configuration of the integrated control unit 12050.

[0213] The drive system control unit 12010 controls the operation of the devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 is used as a control device to control: a device for generating a driving force for the vehicle, such as an internal combustion engine, a drive motor, etc., a driving force transmission mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force for the vehicle.

[0214] The body system control unit 12020 controls the operation of various types of equipment configured for the body according to various programs. For example, the body system control unit 12020 is used as a control device to control the following items: a keyless entry system, a smart key system, a power window device, or various lights such as headlights, reverse lights, brake lights, turn signals, fog lights, etc. In this case, the body system control unit 12020 may receive as input radio waves transmitted from a mobile device that replaces the key or signals from various switches. The body system control unit 12020 receives these input radio waves or signals to control the door lock device, power window device, lights, etc. of the vehicle.

[0215] The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to an imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image an image of the vehicle exterior, and receives the imaged image. Based on the received image, the vehicle exterior information detection unit 12030 may perform a process of detecting an object (such as a person, vehicle, obstacle, sign, symbol, etc. on the road), or perform a process of detecting the distance to the object.

[0216] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0217] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 may be connected to a driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that photographs the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 may calculate the driver's fatigue level or the driver's concentration level, or may distinguish whether the driver is dozing off.

[0218] The microcomputer 12051 can calculate a control target value for a driving force generation device, a steering mechanism, or a braking device based on information about the interior or exterior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing functions of an advanced driver assistance system (ADAS), including collision avoidance or impact buffering for the vehicle, following driving based on vehicle-to-vehicle distance, vehicle speed maintenance driving, an alarm for vehicle collision, an alarm for vehicle lane deviation, and the like.

[0219] In addition, the microcomputer 12051 can control the driving force generating device, the steering mechanism, and the braking device based on the information about the outside or inside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, thereby performing collaborative control intended for automatic driving, etc. that is independent of the driver's operation.

[0220] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the exterior of the vehicle obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 can control the headlights to change from high beam to low beam based on the position of the preceding vehicle or oncoming vehicle detected by the exterior information detection unit 12030, thereby performing cooperative control aimed at preventing glare by controlling the headlights.

[0221] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device, which can notify information to the passengers of the vehicle or the outside of the vehicle in a visual or auditory manner. Fig.21 In the example of FIG. 1206 , an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as output devices. The display portion 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0222] Fig. 22 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0223] exist Fig. 22 In the figure, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0224] The imaging units 12101, 12102, 12103, 12104 and 12105 may be arranged at the positions of the front nose, side mirrors, rear bumper, rear door and the upper portion of the windshield inside the vehicle 12100. The imaging unit 12101 arranged at the front nose and the imaging unit 12105 arranged at the upper portion of the windshield inside the vehicle mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 arranged at the side mirrors mainly obtain images of the sides of the vehicle 12100. The imaging unit 12104 arranged at the rear bumper or rear door mainly obtains images of the rear of the vehicle 12100. The imaging unit 12105 arranged at the upper portion of the windshield inside the vehicle is mainly used to detect the front vehicle, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0225] By the way, Fig. 22 An example of the shooting range of the imaging units 12101 to 12104 is shown. Imaging range 12111 represents the imaging range of the imaging unit 12101 arranged at the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 arranged at the side mirrors. Imaging range 12114 represents the imaging range of the imaging unit 12104 arranged at the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 observed from above can be obtained by superimposing the image data imaged by the imaging units 12101 to 12104.

[0226] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0227] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and thereby extract the nearest three-dimensional object as the leading vehicle, which specifically exists on the driving path of the vehicle 12100 and travels at a predetermined speed (e.g., equal to or greater than 0 km / h) in the substantially same direction as the vehicle 12100. In addition, the microcomputer 12051 can pre-set the following distance to be maintained from the leading vehicle, and perform automatic braking control (including following parking control), automatic acceleration control (including following starting control), etc. Therefore, cooperative control intended for automatic driving, etc. that does not depend on the operation of the driver, can be performed.

[0228] For example, the microcomputer 12051 can classify the three-dimensional object data about the three-dimensional object into three-dimensional object data of two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, and extract the classified three-dimensional object data for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes whether the obstacles around the vehicle 12100 are obstacles that can be visually identified by the driver of the vehicle 12100, or obstacles that are difficult for the driver of the vehicle 12100 to visually identify. Then, the microcomputer 12051 determines the collision risk, which indicates the risk of collision with each obstacle. In the case where the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 outputs an alarm to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or avoidance steering via the drive system control unit 12010. Thus, the microcomputer 12051 can assist driving to avoid collisions.

[0229] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 is capable of identifying pedestrians by determining whether there are pedestrians in the imaging images of the imaging units 12101 to 12104. This pedestrian recognition is performed, for example, by the following programs: a program for extracting characteristic points in the imaging images of the imaging units 12101 to 12104 as infrared cameras, and a program for determining whether it is a pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there are pedestrians in the imaging images of the imaging units 12101 to 12104 and thus identifies the pedestrians, the sound / image output unit 12052 controls the display unit 12062 to display a square outline superimposed on the identified pedestrian for emphasizing the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 to display an icon representing a pedestrian at a desired position.

[0230] An example of a vehicle control system to which the technology according to the present disclosure is applied has been described. The technology according to the present disclosure can be applied to any configuration in which at least any one of the semiconductor devices, optical devices, semiconductor packages, and circuit boards in the above-mentioned configurations is used. Specifically, the above-mentioned semiconductor devices 100 to 800 and the like can be applied to at least any one of the configurations of the vehicle control system 12000. By applying the technology according to the present disclosure to the vehicle control system 12000, at least a part of the functions of the vehicle control can be realized while suppressing the influence of noise and suppressing the increase in the installation area.

[0231] It should be noted that the above-mentioned embodiments represent examples for embodying the present technology, and the matters in the embodiments and the matters for specifying the technology in the claims have a corresponding relationship, respectively. Similarly, the matters used to specify the technology in the claims and the matters in the embodiments of the present technology have a corresponding relationship individually by the same name as the matters used to specify the technology in the claims. However, it should be noted that the present technology is not limited to the embodiments, and can be implemented by applying various modifications to the embodiments without departing from the gist of the present technology. In addition, the beneficial effects described in this specification are merely exemplary and non-restrictive, and other beneficial effects may be available.

[0232] It should be noted that this technology can also be used in the following configurations: (1)

[0234] An electronic device, comprising:

[0235] substrate;

[0236] a through hole penetrating the substrate;

[0237] A through electrode formed on a side wall of the through hole;

[0238] a capacitor element formed on the substrate; and

[0239] A line is formed by extending the conductor film for the through-electrode and is connected to the capacitive element. (2)

[0241] The electronic device according to (1) above, wherein:

[0242] The substrate includes a semiconductor substrate on which a semiconductor element is formed or a wiring substrate on which a circuit is formed. (3)

[0244] An electronic device according to one or more of (1) and (2) above, wherein:

[0245] The capacitive element comprises:

[0246] Upper electrode,

[0247] The lower electrode, and

[0248] a dielectric film disposed between the upper electrode and the lower electrode,

[0249] The through electrode comprises:

[0250] a first through electrode, and

[0251] a second through electrode, and

[0252] The circuit comprises:

[0253] a first wiring formed by extending a conductor film for the first through-electrode and connected to the upper electrode, and

[0254] A second wiring is formed by extending the conductor film for the second through-electrode and is connected to the lower electrode. (4)

[0256] The electronic device according to (3) above, wherein:

[0257] The upper electrode and the lower electrode each include at least one of TiN, TaN, and WN. (5)

[0259] An electronic device according to one or more of (3) and (4) above, wherein:

[0260] The dielectric film includes at least any one of SiO2, Si3N4, HfO2, Al2O3, ZrO2 and HfAlO. (6)

[0262] An electronic device according to any one or more of (3) to (5) above, wherein:

[0263] The dielectric film and the lower electrode have substantially the same planar dimensions as each other, and the upper electrode has a planar dimension smaller than the planar dimensions of the dielectric film and the lower electrode. (7)

[0265] The electronic device according to (3) above, further comprising:

[0266] The sealing film is formed on the capacitor element and includes at least one of Si3N4 and Al2O3. (8)

[0268] The electronic device according to (7) above, further comprising:

[0269] The capacitor electrode is formed on the upper electrode, the sealing film is interposed between the capacitor electrode and the upper electrode, and the capacitor electrode is configured by a conductor film for the second line. (9)

[0271] An electronic device according to any one or more of (3) to (8) above, wherein:

[0272] The parasitic capacitance between the substrate and the lower electrode is equal to or less than 1 / 10 of the capacitance of the capacitance element. (10)

[0274] The electronic device according to any one or more of (1) to (9) above, further comprising:

[0275] an insulating film formed on the capacitor element; and

[0276] At least one of the line and the external connection terminal is formed above the capacitor element, and an insulating film is interposed between the capacitor element and at least one of the line and the external connection terminal. (11)

[0278] The electronic device according to any one or more of (1) to (10) above, further comprising:

[0279] A photosensitive insulating resin film covering the through-hole. (12)

[0281] An electronic device according to any one or more of (1) to (11) above, wherein:

[0282] The substrate further includes a trench in which a capacitive element is formed. (13)

[0284] The electronic device according to (12) above, further comprising:

[0285] A cavity is disposed in the groove. (14)

[0287] The electronic device according to (13) above, further comprising:

[0288] The insulating film is disposed on the cavity. (15)

[0290] An electronic device according to any one or more of (1) to (14) above, wherein:

[0291] The capacitive element includes capacitive electrodes having polarities different from each other and having sides opposite to each other. (16)

[0293] An electronic device according to any one or more of (1) to (15) above, wherein:

[0294] The circuit includes a plurality of vias connected to capacitor electrodes of the capacitor element. (17)

[0296] An electronic device according to any one or more of (1) to (16) above, wherein:

[0297] The capacitive element includes a plurality of capacitive elements having planar sizes different from each other. (18)

[0299] An electronic device according to any one or more of (1) to (17) above, wherein:

[0300] The capacitive element includes a plurality of upper electrodes which are arranged on the lower electrode and have planar dimensions different from each other. (19)

[0302] The electronic device according to any one or more of (1) to (18) above, further comprising:

[0303] Vias connect to the lower electrode through the gap between the upper electrodes. (20)

[0305] An electronic device according to any one or more of (1) to (19) above, wherein:

[0306] The through-electrode penetrates the capacitor element. (twenty one)

[0308] The electronic device according to any one or more of (1) to (20) above, further comprising:

[0309] a wiring layer formed on a surface of the substrate opposite to a surface on which the capacitor element is formed and connected to the through-electrode; and

[0310] A semiconductor chip is connected to the wiring layer and has a solid-state imaging device formed therein. (twenty two)

[0312] An electronic device, comprising:

[0313] substrate;

[0314] a capacitor element formed on the substrate; and

[0315] A through electrode that penetrates the substrate and the capacitor element. (twenty three)

[0317] The electronic device according to the above (22), further comprising:

[0318] The line is formed by extending the conductor film for penetrating the electrode, and is connected to the capacitor element. (twenty four)

[0320] An electronic device, comprising:

[0321] Semiconductor substrates;

[0322] a wiring layer formed on the front surface side of the semiconductor substrate;

[0323] A through electrode penetrates the semiconductor substrate and is connected to the wiring layer;

[0324] a trench formed on a back side of the semiconductor substrate;

[0325] a capacitor element formed in the trench; and

[0326] A line that connects the through-electrode and the capacitor element to each other. (25)

[0328] An electronic device according to (24) above, wherein

[0329] The wiring is configured by extending a conductor film to penetrate the electrode. (26)

[0331] An electronic device according to one or more of (24) and (25) above, wherein the capacitive element is formed along the sidewall of the trench, and

[0332] The trench has an irregular surface formed on a sidewall of the trench. (27)

[0334] The electronic device according to any one or more of (24) to (26) above further comprises: a cavity disposed in the groove. (28)

[0336] A method for manufacturing an electronic device, comprising:

[0337] forming a capacitor element on a substrate;

[0338] forming a through hole in a substrate on which a capacitor element is formed; and

[0339] A through electrode electrically connected to the capacitor element is formed on a side wall of the through hole. (29)

[0341] The method for manufacturing an electronic device according to (28) above, wherein:

[0342] The conductor film for the through electrode extends and is electrically connected to the capacitive element. (30)

[0344] The method for manufacturing an electronic device according to one or more of (28) and (29) above, further comprising:

[0345] forming an insulating film covering the side wall of the through hole and the capacitive element; and

[0346] The insulating film is removed from the bottom surface of the through hole, and an opening is formed in the insulating film on the capacitive element. (31)

[0348] The method for manufacturing an electronic device according to any one or more of (28) to (30) above, further comprising:

[0349] A sealing film is formed on the capacitor element formed on the substrate, wherein

[0350] The sealing film is used as an etching stopper when an opening is formed in the insulating film on the capacitive element. (32)

[0352] An electronic device, comprising:

[0353] substrate;

[0354] A first through hole penetrating the substrate;

[0355] a capacitive element over the substrate; and

[0356] A first conductor film, wherein a first portion of the first conductor film passes through the substrate along a side wall of the first through hole, and a second portion of the first conductor film contacts the capacitive element. (33)

[0358] An electronic device according to (32) above, wherein:

[0359] The substrate includes one or both of a semiconductor substrate including a semiconductor element and a wiring substrate including wiring. (34)

[0361] An electronic device according to one or more of (32) and (33) above, wherein:

[0362] The capacitor element includes an upper electrode, a lower electrode, and a dielectric film between the upper electrode and the lower electrode, the second portion of the first conductor film is in contact with the upper electrode, and

[0363] The electronic device further includes a second conductor film and a second through hole penetrating the substrate, wherein a first portion of the second conductor film passes through the substrate along a sidewall of the second through hole, and a second portion of the second conductor film contacts the lower electrode. (35)

[0365] An electronic device according to (34) above, wherein the upper electrode and the lower electrode each contain one or more of TiN, TaN and WN. (36)

[0367] An electronic device according to one or more of (34) and (35) above, wherein the dielectric film comprises one or more of SiO2, Si3N4, HfO2, Al2O3, ZrO2 and HfAlO. (37)

[0369] An electronic device according to any one or more of (34) to (36) above, wherein the dielectric film and the lower electrode have substantially the same planar dimensions as each other, and the upper electrode has a planar dimension smaller than the planar dimension of each of the dielectric film and the lower electrode. (38)

[0371] The electronic device according to any one or more of (34) to (37) above further comprises a sealing film on the capacitor element, the sealing film comprising one or more of Si3N4 and Al2O3. (39)

[0373] The electronic device according to (38), wherein the third portion of the second conductor film is separated from the upper electrode by the sealing film. (40)

[0375] An electronic device according to any one or more of (34) to (39) above, wherein the parasitic capacitance between the substrate and the lower electrode is equal to or less than one tenth of the capacitance of the capacitive element. (41)

[0377] The electronic device according to any one or more of (32) to (40) above, further comprising: an insulating film on the capacitor element; and

[0378] One or more of the wiring and the external connection terminal above the capacitor element, an insulating film is interposed between the capacitor element and the one or more of the wiring and the external connection terminal. (42)

[0380] The electronic device according to any one or more of (32) to (41) above, further comprising: a photosensitive insulating resin film covering the opening of the first through hole. (43)

[0382] An electronic device according to any one or more of (32) to (42) above, wherein the substrate includes a groove in which the capacitive element is embedded. (44)

[0384] The electronic device according to the above (43) further comprises: a cavity arranged in the groove. (45)

[0386] The electronic device according to one or more of (43) and (44) above further includes: an insulating film disposed above the cavity. (46)

[0388] An electronic device according to any one or more of (32) to (45) above, wherein the capacitor element includes capacitor electrodes having polarities different from each other and having side surfaces opposite to each other. (47)

[0390] An electronic device according to any one or more of (32) to (46) above, wherein the first conductor film includes a plurality of vias connected to the capacitive electrodes of the capacitive element. (48)

[0392] An electronic device according to any one or more of (32) to (47) above, wherein the capacitive element includes a plurality of capacitive elements having planar dimensions different from each other. (49)

[0394] An electronic device according to any one or more of (32) to (49) above, wherein the capacitive element includes a plurality of upper electrodes above the lower electrode, wherein the plurality of upper electrodes have different planar dimensions from each other. (50)

[0396] The electronic device according to (49), further comprising: a via hole connected to the lower electrode through the gap between the upper electrodes. (51)

[0398] An electronic device according to any one or more of (32) to (50) above, wherein the first through hole penetrates the capacitive element. (52)

[0400] The electronic device according to any one or more of (32) to (51) above, further comprising:

[0401] a wiring layer located on a bottom surface of the substrate and in contact with the first portion of the first conductor film, wherein the bottom surface of the substrate is opposite to the top surface of the substrate; and

[0402] A semiconductor chip is connected to the wiring layer, the semiconductor chip including a solid-state imaging device. (53)

[0404] An electronic device, comprising:

[0405] substrate;

[0406] a capacitive element over the substrate; and

[0407] A through electrode that penetrates the substrate and the capacitor element. (54)

[0409] The electronic device according to (53) above, wherein the through-electrode includes a first portion of the first conductor film, and wherein a second portion of the first conductor film is in contact with the capacitive element. (55)

[0411] An electronic device, comprising:

[0412] Semiconductor substrates;

[0413] a wiring layer located on the front side of the semiconductor substrate;

[0414] A through electrode penetrates the semiconductor substrate and is connected to the wiring layer;

[0415] a trench in a back side of a semiconductor substrate;

[0416] a capacitive element embedded in the trench; and

[0417] The through-electrodes are connected to the capacitor elements by wiring. (56)

[0419] The electronic device according to (55) above, wherein the wiring includes a conductor film, wherein the through electrode includes a portion of the conductor film. (57)

[0421] An electronic device according to one or more of (55) and (56) above, wherein at least a portion of the capacitive element extends along a sidewall of the trench, and the sidewall of the trench includes a textured surface. (58)

[0423] The electronic device according to any one or more of (55) to (57) above further includes a cavity in the groove. (59)

[0425] A method for manufacturing an electronic device, the method comprising:

[0426] forming a capacitor element on a substrate;

[0427] forming a through hole in the substrate; and

[0428] A through electrode is formed along a sidewall of the through hole, wherein the through electrode is electrically connected to the capacitive element. (60)

[0430] The method for manufacturing an electronic device according to the above (59), wherein the through electrode includes a portion of the conductor film, wherein the through electrode is electrically connected to the capacitive element. (61)

[0432] The method for manufacturing an electronic device according to one or more of (60) and (61) above, further comprising:

[0433] forming an insulating film covering the side wall of the through hole and the capacitive element; and

[0434] The insulating film is removed from the bottom surface of the through hole to form an opening in the insulating film. (62)

[0436] The method for manufacturing an electronic device according to (61) above, further comprising: forming a sealing film on the capacitive element, wherein a portion of the insulating film is removed by etching the insulating film using the sealing film as an etching stopper.

[0437] [Reference Numbers List]

[0438] 100 Semiconductor Devices

[0439] 110 Semiconductor Chip

[0440] 101 Semiconductor substrate

[0441] 102 Wiring Layer

[0442] 112 lines

[0443] 122 pad electrode

[0444] 132 Gate electrode

[0445] 103 Capacitor Components

[0446] 113 Lower electrode

[0447] 123 Dielectric Film

[0448] 133 Upper electrode

[0449] 114 Sealing film

[0450] 104 Back insulation film

[0451] 105, 115 insulation film

[0452] 106, 116 through-electrode

[0453] 107, 117 bump electrode

[0454] 111, 121 through holes

[0455] 118 protective film

[0456] 131, 141 cavity

[0457] 126, 136, 166, 176 back line

[0458] 142, 145, 155 openings

[0459] 146, 156 vias.

Claims

1. An electronic device comprising: substrate; A first through hole penetrating the substrate; a capacitive element, above the substrate; as well as A first conductor film, wherein a first portion of the first conductor film passes through the substrate along a side wall of the first through hole, and a second portion of the first conductor film contacts the capacitive element.

2. The electronic device according to claim 1, wherein: The substrate includes one or both of a semiconductor substrate including a semiconductor element and a wiring substrate including wiring.

3. The electronic device according to claim 1, wherein: The capacitor element includes an upper electrode, a lower electrode, and a dielectric film between the upper electrode and the lower electrode. A second portion of the first conductor film is in contact with the upper electrode, and The electronic device further includes a second conductor film and a second through hole penetrating the substrate, wherein a first portion of the second conductor film passes through the substrate along a sidewall of the second through hole, and a second portion of the second conductor film contacts the lower electrode.

4. The electronic device according to claim 3, wherein: The upper electrode and the lower electrode each include one or more of TiN, TaN, and WN.

5. The electronic device according to claim 3, wherein: The dielectric film includes one or more of SiO2, Si3N4, HfO2, Al2O3, ZrO2 and HfAlO.

6. The electronic device according to claim 3, wherein: The dielectric film and the lower electrode have substantially the same planar dimensions as each other, and the upper electrode has a planar dimension smaller than a planar dimension of each of the dielectric film and the lower electrode.

7. The electronic device according to claim 3, further comprising: A sealing film on the capacitor element, wherein the sealing film comprises one or more of Si3N4 and Al2O3.

8. The electronic device according to claim 7, wherein: A third portion of the second conductor film is separated from the upper electrode by the sealing film.

9. The electronic device according to claim 3, wherein: A parasitic capacitance between the substrate and the lower electrode is equal to or less than one tenth of a capacitance of the capacitive element.

10. The electronic device according to claim 1, further comprising: An insulating film on the capacitive element; as well as At one or more of a wiring and an external connection terminal above the capacitor, the insulating film is interposed between the capacitor and the one or more of the wiring and the external connection terminal.

11. The electronic device according to claim 1, further comprising: A photosensitive insulating resin film covers the opening of the first through hole.

12. The electronic device according to claim 1, wherein: The substrate includes a groove in which the capacitive element is embedded.

13. The electronic device according to claim 12, further comprising: A cavity is disposed in the groove.

14. The electronic device according to claim 13, further comprising: An insulating film is disposed above the cavity.

15. The electronic device according to claim 1, wherein: The capacitive element includes capacitive electrodes having polarities different from each other and having sides opposite to each other.

16. The electronic device according to claim 1, wherein: The first conductor film includes a plurality of vias connected to capacitor electrodes of the capacitor element.

17. The electronic device according to claim 1, wherein: The capacitive element includes a plurality of capacitive elements having planar sizes different from each other.

18. The electronic device according to claim 1, wherein: The capacitive element includes a plurality of upper electrodes over a lower electrode, wherein the plurality of upper electrodes have different planar dimensions from each other.

19. The electronic device according to claim 18, further comprising: A via hole is connected to the lower electrode through the gap between the upper electrodes.

20. The electronic device according to claim 1, wherein The first through hole penetrates the capacitor element.

21. The electronic device according to claim 1, further comprising: a wiring layer located on a bottom surface of the substrate and in contact with a first portion of the first conductor film, wherein the bottom surface of the substrate is opposite to a top surface of the substrate; and A semiconductor chip is connected to the wiring layer, the semiconductor chip including a solid-state imaging device.

22. An electronic device comprising: substrate; a capacitive element, above the substrate; as well as The through electrode penetrates the substrate and the capacitor element.

23. The electronic device according to claim 22, wherein: The through-electrode includes a first portion of a first conductor film, and wherein a second portion of the first conductor film is in contact with the capacitive element.

24. An electronic device comprising: Semiconductor substrates; a wiring layer located on the front side of the semiconductor substrate; A through electrode penetrates the semiconductor substrate and is connected to the wiring layer; a trench in a back surface of the semiconductor substrate; A capacitor element embedded in the groove; as well as A wiring is provided to connect the through-electrode to the capacitor element.

25. The electronic device according to claim 24, wherein: The wiring includes a conductor film, wherein the through-electrode includes a portion of the conductor film.

26. The electronic device according to claim 24, wherein: At least a portion of the capacitive element extends along a sidewall of the trench, and the sidewall of the trench includes a textured surface.

27. The electronic device according to claim 24, further comprising: A cavity in the groove.

28. A method for manufacturing an electronic device, the method comprising: forming a capacitor element on a substrate; forming a through hole in the substrate; as well as A through electrode is formed along a sidewall of the through hole, wherein the through electrode is electrically connected to the capacitive element.

29. The method for manufacturing an electronic device according to claim 28, wherein: The through-electrode includes a portion of a conductor film, wherein the through-electrode is electrically connected to the capacitive element.

30. The method for manufacturing an electronic device according to claim 28, further comprising: forming an insulating film covering the sidewall of the through hole and the capacitive element; as well as The insulating film is removed from a bottom surface of the through hole to form an opening in the insulating film.

31. The method for manufacturing an electronic device according to claim 30, further comprising: A sealing film is formed on the capacitive element, wherein a portion of the insulating film is removed by etching the insulating film using the sealing film as an etching stopper.

Images