Backside layer of semiconductor substrate

Abstract

A composite nanocrystalline silicon layer may be formed by directly or indirectly depositing a polysilicon sub-layer on a substrate. An amorphous silicon sub-layer is deposited on the polysilicon sub-layer. The composite nano crystalline silicon layer may be formed by repeatedly depositing a polysilicon sub-layer and an amorphous silicon sub-layer.

Description

Incorporated by Reference The PCT application form is filed concurrently with this specification as a part of this application. Each application identified in the concurrently filed Application Data Sheet to which this application claims the benefit or priority is incorporated herein by reference in its entirety and for all purposes. Background Art

[0001] Certain semiconductor device manufacturing operations require clamping or "chucking" a semiconductor wafer or substrate. In some cases, this operation uses an electrostatic chuck (ESC). An example of such an operation is for transferring a pattern to a wafer in photolithography.

[0002] The background description provided here is for the purpose of generally presenting the context of the present disclosure. The work of the presently designated inventors is neither explicitly nor implicitly admitted to be prior art against the present disclosure to the extent that it is described in this background section and to aspects of the specification that could not be determined as prior art at the time of filing the application. Summary of the invention

[0003] A method for forming a composite nanocrystalline silicon sublayer is provided. The method may include: (a) directly or indirectly depositing a polycrystalline silicon sublayer on a substrate; (b) depositing an amorphous silicon sublayer on the polycrystalline silicon sublayer; and (c) repeating (a) and (b) one or more times.

[0004] In some embodiments, the polysilicon sublayer can be deposited by chemical vapor deposition, plasma assisted chemical vapor deposition, atomic layer deposition, plasma assisted atomic layer deposition, or epitaxial growth.

[0005] In some embodiments, the amorphous silicon sublayer can be deposited by chemical vapor deposition, plasma assisted chemical vapor deposition, atomic layer deposition, plasma assisted atomic layer deposition, or epitaxial growth.

[0006] In some embodiments, (c) may be performed at least twice.

[0007] In some embodiments, the polysilicon sublayer and the amorphous silicon sublayer can be deposited on the back side of the substrate.

[0008] In some embodiments, a thickness ratio of the polysilicon sublayer to the amorphous silicon sublayer may be about 0.2 to 3.0.

[0009] In some embodiments, the amorphous silicon sublayer may have a thickness of about 5 nm to 50 nm.

[0010] In some embodiments, the polysilicon sublayer may have a thickness of about 5 nm to 50 nm.

[0011] In some embodiments, the amorphous silicon sublayer may be deposited at a temperature of about 200°C-600°C.

[0012] In some embodiments, the polysilicon sublayer may be deposited at a temperature of about 200°C-600°C.

[0013] In some embodiments, the amorphous silicon sublayer can be deposited at a pressure of about 1 Torr to 9 Torr.

[0014] In some embodiments, the polysilicon sublayer can be deposited at a pressure of about 1 Torr to 9 Torr.

[0015] In some embodiments, the amorphous silicon sublayer may be deposited at an RF power of about 100 watts to about 500 watts per station.

[0016] In some embodiments, the polysilicon sublayer may be deposited at an RF power of about 100 watts to about 500 watts per station.

[0017] In some embodiments, the amorphous silicon sublayer can be deposited at an RF frequency of about 13.56 MHz or about 27 MHz.

[0018] In some embodiments, the polysilicon sublayer can be deposited at an RF frequency of about 13.56 MHz or about 27 MHz.

[0019] In some embodiments, the composite nanocrystalline silicon layer may have a hardness of 9 GPa or less.

[0020] In some embodiments, the composite nanocrystalline silicon layer may have a surface roughness of about 0.2 nm to about 10 nm.

[0021] Another aspect of the present disclosure relates to an apparatus. The apparatus includes: a reaction chamber; a pedestal for supporting a substrate in the reaction chamber during a deposition process, the substrate including a front side and a back side; a gas supply configured to deliver a silicon-containing precursor to the substrate while the substrate is held by the pedestal; a radio frequency (RF) power supply for providing power to the showerhead to generate a plasma; and a controller. The controller is configured to cause: (a) directly or indirectly depositing a polycrystalline silicon sublayer on the substrate; (b) depositing an amorphous silicon sublayer on the polycrystalline silicon sublayer; and (c) repeating (a) and (b) one or more times.

[0022] In some embodiments, the gas supply can be fluidly coupled to the susceptor to deliver the silicon-containing precursor to the backside of the substrate.

[0023] In some embodiments, the pedestal can be configured to cause the polysilicon sublayer or the amorphous silicon sublayer to be deposited on the back side of the substrate.

[0024] In some embodiments, the polysilicon sublayer and the amorphous silicon sublayer may be deposited by plasma enhanced chemical vapor deposition or plasma enhanced atomic layer deposition.

[0025] Yet another aspect of the present disclosure relates to a method. The method may include: (a) forming a warpage compensating backside layer on a substrate, wherein the backside layer has a surface roughness of about 1 nm to 4 nm; (b) attaching the substrate to a substrate support; and (c) performing a manufacturing operation on the substrate while the substrate is attached to the substrate support.

[0026] In some embodiments, the warp compensating layer has a hardness of about 10 GPa or less.

[0027] In some embodiments, the substrate support is a clamp or a chuck.

[0028] In some embodiments, the substrate support is a lithography stage for a UV or EUV lithography system.

[0029] Another aspect of the present disclosure relates to a substrate. The substrate includes an electronic device partially fabricated on the substrate. The substrate includes a semiconductor wafer. The front side of the semiconductor wafer includes the partially fabricated electronic device. The substrate includes a backside layer on the semiconductor wafer. The backside layer is opposite the front side. The backside layer includes a composite nanocrystalline silicon layer.

[0030] In some embodiments, the composite nanocrystalline silicon layer includes alternating amorphous silicon layers and polycrystalline silicon layers.

[0031] In some embodiments, the semiconductor wafer is a single crystal silicon wafer.

[0032] These and other aspects will be further described below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A process flow diagram is shown that depicts some embodiments.

[0034] Figure 2A-2E is a schematic diagram of an exemplary cross-section of a substrate during semiconductor processing according to some embodiments.

[0035] Figure 3A-3B A block diagram of an exemplary substrate processing chamber is shown according to some embodiments.

[0036] Figure 4A schematic diagram of an exemplary processing system that can be used to perform methods according to some embodiments is shown.

[0037] Figure 5 is the hardness measured for an a-Si sub-layer, a composite nanocrystalline silicon layer, a poly-Si sub-layer, and a silicon wafer according to some embodiments. DETAILED DESCRIPTION

[0038] In the following description, several specific details will be presented to provide a thorough understanding of the embodiments. The disclosed embodiments may be practiced in the absence of some or all of these specific details. In other cases, well-known processing operations are not described in detail to avoid unnecessarily obscuring the disclosed embodiments. Although specific embodiments will be used to illustrate the disclosed embodiments, it should be understood that they are not intended to limit the disclosed embodiments. the term

[0039] The terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially fabricated integrated circuit" may be used interchangeably. One of ordinary skill in the art will appreciate that the term "partially fabricated integrated circuit" may refer to a silicon wafer during any of many stages of integrated circuit fabrication thereon. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. Examples of wafer materials include silicon (Si), gallium arsenide (GaAs), and silicon germanium (SiGe). In addition to semiconductor wafers, other workpieces that may utilize the disclosed embodiments include various articles of manufacture, such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, display devices or components, such as backplanes for pixelated display devices, flat panel displays, micromechanical devices, and the like. The workpiece may have many shapes, sizes, and materials.

[0040] As used herein, "semiconductor device manufacturing operations" are operations performed during the manufacture of semiconductor devices. Typically, the entire manufacturing process includes multiple semiconductor device manufacturing operations, each of which is performed in its own unique semiconductor manufacturing tool, such as a plasma reactor, an electroplating tank, a chemical mechanical planarization tool, a wet etching tool, and the like. Categories of semiconductor device manufacturing operations include subtractive processes, such as etching processes and planarization processes, and additive processes, such as deposition processes (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, electrochemical deposition, electroless deposition). In the context of etching processes, substrate etching processes include processes that etch mask layers, or more generally, processes that etch any material layer previously deposited on the substrate surface and / or otherwise left on the substrate surface. Such etching processes can etch stacks of layers in a substrate.

[0041] "Fabrication apparatus" refers to an apparatus in which a manufacturing process is performed. A fabrication apparatus typically has a reaction chamber in which a workpiece resides during processing. Typically, when in use, a fabrication apparatus performs one or more semiconductor device fabrication operations. Examples of fabrication apparatus used for semiconductor device fabrication include deposition reactors, such as plating tanks, physical vapor deposition reactors, chemical vapor deposition reactors, and atomic layer deposition reactors, and subtractive processing reactors, such as dry etching reactors (e.g., chemical and / or physical etching reactors, wet etching reactors, and ashers.

[0042] As used herein, "wafer bow" may refer to deformation of a wafer. Wafer bow may occur during manufacturing due to, for example, stresses caused to the wafer during deposition of material on the active surface of the wafer substrate. Wafer bow may occur during various types of manufacturing, such as when depositing large amounts of stack material. Wafer bow may cause complications in subsequent processing steps. For example, if the amount of warpage is too great, the wafer may not be properly clamped. In addition, some processing steps, particularly lithography and etching, may produce poor results if performed on an excessively warped wafer.

[0043] Wafer warpage can be measured as the deviation of the average or median distance of the wafer surface to a reference plane. The point of the mid-plane of the wafer can be the center point (e.g., in the case of concave or dome-shaped warpage), or the edge point of the wafer and / or the average edge point of the wafer (e.g., in the case of bow or convex warpage).

[0044] As used herein, "backside layer" refers to any layer formed on one side of a substrate opposite to the front side of the substrate. The front side is where electronic devices are usually formed on a semiconductor substrate (e.g., a single crystal silicon wafer). For many applications, the backside layer compensates for wafer warpage. The backside layer can be formed by any of many possible materials. In some embodiments, the material is a composite nanocrystalline silicon layer, including an amorphous silicon layer and a polycrystalline silicon layer. The "backside layer" can be characterized by certain physical properties as disclosed herein, such as roughness and / or hardness.

[0045] As used herein, "electrostatic chuck" (ESC) refers to a chuck that uses electrostatic force to clamp a wafer to the chuck during processing. An ESC may use one or more electrodes. A voltage may be applied to each of the one or more electrodes. The applied voltage may cause a current to flow, thereby causing charge to migrate through a dielectric layer between the chuck and the wafer or substrate being processed. Thus, a charge that accumulates at the electrode, opposite to the wafer, causes the wafer to be clamped or clamped to the chuck by electrostatic force. In some cases, the electrode may be integrated into the ESC or may be separate from the ESC. In some embodiments, an ESC may refer to an electrode that generates an electrostatic force.

[0046] As used herein, "pedestal" may refer to a structure or housing that supports or contains a chuck. Introduction and Background

[0047] Semiconductor device manufacturing typically involves depositing a stack of layers on a wafer substrate. Typically, most deposition and other processing to form the device occurs on one side of the substrate, commonly referred to as the front side of the wafer. As the deposited layers accumulate, they introduce stress into the wafer. Large net compressive or tensile stresses can cause the wafer to warp, which is undesirable.

[0048] Warping can be particularly likely when depositing large amounts of stack material, such as in the case of 3D-NAND devices. When warping is significant, it can have an adverse effect on subsequent processing steps. For example, if the warping is too large, the wafer may not be properly clamped. Figure 1 A and 1B show a wafer on an electrostatic chuck. In addition, certain processing steps (e.g., photolithography) are very precise and produce poor results if the wafer is not substantially flat. This problem may manifest as photolithography defocus and / or overlay problems.

[0049] An exemplary stack that may cause these problems is a stack having alternating oxide layers and nitride layers (e.g., silicon oxide / silicon nitride / silicon oxide / silicon nitride, etc.). Another exemplary stack that may cause warpage includes alternating oxide layers and polysilicon layers (e.g., silicon oxide / polysilicon / silicon oxide / polysilicon, etc.). Other examples of potentially problematic stack materials include, but are not limited to, tungsten, titanium nitride, and carbon.

[0050] The materials in the stack may be deposited by chemical vapor deposition (CVD) techniques, such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or by direct metal deposition (DMD), etc. These examples are not intended to be limiting. Certain disclosed embodiments may be useful whenever wafer stress and / or warpage is caused by the presence of materials on the front side of the wafer.

[0051] Various techniques have been devised to combat warpage. Many such techniques involve adjusting the deposition process to reduce or counteract internal stresses in the deposited layer. For example, some processes deposit the film on the back side of the wafer. Alternatively, electrostatic chucking (ESC) can be performed in a manner that reduces or eliminates warpage (e.g., the clamped wafer exhibits warpage of less than about 150 μm).

[0052] A widely used technique to combat warpage involves depositing a high stress dielectric film on the backside of the wafer using chemical vapor deposition (CVD). If the backside film has the same type and magnitude of internal stress as on the frontside, the backside film effectively counteracts and corrects the warpage.

[0053] A typical scenario may involve the following operations: 1. Deposition of one or more front-side layers with high internal stress, resulting in significant warpage (chamber A) 2. Deposit a backside layer with intrinsic stress that counteracts the intrinsic stress of the one or more frontside layers and reduces or eliminates warpage (Chamber B) 3. Patterning the front side of the non-warped substrate by photolithography 4. Etching of non-warped, patterned substrate (Chamber C) Chambers A, B, and C may be different, but this is not always the case. For example, in some embodiments, chambers A and C are the same.

[0054] Photolithography is the process used to define the patterns of features on the layers of an integrated circuit. It specifies the shape, size, and location of the different parts of an integrated circuit. As device geometries have shrunk, IC manufacturers have been able to extend 193nm photolithography far beyond what was thought possible when using complex multiple patterning techniques. However, adding more and more optical steps is not sustainable because it results in longer manufacturing cycle times and a greater risk of affecting yield. In addition, the ability to resolve yield issues becomes extremely complex.

[0055] Therefore, starting with the 5nm technology node, IC logic manufacturers are transitioning to extreme ultraviolet lithography (EUVL). EUVL has a 13.5nm wavelength and provides simplified patterning. However, using EUVL in HVM (high-volume manufacturing) faces many challenges, including cost and scanner uptime.

[0056] During patterning and during many other processes, an electrostatic chuck is used to keep the wafer flat on the lithography table to prevent movement and minimize overlay errors related to wafer bow. Due to the high forces required to keep the wafer flat during processing, the electrostatic chuck may become damaged. Scratches and dents sometimes seen on the back side of the wafer from upstream processing may cause corrosion and / or deformation of the lithography electrostatic chuck table surface over time. Corrosion of the lithography table surface is related to the hardness of the material on the back side of the wafer. Such material is often a silicon-containing backside layer that compensates for warpage.

[0057] The surface of the lithography table is designed with precisely defined features to improve clamping and minimize overlay errors. If surface corrosion occurs and chuck spots (localized uncorrectable overlay errors) lead to significant yield loss, the lithography table must be replaced. Due to these failures, EUV lithography tables often need to be replaced frequently, resulting in significant cost and uptime challenges.

[0058] According to the embodiments herein, a method for forming a composite nanocrystalline silicon layer is disclosed. Compared with some other silicon layers, the layer may have a relatively low hardness, and it may have other beneficial properties. In some embodiments, the composite nanocrystalline silicon layer reduces the possibility of damaging the chuck in subsequent processing. Such a chuck includes the chuck used in any downstream processing, including the photolithography chuck workbench. In some embodiments, the composite nanocrystalline silicon layer is used as a backside layer to offset warpage, and when the substrate is clamped or clamped (for example, electrostatic clamping) to the substrate support component (for example, the photolithography workbench), it may produce reduced damage or no damage. In some embodiments, the composite nanocrystalline silicon layer with reduced hardness as described herein may be applied to the back side of the substrate independently of one or more other backside layers to offset warpage or in combination with the backside layer. For example, the composite nanocrystalline silicon layer may be deposited on or above the backside layer to offset warpage (including, for example, the compensating warpage layer of silicon nitride and / or silicon oxide on the back side of the wafer). Deposition Processing

[0059] Conventionally, the silicon layer can be deposited using CVD, PECVD, ALD, PEALD, or epitaxial growth processes. If the silicon layer is a backside layer, it can be deposited in a specially designed backside deposition apparatus, such as the one available from Lam Research Corp. (Fremont, CA). and Datum tools.

[0060] Certain embodiments disclosed herein employ a cyclical approach of alternating deposition of amorphous silicon (a-Si) layers and polycrystalline silicon (poly-Si) layers to produce a composite nanocrystalline silicon layer. The composite nanocrystalline silicon layer may have a lower hardness than any of the constituent layers alone.

[0061] In some embodiments, the various layers are deposited by PECVD or PEALD. When a plasma assisted deposition method is used, the composite nanocrystalline silicon layer can be formed at a relatively low temperature (e.g., about 400° C. or lower), making the entire deposition process compatible with both the front-end of the line (FEOL) and the back-end of the line (BEOL) integration flow. In some embodiments, the composite nanocrystalline silicon layer can be manufactured without the use of post-deposition operations (e.g., annealing). In other words, after the cyclic a-Si / poly-Si (or poly-Si / a-Si) process is completed, the resulting layer can be used without any further processing.

[0062] In some embodiments, a tool designed to deposit material only on the back side of the substrate is used to deposit the composite nanocrystalline silicon layer. An example of such a tool is the Vector 1000 available from Lam Research Corp. (Fremont, CA). Tools. In some embodiments, the composite nanocrystalline silicon layer can be made without using thermal treatments, such as those requiring a high temperature furnace (e.g., about 650-850° C. or 700° C.). Deposition processes such as CVD may require the use of a furnace, which typically deposits material over the entire substrate, including on the back side, the front side, and the edge of the wafer. Amorphous silicon (a-Si) sublayer Precursor

[0063] By using a low temperature treatment (e.g., PECVD or PEALD) of one or more silicon-containing precursors, an amorphous silicon (a-Si) layer can be formed on the back side of the substrate. In some embodiments, the silicon-containing precursor may include one or more Si-H bonds. In some cases, the silicon-containing precursor includes one or more Si-Si bonds. Silicon-containing precursors suitable for use according to the disclosed embodiments may include silanes, including polysilanes (H3Si-(SiH2)n-SiH3), where n≥0. Examples of silanes include monosilane (SiH4), disilane (Si2H6), trisilane (Si3H8), and organosilanes, such as methylsilane, ethylsilane, isopropylsilane, tert-butylsilane, dimethylsilane, diethylsilane, di-tert-butylsilane, allylsilane, sec-butylsilane, tert-hexylsilane (thexylsilane), isopentylsilane, tert-butyldisilane, di-tert-butyldisilane, and the like.

[0064] In some embodiments, the silicon-containing precursor may also include halosilanes. Halosilanes include at least one halogen atom and may or may not include hydrogen and / or carbon groups. Examples of halosilanes are iodosilanes, bromosilanes, chlorosilanes and fluorosilanes. Specific chlorosilanes are tetrachlorosilane, trichlorosilane, dichlorosilane, monochlorosilane, chloroallylsilane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, tert-butylchlorosilane, di-tert-butylchlorosilane, chloroisopropylsilane, chlorosec-butylsilane, tert-butyldimethylchlorosilane, tert-hexyldimethylchlorosilane, etc.

[0065] In some embodiments, the silicon-containing precursor may also include aminosilanes. Aminosilanes contain at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogen, oxygen, halogens, and carbon. Examples of aminosilanes are monoaminosilane, diaminosilane, triaminosilane, and tetraaminosilane (H3Si(NH2), H2Si(NH2)2, HSi(NH2)3, and Si(NH2)4, respectively), as well as substituted monoaminosilanes, diaminosilanes, triaminosilanes, and tetraaminosilanes, such as tert-butylaminosilane, methylaminosilane, tert-butylsilylamine, bis(tert-butylamino)silane (SiH2(NHC(CH3)3)2, BTBAS), tert-butyl silylcarbamate, SiH(CH3)-(N(CH3)2)2, SiHCl-(N(CH3)2)2, (Si(CH3)2NH)3, and the like. A further example of an aminosilane is trisilylamine (N(SiH3)). In some embodiments, aminosilanes having two or more amine groups attached to the central Si atom may be used. These may cause less damage (compared to aminosilanes having only a single amine group attached).

[0066] In addition to the silicon-containing precursor, one or more carrier gases may also flow to an environment adjacent to the substrate. Examples of carrier gases include, but are not limited to, helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), deuterium (D2), hydrogen (H2), and nitrogen (N2). In some embodiments, a gas mixture of one or more source gases (e.g., silicon-containing precursors) and one or more of these inert carrier gases may be provided. In some embodiments, the flow rate ratio of the silicon-containing precursor to the carrier gas may be between about 1 / 1 and about 1 / 1,000, or between about 1 / 3 and about 1 / 300. In some embodiments, the a-Si sublayer may be a hydrogenated amorphous silicon (a-Si:H) layer. pressure

[0067] In some embodiments, the chamber pressure during deposition of the a-Si sub-layer can be about 1-9 Torr, or about 2-6 Torr, or about 3-5 Torr. temperature

[0068] In some embodiments, the deposition temperature may be about 200-600°C, or about 250-450°C, or about 300-420°C, or about 350-400°C. Plasma parameters

[0069] In the case where the a-Si sublayer is deposited by a plasma assisted deposition process (e.g., PECVD or PEALD), the plasma may be generated by applying radio frequency (RF) power to the process chamber. In some embodiments, the RF power has a high frequency (e.g., 13 MHz-40 MHz) and / or a low frequency (e.g., <1 MHz). In some embodiments, the high frequency RF power is provided at a frequency of about 13.56 MHz or about 27 MHz. The plasma power (i.e., RF power) may be about 50 to 1,000 watts (W), or 100-500 W per wafer in process (e.g., at each station in a multi-station deposition chamber). Film thickness

[0070] The a-Si sub-layer formed according to some embodiments herein may have a thickness of about 5-50 nm, or about 10-20 nm. Polysilicon (poly-Si) sublayer Precursor

[0071] The polysilicon (poly-Si) sublayer can be formed by providing one or more silicon-containing precursors to the substrate in the reaction chamber. In some embodiments, the silicon-containing precursor includes one or more Si-H bonds. In some cases, the silicon-containing precursor includes one or more Si-Si bonds. Silicon-containing precursors suitable for use according to the disclosed embodiments may include silanes, including polysilanes (H3Si-(SiH2)n-SiH3), where n≥0. Examples of silanes include monosilane (SiH4), disilane (Si2H6), trisilane (Si3H8), and organosilanes, such as methylsilane, ethylsilane, isopropylsilane, tert-butylsilane, dimethylsilane, diethylsilane, di-tert-butylsilane, allylsilane, sec-butylsilane, tert-hexylsilane (thexylsilane), isopentylsilane, tert-butyldisilane, di-tert-butyldisilane, etc.

[0072] In some embodiments, the silicon-containing precursor may also include halosilanes. Halosilanes include at least one halogen atom and may or may not include hydrogen and / or carbon groups. Examples of halosilanes are iodosilanes, bromosilanes, chlorosilanes and fluorosilanes. Specific chlorosilanes are tetrachlorosilane, trichlorosilane, dichlorosilane, monochlorosilane, chloroallylsilane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, tert-butylchlorosilane, di-tert-butylchlorosilane, chloroisopropylsilane, chlorosec-butylsilane, tert-butyldimethylchlorosilane, tert-hexyldimethylchlorosilane, etc.

[0073] In some embodiments, the silicon-containing precursor may also include aminosilanes. Aminosilanes contain at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogen, oxygen, halogens, and carbon. Examples of aminosilanes are monoaminosilane, diaminosilane, triaminosilane, and tetraaminosilane (H3Si(NH2), H2Si(NH2)2, HSi(NH2)3, and Si(NH2)4, respectively), as well as substituted monoaminosilanes, diaminosilanes, triaminosilanes, and tetraaminosilanes, such as tert-butylaminosilane, methylaminosilane, tert-butylsilylamine, bis(tert-butylamino)silane (SiH2(NHC(CH3)3)2, BTBAS), tert-butyl silylcarbamate, SiH(CH3)-(N(CH3)2)2, SiHCl-(N(CH3)2)2, (Si(CH3)2NH)3, and the like. A further example of an aminosilane is trisilylamine (N(SiH3)). In some embodiments, aminosilanes having two or more amine groups attached to the central Si atom may be used. These may cause less damage (compared to aminosilanes having only a single amine group attached).

[0074] In some embodiments, the silicon-containing precursor used for the poly-Si sublayer can be the same as the silicon-containing precursor used to deposit the a-Si sublayer. In some embodiments, different silicon-containing precursors can be provided when depositing the poly-Si sublayer and the a-Si sublayer.

[0075] In addition to the silicon-containing precursor, one or more carrier gases may be flowed to an environment adjacent to the substrate for deposition of the poly-Si sublayer. Examples of carrier gases include, but are not limited to, helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), deuterium (D2), hydrogen (H2), and nitrogen (N2). In some embodiments, a gas mixture of one or more source gases and one or more of these inert carrier gases may be provided. Alternatively, the silicon-containing precursor and the inert carrier gas may be provided separately to the reaction chamber. In some embodiments, the flow rate ratio of the silicon-containing precursor to the carrier gas may be between about 1 / 1 and about 1 / 1,000, or between about 1 / 3 and about 1 / 300, or between about 1 / 100 and about 1 / 300. pressure

[0076] In some embodiments, the chamber pressure during deposition of the poly-Si sub-layer can be about 1 Torr-9 Torr, or about 2 Torr-6 Torr, or about 3 Torr-5 Torr. temperature

[0077] In some embodiments, the deposition temperature may be about 200-600°C, or about 250-450°C, or about 300-420°C, or about 350-400°C. Plasma parameters

[0078] In the case where the poly-Si sublayer is deposited by a plasma assisted deposition process (e.g., PECVD or PEALD), the plasma may be generated by applying radio frequency (RF) power to the process chamber. In some embodiments, the RF power has a high frequency (e.g., 13 MHz-40 MHz) and / or a low frequency (e.g., <1 MHz). In some embodiments, the high frequency RF power is provided at a frequency of about 13.56 MHz or about 27 MHz. The plasma power (i.e., RF power) may be about 50 watts (W) to 1,000 W, or 100 W to 500 W per wafer in process (e.g., at each station in a multi-station deposition chamber). Film thickness

[0079] The poly-Si sub-layer formed according to some embodiments herein has a thickness of about 5 nm-50 nm, or about 10 nm-20 nm. Composite nanocrystalline silicon layer formation

[0080] The composite nanocrystalline silicon layer can be formed by alternately depositing a-Si sublayers and poly-Si sublayers on a substrate. The substrate may include a front side and a back side. In some embodiments, the front side of the substrate is patterned. The patterned substrate may have "features", such as pillars, rods, grooves, through holes or contact holes, which may be characterized as narrow and / or concave openings, contractions within features, and one or more of high aspect ratios. Features may be formed in one or more of a material (e.g., a dielectric, conductive or semiconductor material deposited thereon) layer. In some embodiments, the front side of the substrate does not include any features. In some embodiments, the composite nanocrystalline silicon layer may be formed on the back side of the substrate.

[0081] Figure 1 A process flow diagram is presented according to some embodiments. The process flow diagram depicts some embodiments of forming a composite nanocrystalline silicon layer having a controlled hardness and / or a controlled surface roughness on the back side of a substrate. In one example, the process flow diagram describes some embodiments of forming a soft composite nanocrystalline silicon layer that prevents damage to a clamping surface of an electrostatic chuck (ESC).

[0082] In operation 110, a substrate may be received in a reaction chamber, the substrate including a front side and a back side. In some embodiments, the substrate may include one or more features formed on the front side of the substrate. The features may be patterned or unpatterned metal films, oxide films, nitride films, carbide films, etc. In some embodiments, features may not be formed on the front side of the substrate. In some embodiments, the back side of the substrate may not have any features. In some embodiments, the back side of the substrate may have a higher surface roughness than the front side of the side of the substrate.

[0083] In operation 120, one of a poly-Si sublayer or an a-Si sublayer may be deposited on the back side of the substrate by CVD, PECVD, ALD, PEALD, or epitaxial growth processing. The thickness of the poly-Si or a-Si sublayer on the back side of the substrate may be about 5nm-50nm, or about 10nm-20nm. The flow rate ratio of the silicon-containing precursor to one or more carrier gases may be related to the resulting film properties (e.g., the crystallinity of the layer). In some embodiments, a lower flow rate ratio of the silicon-containing precursor to one or more carrier gases may result in the formation of a poly-Si layer with columnar grain growth. A higher flow rate ratio may result in the formation of an a-Si layer with non-directional, random grain growth. For example, when the flow rate ratio of the silicon-containing precursor to one or more carrier gases (e.g., hydrogen) is low, the amount of hydrogen incorporated into the amorphous silicon will increase up to the solubility limit. Beyond the solubility limit, the reaction may be primarily based on hydrogen-hydrogen recombination, which may be highly exothermic, and energy may be released locally in a small area to favor the formation of silicon nuclei. Once nucleation has begun, crystal growth can follow.

[0084] After operation 120, one or more purge gases may be optionally provided to the reaction chamber to remove from the reaction chamber any excess precursor and / or other carrier gas in operation 120. Alternatively, after completing operation 120, operation 130 may be performed immediately after modifying the deposition parameters (e.g., flow rate, pressure, temperature, plasma power, plasma frequency, etc.) of operation 130 without purging the reaction chamber.

[0085] In operation 130, one of the a-Si sublayer or the poly-Si sublayer may be deposited on the poly-Si sublayer or the a-Si sublayer formed in operation 120 to form an alternating two-layer stack. For example, after depositing the poly-Si sublayer in operation 120, the a-Si sublayer may be deposited in operation 130. In another example, after depositing the a-Si sublayer in operation 120, the poly-Si sublayer may be deposited in operation 130. In operation 130, the a-Si sublayer or the poly-Si sublayer may be deposited by CVD, PECVD, ALD, PEALD, or epitaxial growth process. The thickness of the a-Si sublayer or the poly-Si sublayer formed in operation 130 may be about 5 nm-50 nm, or about 10 nm-20 nm.

[0086] Operations 120 and 130 may be repeated until the thickness of the composite nanocrystalline silicon layer reaches a predetermined thickness to form a composite nanocrystalline silicon layer at operation 140. In some embodiments, operations 120 and 130 may be repeated twice or 5-10 times to adjust the thickness of the composite nanocrystalline layer to be in the range of about 50nm-200nm, or about 70nm-150nm. In other embodiments, operations 120 and 130 may be repeated 5-20 times until the thickness of the composite nanocrystalline layer is in the range of about 100nm-700nm, or about 200nm-500nm, or about 300nm-400nm. In some embodiments, the composite nanocrystalline silicon layer may include the same number of a-Si sublayers and poly-Si sublayers. For example, the first layer directly deposited on the back side of the substrate may be a poly-Si sublayer, and the uppermost layer of the composite nanocrystalline silicon layer may be an a-Si sublayer. In other embodiments, the composite nanocrystalline silicon layer may include different numbers of a-Si sublayers and poly-Si sublayers.

[0087] In operations 120 and 130, deposition parameters for the a-Si sublayer and the poly-Si sublayer may be configured to control the thickness of each of the plurality of a-Si sublayers and the plurality of poly-Si sublayers in the composite nanocrystalline silicon layer. In one example, in the composite nanocrystalline silicon layer, the thickness of each of the plurality of a-Si sublayers may be the same or substantially the same. In another example, in the composite nanocrystalline silicon layer, the thickness of each of the plurality of poly-Si sublayers may be the same or substantially the same.

[0088] In some embodiments, the process can be adjusted to adjust the hardness of the composite nanocrystalline silicon layer. For example, the hardness of the resulting composite nanocrystalline silicon layer can be adjusted to a value that is up to 40% lower than the hardness of the PECVD-formed a-Si sublayer or the hardness of the poly-Si sublayer. The composite nanocrystalline silicon layer can be deposited under conditions that produce a relatively high surface roughness (compared to the a-Si or crystalline silicon substrate).

[0089] According to some embodiments, Figure 2A-2E Exemplary cross-sections of substrate 200 are shown after different operations. Figure 2A A cross-section of substrate 200 is shown after being received into a reaction chamber for backside deposition. According to some embodiments, one or more layers may have been formed on the front side 220 of substrate 200 prior to operation. One or more layers may include features, such as columns, rods, grooves, through holes, or contact holes, which may be characterized as one or more of narrow and / or recessed openings, constrictions within features, and high aspect ratios. Features may be formed in one or more of a material (e.g., a dielectric, conductive, or semiconductor material deposited thereon) layer. According to some embodiments, no layers may be deposited on the back side 230 of substrate 210 prior to depositing an a-Si sublayer or a poly-Si sublayer.

[0090] Figure 2B 2 shows substrate 210 after depositing a poly-Si sublayer 240 on the back side 230 of substrate 210. Poly-Si sublayer 240 may be deposited on the substrate with columnar grain growth extending in a direction perpendicular to the substrate. Figure 2B The poly-Si sublayer 240 is shown formed as the first layer deposited directly on the backside 230 of the substrate, but in other embodiments, the a-Si sublayer may be formed as the first layer on the backside of the substrate 210 .

[0091] Figure 2C Substrate 210 is shown after depositing a-Si sublayer 250 on poly-Si sublayer 240 to form alternating layers of poly-Si sublayer 240 and a-Si sublayer 250 on substrate 200. Crystallites in a-Si sublayer 250 may be amorphous and may not show any consistent directional growth on poly-Si sublayer 240. Columnar grain growth of poly-Si sublayer 240 may be at least partially prevented by a-Si sublayer 250. a-Si sublayer 250 may also provide reduced surface roughness.

[0092] Figure 2D 2 shows substrate 200 after depositing another poly-Si sublayer 260 on a-Si sublayer 250. Columnar grain growth of poly-Si sublayer 260 may restart on a-Si sublayer 250 without any directional grain growth. In some embodiments, columnar grains grown in poly-Si sublayer 260 may not be as significant as columnar grain growth in poly-Si sublayer 240. Figure 2EShown is a substrate 200 including alternating layers of a poly-Si sublayer 240, an a-Si sublayer 250, and a poly-Si sublayer 260. An a-Si sublayer 270 may be formed on the poly-Si sublayer 260. Optionally, the alternating deposition of the poly-Si sublayer and the a-Si sublayer may be repeated until a desired thickness of the composite nanocrystalline silicon layer is obtained to form the composite nanocrystalline silicon layer. Properties of composite nanocrystalline silicon layer

[0093] The composite nanocrystalline silicon layer produced using the cyclic treatment as described herein may have one or more interesting properties. For example, the composite nanocrystalline silicon layer may have a relatively low hardness and / or a specially adjusted roughness. As described above, the hardness of the composite nanocrystalline silicon layer may be lower than the hardness of the a-Si sublayer produced using only the a-Si sublayer treatment described herein, or the hardness of the poly-Si sublayer produced using only the poly-Si sublayer treatment described herein. hardness The hardness of the composite nanocrystalline silicon layer can be determined using any one of various techniques. Unless otherwise stated, the hardness values ​​presented herein can be determined by the nanoindentation technique (e.g., nanomechanical testing system, Hysitron, Inc, USA) performed on a composite nanocrystalline silicon film having a thickness of about 650 nm. Forces of 1050 μN, 1200 μN, and 1250 μN are applied to the tip of the indenter (Diamond Berkovich indenter tip), while measuring the displacement of the tip in the composite nanocrystalline silicon film sample. The load-displacement curve obtained from each load can be determined by applying the Oliver and Pharr method and a pre-calibrated indenter tip area function and a predetermined machine force displacement ratio (machine compliance) value (i.e., nanohardness). In certain embodiments, the hardness of the composite nanocrystalline silicon layer is about 10 GPa or less, or about 9 GPa or less, or about 8 GPa or less. In certain embodiments, the hardness (or the average normalized hardness of multiple samples) is less than about 0.80, or less than about 0.75, or less than about 0.65 relative to a silicon substrate having a hardness value of 1.0.

[0094] The hardness of the composite nanocrystalline silicon layer is lower than any one of the a-Si sublayer or poly-Si sublayer grown by PECVD or PEALD as described in the example section. Although not limited to any mechanism or theory, the following is provided to explain why the composite nanocrystalline silicon layer can have a lower hardness than any one of the individual component layers that exist alone. When the poly-Si crystallite growth is interrupted by depositing the a-Si layer, the poly-Si crystallites grown on the a-Si layer are not grown in a consistent columnar form. Therefore, the poly-Si crystallites grow in a more random direction, resulting in a layer presenting a lower hardness than the poly-Si sublayer deposited in a non-cyclic manner. In some embodiments, the hardness of the composite nanocrystalline silicon layer can be adjusted relative to the thickness ratio of the a-Si sublayer to the poly-Si sublayer in the composite nanocrystalline silicon layer. For example, the thickness ratio of the a-Si sublayer to the poly-Si sublayer can be about 0.2 to 3.0, or about 0.3 to 2.5, or about 0.5 to 2.0. Roughness

[0095] The surface roughness of the composite nanocrystalline silicon layer can be measured by an in-situ scanning probe microscope (SPM) image obtained on an area of ​​3 μm×3 μm. The surface roughness can be determined in units of Ra, which is the arithmetic mean of the absolute values ​​of the profile height deviations from the average line recorded within the evaluation length. In certain embodiments, the Ra of the composite nanocrystalline silicon layer is about 0.2nm-10nm, or about 1nm-4nm. Typically, the Ra of the a-Si sublayer is about 0.2nm-3nm. Typically, the Ra of the poly-Si sublayer is about 0.2nm-10nm. Ra can be adjusted by the thickness ratio of the a-Si sublayer to the poly-Si sublayer. For example, when the thickness ratio of the a-Si sublayer to the poly-Si sublayer increases, a low Ra composite nanocrystalline silicon layer can be obtained, and for a composite nanocrystalline silicon layer with a low thickness ratio, Ra can be high. thickness

[0096] Depending on the application, the composite nanocrystalline silicon layer can be about 1nm-1000nm thick, or about 20nm-800nm ​​thick, or about 100nm-700nm thick, or about 200nm-500nm thick. According to some embodiments herein, in order to protect the workbench surface of the ESC, the composite nanocrystalline silicon layer can have a thickness of about 100nm-700nm, or about 200nm-500nm on the back side of the substrate by, for example, PECVD or PEALD. In certain embodiments, a composite nanocrystalline silicon layer with an appropriate thickness can be formed by repeating the deposition of the a-Si sublayer and the poly-Si sublayer 5 to 20 times. Grain size

[0097] The composite nanocrystalline silicon layer may have an average grain size of about 1 nm-100 nm, or about 2 nm-80 nm, or about 3 nm-60 nm, or about 4 nm-40 nm, or about 5 nm-20 nm. The grain size may be measured by low angle X-ray diffraction (XRD; Bruker Semiconductor Division, USA). Chemical composition

[0098] In certain embodiments, in addition to silicon (Si), the composite nanocrystalline silicon layer may also include hydrogen (H), nitrogen (N), and / or oxygen (O). H, N, and O may come from one or more carrier gases in the deposition of a-Si sublayers or poly-Si sublayers. In certain embodiments, the concentration of silicon is at least about 50 mass %. Qualitative analysis of the composite nanocrystalline silicon layer may be performed by secondary ion mass spectrometry (SIMS; EAG Laboratories, USA). application

[0099] Deposition method and composite nanocrystalline silicon layer described herein can be used in many applications. Some of these applications use composite nanocrystalline silicon layer as the backside layer on the substrate used in semiconductor device manufacturing. As explained, such layer can compensate for the warpage produced by the internal stress on the substrate front side. In some cases, the semiconductor device manufactured using the backside layer is a logic device, and in some cases, the device is a memory device, such as NAND and DRAM memory. The backside layer can be deposited on a wafer subjected to various downstream processes (including, but not limited to, photolithography, etching, deposition and polishing). In some embodiments, the semiconductor device has a critical dimension of approximately 50nm or less, approximately 20nm or less, or approximately 10nm or less.

[0100] In certain embodiments, the composite nanocrystalline silicon layer as a backside protective layer is used in UV or EUV lithography. Using such a composite nanocrystalline silicon layer as a backside protective layer can significantly increase the service life of the lithography workbench in semiconductor device manufacturing, thereby bringing significant cost savings in the process of adopting EUV patterning.

[0101] Other applications and processes of substrates having a composite nanocrystalline silicon backside layer include all applications where a warp-compensating backside layer can be used. This includes etching processes, polishing applications, and deposition processes.

[0102] As noted, the composite nanocrystalline silicon layer has a carefully controlled roughness. In some cases, it has been demonstrated that a higher backside roughness improves overlay. For some applications, the composite nanocrystalline silicon layer may have a roughness of about 0.2 nm-10 nm, or about 1 nm-4 nm.

[0103] Although most of the discussion focuses on the use of composite nanocrystalline silicon as the application of the backside layer, the composite nanocrystalline silicon layer can also be used as the front side material. For example, the composite nanocrystalline silicon described in this article can be used in transistor gates, contacts, virtual structures removed by etching subsequently, etc. In other embodiments, the MEMS (micro-electromechanical system) with the feature (for example, cantilever) of silicon that needs to have specific mechanical and / or electrical properties can be produced by the method in this article. The poly-Si MEMS structure may need elastic modulus and hardness within the scope disclosed in this article.

[0104] The disclosed deposition methods and composite nanocrystalline silicon layers are not limited to the applications listed herein.The composite nanocrystalline silicon layers described herein may be used in any application where film hardness adjustment may be useful.

[0105] Although the discussion to this point has focused on a composite nanocrystalline silicon layer as a compensating warp layer that provides protection from damage to substrate support components in downstream processing, aspects of the present disclosure are suitable for other materials that can provide a similar combination of advantages; that is, warp compensation and protection of substrate support components. In some embodiments, the backside compensating warp layer (which can be made of any material) has a roughness (Ra) of about 1nm-4nm. It should be noted that the roughness is on the side of the layer that will be engaged with the chuck or other substrate support component (e.g., a lithography wafer workbench). In some other embodiments, the backside compensating warp layer has a hardness of about 9GPa or less. Examples of materials that can provide a backside layer with such properties include layers containing various metals and metal compounds (e.g., metal oxides, metal nitrides, metal carbides, etc.).

[0106] The substrate with the backside layer of the roughness of about 1nm-4nm (optionally, the hardness of about 9GPa or less) can be used in many different applications involving the clamping, clamping or other support of the substrate in the downstream processing. As mentioned, such a process can be a deposition process, an etching process, a polishing process, a photolithography process, etc. An interesting downstream process is UV or EUV lithography. Such a process involves a substrate support including alignment marks. Typically, the substrate is slightly misaligned with the lithography table (sometimes referred to as a lithography wafer table or just a wafer table), and such misalignment is referred to as an overlay error. Typically, during the service life of the lithography table (when it supports thousands of substrates), the overlay error will degrade (degrade), for example from about 0.1nm to 3nm-4nm. It has been found that a substrate with a backside layer having a surface roughness value of about 1nm-4nm can offset this overlay error degradation. For example, performing UV or EUV lithography on a substrate having a warp-compensating backside layer with a roughness value of about 1 nm-4 nm preserves the performance of the associated lithography workstation, in particular it reduces overlay error degradation over time. It is believed that protrusions provided on the substrate bonding surface of the UV or EUV lithography workstation wear over time. A substrate having a warp-compensating layer with the described surface roughness can counteract the increased overlay error that would otherwise occur due to the wear of the protrusions.

[0107] In general, the integrated process may include the following operations: (a) forming a warp-compensating backside layer on a substrate, wherein the backside layer has a surface roughness of about 1 nm-4 nm, (b) attaching the substrate to a substrate support, and (c) performing a manufacturing operation on the substrate while the substrate is attached to the substrate support. In some embodiments, the warp-compensating layer has a hardness of about 10 GPa or less. In some embodiments, the substrate support is a lithography table for a UV or EUV lithography system. Device

[0108] Figure 3A 302 is a block diagram illustrating a substrate processing system 332 for performing processing on a wafer 302 according to some embodiments. As shown, the substrate processing system may include a chamber 334. The central column may be configured to support a pedestal on which the wafer 302 is being processed, for example, a film is being formed on a top surface of the wafer 302 or on a backside of the wafer 302. According to some embodiments disclosed herein, the pedestal may be referred to as a showerhead pedestal ("ShoPed") 306. A showerhead 336 may be disposed above the showerhead 306.

[0109] In some embodiments, the showerhead 336 can be electrically coupled to a power supply 338 via a matching network 340 for powering the plasma. The power supply 338 can be controlled by a control module 342, for example, a controller. In some embodiments, power can be provided to the showerhead 306 instead of the showerhead 336. The control module 342 can be configured to operate the substrate processing system 332 by executing process inputs and controls for a particular process recipe. Depending on whether the top surface of the wafer 302 is receiving a deposited film or whether the bottom surface of the wafer 302 is receiving a deposited film, the controller module 342 can set a number of operational inputs for the process recipe, such as power levels, timing parameters, process gases, mechanical movement of the wafer 302, and / or the height of the wafer 302 relative to the showerhead 306.

[0110] In some embodiments, the plasma energy can be controlled by controlling one or more of the chamber pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power supply 338 and the matching network 340 can be operated at any suitable power to form a plasma with a desired free radical species composition. An example of a suitable RF power range can be about 50 watts (W)-1,000W or 100W-500W per station. Similarly, the RF power supply 338 can provide RF power of any suitable frequency. In some embodiments, the RF power supply 338 can be configured to control high-frequency and low-frequency RF power sources independently of each other. Exemplary low-frequency RF frequencies can include, but are not limited to, frequencies less than 1MHz, or between 50kHz and 600kHz. Exemplary high-frequency RF frequencies can include, but are not limited to, frequencies between 1.8MHz and 2.45GHz. In some embodiments, a high frequency of 13.56MHz or about 27MHz can be provided. It should be understood that any suitable parameter can be adjusted intermittently or continuously to provide plasma energy for surface reactions. In one non-limiting example, the plasma power may be intermittently pulsed to reduce ion bombardment of the substrate surface relative to a continuously powered plasma.

[0111] In some embodiments, the center column may also include lift pins that are controlled by a lift pin controller. These lift pins may be used to lift the wafer 302 from the nozzle holder 306 to allow the end effector (not shown) to pick up the wafer and lower the wafer 302 after the wafer 302 is placed by the end effector. The end effector may also place the wafer 302 over the spacer 344. As will be described below, the spacer 344 may be sized to provide a controlled separation of the wafer 302 between the top surface of the nozzle head 336 (facing the wafer) and the top surface of the nozzle holder 306 (facing the wafer).

[0112] In some embodiments, the substrate processing system 332 may further include a first gas supply connected to a first gas manifold 346 of a first gas source 348 (e.g., gas chemicals and / or inert gases supplied from a facility). For example, the gas chemical supply source may include one or more silicon-containing precursors (described herein) and one or more carrier gases. Examples of carrier gases include, but are not limited to, helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), deuterium (D2), hydrogen (H2), and nitrogen (N2). Depending on the process being performed above the top surface of the wafer 302, the control module 342 may control the delivery of the first gas source 348 through the first gas manifold 346. The selected gas may then flow into the showerhead 336 and be distributed in the volume of space defined between the surface of the showerhead 336 facing the wafer 302 when the wafer is placed above the susceptor.

[0113] In some embodiments, the substrate processing system 332 may further include a second gas supply, which includes a second gas manifold 350 connected to a second gas source 352 (e.g., gas chemicals and / or inert gases supplied from a facility). For example, the gas chemical supply may include one or more silicon-containing precursors (described herein) and one or more carrier gases. Examples of carrier gases include, but are not limited to, helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), deuterium (D2), hydrogen (H2), and nitrogen (N2). Depending on the process being performed above the bottom surface of the wafer 302, the control module 342 may control the delivery of the second gas source 352 through the second gas manifold 350. The selected gas may then flow into the nozzle seat 306 and be distributed in the spatial volume defined between the wafer 302 and the nozzle seat 306 surface facing the back side or underside (back side) of the wafer 302 when the wafer is placed above the spacer 344. Spacers 344 may provide separation that optimizes deposition on the back side of wafer 302 and reduces deposition above the top surface of wafer 302. In some embodiments, when deposition is targeted to the back side of wafer 302, an inert gas may flow over the top surface of wafer 302 via showerhead 336, which may push reactant gases away from the top surface and enable reactant gases provided from showerhead 306 to be directed to the back side of wafer 302.

[0114] Further, the gases may be premixed or not. Appropriate valves and mass flow control mechanisms may be employed to ensure that the correct gases are delivered during the deposition and plasma processing phases of the process. The process gases may exit the chamber 334 via an outlet. A vacuum pump (e.g., a single or two-stage mechanical dry pump and / or a turbomolecular pump) may pump the process gases out and maintain an appropriate low pressure within the reactor through a closed loop flow restriction device (e.g., a throttle valve or a pendulum valve).

[0115] In some embodiments, the carrier ring 354 may surround an outer region of the showerhead 306. When the top surface of the wafer 302 is being processed, for example, when material is being deposited thereon, the carrier ring 354 may be configured to be located above a carrier ring support area that is stepped downward from a wafer support area in the center of the pedestal showerhead 306. The top surface of the carrier ring 354 may be substantially coplanar with the top surface of the wafer 302. The carrier ring 354 may include an outer edge side (e.g., an outer radius) of its disk structure and a wafer edge side (e.g., an inner radius) of its disk structure that is closest to where the wafer 302 is located. The wafer edge side of the carrier ring 354 may also include a plurality of contact support structures or "tabs" that may be configured to elevate the wafer 302 when the carrier ring 354 is held by the spacer 344. The carrier ring 354 may include a plurality of tabs, the number of which is selected from a range that supports the wafer 302 during processing. Additional details regarding the tab embodiments are as follows.

[0116] Figure 3B is a block diagram illustrating another substrate handling system 332 for performing processing on a wafer 302 according to some embodiments. In some embodiments, a spoke fork 356 may be used to raise and hold a carry ring 354 at its processing height, for example, to allow deposition on the back side of the wafer 302. Thus, the carry ring 354 may be raised along with the wafer 302. In some implementations, the carry ring 354 may be rotated to another station, for example in a multi-station system.

[0117] Broadly, embodiments disclosed herein are systems for depositing PECVD films on selected sides (front and / or back) of a wafer by dynamic control. Some embodiments may include dual gas flow electrodes for defining a capacitively coupled PECVD system. The system may include a gas flow showerhead 336 and a showerhead 36. In some embodiments, the gas flow base (i.e., showerhead) is a combination of a showerhead and a pedestal that performs deposition on the back side of the wafer. The electrode geometry combines features of the showerhead (e.g., gas mixing plenum, holes, hole patterns, anti-gas spray baffles) and features of the pedestal. Examples of pedestal features include embedded controlled heaters, wafer lifting mechanisms, the ability to hold a plasma suppression ring, and movability. This enables wafer transfer and gas handling with or without RF power from the pedestal.

[0118] In some embodiments, the system may have a wafer lift mechanism that tightly controls the parallelism of the substrate relative to the electrodes. In one example, this can be achieved by setting the lift mechanism (e.g., a spindle or lift pin mechanism) parallel to the two electrodes and controlling manufacturing tolerances. In another example, the lift can be achieved by raising the wafer lift component. This option may not allow for dynamic control of the side where deposition is performed.

[0119] In some configurations, the lift mechanism may allow for dynamic control of the substrate position during processing (before plasma, during plasma, after plasma) to control the side of deposition, the profile of deposition, and the properties of the deposited film. The system may further allow for selective activation / deactivation of the side of reactant flow. One side may flow reactants and the other side may flow inert gas to suppress deposition and plasma.

[0120] In some embodiments, the gap between the side of the wafer where plasma / deposition is not desired can be strictly controlled. The distance can be controlled to suppress plasma. If the distance is not controlled, the wafer may be susceptible to plasma damage. For example, the system can allow a minimum gap of about 2 mm to about 0.5 mm, and in another embodiment about 1 mm to about 0.05 mm (limited by wafer warpage), and such a gap can be controlled. The gap can be controlled according to processing conditions.

[0121] In some embodiments, the gas flow base (i.e., nozzle base) can achieve, but is not limited to: (a) thermal stabilization of the wafer to the processing temperature before processing; (b) selective design of the hole pattern on the nozzle base to selectively deposit films on different areas of the back side of the wafer; (c) replaceable rings can be attached to achieve appropriate plasma confinement and hole pattern; (d) stable wafer transfer mechanism within the chamber for transferring the wafer out to another chamber or a wafer boat - such as lift pins, RF coupling features, minimum contact arrays; (e) implementation of gas mixing features, such as internal gas chambers, baffles, and manifold pipeline openings; and (f) providing compartments in the gas flow base (i.e., nozzle base) to enable selective gas flow to different areas of the back side of the wafer, and control the flow rate through flow controllers and / or multiple gas chambers.

[0122] In another embodiment, dynamic gap control using a wafer lift mechanism is achieved: (a) controlling the distance from the deposition or reactant flow electrode to the side or middle of the wafer where deposition is desired so that deposition can be performed on both sides; and (b) a lift mechanism for dynamically controlling the distance during processing (before plasma, during plasma, after plasma) to control the side of deposition, deposition profile, and deposited film properties. In another embodiment, for deposition modes used to deposit on the back side of the wafer, film edge exclusion control is highly desirable to avoid overlay issues associated with lithography. The lift mechanism used in this system is accomplished by a carrier ring 354 that has a design feature for shielding deposition on the edge. This specifies edge exclusion control through the design and shape of the carrier ring.

[0123] Figure 4Schematic diagram of a processing system suitable for performing deposition processing according to an embodiment. System 400 includes a transport module 403. The transport module 403 provides a clean, pressurized environment to minimize the risk of contamination of the substrate being processed when it is moved between the various reactor modules. Mounted on the transport module 403 is a multi-station reactor 409 capable of performing ALD, processing, and CVD according to various embodiments. The multi-station reactor 409 may include a plurality of stations 411, 413, 415, and 417, which may perform operations sequentially according to the disclosed embodiments. For example, the multi-station reactor 409 may be configured such that station 411 performs backside deposition of a poly-Si sublayer by PECVD or PEALD, station 413 performs backside deposition of an a-Si sublayer by PECVD or PEALD, station 415 performs first frontside deposition of a silicon-based film by PECVD or PEALD, and station 417 may perform second frontside deposition of a silicon-based film by PECVD or PEALD. The station may include a heated pedestal or substrate support, one or more gas inlets, or a showerhead or dispersion plate.

[0124] return Figure 4 , one or more single-station or multi-station modules 407 capable of performing plasma or chemical (non-plasma) pre-cleaning, other deposition operations, or etching operations may also be mounted on the transfer module 403. The modules may also be used for various processes, for example, to prepare substrates for deposition processes. The system 400 also includes one or more wafer source modules 401, where wafers are stored before and after processing. An atmospheric robot (not shown) in the atmospheric transfer chamber 419 may first move the wafers from the source module 501 to the load lock 421. The wafer transfer equipment (typically a robot arm unit) in the transfer module 503 may move the wafers from the load lock 421 to the modules mounted on the transfer module 403 and between these modules.

[0125] In various embodiments, a system controller 442 is used to control the process conditions during the deposition process. The controller 442 will typically include one or more memory devices and one or more processors. The processor may include a CPU or computer, analog and / or digital input / output connections, a stepper motor controller board, etc.

[0126] The controller 442 can control all activities of the deposition apparatus. The system controller 442 runs system control software, which includes instruction sets for controlling timing, gas mixing, chamber pressure, chamber temperature, wafer temperature, radio frequency (RF) power level, wafer chuck or pedestal position, and other parameters of a particular process. In some embodiments, other computer programs stored on a memory device associated with the controller 442 can be used. For example, the system controller 442 can be designed to alternately deposit a-Si sublayers and poly-Si sublayers by changing the process parameters for a-Si deposition and poly-Si deposition (e.g., flow rate and duration of silicon-containing precursors and carrier gases, chamber temperature, substrate temperature, chamber pressure, RF frequency, and RF power).

[0127] Typically, there will be a user interface associated with the controller 442. The user interface may include a display screen, a graphical software display of the device and / or processing conditions, and a user input device such as a pointing device, keyboard, touch screen, microphone, or the like.

[0128] The system control logic may be configured in any suitable manner. In general, the logic may be designed or configured in hardware and / or software. The instructions for controlling the drive circuit may be hard-coded or provided as software. The instructions may be provided by "programming". Such programming is understood to include any form of logic including hard-coded logic in digital signal processors, application specific integrated circuits, and other devices having specific algorithms implemented as hardware. Programming is also understood to include software or firmware instructions that can be executed on a general purpose processor. The system control software may be encoded in any suitable computer readable programming language.

[0129] The computer program code for controlling the germanium-containing reducing agent pulses, hydrogen gas flow, and tungsten-containing precursor pulses and other processes in the process sequence can be written in any conventional computer-readable programming language: for example, assembly language, C, C++, Pascal, Fortran, or others. The compiled object code or script is executed by the processor to perform the tasks identified in the program. As also indicated, the program code can be hard-coded.

[0130] Controller parameters relate to process conditions such as, for example, process gas composition and flow rate, temperature, pressure, cooling gas pressure, substrate temperature and chamber wall temperature. These parameters are provided to the user in the form of a recipe and can be input using a user interface.

[0131] Signals used to monitor the process may be provided through analog and / or digital input connections of system controller 442. Signals used to control the process are output through analog and digital output connections of device 400.

[0132] The system software may be designed or configured in different ways. For example, multiple chamber component subroutines or control targets may be written to control the operation of chamber components required to perform deposition processes according to the disclosed embodiments. Examples of programs or program segments for this purpose include substrate positioning code, process gas control code, pressure control code, and heater control code. For example, the system software may be designed such that the program or program segment includes performing alternating deposition of a-Si sublayers and poly-Si sublayers by changing the flow rate of silicon-containing precursors and carrier gases used for a-Si deposition and poly-Si deposition, as well as the duration, temperature, chamber pressure, RF frequency, and RF power.

[0133] In some embodiments, the system controller 442 is part of a system, which can be part of the above-mentioned embodiments. Such a system includes a semiconductor processing device, which includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronic devices to control the operation of these systems before, during, or after the processing of semiconductor wafers or substrates. The electronic device can be referred to as a "controller" that can control various components or sub-parts of one or more systems. Depending on the processing requirements and / or the type of system, the system controller 442 can be programmed to control any of the processes disclosed in the present invention, including controlling the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings in some systems, RF matching circuit settings, frequency settings, flow rate settings, plasma pulse frequency settings, fluid delivery settings, position and operation settings, wafer entry and exit tools and other transport tools and / or delivery of load locks connected to a specific system or interfaced with the system.

[0134] Broadly speaking, a controller can be defined as an electronic device with various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, can perform cleaning operations, can perform endpoint measurements, etc. The integrated circuit may include a chip storing program instructions in the form of firmware, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions delivered to a controller or system in the form of various different settings (or program files), and different settings (or program files) define operating parameters for specific processing on or for semiconductor wafers. In some embodiments, the operating parameters may be a part of a recipe defined by a processing engineer to complete one or more processing steps in the manufacturing process of one or more (kinds) layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or bare chips of a wafer.

[0135] In some embodiments, the system controller 442 can be a part of or coupled to a computer that is integrated, coupled, or connected to the system or a combination thereof through a network. For example, the system controller 442 can be in the "cloud" or all or part of a wafer factory (fab) main computer system, which can allow remote access to wafer processing. The computer can enable remote access to the system to monitor the current progress of the manufacturing operation, check the history of past manufacturing operations, check the trends or performance standards of multiple manufacturing operations, change the parameters of the current processing, set the processing steps to follow the current processing or start a new processing. In some embodiments, a remote computer (e.g., a server) can provide a processing recipe to the system through a network, which can include a local network or the Internet. The remote computer can include a user interface that allows input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, the controller receives instructions in the form of data, which specify the parameters of each processing step to be performed during one or more operations. It should be understood that these parameters can be for the type of processing to be performed and the type of tool, and the controller is configured to connect or control the tool type. Thus, as described above, the controller may be distributed, for example, by including one or more discrete controllers that are networked together and work toward a common goal (e.g., the processing and control described herein). An example of a distributed controller for these purposes would be one or more integrated circuits in the room that communicate with one or more remote integrated circuits (e.g., at the platform level or as part of a remote computer) that combine to control the processing in the room.

[0136] Exemplary systems may include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, chamfer edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, CVD chambers or modules, ALD chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used in the preparation and / or manufacture of semiconductor wafers.

[0137] As described above, depending on one or more processing steps to be performed by the tool, the controller can communicate with one or more other tool circuits or modules, other tool components, combination tools, other tool interfaces, adjacent tools, adjacent tools, tools located throughout the factory, a host computer, another controller, or tools used in material handling to move containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

[0138] The system controller 442 may include different programs. The substrate positioning program may include program code for controlling chamber components that are used to load the substrate onto a pedestal or chuck and control the spacing between the substrate and other components of the chamber, such as a gas inlet and / or a target. The process gas control program may include code for controlling gas composition, flow rate, pulse time, and optionally for flowing gas into the chamber to stabilize the pressure in the chamber before deposition. The pressure control program may include code for controlling the pressure in the chamber by adjusting, for example, a throttle valve in an exhaust system in the chamber. The heater control program may include code for controlling the current of a heating unit for heating the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas, such as helium, to a wafer chuck.

[0139] Examples of chamber sensors that can be monitored during deposition include mass flow controllers, pressure sensors such as manometers, and thermocouples located in the pedestal or chuck. Appropriately programmed feedback and control algorithms can be used with data from these sensors to maintain desired processing conditions.

[0140] The foregoing describes implementations of the present invention as implemented in a single-chamber or multi-chamber semiconductor processing tool. The apparatus and processes described herein can be used in conjunction with lithography patterning tools or processes, for example, to prepare or manufacture semiconductor devices, displays, LEDs, photovoltaic panels, etc. Typically, although not necessarily, these tools / processes will be used or operated together in a common manufacturing facility. Photolithographic patterning of films typically includes some or all of the following steps, each of which enables multiple available tools: (1) coating a workpiece, i.e., a substrate, with photoresist using a spin coating or spray coating tool; (2) curing the photoresist using a hot plate or oven or a UV curing tool; (3) exposing the photoresist to visible light or UV light or X-rays using a tool such as a wafer stepper; (4) developing the resist to selectively remove the resist and thereby pattern it using a tool such as a wet cleaning station; (5) transferring the resist pattern to an underlying film or workpiece by using a dry or plasma assisted etching tool; and (6) removing the resist using a tool such as a radio frequency or microwave plasma resist stripper. Example

[0141] Figure 5 A comparison of normalized hardness of four examples is shown, including different silicon films and silicon substrates deposited by PECVD. The hardness was measured under the same measurement conditions. Example 1 is a hydrogenated amorphous silicon (a-Si:H) sublayer prepared by PECVD on a substrate. Example 2 is a composite nanocrystalline silicon layer prepared on a substrate according to some embodiments. Example 3 is a poly-Si sublayer prepared by PECVD on a substrate. Example 4 is a silicon substrate. The hardness data measured for Examples 1-3 are normalized to the hardness measured for Example 4. For normalization, the hardness of Example 4 (silicon substrate) is set to 1.0.

[0142] The composite nanocrystalline silicon layer in Example 2 has the lowest average normalized hardness, about 0.59. The average normalized hardness of the poly-Si sublayer (Example 3) is about 0.73, which is more than 22% higher than the average normalized hardness of the composite nanocrystalline silicon layer (Example 2). The a-Si:H sublayer (Example 1) has an average normalized hardness of about 0.89, which is about 49% higher than the composite nanocrystalline silicon layer (Example 2). As described above, the average normalized hardness of the silicon substrate (Example 4) is set to 1.0. The hardness is measured using the nanoindentation technique described in this article. In all the examples tested, the composite nanocrystalline silicon layer showed the lowest hardness value, which corresponds to the softest material tested. Using a composite nanocrystalline silicon layer as the back side layer of the substrate can reduce or eliminate damage to the workbench surface caused by contact with the back side of the substrate, thereby helping to extend the service life of the ESC. in conclusion

[0143] Although the above embodiments have been described in some detail for the purpose of clear understanding, it is apparent that certain variations and modifications may be implemented within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and devices of the embodiments of the present invention. Therefore, the embodiments of the present invention should be considered illustrative rather than restrictive, and these embodiments are not limited to the details given herein.

Claims

1. A method for forming a composite nanocrystalline silicon layer, the method comprising: (a) depositing a polysilicon sublayer directly or indirectly on a substrate; (b) depositing an amorphous silicon sublayer on the polycrystalline silicon sublayer; as well as (c) Repeat (a) and (b) one or more times. 2 . The method of claim 1 , wherein the polysilicon sublayer and the amorphous silicon sublayer are deposited on a back side of the substrate. 3 . The method of claim 1 , wherein a thickness ratio of the polysilicon sublayer to the amorphous silicon sublayer is about 0.2 to 3.

0. The method of claim 1 , wherein the amorphous silicon sublayer has a thickness of about 5 nm to 50 nm. The method of claim 1 , wherein the polysilicon sublayer has a thickness of about 5 nm to 50 nm. The method of claim 1 , wherein the composite nanocrystalline silicon layer has a hardness of about 9 GPa or less. 7 . The method of claim 1 , wherein the composite nanocrystalline silicon layer has a surface roughness of about 0.2 nm to about 10 nm.

8. An apparatus comprising: Reaction chamber; a susceptor for supporting a substrate in the reaction chamber during a deposition process, the substrate comprising a front side and a back side; a gas supply configured to deliver a silicon-containing precursor to the substrate while the substrate is held by the susceptor; a radio frequency (RF) power supply for providing power to the showerhead to generate plasma; as well as A controller configured to cause: (a) directly or indirectly depositing a polysilicon sublayer on the substrate; (b) depositing an amorphous silicon sublayer on the polycrystalline silicon sublayer; and (c) Repeat (a) and (b) one or more times.

9. The apparatus of claim 8, wherein the gas supply is fluidly coupled to the pedestal to deliver the silicon-containing precursor to the backside of the substrate.

10. The apparatus of claim 8, wherein the pedestal is configured to cause the polysilicon sublayer or the amorphous silicon sublayer to be deposited on the back side of the substrate.

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