Semiconductor structure

Abstract

The invention provides a semiconductor structure (10). The semiconductor structure (10) comprises a silicon substrate (12) in a [100] orientation; a scandium oxide layer (14) on the substrate (12) in the [111] orientation; and a scandium-rare earth-oxide layer (16) on the scandium oxide layer (14). The scandium-rare earth-oxide layer can have a graded composition to transition the lattice constant to match a subsequent layer, such as an indium nitride layer having a very high electron drift velocity. InN over Si (100) provides transistors, photons, and passive electronics that operate in the terahertz frequency range.

Description

[0001] A semiconductor structure particularly but not exclusively useful for providing a template for high frequency electronic devices.

[0002] Many applications require a high quality lll-N layer on which one or more device layers are grown or placed. For example, a high frequency switch (e.g., a metal oxide semiconductor field effect transistor (MOSFET) or a high electron mobility transistor (HEMT)) can be epitaxially grown on the lll-N layer to obtain suitable characteristics. There are usually multiple layers on the substrate below the lll-N layer.

[0003] For epitaxial growth, the crystal structure of a layer must match or be compatible with the layer below it. The crystal alignment of each layer is determined by the lowest energy state of the material and the crystal orientation of the layer below it. Thus, for homoepitaxy (growth of the same material as the previous layer), the crystal orientation will be the same, and for most heteroepitaxy (growth of a different material than the previous layer), the crystal orientation will also be the same. In cases where the crystal structure of subsequent layers is different, such as hexagonal form InN grown on cubic silicon, then the subsequent layers grow in compatible crystal orientations. Thus, InN grows in a polar

[0001] orientation on Si(111), but grows in a semipolar [11-20] orientation on a previous layer of (110) rare earth oxide.

[0004] It has been previously determined that the crystals of crystalline rare earth oxides grow epitaxially with a different orientation than the layer below them. Applicants refer to this as “epi Twist TM ”. This can be used to grow subsequent layers with different crystal orientations from the substrate or previous layer, provided that the lattice constants are approximately matched or that the lattice constant of the upper layer is an integer multiple of that of the lower layer.

[0005] Wurtzite (c-direction) llll-N materials such as InN

[0001] are preferred industrially for electronic and photonic devices. For electronic devices, the polar properties of this form of InN are necessary for the manufacture of high electron mobility transistors (HEMTs). It is also preferred to use Si (100) substrates because they are widely available and therefore inexpensive. Si (100) substrates are also commercially available with larger diameters (up to 300 mm) compared to other oriented silicon (such as Si (111)). In addition, Si (100) provides the opportunity for photonic devices to be integrated with electronic devices that are typically produced on Si (100).

[0006] One problem with current InN chips is that in order to integrate them into a module with the drive electronics, it is necessary to bond the GaN chip to the module on Si(100) and then connect them with wires. This introduces additional failure modes and losses. It also limits the speed of the device to the current capacity of the wires.

[0007] Typically, indium nitride (InN) is grown on gallium nitride (GaN). However, there is a relatively high lattice mismatch between InN and GaN, which results in a high density of crystal defects. Therefore, for InN, the electron mobility is lower than the theoretical value. InN can also be grown on indium aluminum nitride (InAlN), which has a better lattice match. However, this is complicated because InN and InAlN have very different surface atomic mobilities and therefore different growth temperatures.

[0008] The present invention aims to provide a layer structure which prevents or overcomes the above mentioned problems.

[0009] The present invention provides a semiconductor structure, comprising: a silicon substrate in a

[100] orientation; a scandium oxide layer in a

[111] orientation on the substrate; and a scandium-rare earth-oxide layer on the scandium oxide layer.

[0010] The semiconductor structure advantageously includes a scandium oxide layer grown in a

[111] orientation on Si(100) and crystallographically decoupled therefrom, and a scandium-rare earth-oxide layer that can transition from lattice matching with the scandium oxide layer to lattice matching with a subsequent layer. Advantageously, the scandium oxide grows on Si(100) in a

[111] orientation under suitable growth conditions and therefore does not need to be lattice matched or lattice consistent with Si(100). Thus, the semiconductor structure forms a template for a polar 111-N layer suitable for very high speed electronic and photonic applications on Si(100) substrates, which are widely used in electronic devices and are available in large diameters.

[0011] The semiconductor structure may also include an indium nitride layer on top of the scandium-rare earth-oxide layer. The indium nitride layer may be polar. Advantageously, InN is grown on Sc-RE-0(111) in the

[0001] (polar) orientation, as this is its lowest energy state. Advantageously, InN(0001) has very high electron mobility and is therefore suitable for high speed, THz frequency, electronic or photonic applications.

[0012] Scandium-rare earth-oxide has Sc x RE 1-x O, and x may decrease from 1 adjacent to the scandium oxide layer, and RE is a rare earth element. Advantageously, at x=1, the scandium-rare earth-oxide is ScO and is therefore fully lattice matched to the scandium oxide layer. Advantageously, decreasing x reduces the proportion of Sc and increasing the rare earth (RE) element to adjust (increase) the lattice constant for lattice matching with subsequent layers.

[0013] x can be decreased linearly, stepwise, nonlinearly, exponentially, polynomially, or in another graded pattern. When the change is a stepwise change, the steps can be equal or unequal. For example, the thickness grown before x is changed stepwise can be variable, and / or the amount by which x is decreased can be different between steps. Advantageously, the value of x can be decreased gradually so that the lattice constant does not change (increase) too abruptly, which can introduce excessive strain, leading to defects such as dislocations.

[0014] The scandium-rare earth-oxide layer may include a SC x Er 1-x The invention relates to a scandium erbium oxide having a composition of 1000 nm and 1000 nm. At a layer surface away from the scandium oxide layer, the value of x may be equal to 0.767. Advantageously, at x=0.767, ScErO is lattice matched to InN.

[0015] The scandium-rare earth-oxide layer may include scandium yttrium oxide, scandium ytterbium oxide or scandium lutetium oxide. Advantageously, each of these compounds can be lattice matched to InN.

[0016] The thickness of the scandium oxide layer may be less than or equal to 20 nm. Advantageously, when grown on Si(100), a thin layer of scandium oxide is sufficient to stabilize the

[111] orientation.

[0017] The thickness of the scandium-rare earth-oxide layer can be greater than or equal to 10 nm. The thickness of the scandium-rare earth-oxide layer can be less than or equal to 100 nm. The thickness of the scandium-rare earth-oxide layer can be between 10 nm and 50 nm. A lattice constant transition, a reduction in the value of x, can be achieved in a layer of 10 nm to 50 nm without introducing strain and / or defects such as dislocations. Thicker layers (up to 100 nm in thickness in the growth direction) can also serve as an insulating buffer between the substrate and one or more layers grown, deposited or bonded to the scandium-rare earth-oxide layer.

[0018] The scandium-rare earth-oxide layer may be lattice matched to the scandium oxide layer. For example, a small or negligible amount of rare earth elements may be present immediately adjacent to the scandium oxide layer for lattice matching.

[0019] The indium nitride layer can be lattice matched with the scandium-rare earth-oxide layer. The value of x in the scandium-rare earth-oxide layer can be reduced to a value that matches the indium nitride lattice at its upper surface. For example, when the rare earth is erbium, x=0.767 for lattice matching. When it is yttrium oxide (Y), the value of x that matches the InN lattice is 0.786. When it is ytterbium (Yb), the value of x is 0.729 for lattice matching with InN. When the rare earth is lutetium (Lu), x=0.68 for lattice matching with InN.

[0020] The semiconductor structure may also include a dielectric layer on the indium nitride layer. The dielectric layer may include crystalline bixbyite oxide. The crystalline bixbyite oxide may be a crystalline rare earth oxide. The crystalline rare earth oxide may be scandium erbium oxide. The dielectric layer may have the same composition as the scandium-rare earth-oxide. For example, the dielectric layer may include (Sc 0.7S7 Er 0.233 )2O3. Advantageously, crystalline rare earth oxides are good electrical insulators and therefore make good dielectrics. Advantageously, using the same material as the scandium-rare earth-oxide layer as the dielectric layer makes it easy to grow in the same epitaxial reactor, since no additional element sources or precursors are required.

[0021] Alternatively, the dielectric layer may include silicon nitride or silicon oxide, such as silicon dioxide. Advantageously, both materials are common dielectric materials that can be easily deposited, grown, bonded or sputtered onto the indium nitride layer. Alternatively, the dielectric layer may include indium oxide, In2O3, which has the same crystal structure as scandium-rare earth-oxide.

[0022] The present invention also provides a transistor comprising a semiconductor structure according to any of the preceding paragraphs. Advantageously, the InN transistor has a very high electron mobility. The transistor may include a source, a gate and a drain. Applying a current to the gate causes a very high electron drift through the indium nitride layer between the source and the drain. The transistor may be configured to operate at a frequency of 1 terahertz (THz) or faster. For example, it may operate between 1THz and 4THz.

[0023] The present invention also provides a layered structure comprising: a silicon substrate in a

[100] orientation, the substrate having a first portion and a second portion; a semiconductor structure as described in any one or more of the above paragraphs, wherein the semiconductor structure is formed on the first portion of the substrate; and a photonic structure formed on the second portion of the substrate. Advantageously, the layered structure enables the integration of very high speed (>lTHz) photonic and electronic components, particularly drive electronics, on a single Si(100) chip. Advantageously, there is no longer a need to pick and place such components and connect them with wires. Thus, device speed, rather than the wires, becomes the limiting factor in speed, and failure modes, wires, and connection points are eliminated.

[0024] The present invention also provides a layered structure comprising: a silicon substrate in a

[100] orientation, the substrate having a first portion and a second portion; a semiconductor structure as described in any one or more of the above paragraphs, wherein the semiconductor structure is formed on the first portion of the substrate; and a passive electronic structure formed on the second portion of the substrate. Advantageously, the layered structure enables the integration of very high speed (>lTHz) passive electronic structures and electronic components, particularly drive electronics, on a single Si(100) chip. Advantageously, there is no longer a need to pick and place such components and connect them with wires. Thus, device speed, rather than the wires, becomes the limiting factor in speed, and failure modes, wires, and connection points are eliminated.

[0025] The present invention will now be described more fully by way of example with reference to the accompanying drawings, in which:

[0026] Figure 1 is an illustrative semiconductor structure according to the present disclosure;

[0027] Figure 2 is an illustrative semiconductor structure according to the present disclosure;

[0028] Figure 3 is an illustrative semiconductor structure according to the present disclosure;

[0029] Figure 4 is an illustrative semiconductor structure according to the present disclosure;

[0030] Figure 5 is a graph of the lattice constants of various III-V compounds;

[0031] Figure 6 is a graph of the lattice constants of various III-V compounds;

[0032] Figure 7 is an illustrative semiconductor structure according to the present disclosure;

[0033] Figure 8 is an illustrative semiconductor structure according to the present disclosure.

[0034] Epitaxy or epitaxial means the crystalline growth of a material, usually via high temperature deposition. Epitaxy can be performed in a molecular beam epitaxy (MBE) tool, where layers are grown on a heated substrate in an ultra-high vacuum environment. Elemental sources are heated in a furnace and directed toward the substrate in the absence of a carrier gas. The elemental components react at the substrate surface to create deposited layers. Each layer is allowed to reach its lowest energy state before the next layer is grown so that bonds are formed between the layers. Epitaxy can also be performed in a metal organic vapor phase epitaxy (MOVPE) tool, also known as a metal organic chemical vapor deposition (MOCVD) tool. Compound metal organics and hydride sources are flowed over the heated surface using a carrier gas, usually hydrogen. Epitaxial deposition occurs at much higher pressures than in an MBE tool. The compound components are cracked in the gas phase and then react at the surface to grow layers of the desired composition.

[0035] Deposition means depositing one layer onto another layer or substrate. It encompasses epitaxy, chemical vapor deposition (CVD), powder bed deposition and other known techniques for depositing materials in layers.

[0036] Compound materials that include one or more materials from Group III and one or more materials from Group V of the periodic table are called III-V materials. Compounds have a 1:1 combination of Group III and Group V, regardless of the number of elements from each group. The subscript in the chemical symbol of the compound refers to the proportion of the element in that group. Thus, Al 0.25 GaAs means that the Group III portion comprises 25% Al and therefore 75% Ga, while the Group V portion comprises 100% As.

[0037] Crystalline means a material or layer having a single crystal orientation. In epitaxial growth or deposition, subsequent layers of the same or similar lattice constant follow the registration of the previous crystalline layer and thus grow in the same crystal orientation. In-plane is used herein to mean parallel to the substrate surface; out-of-plane is used to mean perpendicular to the substrate surface.

[0038] Throughout this disclosure, as readers of ordinary skill in the art will understand, crystal orientation <100> implies the faces of a cubic crystal structure and uses Miller indices covering the

[100] ,

[010] , and

[001] orientations. Similarly, <0001>

[0001] and [000-1] are covered unless material polarity is critical. Any integer multiple of one or more of the indices is equivalent to the unit version of the index. For example, (222) is equivalent to (111), which is the same as it.

[0039] Substrate means a flat wafer on which subsequent layers can be deposited or grown. The substrate can be formed of a single element or compound material, and can be doped or undoped. For example, common substrates include silicon (Si), gallium arsenide (GaAs), silicon germanium (SiGe), silicon germanium tin (SiGeSn), indium phosphide (InP), and gallium antimonide (GaSb).

[0040] The substrate may be on-axis, i.e., the growth surface is aligned with the crystal plane. For example, it may have <100> Crystalline Orientation. Reference herein to a substrate in a given orientation also encompasses a substrate that is mis-cut by up to 20° toward another crystallographic orientation, for example a (100) substrate that is mis-cut toward the (111) plane.

[0041] Vertical or out-of-plane means in the growth direction; lateral or in-plane means parallel to the substrate surface and perpendicular to the growth direction.

[0042] Doping means that a layer or material contains a small impurity concentration of another element (dopant) that donates (donor) or extracts (acceptor) charge carriers from the parent material, thus changing the conductivity. Charge carriers can be electrons or holes. Doped materials with extra electrons are called n-type, while doped materials with extra holes (fewer electrons) are called p-type.

[0043] Lattice matching means that two crystalline layers have the same or similar lattice spacing, so the second layer will tend to grow isomorphically on the first layer. The lattice constant is the strain-free lattice spacing of the crystal unit cell. Lattice consistency means that a crystalline layer has a lattice constant that is an integer multiple of or close to that of the previous layer, so the atoms can align with the previous layer. Lattice mismatch is a situation where the lattice constants of two adjacent layers are neither lattice matched nor lattice consistent. This mismatch introduces elastic strain into the structure, especially the second layer, because the second layer adopts the in-plane lattice spacing of the first layer. When the second layer has a larger lattice constant, the strain is compressive, and when the second layer has a smaller lattice constant, the strain is tensile.

[0044] When the strain is too great, the structure relaxes to minimize energy by defect creation (usually dislocations, called slips) or additional interstitial bonds, each of which allows the layer to recover toward its lattice constant. The strain can be too great due to a large lattice mismatch or due to the accumulation of small mismatches over many layers. Relaxed layers are called degenerate, inconsistent, incongruous, or relaxed, and these terms are often interchangeable.

[0045] A pseudomorphic system is a system in which a single crystalline thin layer is overlaid on a single crystalline substrate and the layer and substrate have similar crystal structures and almost identical lattice constants. In a pseudomorphic structure, the in-plane lattice spacing of the thin layer adopts the in-plane lattice constant of the substrate, so elastic strains are either compressive strains in which the layer has a lattice spacing greater than that of the substrate, or tensile strains in which the layer has a lattice spacing less than that of the substrate. The pseudomorphic structure is not constrained in an out-of-plane direction, so the lattice spacing of the thin layer in this direction can change to accommodate the strain generated by the mismatch between the lattice spacings. The thin layer can alternatively be described as "conform", "commensurate", "strained" or "unrelaxed", and these terms are often used interchangeably. In a pseudomorphic structure, all layers adopt the lattice spacing of the substrate in their corresponding in-plane lattice spacing.

[0046] The layer can be monolithic, that is, the entire layer includes bulk material. Alternatively, it can be porous over some or all of its thickness. The porous layer includes air or vacuum pores, and the porosity is defined as the proportion of the area occupied by pores rather than bulk material. The porosity can vary over the thickness of the layer. For example, the layer can be porous in one or more sublayers. The layer can include a porous upper part and a non-porous lower part. Alternatively, the layer can include one or more discrete, discontinuous parts (domains), which are porous and the rest are non-porous (having bulk material properties). These parts can be discontinuous in the plane of the sublayer and / or in the entire thickness of the layer (horizontally and / or vertically in the sense of the growth direction). These parts can be distributed across the layer and / or through it in a regular array or irregular pattern. In the porous region, the porosity can be constant or variable. When the porosity is variable, it can vary linearly over the entire thickness, or it can vary according to different functions (such as quadratic functions, logarithmic functions or step functions).

[0047] A porous layer means that pores have been formed through the bulk material, thereby intentionally introducing voids. Porosity is expressed as a percentage and refers to the volume of bulk material that has been removed, so a porosity of 25% means that 25% of the equivalent volume of the bulk material is voids.

[0048] A fully depleted porous layer means a layer in which there are no charge carriers.

[0049] The crystalline ferromanganese oxide layer can be a rare earth oxide layer. Rare earth elements are scandium (Sc), yttrium (Y) and all lanthanide elements, i.e., lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) and lutetium (Lu). The crystal structure of ferromanganese oxide is a ferromanganese structure. Other ferromanganese oxides include indium oxide (In2O3), vanadium oxide (V2O5), iron oxide (Fe2O3), manganese oxide (Mn2O3) and ternary compounds (RE-MO) of rare earth, metal and oxygen.

[0050] When describing devices, it should be understood that the devices are typically formed on a circular substrate wafer having a diameter of 4 inches (100 mm), 6 inches (150 mm), 8 inches (200 mm), 12 inches (300 mm), or larger. After growth, deposition, bonding, and other manufacturing steps, the devices are separated by cutting the wafers and layers into devices (chips) of appropriate dimensions. Typically, tens, hundreds, or thousands of devices are cut from a single wafer.

[0051] Figure 1 An exemplary semiconductor structure 10 according to the present disclosure is illustrated. The semiconductor structure 10 includes a plurality of layers. First is a substrate 12 in a

[100] crystal orientation. The substrate 12 is on-axis silicon (Si), so it has <100> Crystal orientation. As will be appreciated by those skilled in the art, crystal orientation <100> Means the faces of a cubic crystal structure and uses Miller indices to encompass

[100] ,

[010] , and

[001] orientations. References to Si(100) herein also encompass silicon substrates 12 that are mis-cut by up to 20° toward another crystal direction, such as toward the (111) plane. Si <100> It is readily available in large quantities at relatively low cost because it is used in consumer electronic devices such as computer chips for processing, memory, or graphics. <100> It is also widely used in electronic circuits driving photonic devices, such as complementary metal oxide semiconductors (CMOS), because it has high charge carrier mobility (higher than other orientations of Si). Therefore, if sufficient crystal quality can be obtained, it is possible to obtain the same by using Si <100> By growing photonic devices on Si(100) and placing appropriate layers in between, integration benefits can be obtained. In the case where the devices grown on Si(100) are driving power electronics for those grown on the layered structures described herein, this can eliminate the need for wiring to connect the devices. Advantageously, device performance becomes the speed limiting factor, rather than the wiring. Advantageously, a potential failure mode is removed by omitting wiring.

[0052] The silicon substrate 12 may be monolithic; that is, the entire silicon substrate comprises bulk single crystal silicon. Alternatively, the silicon substrate 12 may also comprise porous silicon for some or all of its thickness, for example, it may form a sublayer. The substrate 12 may comprise a porous upper portion and a non-porous lower portion. Alternatively, the substrate 12 may comprise one or more discrete, discontinuous porous portions, the remainder being non-porous (having bulk silicon characteristics). These portions may be discontinuous in the plane of the sublayer and / or through the thickness of the layer (horizontally and / or vertically in the sense of the growth direction). These portions may be distributed across the substrate 12 and / or through the substrate 12 in a regular array or an irregular pattern. The porosity within the porous region may be constant or variable. When the porosity is variable, it may vary linearly over the thickness, or may vary according to different functions (such as quadratic, logarithmic, or step functions).

[0053] Alternatively, the substrate may include silicon germanium (SiGe), such as Si 0.8 Ge 0.2 , or silicon-on-insulator (SOI).

[0054] On or above substrate 12 is a scandium oxide layer 14. Scandium oxide layer 14 may be positioned on, grown on or above, or deposited on substrate 12. Preferably, scandium oxide layer 14 is epitaxially grown (deposited) on substrate 12 to form a layer adjacent thereto. High quality, good crystallinity is more easily obtained by epitaxial deposition or growth.

[0055] When a crystalline ferromanganese oxide (such as scandium oxide or another rare earth oxide) is deposited on a substrate 12 or another layer at a sufficient surface temperature, a low enough oxygen concentration, and a slow enough growth rate, it does not match the crystal orientation of the previous layer, depending on the orientation of the substrate 12 or the previous layer. Instead, it grows in a different orientation, a process the inventors call "epi Twist". TM When most crystalline ferrous oxide is grown on Si(100), the crystalline ferrous oxide layer grows in the

[110] orientation, which has a lower surface energy than the

[100] orientation.

[0056] Scandium oxide, which is a rare earth oxide but not a lanthanide, surprisingly behaves differently from other crystalline ferromanganese oxides (especially rare earth oxides) because its lowest energy orientation is

[111] , so it grows on Si(100) in this orientation. The preferred crystal orientation of a material depends on its surface energy and the lattice mismatch with the underlying layer. The arrangement of atoms within the crystal is also a factor, because this affects the spacing between atoms on different surfaces, and whether the surface has only oxygen atoms, only metal atoms, or both. Sc is a smaller atom than the other rare earth elements, and the lattice spacing of SC2O3 is smaller than that of other crystalline ferromanganese oxides. Therefore, SC2O3(111) exhibits a larger lattice mismatch with Si(100): about -9%. For this reason, surface energy becomes the main factor in defining the crystal orientation, and in crystalline ferromanganese oxides that have a better lattice match with Si(100), for example up to ±2%, lattice matching is the main factor even though the surface energy in the (110) orientation can be twice that in the (111) orientation.

[0057] The scandium oxide layer 14 only needs to be thick enough for the

[111] orientation to be stable on the Si (100) substrate 12. For example, its thickness in the growth direction is about 20 nm.

[0058] Positioned on, grown on or above the scandium oxide layer 14, or deposited on the scandium oxide layer 14 is a scandium-rare earth-oxide layer 16. The scandium-rare earth-oxide layer 16 is grown on the scandium oxide layer 14 in the

[111] orientation. The scandium-rare earth-oxide layer 16 may include scandium erbium oxide, ScErO. For example, the scandium erbium oxide may have a composition of ScErO. x Er 1- x O, where x is selected to match the lattice of the adjacent layer. The scandium erbium oxide layer 16 acts as a lattice constant (approximately ) to the transition of the lattice constant of the subsequent layers.

[0059] The composition of the scandium-rare earth-oxide layer 16 can vary throughout the layer. For example, x can decrease from 1 adjacent to the scandium oxide layer 14 to a value desired for lattice matching with the layer to be grown or deposited thereon. The value of x can decrease linearly from 1 to a lattice matching value, or can decrease in another graded pattern, such as a stepwise decrease, or a nonlinear decrease (such as an exponential, parabolic, or other manner). By increasing the Er content of the layer and decreasing the Sc content, the lattice constant increases, such as Figure 5 As shown in Figure 5 It can be seen that Sc x Er 1-x The lattice constant of O (indicated by the solid line) changes from x = 0 (ErO) to It decreases linearly to x = 1 (ScO, shown as dot-dash line).

[0060] Alternatively, the scandium-rare earth-oxide layer 16 may include a different compound, such as scandium yttrium oxide (ScYO), scandium ytterbium oxide (ScYbO), or scandium lutetium oxide (ScLuO). Figure 6 For each of these compounds, the lattice constant is plotted against the percentage of Sc. 0% Sc is the same as x=0, and 100% Sc is the same as x=1, as shown in Figure 5 As shown in . Y2O3 (dotted line) has the largest lattice constant, which is Then Er2O3 (solid line), Yb2O3 (dotted line), Finally, Lu2O3 (long dashed line) is and (Sc x Er 1-x )2O3, the value of x can decrease linearly through the scandium-rare earth-oxide layer 16, from x=1 to a desired value for lattice matching with subsequent layers, or can decrease in another graded pattern, such as stepwise, exponentially, parabolically, or in other ways.

[0061] The semiconductor structure 10 may be grown by molecular beam epitaxy (MBE). Alternatively, it may be grown by metal organic vapor phase epitaxy (MOVPE, also known as metal organic chemical vapor deposition, MOCVD). Alternatively, it may be grown by atomic layer deposition (ALD).

[0062] The semiconductor structure 10 may be a template for growing, depositing or bonding one or more additional layers, such as device layers. Such a template includes a substrate 12 , a scandium oxide layer 14 , and a scandium-rare earth-oxide layer 16 .

[0063] In another aspect of the present disclosure, the semiconductor structure 10 may include one or more additional layers, such as Figure 3 As shown in . The indium nitride layer 18 is located on the scandium-rare earth-oxide layer 16. The indium nitride layer 18 can be positioned on the scandium-rare earth-oxide layer 16, grown on or on the scandium-rare earth-oxide layer 16, or deposited on the scandium-rare earth-oxide layer 16. Preferably, it is epitaxially grown. The indium nitride layer 18 can be in a

[0001] crystal orientation, that is, a polar orientation, due to the way it nucleates. The polarity (N polarity or In polarity) affects the carrier mobility. The

[0001] orientation is the lowest energy state of indium nitride grown on scandium-rare earth-oxide (111). Advantageously, polar indium nitride (InN) has a very high electron drift velocity, making it suitable for transistors operating at high frequencies, for example at frequencies of 1 THz or faster. InN has The lattice constant of Figure 5 and Figure 6 As shown by the dotted line in .

[0064] The indium nitride layer 18 may be grown by MBE or by MOVPE. Alternatively, it may be deposited by, for example, sputtering, or bonded to a template.

[0065] When InN is strained due to lattice mismatch, the density of crystal defects increases, which scatter charge carriers (electrons), thereby reducing their drift velocity. Therefore, it is beneficial to use the scandium-rare earth-oxide layer 16 to transition the lattice constant to match InN. When the scandium-rare earth-oxide is (Sc x Er 1-x )2O3, it is lattice-matched with InN at x=0.767. Therefore, the value of x can be reduced from 1 to approximately 0.767 through the thickness of the scandium-rare earth-oxide layer 16 in the growth direction. For example, x can be reduced linearly or stepwise, with equal or unequal steps, from x=1 to x=0.767. x Y 1-x )2O3, the value of x that matches the InN lattice is 0.786; for (Sc x Yb 1-x )2O3, which is 0.729; and for (Sc x Lu 1-x )2O3, which is 0.68. In some cases, it may be beneficial to set the value of x so that InN is not completely lattice matched to the scandium-rare earth-oxide layer 16. In this case, the resulting compressive or tensile strain (less than 1%, such as 0.2% to 0.5%) can enhance material or device properties, such as drift velocity, to a greater extent than when there is a complete lattice match.

[0066] Scandium-rare earth-oxide layer 16 can achieve lattice matching with the next layer, for example, indium nitride layer 18 with a thickness of 10 to 50 nm. Alternatively, it can be thicker, for example up to 100 nm, to additionally act as an insulating buffer for certain devices grown in or on indium nitride layer 18.

[0067] On or above the indium nitride layer 18 may be a dielectric layer 20, such as Figure 3 As shown in . Dielectric layer 20 may include a crystalline rare earth oxide. For example, it may include a scandium-rare earth-oxide having the same composition as scandium-rare earth-oxide layer 16, such as scandium erbium oxide. Alternatively, it may include a different rare earth oxide. Alternatively, it may include a different dielectric, such as silicon nitride (SiN x ) or silicon dioxide (SiO2).

[0068] The dielectric layer 20 may be fabricated into a device such as a FET. Figure 4 As shown in . Thus, transistor 27 includes source 22 and drain 24, which can be formed by etching away part of the dielectric to expose the indium nitride layer 18 and depositing the source 22 and drain 24. Gate 26 can be formed on dielectric layer 20, for example in the central portion, to switch the flow of current from source 22 to drain 24 via indium nitride layer 18 or to block the flow of electrons. Indium nitride layer 18 has a very high electron drift velocity, thus enabling switching at terahertz frequencies, for example at frequencies greater than or equal to 1 THz up to, for example, 4 THz. Therefore, semiconductor structure 10 is suitable for manufacturing into FinFET, MOSFET or other transistors. Advantageously, InN FinFET gives more charge than Si-based FinFET.

[0069] There are many terahertz applications, such as in imaging and spectroscopy, where high frequencies enable higher resolution. Far infrared devices operating at 75-300 μm (1-4 THz) can be used for security, sensing, and wireless applications. For example, security screening at airports can utilize THz frequency transistors to detect explosives, hidden weapons, and biological agents. In this case, the dielectric layer 20 can be a high-K dielectric. In medical environments, imaging at wavelengths below 300 μm can assist in the early diagnosis of diseases such as cancer. Terahertz frequencies are also beneficial in astronomy, spectroscopy, transportation, radar and lidar, and communications.

[0070] Currently, InN devices such as HEMTs are connected to Si-based CMOS electronics, such as in telecommunications or internet base stations, via wires. The wiring presents a potential failure mode. It can also limit the speed of operation. The present invention allows InN devices to be grown on top of a Si(100) substrate that can also host the CMOS electronics. Since the CMOS electronics and InN devices are adjacent, the wiring is eliminated, which removes the associated failure mode and means that the device performance is controlled by the device itself, rather than by the limitations of the connections. Advantageously, the ability to grow InN(0001) means that intrinsic charge is available, as GaN is polar, which enables piezoelectric switching without doping. InN devices can be configured to manage power, for example by performing step-down voltage conversion in a microprocessor.

[0071] Similarly, for LED or μLED applications, an InN-based emitter or an array of InN-based emitters can be grown on Si(100) according to the present semiconductor structure 10. Thus, the InN layer 18 can be replaced by a compound including InN that forms a quantum well that emits light (e.g., red light around 650 nm). The indium nitride layer 18 can include sublayers so that the quantum well is surrounded by a cladding AlInN that includes some aluminum. The value of x that is lattice-matched to the AlInN can be different from the value required for lattice matching to the InN. Each emitter corresponds to a pixel of the display. One or more emitters can be controlled by an electronic control component or device that is also grown or mounted on Si(100). Thus, the emitter and controller can be juxtaposed, preferably adjacent, so that each pixel in the array can be easily and directly addressed individually. Advantageously, the pixels can be turned on and off quickly and accurately.

[0072] For example, the semiconductor structure 10 can be grown on a first component (portion) 12a of a Si (100) substrate 12, and the electronic control components can be grown on a second component (portion) 12b of the Si (100) wafer, such as Figure 7 . The second part 12b of the wafer (substrate 12) may include a pyroxenite oxide layer 28 in a

[110] orientation. The pyroxenite oxide layer 28 may include erbium oxide (Er2O3) which, when grown on Si(100), twists to a

[110] orientation. A layer 30 compatible with the

[110] orientation may then be grown. For example, layer 20 may include molybdenum (Mo) in a

[112] orientation.

[0073] Alternatively, the semiconductor structure 10 may be grown on a first portion 12a of a Si(100) substrate 12 , and the electronic circuitry grown directly on another portion (second portion 12b ) of the Si(100) substrate 12 , without an intermediate ferromanganese oxide layer 28 .

[0074] Advantageously, growing indium nitride on semiconductor structure 10 enables integration of THz frequency photonics or passive electronic structures (such as resistors, capacitors, inductors that drive transistors) with electronic circuits on the same chip without the need for frequency converters. Figure 8As shown in , Si photonic devices 32 (such as active photonic elements 34 (e.g., quantum cascade lasers QCL or avalanche photodiodes APD), waveguides 36, and modulators 38) can all be grown or fabricated on a first portion 12a of a Si (100) substrate 12 and operate at THz frequencies. An electronic device 40 operating in the THz frequency range includes a semiconductor structure 10 configured as a transistor 27 and a passive electronic component 40. Advantageously, they can be grown or fabricated on a second portion 12b of the same Si (100) substrate 12. Advantageously, no frequency converter is required because both the photonic 32 and electronic 40 components operate in the same frequency range. By integrating the photonic and electronic components on the same substrate 12, manufacturing is less complex, does not require interconnects, peeling, or frequency converters, and is therefore cheaper and more reliable.

Claims

1. A semiconductor structure (10), comprising: A silicon substrate (12) in a [100] orientation; A scandium oxide layer (14) on the substrate (12) in a [111] orientation; as well as A scandium-rare earth oxide layer (16) on the scandium oxide layer (12).

2. The semiconductor structure (10) of claim 1, further comprising an indium nitride layer (18) above the scandium-rare earth-oxide layer (16).

3. The semiconductor structure (10) of claim 2, wherein the indium nitride layer (18) is polar.

4. A semiconductor structure (10) as claimed in any preceding claim, wherein the scandium-rare earth-oxide has a composition Sc x RE 1- x O, and wherein x decreases from 1 adjacent to the scandium oxide layer (14) and wherein RE is a rare earth element.

5. A semiconductor structure (10) as claimed in any preceding claim, wherein the scandium-rare earth-oxide layer (16) comprises a layer having a composition Sc x Er 1-x O of scandium erbium oxide, and wherein x is equal to 0.767 at a layer surface remote from the scandium oxide layer (14).

6. The semiconductor structure (10) of any preceding claim, wherein the scandium oxide layer (14) has a thickness less than or equal to 20 nm.

7. The semiconductor structure (10) of any preceding claim, wherein the scandium-rare earth-oxide layer (16) has a thickness greater than or equal to 10 nm and / or less than or equal to 100 nm.

8. A semiconductor structure (10) as claimed in any preceding claim, wherein the scandium-rare earth-oxide layer (16) has a thickness between 10 nm and 50 nm.

9. The semiconductor structure (10) of any preceding claim, wherein the scandium-rare earth-oxide layer (16) is lattice matched to the scandium oxide layer (14).

10. The semiconductor structure (10) of any preceding claim, wherein the scandium oxide layer (14) is crystallographically decoupled from the substrate (12).

11. The semiconductor structure (10) of claim 2 or claim 3, wherein the indium nitride layer (18) is lattice matched to the scandium-rare earth-oxide layer (16).

12. The semiconductor structure (10) of any one of claims 2, 3 and 11, further comprising a dielectric layer (20) on the indium nitride layer (18).

13. The semiconductor structure (10) of claim 12, wherein the dielectric layer (20) comprises crystalline bismuthite oxide or crystalline rare earth oxide or scandium erbium oxide or silicon nitride, silicon oxide or indium oxide.

14. The semiconductor structure (10) of any one of claims 12 to 13, wherein the dielectric layer (20) has the same composition as the scandium-rare earth-oxide layer (16).

15. A transistor (27) comprising a semiconductor structure (10) according to any preceding claim.

16. A transistor (27) as claimed in claim 15, configured to operate at 1 THz or faster.

17. A layered structure comprising: A silicon substrate (12) in a [100] orientation, the substrate (12) having a first portion (12a) and a second portion (12b); · A semiconductor structure (10) as claimed in any one of claims 1 to 14, wherein the semiconductor structure (10) is formed on a first portion (12a) of a substrate (12); and • A photonic structure (32) or a passive electronic structure (40) formed on the second portion (12b) of the substrate (12).

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