Plasma processing apparatus and plasma processing method

Abstract

In order to provide a plasma processing method capable of reducing foreign matter by suppressing adhesion of charged foreign matter to a sample during plasma etching processing, the present invention provides a plasma processing method comprising: a plasma processing chamber for processing a sample using plasma; a high-frequency power supply for supplying high-frequency power for generating the plasma; the electrostatic adsorption electrode is used for applying voltage to the sample so as to fix the sample in an electric adsorption manner; and a DC power source for applying a voltage to the electrostatic adsorption electrode, the plasma processing method comprising: an ignition step for generating plasma on the sample placed on the electrostatic adsorption electrode by means of the high-frequency power source; a plasma discharge step for etching the sample after the ignition step; and a de-electrifying step for removing the adsorption fixation by de-electrifying after the plasma discharge step, the voltage applied to the electrostatic adsorption electrode of the sample being greater than 0 V during the period from the ignition step to the de-electrifying step.

Description

Technical Field

[0001] The present invention relates to a manufacturing technology for semiconductor devices, and more particularly to a plasma processing apparatus and a plasma processing method suitable for suppressing adhesion of foreign matter during a plasma etching process. Background Art

[0002] In the development of semiconductor devices in recent years, as represented by the roadmaps such as IRDS (International Roadmap for Devices and Systems), the direction of miniaturization and high integration of circuits continues to advance. In this trend, semiconductor manufacturing equipment is required to have higher device specifications than ever before in terms of processing accuracy and mass production. The suppression of foreign matter adhesion to sample substrates (wafers) is also cited as one of the requirements. With the shortening of the pitch width of semiconductor devices, foreign matter with small particle diameters that has been ignored so far has attracted attention as an important factor of poor processing. Specifically, since it is expected that non-electroactive particles with a particle diameter of ≥7nm will have an impact as critical particles by 2025, measures to suppress the adhesion of these foreign matter to wafers will become important in the future.

[0003] The foreign matter issue as described above is particularly important in plasma etching, which is used for etching of samples in semiconductor manufacturing. In plasma etching, after a wafer is placed on a sample stage inside a processing chamber, electrostatic adsorption is performed to suppress the positional deviation of the wafer, and then the wafer is exposed to plasma. At this time, by adjusting various processing conditions such as the type of gas introduced into the processing chamber and the high-frequency power applied to the wafer, specific laminated films on the wafer are selectively removed to form a fine circuit pattern on the wafer. In the case where foreign matter adheres to the wafer during the above-mentioned plasma processing, it may cause fatal defects to the semiconductor device due to disconnection of wiring, short circuit, etc., so it is currently required to achieve low foreign matter for improving yield.

[0004] In view of the above-mentioned situation, technologies have been proposed so far for suppressing the adhesion of charged foreign matter that is easily generated in a plasma processing device to the surface of the wafer. For example, in Patent Document 1, the following electrostatic adsorption method is proposed: in the electrostatic adsorption of the wafer, the voltage applied to the wafer from the electrostatic adsorption electrode is adjusted to be fixed so that the surface potential of the wafer is close to ±0V, thereby suppressing the attraction of charged foreign matter to the wafer. However, in the above-mentioned electrostatic adsorption method, sometimes the wafer is negatively charged due to the influx of floating charges into the wafer during the etching process, and the charged state is not pulled back to ±0V after the plasma discharge is interrupted. The above-mentioned wafer charging attracts charged foreign matter in the sample chamber to the wafer, which may deteriorate the yield, so it is hoped to eliminate the negative charge of the wafer. During plasma etching, as an electrostatic adsorption method for suppressing the negative charge of the wafer, the method described in Patent Document 2 is proposed.

[0005] In Patent Document 2, due to the inflow of floating charges into the wafer during the plasma treatment of the wafer, the surface potential of the wafer changes in the negative direction, and after the completion of the plasma treatment, the surface potential of the wafer tends not to return to the state of ±0 V before the start of the treatment. In contrast, the following technology is disclosed: in the plasma discharge treatment step of the wafer, the voltage applied to the wafer is shifted in the negative direction by a first shift amount so as to have the same magnitude as the amount of change in the wafer potential accompanying the inflow of floating charges, and after the completion of the plasma discharge treatment, the DC voltage shifted in the negative direction by the first shift amount is shifted in the positive direction by a second shift amount, thereby eliminating the charging of the wafer caused by the floating charges.

[0006] Prior Art Literature

[0007] Patent Literature

[0008] Patent Document 1: International Publication No. 2009 / 013803

[0009] Patent Document 2: Japanese Patent Application Publication No. 2016-213358 Summary of the invention

[0010] -Problems to be solved by the invention-

[0011] In Patent Document 1, the applied voltage for electrostatic adsorption of the wafer is changed during the plasma etching process. However, in this control method, the current generated in the wafer accompanying the rapid change of the applied voltage cannot be considered. During the plasma etching process, the plasma generation state may become unstable due to the rapid change of the current in the wafer. If the plasma state becomes unstable, abnormal discharge is induced, which becomes the cause of the generation of foreign matter. Therefore, it is not desirable to rapidly change the parameters such as the applied voltage.

[0012] Furthermore, the technology described in Patent Document 2 can eliminate the charging of the wafer due to floating charges, but the present inventors' research has found that the effect of suppressing the adhesion of foreign matter is insufficient.

[0013] An object of the present invention is to provide a plasma processing apparatus and a plasma processing method that can suppress the adsorption of charged foreign matter to a wafer while maintaining a stable plasma generation state, thereby reducing the adhesion of foreign matter to the wafer.

[0014] -Methods for solving the problem-

[0015] The plasma processing device of the present invention comprises: a processing chamber for performing plasma processing on a sample using plasma; a high-frequency power supply for supplying high-frequency power for generating the plasma; a sample table having an electrode to which a voltage is applied for electrostatically adsorbing the sample, on which the sample is placed; a direct current power supply for applying the voltage to the electrode; and a control device for controlling the direct current power supply so that the positive voltage is applied to the electrode during the period from the ignition of the plasma to the detachment of the sample from the sample table.

[0016] -Effects of the Invention-

[0017] Provided is a plasma processing apparatus and a plasma processing method that can suppress the adsorption of charged foreign matter to a wafer while maintaining a stable plasma generation state, thereby reducing the adhesion of foreign matter to the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram showing the structure of a plasma processing apparatus according to the present invention.

[0019] Figure 2 This is a timing chart of the processing involved in Example 1 of the present invention.

[0020] Figure 3 This is a timing chart showing the conventional example 1.

[0021] Figure 4 This is the result of investigation on the effect of reducing adhesion of foreign matter to the wafer involved in Example 1.

[0022] Figure 5 This is a timing chart of the processing involved in Example 2 of the present invention.

[0023] Figure 6 This is a timing chart of the processing involved in the development example of the second embodiment of the present invention.

[0024] Figure 7 This is the result of investigation on the effect of reducing adhesion of foreign matter to the wafer involved in Example 2.

[0025] Figure 8 This is a timing chart of the processing involved in Example 3 of the present invention.

[0026] Fig. 9 These are the results of investigation into the effect of reducing adhesion of foreign matter to the wafer according to the third embodiment.

[0027] Fig.10 This is a timing chart of the processing involved in Example 4 of the present invention.

[0028] Fig.11 This is a timing chart showing the conventional example 2.

[0029] Fig.12 These are the results of investigation into the effect of reducing adhesion of foreign matter to the wafer according to the fourth embodiment. DETAILED DESCRIPTION

[0030] Hereinafter, embodiments of the present invention will be described using the accompanying drawings. Note that the following are merely embodiments, and the scope of rights of the present application is not limited to these embodiments.

[0031] Example 1

[0032] use Figure 1 to Figure 4 The first embodiment of the present invention is described. First, use Figure 1 A plasma processing apparatus for implementing the present invention will be described. Figure 1 This is a schematic diagram showing the structure of a plasma processing apparatus according to the present invention.

[0033] In the plasma processing apparatus used in this embodiment, a semiconductor substrate, namely a wafer 1, which is a sample, is carried from a gate 2 for wafer transfer into a processing chamber 3, which is a vacuum processing chamber, and is placed on a sample stage 4 for placing wafers.

[0034] The present plasma processing device is provided with a solenoid coil 5, a high frequency power supply 6 for generating μ waves, a μ wave oscillation source 7, a resonance unit 8, and a gas supply unit 9 as a mechanism for generating plasma. In the processing device, a magnetic field is generated by the solenoid coil 5. In addition, μ waves generated by the μ wave oscillation source 7 by the high frequency power from the high frequency power supply 6 are introduced into the processing chamber 3 via the resonance unit 8. The μ waves give energy to electrons in the magnetic field generated by the solenoid coil 5. The gas supplied from the gas supply unit 9 is ionized by the electrons to generate plasma.

[0035] During the plasma treatment, cooling gas is supplied to the back side of the wafer 1 for adjusting the temperature of the wafer 1. In order to prevent the wafer 1 from being deviated by the cooling gas, the wafer 1 is adsorbed on the sample stage 4 by bipolar electrostatic adsorption electrodes 10 and 11, which are electrodes with different polarities. The electrostatic adsorption electrodes 10 and 11 are arranged concentrically, with one electrode 10 arranged inside and the other electrode 11 arranged outside.

[0036] Independent power sources 12 and 13 are connected to electrostatic attraction electrodes (hereinafter sometimes referred to as ESC) 10 and 11. The DC power source 12 is connected to the inner electrostatic attraction electrode 10, and the DC power source 13 is connected to the outer electrostatic attraction electrode 11.

[0037] The electrostatic adsorption electrode is insulated from the wafer, but if a positive voltage is applied to the electrostatic adsorption electrode, negative charges are generated on the back of the wafer near the electrode, and the wafer is adsorbed to the electrode by Coulomb force. In the case of applying a negative voltage, positive charges are generated on the back of the wafer.

[0038] When negative charges are generated on the back of the wafer, positive charges are generated on the wafer surface opposite to the back, and the potential of the wafer as a whole becomes zero. Conversely, when positive charges are generated on the back of the wafer, negative charges are generated on the wafer surface opposite to the back.

[0039] The electrostatic adsorption electrodes 10 and 11 are applied with voltages of opposite polarities by respective DC power supplies. For example, a voltage of +800V is applied to the inner electrostatic adsorption electrode 10 from the DC power supply 12, and a voltage of -200V is applied to the outer electrostatic adsorption electrode 11 from the DC power supply 13.

[0040] The inventors of the present invention conducted research and found that if a voltage is applied to the electrostatic adsorption electrode under the condition that the total value of the voltages applied to the electrostatic adsorption electrode is positive (in the above case, (+800V)+(-200V)=(+600V), hereinafter, this voltage is defined as the sum of the applied voltages), the adhesion of foreign matter to the chip surface can be suppressed.

[0041] As a principle, positive charges proportional to +800V are generated on the wafer surface facing the inner electrostatic adsorption electrode 10, and negative charges proportional to -200V are generated on the wafer surface facing the outer electrostatic adsorption electrode 11. Therefore, positive charges are generated on the wafer surface on average, and in most cases, positively charged foreign matter is forced away from the wafer surface by Coulomb force. The following describes the experimental results conducted by the inventors.

[0042] The present plasma processing apparatus is provided with a control device 14 for controlling the output values ​​of the DC power supplies 12 and 13. The variable DC power supplies 12 and 13 are connected to the control device 14, and the output values ​​of the voltages are controlled by the control device 14. In addition, the control device 14 is also connected to the high-frequency power supply 6 for μ-wave generation, and controls the power output value from the high-frequency power supply 7 and the timing of output switching.

[0043] Here, in the structural example of the present plasma processing device, as described above, a bipolar electrostatic adsorption electrode is used, and two different DC power supplies are used to electrostatically adsorb the wafer, but a monopolar electrostatic adsorption electrode in which one side of the electrode is grounded may also be used. In the case of using a monopolar adsorption electrode, the device structure can be further simplified, and the design difficulty and manufacturing cost of the plasma processing device can be suppressed. In addition, a multipolar electrostatic adsorption electrode that uses three or more DC power supplies to electrostatically adsorb the wafer may also be used. In the case of using a multipolar electrostatic adsorption electrode, the voltage applied to the wafer can be locally controlled, and the distribution of plasma can be adjusted.

[0044] Figure 2 1 is a timing diagram of the processing involved in the first embodiment of the present invention. The content of the present invention is explained using the timing diagram. Figure 2 The plasma treatment process shown in FIG. 1 is composed of three steps: an ignition step performed between t2-1 and t2-3, a plasma discharge step performed between t2-3 and t2-4, and a static elimination step performed between t2-4 and t2-6. Figure 2 The “μ-wave incident power” here is the high-frequency power from the high-frequency power supply located at the top of the processing chamber, the “ESC voltage (+)” is the positive voltage output from the DC power supply 12, and the “ESC voltage (-)” is the negative voltage output from the DC power supply 13.

[0045] In this embodiment, Figure 2 Before the timing of t2-1 shown, first, the wafer 1 is carried into the processing chamber 3 and placed on the sample stage 4. Next, at the timing of t2-1, the DC power supplies 12 and 13 simultaneously output positive and negative voltages to the electrostatic adsorption electrodes 10 and 11, respectively, so that the wafer 1 is adsorbed to the sample stage 4.

[0046] Here, the inventors have found that if the net applied voltage to the electrostatic adsorption electrode is a value of +1V or more, foreign matter can be reduced. In addition, in order to stably adsorb the chip, from the viewpoint of maintaining the electrostatic adsorption force of the chip, the potential difference between the electrodes is preferably a value of 1000V or more. In this embodiment, the ESC voltage (+) is set to +800V, and the ESC voltage (-) is set to -200V, that is, the net applied voltage is set to +600V for processing. Next, at the timing of the start of the ignition step t2-2, 1000W of power is supplied from the high-frequency power supply 6, and current is passed through the solenoid coil 5, thereby generating plasma in the processing chamber 3. In addition, in order to prevent the plasma from igniting, the power supplied here is set to be higher than the power used in the normal plasma etching process. Next, at the timing of t2-3, the power supplied from the high-frequency power supply is changed to 800W, and the plasma discharge step is started.

[0047] Next, at the timing of starting the static elimination step at t2-4, the power supplied from the high frequency power supply is changed to 450 W, and the output of the plasma discharge is gradually reduced. Next, at the timing of t2-5, the voltage supplied from the DC power supply to the electrostatic adsorption electrode is changed to 0 V, and the electrostatic adsorption is stopped. Finally, at the timing of t2-6, the power supplied from the high frequency power supply is changed to 0 W, thereby ending the static elimination step (hereinafter sometimes referred to as the chuck unblocking step).

[0048] Here, a plasma treatment process of Conventional Example 1 for comparing the level of foreign matter reduction effect with that of Example 1 described above will be described. Figure 3 The timing chart of the conventional process corresponding to the conventional example 1 is shown. The conventional example 1 is a plasma processing process as follows: during the period t3-1 to t3-6, the voltage values ​​of the ESC voltage (+) and the ESC voltage (-) are set to +500V and -500V, respectively, and the net applied voltage during electrostatic adsorption is changed to ±0V.

[0049] The above-mentioned Example 1 and the previous example 1 were subjected to an evaluation experiment on the number of foreign matter attached to the wafer after plasma etching. In the experiment, the pressure inside the processing chamber 3 was 0.5Pa, and a mixed gas of Ar and O2 was continuously supplied into the chamber from the start of the ignition step to the timing of the end of the static elimination step. In addition, the flow rate of Ar was 100mL / min, and the flow rate of O2 was 30mL / min. In addition, the temperature of the sample stage 4 was 50°C, and He was used as the back gas for cooling the wafer, and the supply of gas was maintained so that the pressure at the back was maintained at 2kPa.

[0050] In this experiment, the above-mentioned plasma etching process was performed more than 30 times for each condition, and the number of foreign matter attached to the wafer in each implementation was counted, and then the median value of the number of foreign matter attached under each condition was compared with the target. In addition, in this experiment, the target particle diameter of the foreign matter was set to be 0.025μm or more.

[0051] Figure 4 The results of the investigation on the effect of reducing the adhesion of foreign matter to the wafer according to Example 1 are shown. Figure 4 The vertical axis is the conversion value of the number of foreign matter attachments when the number of foreign matter attachments in the conventional example 1 is normalized to 100%. Figure 4 In order to show the correlation between the applied voltage to the wafer and the number of foreign matter attachments, the results of the investigation are shown in the case where the ESC voltage (+) between t2-1 and t2-5 is set to +600V, the ESC voltage (-) is set to -400V, that is, the net applied voltage is set to +200V, and the ESC voltage (+) is set to +700V, the ESC voltage (-) is set to -300V, that is, the net applied voltage is set to +300V. As shown in the results, in the plasma processing process of Example 1 in which the total value of the applied voltage for electrostatic adsorption is maintained at a positive value between t2-1 and t2-5, the number of foreign matter decreases as the net applied voltage increases. Furthermore, in the results of Comparative Example 1 when the net applied voltage is set to +600V, the number of foreign matter can be reduced to less than half compared with the conventional example 1.

[0052] Example 2

[0053] Figure 5 2 is a timing chart of processing according to the second embodiment of the present invention. The second embodiment of the present invention will be described while paying attention to the structural differences from the first embodiment. Figure 5 In the period from t5-3 to t5-4, the total value of the net applied voltage applied to the electrostatic adsorption electrode is changed to 0V, which is a change from the adopted value of +600V in the aforementioned embodiment 1. Figure 5 The operation conditions during the period before t5-3 and after t5-4 are the same as those of the plasma processing process ( Figure 2 ) The actions in the period before t2-3 and the period after t2-4 are the same, so the description is omitted.

[0054] like Figure 5As shown, in this embodiment, at the timing of t5-3, the voltage value used for electrostatic adsorption is changed so that the net applied voltage from the DC power supplies 12 and 13 to the electrostatic adsorption electrodes becomes 0V. In addition, in this embodiment, in order to suppress the reduction of the electrostatic adsorption force of the chip, the voltage values ​​of the ESC voltage (+) and the ESC voltage (-) are set to +600V and -600V, respectively, and the potential difference between the two electrodes is maintained at 1200V. By controlling the applied voltage in this way, it is possible to suppress the rapid parameter changes generated in the process adopted in Patent Document 2, and as a result, it is possible to suppress the changes in the etching process caused by the changes in the plasma distribution accompanying the changes in the chip potential. Next, at the timing of t5-4, by changing the total value of the net applied voltage applied to the electrostatic adsorption electrodes to a positive value again, the adhesion of charged foreign matter can be suppressed as described above.

[0055] In addition, in this embodiment, the total value of the net applied voltage to the electrostatic adsorption electrode in the plasma discharge step from t5-3 to t5-4 is set to 0 V, but due to the inflow of floating charges during this period, the plasma potential of the wafer may shift in the negative direction. In contrast, as a development example of the second embodiment, the net applied voltage to the electrostatic adsorption electrode during the period may be set to a value shifted in the negative direction by the amount of the shift of the plasma potential. Figure 6 A sequence diagram showing processing according to a development example of the second embodiment of the present invention. This development example will be described below while paying attention to differences in configuration from the second embodiment.

[0056] exist Figure 6 In the period from t6-3 to t6-4, the total value of the net applied voltage to the electrostatic adsorption electrode is changed to a value below 0V, which is a change compared to the adopted value of 0V in the aforementioned embodiment 2. Figure 6 The operation conditions during the period before t6-3 and after t6-4 are the same as those of the plasma processing process ( Figure 5 ) The actions in the period before t5-3 and the period after t5-4 are the same, so the description is omitted.

[0057] like Figure 6As shown, in this development example, at the timing of t6-3, the total value of the net applied voltage applied from the DC power supplies 12 and 13 to the electrostatic adsorption electrode is changed to a value below 0V so as to be equal to the amount of negative displacement of the plasma potential of the wafer in the plasma discharge. In addition, in order to suppress the reduction of the electrostatic adsorption force of the wafer, the applied voltage is set so that the potential difference between the two electrodes becomes 1000V or more. Thus, the change of the plasma potential of the wafer can be offset by the change of the applied voltage applied to the electrostatic adsorption electrode, and the reduction of the adsorption force of the wafer can be suppressed, and the occurrence of positional deviation of the wafer can be suppressed.

[0058] In this embodiment, the total value of the net voltage applied to the electrostatic adsorption electrode during the neutralization step from t5-4 to t5-6 is set equal to Figure 2 Although the net applied voltage in the period t5-4 to t5-6 is set to +600 V as in the first embodiment shown, the net applied voltage in the period t5-4 to t5-6 may be set to the same value as the setting value in the period t5-3 to t5-4. In this case, the rapid change of the adsorption force associated with the change of the net applied voltage between the plasma discharge step and the static elimination step can be suppressed, and the occurrence of positional deviation of the wafer can be further suppressed.

[0059] The above-mentioned Example 2 was subjected to an evaluation experiment of the number of foreign matter attached to the wafer after the plasma etching process. In addition, as a comparison condition for comparing the level of foreign matter attached, the previous example 1 was used here. In addition, regarding the experimental conditions, during the period of t3-1 to t3-6, the voltage values ​​of the ESC voltage (+) and the ESC voltage (-) were set to +600V and -600V, respectively, and the potential difference between the two electrodes was maintained at 1200V. In addition, the other experimental conditions were the same as the evaluation test of the above-mentioned Example 1, so the description was omitted.

[0060] exist Figure 7 The results of the investigation on the effect of reducing the adhesion of foreign matter to the wafer according to Example 2 are shown in FIG. Figure 7 The vertical axis is the conversion value of the number of foreign matter attachments when the number of foreign matter attachments in the conventional example 1 is normalized to 100%. As shown in the results, when the total value of the net applied voltage applied to the electrostatic adsorption electrode between t5-3 and t5-4 is changed, Figure 5 In the plasma treatment process of , the number of foreign matter can be reduced to about half compared to the conventional example 1. Furthermore, in this embodiment, compared to the embodiment 1, the influence of the change in the plasma state can be suppressed to the minimum, which is practical.

[0061] Example 3

[0062] Figure 81 is a timing chart of the processing involved in the third embodiment of the present invention. The third embodiment of the present invention will be described while paying attention to the differences in structure from the first and second embodiments. Figure 8 In the period from t8-1 to t8-3, the total value of the net voltage applied to the electrostatic adsorption electrode is changed to 0V, which is a change from the adopted value of +600V in the aforementioned embodiment 2. Figure 8 The operation of each parameter after t8-3 is similar to the plasma processing process involved in the aforementioned embodiment 2 ( Figure 5 ) The actions of the parameters after t5-3 are the same, so the description is omitted.

[0063] In this embodiment, if Figure 8 As shown, first, at the timing of t8-1, the applied voltage is changed so that the net applied voltage from the DC power supplies 12 and 13 to the electrostatic adsorption electrodes becomes 0V. In addition, in this embodiment, in order to suppress the reduction of the electrostatic adsorption force of the wafer, the voltage values ​​of the ESC voltage (+) and the ESC voltage (-) are set to +600V and -600V respectively, and the potential difference between the two electrodes is maintained at 1200V. Next, at the timing of the start of the plasma ignition step t8-2, 1000W of power is supplied from the high-frequency power supply 6, and current is passed through the solenoid coil 5, thereby generating plasma in the processing chamber. Next, at the timing of the start of the plasma discharge step t8-3, the power supplied from the high-frequency power supply 6 is changed to 800W, and the plasma etching process is performed. In this way, by making the supply voltage from the DC power supplies 12 and 13 constant during the period t8-1 to t8-4, it is possible to suppress the rapid change of the adsorption force accompanied by the change of the net applied voltage to the electrostatic adsorption electrodes, and it is possible to suppress the occurrence of positional deviation of the wafer.

[0064] An evaluation experiment of the number of foreign matter attached to the wafer after plasma etching was performed on the above-mentioned Example 3. In addition, as a comparison condition for comparing the level of foreign matter attached, the previous example 1 was used here. In addition, the experimental conditions are the same as those of the evaluation test of the above-mentioned Example 2, so the description is omitted.

[0065] Fig. 9 The results of the investigation on the effect of reducing the adhesion of foreign matter to the wafer according to Example 3 are shown. Fig. 9 The vertical axis is the conversion value of the number of foreign matter attachments when the number of foreign matter attachments in the conventional example 1 is normalized to 100%. As shown in the results, the net applied voltage to the electrostatic adsorption electrode is changed between t8-1 and t8-3. Figure 8In the plasma processing process of , the number of foreign matter can be reduced to 60% compared with the conventional example 1. Furthermore, in the embodiment 3, compared with the embodiments 1 and 2, the influence of the change of the plasma state and the wafer adsorption force can be suppressed to the minimum.

[0066] Example 4

[0067] Fig.10 4 is a timing chart of the processing involved in the fourth embodiment of the present invention. This embodiment will be described while paying attention to the differences in structure from the first to third embodiments. Fig.10 In the embodiment 1, the timing of the start of the ignition step is changed to before the electrostatic adsorption of the wafer is performed during the period from t10-1 to t10-2, which is opposite to the implementation order in the embodiment 1. Fig.10 The operation of each parameter during the period after t10-2 is similar to the plasma processing process according to the first embodiment of the present invention ( Figure 2 ) After t2-2, the actions of each parameter are the same, so the description is omitted.

[0068] like Fig.10 As shown, in this embodiment, at the timing of t10-1, the Figure 2 The power supply from the high frequency power supply is increased to 1000W at the timing of t2-2. Next, control is performed so that at the timing of t10-2, the power supply starts at Figure 2 The supply of applied voltage for electrostatic adsorption is implemented at the timing of t2-1, and the net applied voltage from the DC power supplies 12 and 13 becomes +600 V. By changing the timing of wafer adsorption in the plasma ignition step, plasma formation is implemented before the potential of the wafer is changed, so that when the supply of applied voltage starts, the plasma captures charged foreign matter flying from the back side of the wafer, which can further suppress the attachment of foreign matter to the wafer.

[0069] Here, a plasma treatment process of a conventional example 2 for comparing the level of foreign matter reduction effect with that of the aforementioned embodiment 4 will be described. Fig.11 A timing diagram of a conventional process corresponding to the conventional example 2 is shown as an implementation for comparison with the embodiment 4. The conventional example 2 is a plasma processing process as follows: during the period from t11-2 to t11-6, the voltage values ​​of the ESC voltage (+) and the ESC voltage (-) are set to +600V and -600V, respectively, and the net applied voltage to the electrostatic adsorption electrode is changed to 0V.

[0070] An evaluation experiment of the number of foreign matter attached to the wafer after plasma etching was conducted on the above-mentioned Example 4 and Conventional Example 2. The experimental conditions were the same as those of the evaluation tests of the above-mentioned Examples 1 to 3, and thus the description thereof is omitted.

[0071] Fig.12 The results of the investigation on the effect of reducing the adhesion of foreign matter to the wafer according to Example 4 are shown. Fig.12 The vertical axis is the conversion value of the number of foreign matter adhesion when the number of foreign matter adhesion in the conventional example 2 is normalized to 100%. As shown in the results, the timing of plasma formation is changed between t10-1 and t10-2. Fig.10 In the plasma treatment process, the number of foreign matter can be reduced compared to the previous example 2 (0V).

[0072] As described in the above embodiments, it can be seen that in the plasma processing involved in the present invention, by changing the net voltage applied to the electrostatic adsorption electrode in the positive direction and maintaining the control parameters of the chip constant during the plasma etching process, the adhesion of foreign matter to the chip can be greatly reduced.

[0073] In addition, in both the ignition step and the de-static step or in only any single step, the net applied voltage to the electrostatic adsorption electrode is changed in the positive direction, and the net applied voltage to the electrostatic adsorption electrode in other steps is set to 0V, which can achieve both the suppression of foreign matter adhesion and the improvement of the stability of the chip adsorption force.

[0074] Furthermore, by changing the start timing of electrostatic adsorption of the wafer from before the ignition step to during the ignition step, the attachment of flying foreign matter caused by the rapid potential change of the wafer can be reduced. As a multiplication effect of these effects, the present invention can prevent foreign matter from adhering to the wafer and improve the yield of equipment manufacturing.

[0075] The present invention is achieved by Figure 2 , Figure 5 , Figure 6 , Figure 8 , Fig.10 By stipulating the shift of the net applied voltage to the electrostatic adsorption electrode of the wafer in the positive direction and maintaining the constant value of the control parameter in the plasma discharge step as in any one of the above, it is possible to suppress the adhesion of foreign matter.

[0076] In addition, the present invention is not limited to the above-mentioned embodiments, and includes various modified examples. For example, the above-mentioned embodiments are described in detail in order to explain the present invention in an easy-to-understand manner, and are not necessarily limited to having all the structures described. In addition, a part of the structure of a certain embodiment can be replaced with the structure of other embodiments, and in addition, the structure of other embodiments can be added to the structure of a certain embodiment. In addition, with respect to a part of the structure of each embodiment, other structures can be added / deleted / replaced. For example, in the above-mentioned embodiments 1 to 4, the ignition step is initially performed, but in a plasma treatment process in which the ignition step is deleted from each embodiment, the present invention is also applicable.

[0077] In addition, each of the above-mentioned processing structures can also be implemented by hardware, for example, by designing a part or all of them using integrated circuits. In addition, each of the above-mentioned processing structures can also be implemented by a processor interpreting and executing a program that implements each function. Information such as programs, tables, and files that implement each function can be placed in a recording device such as a memory, a hard disk, an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, or a DVD.

[0078] Furthermore, the control lines indicate those considered necessary for the explanation, and are not necessarily limited to indicating all the control lines in terms of the product. In reality, it can be considered that almost all the structures are connected to each other.

[0079] -Description of Reference Numerals-

[0080] 1…wafer, 2…gate, 3…processing chamber, 4…sample stage, 5…solenoid coil, 6…high-frequency power supply, 7…μ-wave oscillation source, 8…resonance unit, 9…gas supply unit, 10…first electrostatic adsorption electrode, 11…second electrostatic adsorption electrode, 12…first DC power supply, 13…second DC power supply, 14…control unit.

Claims

1. A plasma processing device, characterized in that: have: a processing chamber for plasma-treating the sample using plasma; A high-frequency power supply for supplying high-frequency power for generating the plasma; A sample stage having an electrode to which a voltage is applied for electrostatically adsorbing the sample, and on which the sample is placed; a direct current power source for applying the voltage to the electrodes; as well as A control device controls the DC power supply so that the positive voltage is applied to the electrode during a period from the ignition of the plasma to the detachment of the sample from the sample stage.

2. The plasma processing device according to claim 1, wherein: The electrode comprises: a first electrode to which a first voltage is applied for electrostatically adsorbing the sample; and a second electrode to which a second voltage is applied for electrostatically adsorbing the sample. The sum of the first voltage and the second voltage during the plasma processing is positive.

3. The plasma processing device according to claim 1, wherein: The voltage has substantially the same value during a period from ignition of the plasma to separation of the sample from the sample stage.

4. A plasma processing device, characterized in that: have: a processing chamber, which processes the sample using plasma; A high-frequency power supply for supplying high-frequency power for generating the plasma; A sample stage having an electrode to which a voltage is applied for electrostatically adsorbing the sample, and on which the sample is placed; a direct current power source for applying the voltage to the electrodes; as well as A control device controls the DC power supply so that the positive voltage is applied to the electrode during a process for igniting the plasma or a process for detaching the sample from the sample stage.

5. The plasma processing apparatus according to claim 4, wherein: The voltage during the plasma treatment is 0 V or less, The magnitude of the voltage during the plasma processing is equal to the amount of shift in plasma potential during the plasma processing.

6. The plasma processing apparatus according to any one of claims 1 to 5, wherein: The voltage before ignition of the plasma is a positive value.

7. The plasma processing apparatus according to claim 1, 2 or 4, wherein: The voltage is a positive value after ignition of the plasma and before the start of the plasma processing.

8. A plasma processing method, wherein a sample placed on a sample stage is subjected to plasma processing by using plasma, wherein: The sample stage includes an electrode to which a voltage is applied for electrostatically adsorbing the sample. The plasma processing method is characterized by comprising the step of applying the positive voltage to the electrode during a period from the ignition of the plasma to the detachment of the sample from the sample stage.

9. The plasma processing method according to claim 8, wherein: The electrode comprises: a first electrode to which a first voltage is applied for electrostatically adsorbing the sample; and a second electrode to which a second voltage is applied for electrostatically adsorbing the sample. The sum of the first voltage and the second voltage during the plasma processing is positive.

10. A plasma processing method, comprising: performing plasma processing on a sample placed on a sample stage using plasma, wherein: The sample stage includes an electrode to which a voltage is applied for electrostatically adsorbing the sample. The plasma processing method is characterized by comprising a step of applying the positive voltage to the electrode during a process for igniting the plasma or during a process for detaching the sample from the sample stage.

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