Semiconductor device and mounting substrate

Abstract

A chip-scale package-type semiconductor device (1) capable of being mounted in a face-up manner is provided with: a semiconductor layer (40); a vertical MOS transistor (10) formed in the semiconductor layer (40); a protective film (35); a first wiring electrode (12) connected to a source electrode (13) of the vertical MOS transistor (10); and a second wiring electrode (52) which is connected to the gate electrode (19) of the vertical MOS transistor (10), and in which a first outer peripheral structure (101), which is formed by laminating the source electrode (13), the protective film (35), and the first wiring electrode (12) in this order, and which protrudes above the semiconductor device (1), is formed on the outer peripheral portion of the first wiring electrode (12) in a plan view of the semiconductor layer (40), and a second outer peripheral structure (101), which is formed by laminating the source electrode (13), the protective film (35), and the first wiring electrode (12) in this order, is formed on the outer peripheral portion of the first wiring electrode (12). In the outer peripheral portion of the second wiring electrode (52) in a plan view of the semiconductor layer (40), a second outer peripheral structure (102) is formed in which the gate electrode (19), the protective film (35), and the second wiring electrode (52) are laminated in this order and which protrudes above the semiconductor device (1).

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a mounting substrate on which the semiconductor device is mounted. Background Art

[0002] Conventionally, there is a known semiconductor device (for example, refer to Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2019-169579 Summary of the invention

[0006] Problems to be solved by the invention

[0007] In recent years, in order to save space on a mounting substrate on which a semiconductor device is mounted, a mounting method has been proposed in which a semiconductor device is embedded in a mounting substrate for mounting.

[0008] Therefore, an object of the present invention is to provide a semiconductor device or the like having a structure suitable for a mounting method in which the semiconductor device is embedded in a mounting substrate and mounted.

[0009] Means for solving problems

[0010] A semiconductor device according to one embodiment of the present invention is a chip size package type semiconductor device that can be mounted face up, and comprises: a semiconductor layer; a vertical MOS (Metal Oxide Semiconductor: Metal Oxide Semiconductor) transistor, formed in the semiconductor layer; a protective film, which is a protective film covering the upper surface of the vertical MOS transistor, having a first opening portion for exposing the source electrode of the vertical MOS transistor to the outside of the protective film and a second opening portion for exposing the gate electrode of the vertical MOS transistor to the outside of the protective film; a first wiring electrode, connected to the source electrode, mainly composed of copper, seamlessly covering the portion of the source electrode exposed to the outside of the protective film in the first opening portion; a second wiring electrode, connected to the gate electrode, mainly composed of copper, seamlessly covering the portion of the gate electrode exposed to the outside of the protective film in the second opening portion, in a plan view of the semiconductor layer, the semiconductor device is rectangular, and a first peripheral structure is formed in which the source electrode, the protective film and the first wiring electrode are stacked in sequence in the outer peripheral portion of the first wiring electrode in the plan view of the semiconductor layer, the uppermost layer of the first peripheral structure is the first wiring electrode, and the second wiring electrode and the semiconductor are connected to the gate electrode and the protective film. The outer peripheral portion in the plan view of the body layer forms a second outer peripheral structure in which the gate electrode, the protective film and the second wiring electrode are stacked in sequence, the uppermost layer of the second outer peripheral structure is the second wiring electrode, the first wiring electrode exposure portion as the upper surface of the first wiring electrode is exposed to the outside of the semiconductor device, the second wiring electrode exposure portion as the upper surface of the second wiring electrode is exposed to the outside of the semiconductor device, the first outer peripheral structure protrudes upward than the upper surface of the portion of the first wiring electrode exposure portion that is not included in the first outer peripheral structure, the second outer peripheral structure protrudes upward than the upper surface of the portion of the second wiring electrode exposure portion that is not included in the second outer peripheral structure, the uppermost position of the semiconductor device exists in the first outer peripheral structure or / and the second outer peripheral structure, in the plan view of the semiconductor layer, the area of ​​the first wiring electrode exposure portion is larger than the area of ​​the first opening portion, in the plan view of the semiconductor layer, the area of ​​the second wiring electrode exposure portion is larger than the area of ​​the second opening portion, and the area of ​​the semiconductor layer in the plan view of the semiconductor layer is set to S [mm 2 ], if the thickness from the lower surface of the semiconductor layer to the upper surface of the protective film is set to h [mm], the relationship h / S≧0.025 holds.

[0011] A semiconductor device according to one embodiment of the present invention is a chip-size package type semiconductor device that can be mounted face-up, and comprises: a semiconductor layer; a vertical MOS (Metal Oxide Semiconductor) transistor formed in the semiconductor layer; a protective film covering the upper surface of the vertical MOS transistor, having a first opening for exposing a source electrode of the vertical MOS transistor to the outside of the protective film and a second opening for exposing a gate electrode of the vertical MOS transistor to the outside of the protective film; a first wiring electrode connected to the source electrode, mainly composed of copper, and covering the exposed portion of the source electrode in the first opening to the outside of the protective film without a gap; and a second wiring electrode connected to the gate electrode, mainly composed of copper, and without a gap. The protective film is a multilayer structure composed of a plurality of protective film layers including a first protective film layer and a second protective film layer located above the first protective film layer, and a first peripheral structure in which the source electrode, the first protective film layer, the first wiring electrode and the second protective film layer are stacked in sequence is formed in the outer peripheral portion of the first wiring electrode and the semiconductor layer in the plan view, the uppermost layer of the first peripheral structure is the second protective film layer, and the second wiring electrode and the semiconductor layer are in the outer peripheral portion of the plan view of the first wiring electrode and the semiconductor layer. The outer peripheral part in the plan view of the layer forms a second outer peripheral structure in which the gate electrode, the first protection film layer, the second wiring electrode and the second protection film layer are stacked in sequence, the uppermost layer of the second outer peripheral structure is the second protection film layer, the first wiring electrode exposure portion, which is a portion of the upper surface of the first wiring electrode not included in the first peripheral structure, is exposed to the outside of the semiconductor device, the second wiring electrode exposure portion, which is a portion of the upper surface of the second wiring electrode not included in the second peripheral structure, is exposed to the outside of the semiconductor device, the first outer peripheral structure protrudes upward from the upper surface of the first wiring electrode exposure portion, the second outer peripheral structure protrudes upward from the upper surface of the second wiring electrode exposure portion, the uppermost position of the semiconductor device exists in the first outer peripheral structure or / and the second outer peripheral structure, if the thickness of the first wiring electrode in the first outer peripheral structure is set to a first thickness, and the thickness of the second protection film layer in the first outer peripheral structure is set to a second thickness, then the second thickness is greater than half of the first thickness and is less than the first thickness, in the plan view of the semiconductor layer, the area of ​​the first wiring electrode exposure portion is greater than the area of ​​the first opening, and in the plan view of the semiconductor layer, the area of ​​the second wiring electrode exposure portion is greater than the area of ​​the second opening.

[0012] A mounting substrate according to one embodiment of the present invention is a mounting substrate on which a first wiring layer, an interlayer insulating layer and a second wiring layer are stacked in sequence, and comprises: the above-mentioned semiconductor device, which is mounted face up in the interlayer insulating layer; a first wiring, which is formed in the second wiring layer; and one or more first connecting wirings, which connect the first wiring to the upper surface of the first wiring electrode and extend in a direction orthogonal to the mounting substrate, and the one or more first connecting wirings are connected to a portion of the upper surface of the first wiring electrode that does not overlap with the first peripheral structure in a plan view of the semiconductor layer.

[0013] A mounting substrate according to one embodiment of the present invention is a mounting substrate on which a first wiring layer, an interlayer insulating layer, and a second wiring layer are stacked in sequence, and comprises a semiconductor device which is mounted face-up in the interlayer insulating layer, the semiconductor device having a semiconductor layer having a first wiring electrode on its upper surface; a first wiring formed in the second wiring layer; and one or more first connecting wirings connecting the first wiring to the upper surface of the first wiring electrode and extending in a direction orthogonal to the mounting substrate, the semiconductor device having a first peripheral structure formed on the outer peripheral portion of the first wiring electrode in a plan view of the semiconductor layer, the first peripheral structure protruding upward from a portion of the upper surface of the first wiring electrode that does not overlap with the first peripheral structure in a plan view of the semiconductor layer, the uppermost position of the semiconductor device being present in the first peripheral structure, the first wiring electrode being exposed to the outside of the semiconductor device at least at a portion of the upper surface of the first wiring electrode that does not overlap with the first peripheral structure in a plan view of the semiconductor layer, and the one or more first connecting wirings being connected to the upper surface of the first wiring electrode at a portion of the upper surface of the first wiring electrode of the semiconductor device that does not overlap with the first peripheral structure in a plan view of the semiconductor layer.

[0014] Effects of the Invention

[0015] According to a semiconductor device or the like according to one embodiment of the present invention, there is provided a semiconductor device or the like having a structure suitable for a mounting method of embedding in a mounting substrate and mounting. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a plan view showing an example of the structure of the semiconductor device according to the first embodiment.

[0017] Figure 2 This is a cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment.

[0018] Figure 3This is a cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment.

[0019] Figure 4 This is an image obtained by photographing a portion of the upper surface of the semiconductor device according to the first embodiment from obliquely above.

[0020] Figure 5 This is an enlarged cross-sectional view showing the structure of the first outer peripheral structure of the first embodiment.

[0021] Figure 6 This is a schematic diagram showing the relationship between the resistance of the semiconductor device according to the first embodiment and the shape and Si thickness of the semiconductor device according to the first embodiment.

[0022] Figure 7 1 is a cross-sectional view of the semiconductor device and the first peripheral structure according to the first embodiment, schematically showing an example of how the semiconductor device according to the first embodiment is deformed by a heat treatment process.

[0023] Figure 8 This is a plan view showing an example of the structure of the semiconductor device according to the first embodiment.

[0024] Fig. 9 This is a cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment.

[0025] Fig.10 This is a plan view showing an example of the structure of the semiconductor device according to the first embodiment.

[0026] Fig.11 This is a cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment.

[0027] Fig.12 This is a plan view showing an example of the structure of the semiconductor device according to the first embodiment.

[0028] Fig.13 This is a plan view showing an example of the structure of a semiconductor device according to the second embodiment.

[0029] Fig.14 This is a cross-sectional view showing an example of the structure of a semiconductor device according to the second embodiment.

[0030] Fig.15 This is an enlarged cross-sectional view showing the structure of the first outer peripheral structure of the second embodiment.

[0031] Fig.16 This is a plan view showing an example of the structure of a mounting substrate according to the third embodiment.

[0032] Fig.17This is a cross-sectional view showing an example of the structure of the mounting substrate according to the third embodiment.

[0033] Fig.18 This is an enlarged plan view showing an example of the structure of the mounting substrate involved in the third embodiment. DETAILED DESCRIPTION

[0034] (Process of obtaining one embodiment of the present invention)

[0035] The inventors have developed a semiconductor device including a vertical MOS transistor.

[0036] On the other hand, in recent years, there has been a demand for space saving of mounting substrates on which semiconductor devices are mounted.

[0037] In response to this demand, the inventors have considered that if a semiconductor device can be embedded in a mounting substrate for mounting, it will be possible to save space on the mounting substrate.

[0038] Therefore, based on this idea, the inventors have developed a semiconductor device including a vertical MOS transistor which is sealed with resin in a mounting substrate and mounted face up.

[0039] The inventors have discovered through this development that there is a semiconductor device having a structure suitable for a mounting method in which the semiconductor device is embedded in a mounting substrate.

[0040] That is, the inventors have reached the following insight: by providing a protrusion on the upper surface of the semiconductor device that is sunken into the resin encapsulating the semiconductor device, the protrusion acts as an anchor that fixes the position of the semiconductor device within the resin. As a result, it is possible to suppress resin peeling in the mounting substrate and stabilize the position of the semiconductor device inside the mounting substrate.

[0041] Furthermore, the inventors have found that when there is a protrusion on the upper surface of the semiconductor device, a protrusion reflecting the protrusion on the upper surface of the semiconductor device is also formed on the upper surface of the resin that is cured after the semiconductor device is encapsulated. Furthermore, the inventors have obtained the following knowledge: by using the protrusion formed on the upper surface of the resin as a guide line when processing the mounting substrate, the mounting substrate can be processed with higher precision than when there is no protrusion.

[0042] Therefore, the inventors have further conducted experiments and studies based on these findings. As a result, the inventors have come up with the following semiconductor device of the present invention.

[0043] A semiconductor device according to one embodiment of the present invention is a chip size package type semiconductor device that can be mounted face up, and comprises: a semiconductor layer; a vertical MOS (Metal Oxide Semiconductor: Metal Oxide Semiconductor) transistor, formed in the semiconductor layer; a protective film, which is a protective film covering the upper surface of the vertical MOS transistor, having a first opening portion for exposing the source electrode of the vertical MOS transistor to the outside of the protective film and a second opening portion for exposing the gate electrode of the vertical MOS transistor to the outside of the protective film; a first wiring electrode, connected to the source electrode, mainly composed of copper, seamlessly covering the portion of the source electrode exposed to the outside of the protective film in the first opening portion; a second wiring electrode, connected to the gate electrode, mainly composed of copper, seamlessly covering the portion of the gate electrode exposed to the outside of the protective film in the second opening portion, in a plan view of the semiconductor layer, the semiconductor device is rectangular, and a first peripheral structure is formed in which the source electrode, the protective film and the first wiring electrode are stacked in sequence in the outer peripheral portion of the first wiring electrode in the plan view of the semiconductor layer, the uppermost layer of the first peripheral structure is the first wiring electrode, and the second wiring electrode and the semiconductor are connected to the gate electrode and the protective film. The outer peripheral portion in the plan view of the body layer forms a second outer peripheral structure in which the gate electrode, the protective film and the second wiring electrode are stacked in sequence, the uppermost layer of the second outer peripheral structure is the second wiring electrode, the first wiring electrode exposure portion as the upper surface of the first wiring electrode is exposed to the outside of the semiconductor device, the second wiring electrode exposure portion as the upper surface of the second wiring electrode is exposed to the outside of the semiconductor device, the first outer peripheral structure protrudes upward than the upper surface of the portion of the first wiring electrode exposure portion that is not included in the first outer peripheral structure, the second outer peripheral structure protrudes upward than the upper surface of the portion of the second wiring electrode exposure portion that is not included in the second outer peripheral structure, the uppermost position of the semiconductor device exists in the first outer peripheral structure or / and the second outer peripheral structure, in the plan view of the semiconductor layer, the area of ​​the first wiring electrode exposure portion is larger than the area of ​​the first opening portion, in the plan view of the semiconductor layer, the area of ​​the second wiring electrode exposure portion is larger than the area of ​​the second opening portion, and the area of ​​the semiconductor layer in the plan view of the semiconductor layer is set to S [mm 2 ], if the thickness from the lower surface of the semiconductor layer to the upper surface of the protective film is set to h [mm], the relationship h / S≧0.025 holds.

[0044] According to the semiconductor device having the above structure, when the semiconductor device is sealed with resin in a mounting substrate and mounted face up, the first peripheral structure and the second peripheral structure are sunken into the resin on the upper surface of the semiconductor device.

[0045] Therefore, the first peripheral structure and the second peripheral structure sunken in the resin function as anchors for fixing the position of the semiconductor device in the resin, resulting in suppression of resin peeling in the mounting substrate and stabilization of the position of the semiconductor device inside the mounting substrate.

[0046] Furthermore, protrusions reflecting the first peripheral structure and the second peripheral structure are formed on the upper surface of the resin that is cured after the semiconductor device is sealed.

[0047] Therefore, when processing the resin to open a hole from the upper surface of the resin to the exposed portion of the first wiring electrode, by using the protrusion formed on the upper surface of the resin corresponding to the first peripheral structure as a guide line, processing is performed to open the hole on the inner side of the protrusion. Compared with a case where the protrusion does not exist, processing can be performed to open the hole from the upper surface of the resin to the exposed portion of the first wiring electrode with higher precision.

[0048] Furthermore, similarly, when the resin is processed to open a hole from the upper surface of the resin to the exposed portion of the second wiring electrode, a protrusion formed on the upper surface of the resin corresponding to the second peripheral structure is used as a guide line to open a hole on the inner side of the protrusion. As a result, compared with a case where the protrusion does not exist, the hole from the upper surface of the resin to the exposed portion of the second wiring electrode can be opened with higher precision.

[0049] As described above, according to the semiconductor device having the above-described structure, a semiconductor device having a structure suitable for the mounting method of embedding in a mounting substrate is provided.

[0050] In addition, it is also possible that there is also a metal layer formed in contact with the lower surface of the semiconductor layer, the thickness of the metal layer is thicker than the maximum thickness of the first wiring electrode, and the peripheral portion of the first wiring electrode in the plan view of the semiconductor layer has a wall surface that is an inverted cone shape toward the outside of the first wiring electrode in the cross-sectional view of the semiconductor layer, and the wall surface is not in contact with the protective film.

[0051] In addition, the protective film may have a portion around the first opening in the plan view of the semiconductor layer having a tapered region that is tapered toward the first opening in the cross-sectional view, and the wall surface may be located inside the tapered region in the plan view of the semiconductor layer.

[0052] A semiconductor device according to one embodiment of the present invention is a chip-size package type semiconductor device that can be mounted face-up, and comprises: a semiconductor layer; a vertical MOS (Metal Oxide Semiconductor) transistor formed in the semiconductor layer; a protective film that covers the upper surface of the vertical MOS transistor, and has a first opening for exposing a source electrode of the vertical MOS transistor to the outside of the protective film, and a second opening for exposing a gate electrode of the vertical MOS transistor to the outside of the protective film; a first wiring electrode connected to the source electrode, mainly composed of copper, and seamlessly covering the portion of the source electrode in the first opening that is exposed to the outside of the protective film; and a second wiring electrode connected to the gate electrode, mainly composed of copper, and seamlessly covering the portion of the source electrode exposed to the outside of the protective film. The protective film is a multilayer structure composed of a plurality of protective film layers including a first protective film layer and a second protective film layer located above the first protective film layer, and a first peripheral structure in which the source electrode, the first protective film layer, the first wiring electrode and the second protective film layer are sequentially stacked is formed in the outer peripheral portion of the first wiring electrode and the semiconductor layer in the plan view, the uppermost layer of the first peripheral structure is the second protective film layer, and the second wiring electrode and the semiconductor layer are in the outer peripheral portion of the first wiring electrode and the plan view. The outer peripheral part in the plan view of the semiconductor device forms a second outer peripheral structure in which the gate electrode, the first protective film layer, the second wiring electrode and the second protective film layer are stacked in sequence, the uppermost layer of the second outer peripheral structure is the second protective film layer, the first wiring electrode exposure portion which is a portion of the upper surface of the first wiring electrode not included in the first peripheral structure is exposed to the outside of the semiconductor device, the second wiring electrode exposure portion which is a portion of the upper surface of the second wiring electrode not included in the second peripheral structure is exposed to the outside of the semiconductor device, the first outer peripheral structure protrudes upward from the upper surface of the first wiring electrode exposure portion, the second outer peripheral structure protrudes upward from the upper surface of the second wiring electrode exposure portion, the uppermost position of the semiconductor device exists in the first outer peripheral structure or / and the second outer peripheral structure, if the thickness of the first wiring electrode in the first outer peripheral structure is set to a first thickness, and the thickness of the second protective film layer in the first outer peripheral structure is set to a second thickness, then the second thickness is greater than half of the first thickness and is less than the first thickness, in the plan view of the semiconductor layer, the area of ​​the first wiring electrode exposure portion is greater than the area of ​​the first opening, and in the plan view of the semiconductor layer, the area of ​​the second wiring electrode exposure portion is greater than the area of ​​the second opening.

[0053] According to the semiconductor device having the above structure, when the semiconductor device is sealed with resin in a mounting substrate and mounted face up, the first peripheral structure and the second peripheral structure are sunken into the resin on the upper surface of the semiconductor device.

[0054] Therefore, the first peripheral structure and the second peripheral structure sunken in the resin function as anchors for fixing the position of the semiconductor device in the resin, resulting in suppression of resin peeling in the mounting substrate and stabilization of the position of the semiconductor device inside the mounting substrate.

[0055] Furthermore, protrusions reflecting the first peripheral structure and the second peripheral structure are formed on the upper surface of the resin that is cured after the semiconductor device is sealed.

[0056] Therefore, when processing the resin to open a hole from the upper surface of the resin to the exposed portion of the first wiring electrode, by using the protrusion formed on the upper surface of the resin corresponding to the first peripheral structure as a guide line, processing is performed to open the hole on the inner side of the protrusion. Compared with a case where the protrusion does not exist, processing can be performed to open the hole from the upper surface of the resin to the exposed portion of the first wiring electrode with higher precision.

[0057] Furthermore, similarly, when the resin is processed to open a hole from the upper surface of the resin to the exposed portion of the second wiring electrode, a protrusion formed on the upper surface of the resin corresponding to the second peripheral structure is used as a guide line to open a hole on the inner side of the protrusion. As a result, compared with a case where the protrusion does not exist, the hole from the upper surface of the resin to the exposed portion of the second wiring electrode can be opened with higher precision.

[0058] As described above, according to the semiconductor device having the above-described structure, a semiconductor device having a structure suitable for the mounting method of embedding in a mounting substrate is provided.

[0059] In addition, it may be that the minimum width of the portion of the second protective film layer that overlaps with the first wiring electrode in the plan view of the semiconductor layer is greater than the thickness of the portion of the second protective film layer that does not overlap with the first wiring electrode or the second wiring electrode in the plan view of the semiconductor layer, and the minimum width of the portion of the second protective film layer that overlaps with the second wiring electrode in the plan view of the semiconductor layer is greater than the thickness of the portion of the second protective film layer that does not overlap with the first wiring electrode or the second wiring electrode in the plan view of the semiconductor layer.

[0060] In addition, the height of the first peripheral structure based on the upper surface of the first wiring electrode exposed portion may be more than 50% of the thickness of the first wiring electrode at the first opening, and the height of the second peripheral structure based on the upper surface of the second wiring electrode exposed portion may be more than 50% of the thickness of the second wiring electrode at the second opening.

[0061] In addition, it is also possible that, when the area of ​​the source electrode in the plan view of the semiconductor layer is set to M1 and the area of ​​the first opening in the plan view of the semiconductor layer is set to S1, a first occupancy ratio of the area of ​​the first opening in the plan view of the semiconductor layer relative to the area of ​​the source electrode in the plan view of the semiconductor layer, which is represented by S1 / M1, is greater than 0.5 and less than 1.0.

[0062] Alternatively, the first occupancy rate may be greater than 0.9 and less than 1.0, and when the area of ​​the first wiring electrode exposed portion in the plan view of the semiconductor layer is set to P1, the second occupancy rate, which is the occupancy rate of the area of ​​the first wiring electrode exposed portion in the plan view of the semiconductor layer relative to the area of ​​the source electrode in the plan view of the semiconductor layer, represented by P1 / M1, may be greater than 0.9 and less than 1.1.

[0063] In addition, when the area of ​​the second opening portion in the plan view of the semiconductor layer is set to S2 and the area of ​​the second wiring electrode exposed portion in the plan view of the semiconductor layer is set to P2, the third occupancy rate, which is the occupancy rate of the area of ​​the second wiring electrode exposed portion in the plan view of the semiconductor layer relative to the area of ​​the second opening portion in the plan view of the semiconductor layer, represented by P2 / S2, is greater than 1.27.

[0064] Furthermore, in a plan view of the semiconductor layer, the shape of the first wiring electrode and the shape of the second wiring electrode may be line symmetric about a center line as an axis of symmetry, and the center line divides the semiconductor device into two equal parts in terms of area.

[0065] A mounting substrate according to one embodiment of the present invention is a mounting substrate on which a first wiring layer, an interlayer insulating layer and a second wiring layer are stacked in sequence, and comprises: a semiconductor device according to claim 1 or 4, which is mounted face up in the interlayer insulating layer; a first wiring, formed in the second wiring layer; and one or more first connecting wirings, which connect the first wiring to the upper surface of the first wiring electrode and extend in a direction orthogonal to the mounting substrate, and the one or more first connecting wirings are connected to a portion of the upper surface of the first wiring electrode that does not overlap with the first peripheral structure in a plan view of the semiconductor layer.

[0066] According to the mounting substrate having the above structure, on the upper surface of the semiconductor device, the first peripheral structure and the second peripheral structure are sunken into the material forming the interlayer insulating layer.

[0067] Therefore, the first peripheral structure and the second peripheral structure sunk into the material forming the interlayer insulating layer act as anchors for fixing the position of the semiconductor device within the interlayer insulating layer, resulting in suppression of interlayer insulating layer peeling in the mounting substrate and stabilization of the position of the semiconductor device inside the mounting substrate.

[0068] Furthermore, when the material forming the interlayer insulating layer is, for example, a resin, protrusions reflecting the first peripheral structure and the second peripheral structure are formed on the upper surface of the resin that is cured after encapsulating the semiconductor device, that is, on the upper surface of the interlayer insulating layer.

[0069] Therefore, when the interlayer insulating layer is processed to open a hole from the upper surface of the interlayer insulating layer to the exposed portion of the first wiring electrode, a protrusion corresponding to the first peripheral structure formed on the upper surface of the interlayer insulating layer is used as a guide line to open the hole on the inner side of the protrusion. As a result, compared with the case where the protrusion does not exist, the hole from the upper surface of the interlayer insulating layer to the exposed portion of the first wiring electrode can be opened with higher precision.

[0070] Furthermore, similarly, when the interlayer insulating layer is processed to open a hole from the upper surface of the interlayer insulating layer to the exposed portion of the second wiring electrode, a protrusion corresponding to the second peripheral structure formed on the upper surface of the interlayer insulating layer is used as a guide line to open a hole on the inner side of the protrusion. As a result, compared with a case where the protrusion does not exist, the hole from the upper surface of the interlayer insulating layer to the exposed portion of the second wiring electrode can be opened with higher precision.

[0071] Thus, according to the mounting substrate having the above structure, there is provided a mounting substrate on which a semiconductor device is mounted, the semiconductor device having a structure suitable for a mounting method in which the semiconductor device is embedded in the mounting substrate for mounting.

[0072] In addition, it may also be that it further comprises: a second wiring formed in the second wiring layer; and a second connecting wiring connecting the second wiring to the upper surface of the second wiring electrode and extending in a direction orthogonal to the mounting substrate, the second connecting wiring is connected to the upper surface of the second wiring electrode at a portion of the upper surface of the second wiring electrode that does not overlap with the second peripheral structure in a plan view of the semiconductor layer, the cross-section of each of the one or more first connecting wirings orthogonal to the direction in which each of the one or more first connecting wirings extends and the cross-section of the second connecting wiring orthogonal to the direction in which the second connecting wiring extends are circular, and the cross-section of at least one of the one or more first connecting wirings is larger than the cross-section of the second connecting wiring.

[0073] A mounting substrate according to one embodiment of the present invention is a mounting substrate on which a first wiring layer, an interlayer insulating layer, and a second wiring layer are stacked in sequence, and comprises: a semiconductor device mounted face-up in the interlayer insulating layer, the semiconductor device having a semiconductor layer having a first wiring electrode on its upper surface; a first wiring formed in the second wiring layer; and one or more first connecting wirings connecting the first wiring to the upper surface of the first wiring electrode and extending in a direction orthogonal to the mounting substrate, wherein the semiconductor device has a first peripheral structure formed on the outer peripheral portion of the first wiring electrode in a plan view of the semiconductor layer, the first peripheral structure protruding upward from a portion of the upper surface of the first wiring electrode that does not overlap with the first peripheral structure in a plan view of the semiconductor layer, the uppermost position of the semiconductor device being present in the first peripheral structure, the first wiring electrode being exposed to the outside of the semiconductor device at least at a portion of the upper surface of the first wiring electrode that does not overlap with the first peripheral structure in a plan view of the semiconductor layer, and the one or more first connecting wirings being connected to the upper surface of the first wiring electrode at a portion of the upper surface of the first wiring electrode of the semiconductor device that does not overlap with the first peripheral structure in a plan view of the semiconductor layer.

[0074] According to the mounting substrate having the above structure, the first peripheral structure is sunken into the material forming the interlayer insulating layer on the upper surface of the semiconductor device.

[0075] Therefore, the first peripheral structure sunk into the substance forming the interlayer insulating layer functions as an anchor for fixing the position of the semiconductor device within the interlayer insulating layer, thereby suppressing peeling of the interlayer insulating layer in the mounting substrate and stabilizing the position of the semiconductor device within the mounting substrate.

[0076] Furthermore, when the material forming the interlayer insulating layer is, for example, a resin, a protrusion reflecting the first peripheral structure is formed on the upper surface of the resin that is cured after encapsulating the semiconductor device, that is, on the upper surface of the interlayer insulating layer.

[0077] Therefore, when the interlayer insulating layer is processed to open a hole from the upper surface of the interlayer insulating layer to the exposed portion of the first wiring electrode, a protrusion corresponding to the first peripheral structure formed on the upper surface of the interlayer insulating layer is used as a guide line to open the hole on the inner side of the protrusion. As a result, compared with the case where the protrusion does not exist, the hole from the upper surface of the interlayer insulating layer to the exposed portion of the first wiring electrode can be opened with higher precision.

[0078] Thus, according to the mounting substrate having the above structure, there is provided a mounting substrate on which a semiconductor device is mounted, the semiconductor device having a structure suitable for a mounting method in which the semiconductor device is embedded in the mounting substrate for mounting.

[0079] Furthermore, the one or more first connecting wirings may be plural in number.

[0080] Furthermore, the height to the uppermost position of the semiconductor device based on the lowest position on the upper surface of the first wiring electrode may be 15% or more of the length of the one or more first connecting wirings in a direction perpendicular to the mounting substrate.

[0081] In addition, it is also possible that there are multiple first wiring electrodes, the one or more first connecting wirings are multiple corresponding to the multiple first wiring electrodes in pairs, the multiple first connecting wirings are respectively connected to the first wiring through one first wiring electrode among the multiple first wiring electrodes corresponding to the first connecting wiring in pairs, and the cross-sections of each of the multiple first connecting wirings that are orthogonal to the direction in which each of the multiple first connecting wirings extends are equal to each other.

[0082] Furthermore, in a plan view of the mounting substrate, the mounting substrate may have a shape having a long side direction, the semiconductor device may have a shape having a long side direction, and the long side direction of the mounting substrate and the long side direction of the semiconductor device may be orthogonal to each other.

[0083] In addition, it is also possible that there is also an electronic component arranged at a position above the interlayer insulating layer, in the plan view of the mounting substrate, the electronic component is a shape with a long side direction, the semiconductor device is a shape with a long side direction, at least a portion of the electronic component overlaps with the semiconductor device, and the long side direction of the electronic component and the long side direction of the semiconductor device are orthogonal to each other.

[0084] Hereinafter, a specific example of a semiconductor device or the like of one embodiment of the present invention will be described with reference to the accompanying drawings. The embodiments shown here all represent a specific example of the present invention. Therefore, the numerical values, shapes, components, configurations and connection methods of the components, and steps (processes) and the order of steps shown in the following embodiments are examples and are not intended to limit the present invention. In addition, each figure is a schematic diagram and may not be strictly illustrated. In each figure, the same figure mark is marked for substantially the same structure, and repeated descriptions are omitted or simplified.

[0085] (Implementation Method 1)

[0086] Hereinafter, a semiconductor device according to Embodiment 1 will be described. This semiconductor device is a chip size package type semiconductor device capable of face-up mounting, and has a structure suitable for a mounting method of embedding in a mounting substrate.

[0087] structure

[0088] The structure of the semiconductor device according to Embodiment 1 is described below. The semiconductor device according to Embodiment 1 is a semiconductor device of a chip size package (CSP) type that can be face-up mounted and has N (N is an integer greater than or equal to 1) vertical MOS (Metal Oxide Semiconductor) transistors formed therein. The N vertical MOS transistors are so-called trench MOSFETs (Field Effect Transistors).

[0089] In the present invention, N is described as 2, but N is not necessarily limited to 2, and N may be 1 or 3 or more.

[0090] Figure 1 FIG. 1 is a plan view showing an example of the structure of the semiconductor device 1 according to the first embodiment. Figure 1 As shown, the semiconductor device 1 has a rectangular shape in a plan view of the semiconductor device 1 (ie, in a plan view of a semiconductor layer 40 described later).

[0091] Figure 2 , Figure 3 It is a cross-sectional view showing an example of the structure of the semiconductor device 1 . Figure 2 express Figure 1 The cut surface of II, Figure 3 express Figure 1 The cross section of II-II.

[0092] like Figure 1 to Figure 3As shown, the semiconductor device 1 includes a metal layer 30, a semiconductor layer 40, an oxide film 34, a protective film 35, a first vertical MOS transistor 10 formed in the semiconductor layer 40, a second vertical MOS transistor 20 formed in the semiconductor layer 40, a first source electrode 13 functioning as a source electrode of the first vertical MOS transistor 10, a first gate electrode 19 functioning as a gate electrode of the first vertical MOS transistor 10, a second source electrode 23 functioning as a source electrode of the second vertical MOS transistor 20, a second gate electrode 29 functioning as a gate electrode of the second vertical MOS transistor 20, a first wiring electrode 12 connected to the first source electrode 13, a second wiring electrode 52 connected to the first gate electrode 19, a third wiring electrode 22 connected to the second source electrode 23, and a fourth wiring electrode 54 connected to the second gate electrode 29.

[0093] In the present invention, a case where the semiconductor device 1 includes the metal layer 30 is described, but the semiconductor device 1 is not necessarily limited to the structure including the metal layer 30 .

[0094] In addition, Figure 1 In FIG. 1 , the first source electrode 13 , the first gate electrode 19 , the second source electrode 23 , and the second gate electrode 29 are illustrated as being visually recognizable by dotted lines, but in reality, these components cannot be directly visually recognizable from the outside of the semiconductor device 1 .

[0095] The semiconductor layer 40 is formed by laminating a semiconductor substrate 32 and a low-concentration impurity layer 33 .

[0096] Here, if the area of ​​the semiconductor layer 40 in the plan view of the semiconductor layer 40 is S [mm 2 ], and the thickness from the lower surface of the semiconductor layer 40 to the upper surface of the protective film 35 is set to h [mm 2 ], then the relationship h / S≧0.025 holds.

[0097] The semiconductor substrate 32 is disposed on the lower surface side of the semiconductor layer 40 , and is made of silicon containing impurities of the first conductivity type.

[0098] The low-concentration impurity layer 33 is disposed on the upper surface side of the semiconductor layer 40, is formed in contact with the semiconductor substrate 32, and contains first-conductivity-type impurities at a concentration lower than the first-conductivity-type impurities of the semiconductor substrate 32. The low-concentration impurity layer 33 may also be formed on the semiconductor substrate 32 by, for example, epitaxial growth.

[0099] The oxide film 34 is disposed on the upper surface of the semiconductor layer 40 and is formed in contact with the low-concentration impurity layer 33 .

[0100] The protective film 35 is a protective film covering the upper surface of the first vertical MOS transistor 10 and the upper surface of the second vertical MOS transistor 20, and has a first opening portion 61 for exposing the first source electrode 13 to the outside of the protective film 35, a second opening portion 62 for exposing the first gate electrode 19 to the outside of the protective film 35, a third opening portion 63 for exposing the second source electrode 23 to the outside of the protective film 35, and a fourth opening portion 64 for exposing the second gate electrode 29 to the outside of the protective film 35.

[0101] Here, the protective film 35 covers the upper surface of the first vertical MOS transistor 10 and the upper surface of the second vertical MOS transistor 20, which means that the protective film 35 is formed on substantially the entire surface of the semiconductor device 1 except for the opening portion in the plan view of the semiconductor layer 40. Here, substantially the entire surface of the semiconductor device 1 refers to the entire surface of the semiconductor device 1 except for the peripheral area slightly remaining on the four sides of the semiconductor device 1 after cutting, in the area of ​​the wafer ensured as a cutting margin when cutting the semiconductor device 1 from the wafer. Therefore, in this peripheral area, the oxide film 34 is exceptionally exposed on the upper surface of the semiconductor device 1.

[0102] In addition, the opening of the protective film 35 referred to in the present invention refers to a shape in which the entire length of the periphery of the opening is closed by the protective film 35 in a plan view of the semiconductor layer 40. Therefore, in a plan view of the semiconductor layer 40, a shape in which a part of the periphery overlaps with the peripheral area of ​​the oxide film 34 that is exceptionally exposed on the upper surface of the semiconductor device 1 does not correspond to the opening of the protective film 35 referred to in the present invention.

[0103] In the present invention, the protection film 35 is described as having one first opening 61 as an opening for exposing the first source electrode 13 to the outside of the protection film 35 . However, the protection film 35 may have a plurality of openings as openings for exposing the first source electrode 13 to the outside of the protection film 35 .

[0104] Similarly, in the present invention, the protective film 35 is described as having one second opening 62 as an opening for exposing the first gate electrode 19 to the outside of the protective film 35 , but the protective film 35 may also have a plurality of openings as openings for exposing the first gate electrode 19 to the outside of the protective film 35 .

[0105] In the present invention, the protection film 35 is described as having one third opening 63 as an opening for exposing the second source electrode 23 to the outside of the protection film 35 . However, the protection film 35 may have a plurality of openings as openings for exposing the second source electrode 23 to the outside of the protection film 35 .

[0106] Similarly, in the present invention, the protective film 35 is described as having one fourth opening 64 as an opening for exposing the second gate electrode 29 to the outside of the protective film 35 , but the protective film 35 may also have a plurality of openings as openings for exposing the second gate electrode 29 to the outside of the protective film 35 .

[0107] In addition, the protective film 35 can be a single-layer structure or a multi-layer structure in which multiple layers are stacked. In the present invention, the protective film 35 is described as having a multi-layer structure (here, a two-layer structure) in which a first protective film layer 35A and a second protective film layer 35B located above the first protective film layer 35A are stacked.

[0108] As an example which is not limited, the first protection film layer 35A may also be made of silicon nitride, and the film thickness thereof may be 0.3 μm, for example.

[0109] As an example which is not limited, the second protective film layer 35B may also be made of polyimide, and the film thickness thereof may be 8 μm, for example.

[0110] The metal layer 30 is formed in contact with the lower surface of the semiconductor substrate 32, and can be made of silver, copper, nickel or their alloys, or can be made of a metal material with good conductivity that can function as an electrode. In addition, the metal layer 30 can also contain trace amounts of elements other than metals mixed as impurities during the manufacturing process of the metal material.

[0111] A first body region 18 containing impurities of a second conductivity type different from the first conductivity type is formed in the region of the low concentration impurity layer 33 where the first vertical MOS transistor 10 is formed. In the first body region 18, a first source region 14 containing impurities of the first conductivity type, a first gate conductor 15, and a first gate insulating film 16 are formed.

[0112] The first source electrode 13 is connected to the first source region 14 and the first body region 18 through the opening of the oxide film 34 .

[0113] As a non-limiting example, the first source electrode 13 may be formed of a metal material including any one or more of aluminum, copper, gold, and silver.

[0114] The first wiring electrode 12 is connected to the first source electrode 13 and seamlessly covers the portion of the first source electrode 13 exposed to the outside of the protective film 35 in the first opening 61. This prevents the first source electrode 13 from being corroded by substances outside the semiconductor device 1.

[0115] The first wiring electrode 12 has copper as a main component and is formed by plating as an example but not limited thereto. The first wiring electrode 12 has a thickness of 10 μm, for example.

[0116] When the protection film 35 has one or more openings for exposing the first source electrode 13 to the outside of the protection film 35 in addition to the first opening 61 , the semiconductor device 1 includes wiring electrodes similar to the first wiring electrode 12 for each of the one or more openings.

[0117] The first gate electrode 19 is electrically connected to the first gate conductor 15 .

[0118] As a non-limiting example, the first gate electrode 19 may be formed of a metal material including any one or more of aluminum, copper, gold, and silver.

[0119] The second wiring electrode 52 is connected to the first gate electrode 19 and seamlessly covers the portion of the first gate electrode 19 exposed to the outside of the protective film 35 in the second opening 62. This prevents the first gate electrode 19 from being corroded by substances outside the semiconductor device 1.

[0120] The second wiring electrode 52 has copper as a main component and is formed by plating as an example but not limited thereto. The second wiring electrode 52 has a thickness of 10 μm, for example.

[0121] When the protection film 35 has one or more openings for exposing the first gate electrode 19 to the outside of the protection film 35 in addition to the second opening 62 , the semiconductor device 1 includes wiring electrodes similar to the second wiring electrode 52 for each of the one or more openings.

[0122] A second body region 28 containing impurities of a second conductivity type different from the first conductivity type is formed in the region of the low concentration impurity layer 33 where the second vertical MOS transistor 20 is formed. In the second body region 28, a second source region 24 containing impurities of the first conductivity type, a second gate conductor 25, and a second gate insulating film 26 are formed.

[0123] The second source electrode 23 is connected to the second source region 24 and the second body region 28 through the opening of the oxide film 34 .

[0124] As a non-limiting example, the second source electrode 23 may be made of a metal material including any one or more of aluminum, copper, gold, and silver.

[0125] The third wiring electrode 22 is connected to the second source electrode 23 and seamlessly covers the portion of the second source electrode 23 exposed to the outside of the protective film 35 in the third opening 63. This prevents the second source electrode 23 from being corroded by substances outside the semiconductor device 1.

[0126] The third wiring electrode 22 has copper as a main component and is formed by plating as an example but not limited thereto. The third wiring electrode 22 has a thickness of 10 μm, for example.

[0127] When the protection film 35 has one or more openings for exposing the second source electrode 23 to the outside of the protection film 35 in addition to the third opening 63 , the semiconductor device 1 includes wiring electrodes similar to the third wiring electrode 22 for each of the one or more openings.

[0128] The second gate electrode 29 is electrically connected to the second gate conductor 25 .

[0129] As a non-limiting example, the second gate electrode 29 may be formed of a metal material including any one or more of aluminum, copper, gold, and silver.

[0130] The fourth wiring electrode 54 is connected to the second gate electrode 29 and seamlessly covers the portion of the second gate electrode 29 exposed to the outside of the protective film 35 in the fourth opening 64. This prevents the second gate electrode 29 from being corroded by substances outside the semiconductor device 1.

[0131] The fourth wiring electrode 54 is mainly composed of copper and is formed by plating as an example but not limited thereto. The fourth wiring electrode 54 has a thickness of 10 μm, for example.

[0132] When the protection film 35 has one or more openings for exposing the second gate electrode 29 to the outside of the protection film 35 in addition to the fourth opening 64 , the semiconductor device 1 includes wiring electrodes similar to the fourth wiring electrode 54 for each of the one or more openings.

[0133] Here, the maximum thickness of the first wiring electrode 12, the maximum thickness of the second wiring electrode 52, the maximum thickness of the third wiring electrode 22, and the maximum thickness of the fourth wiring electrode 54 are thinner than the thickness of the metal layer 30. That is, the thickness of the metal layer 30 is thicker than the maximum thickness of the first wiring electrode 12, the maximum thickness of the second wiring electrode 52, the maximum thickness of the third wiring electrode 22, and the maximum thickness of the fourth wiring electrode 54.

[0134] In the semiconductor device 1, for example, the first conductivity type can be set to N type, the second conductivity type can be set to P type, the first source region 14, the second source region 24, the semiconductor substrate 32 and the low-concentration impurity layer 33 are N-type semiconductors, and the first body region 18 and the second body region 28 are P-type semiconductors.

[0135] In addition, in the semiconductor device 1, for example, the first conductivity type can be set to P type, the second conductivity type can be set to N type, the first source region 14, the second source region 24, the semiconductor substrate 32 and the low-concentration impurity layer 33 are P type semiconductors, and the first body region 18 and the second body region 28 are N type semiconductors.

[0136] In the present invention, the first vertical MOS transistor 10 and the second vertical MOS transistor 20 are described as so-called N-channel transistors in which the first conductivity type is the N-type and the second conductivity type is the P-type.

[0137] In addition, in the present invention, it is assumed that the first vertical MOS transistor 10 is the same as the second vertical MOS transistor 20, the first source electrode 13 is the same as the second source electrode 23, the first gate electrode 19 is the same as the second gate electrode 29, the first wiring electrode 12 is the same as the third wiring electrode 22, and the second wiring electrode 52 is the same as the fourth wiring electrode 54 for explanation.

[0138] Therefore, below, with respect to the first vertical MOS transistor 10 and the second vertical MOS transistor 20, the first vertical MOS transistor 10 is described by taking them as representatives, with respect to the first source electrode 13 and the second source electrode 23, the first source electrode 13 is described by taking them as representatives, with respect to the first gate electrode 19 and the second gate electrode 29, the first gate electrode 19 is described by taking them as representatives, with respect to the first wiring electrode 12 and the third wiring electrode 22, the first wiring electrode 12 is described by taking them as representatives, and with respect to the second wiring electrode 52 and the fourth wiring electrode 54, the second wiring electrode 52 is described by taking them as representatives.

[0139] like Figure 2 , Figure 3 As shown, the upper surface of the first wiring electrode 12 is exposed to the outside of the semiconductor device 1 , and the upper surface of the second wiring electrode 52 is exposed to the outside of the semiconductor device 1 .

[0140] In the present invention, a portion of the upper surface of the first wiring electrode 12 exposed to the outside of the semiconductor device 1 (in Embodiment 2, the semiconductor device 1A described later) is defined as a first wiring electrode exposed portion 71, and a portion of the upper surface of the second wiring electrode 52 exposed to the outside of the semiconductor device 1 (in Embodiment 2, the semiconductor device 1A described later) is defined as a second wiring electrode exposed portion 72.

[0141] Therefore, in the first embodiment, the first wiring electrode exposed portion 71 is the upper surface of the first wiring electrode 12 , and the second wiring electrode exposed portion 72 is the upper surface of the second wiring electrode 52 .

[0142] That is, in the first embodiment, the first wiring electrode exposed portion 71 as the upper surface of the first wiring electrode 12 is exposed to the outside of the semiconductor device 1 , and the second wiring electrode exposed portion 72 as the upper surface of the second wiring electrode 52 is exposed to the outside of the semiconductor device 1 .

[0143] Here, if Figure 1 to Figure 3As shown, in a plan view of the semiconductor layer 40 , the area of ​​the first wiring electrode exposed portion 71 is larger than the area of ​​the first opening 61 , and the area of ​​the second wiring electrode exposed portion 72 is larger than the area of ​​the second opening 62 .

[0144] In addition, if Figure 2 , Figure 3 As shown, in the peripheral part of the first wiring electrode 12 in the plan view of the semiconductor layer 40, a first peripheral structure 101 is formed in which the first source electrode 13, the protective film 35 and the first wiring electrode 12 are stacked in sequence, and in the peripheral part of the second wiring electrode 52 in the plan view of the semiconductor layer 40, a second peripheral structure 102 is formed in which the first gate electrode 19, the protective film 35 and the second wiring electrode 52 are stacked in sequence.

[0145] Here, the uppermost layer of the first peripheral structure 101 is the first wiring electrode 12 , and the uppermost layer of the second peripheral structure 102 is the second wiring electrode 52 .

[0146] like Figure 2 , Figure 3 As shown, the first peripheral structure 101 protrudes upward from the upper surface of the portion of the first wiring electrode exposure portion 71 that is not included in the first peripheral structure 101, and the second peripheral structure 102 protrudes upward from the upper surface of the portion of the second wiring electrode exposure portion 72 that is not included in the second peripheral structure 102, and the top position of the semiconductor device 1 exists in the first peripheral structure 101 and / or the second peripheral structure 102.

[0147] Figure 4 This is a captured image obtained by capturing a portion of the upper surface of the semiconductor device 1 near the second wiring electrode 52 from obliquely above the semiconductor device 1 .

[0148] from Figure 4 It can be seen that, in the outer peripheral portion of the semiconductor layer 40 in the plan view of the second wiring electrode 52 , the second peripheral structure 102 is formed to protrude upward from the upper surface of the portion not included in the second peripheral structure 102 .

[0149] Figure 5 It is an enlarged cross-sectional view showing the structure of the first outer peripheral structure 101 .

[0150] In the present invention, the second peripheral structure 102 is described as being the same as the first peripheral structure 101 except that the first source electrode 13 is replaced by the first gate electrode 19 .

[0151] Therefore, the following, using Figure 5 The first peripheral structure 101 and the second peripheral structure 102 are described.

[0152] like Figure 5As shown, the first wiring electrode 12 has a first wall surface 201 in the outer peripheral portion in the plan view of the semiconductor layer 40 . The first wall surface 201 is inverted tapered toward the outside of the first wiring electrode 12 in the cross-sectional view of the semiconductor layer 40 and does not contact the protective film 35 .

[0153] In addition, if Figure 5 As shown, the protective film 35 has a first tapered region 202 around the first opening 61 in the plan view of the semiconductor layer 40 , which tapers toward the first opening 61 in the cross-sectional view of the semiconductor layer 40 .

[0154] Here, if Figure 5 As shown, in a plan view of the semiconductor layer 40 , the first wall surface 201 is located inside the first tapered region 202 .

[0155] Similarly, the second wiring electrode 52 has a second wall surface in the outer peripheral portion in the plan view of the semiconductor layer 40 . The second wall surface is inverted tapered toward the outside of the second wiring electrode 52 in the cross-sectional view of the semiconductor layer 40 and does not contact the protective film 35 .

[0156] Similarly, the protective film 35 has a second tapered region that is tapered toward the second opening 62 in the cross-sectional view of the semiconductor layer 40 in a portion surrounding the second opening 62 in the plan view of the semiconductor layer 40 .

[0157] Here, too, in the plan view of the semiconductor layer 40 , the second wall surface is located inside the second tapered region.

[0158] <Inspection>

[0159] According to the semiconductor device 1 having the above structure, when the semiconductor device 1 is sealed with resin in a mounting substrate and mounted face up, the first peripheral structure 101 and the second peripheral structure 102 are sunken into the resin on the upper surface of the semiconductor device 1 .

[0160] Therefore, the first peripheral structure 101 and the second peripheral structure 102 sunken in the resin play an anchoring role to fix the position of the semiconductor device 1 in the resin, resulting in suppression of resin peeling in the mounting substrate and stabilization of the position of the semiconductor device 1 inside the mounting substrate.

[0161] Furthermore, on the upper surface of the resin that is cured after sealing the semiconductor device 1 , protrusions reflecting the first peripheral structure 101 and the second peripheral structure 102 are formed.

[0162] Therefore, when processing is performed on the resin to open a hole from the upper surface of the resin to the first wiring electrode exposed portion 71, the protrusion formed on the upper surface of the resin corresponding to the first peripheral structure 101 is used as a guide line to open a hole on the inner side of the protrusion. As a result, compared with a case where the protrusion does not exist, the hole from the upper surface of the resin to the first wiring electrode exposed portion 71 can be opened with higher precision.

[0163] Moreover, similarly, when the resin is processed to open a hole from the upper surface of the resin to the second wiring electrode exposed portion 72, the protrusion formed on the upper surface of the resin corresponding to the second peripheral structure 102 is used as a guide line to open the hole on the inner side of the protrusion, thereby allowing the hole from the upper surface of the resin to reach the second wiring electrode exposed portion 72 to be opened with higher precision compared to a case where the protrusion does not exist.

[0164] As described above, according to the semiconductor device 1 having the above-described structure, a semiconductor device having a structure suitable for the mounting method of embedding in a mounting substrate is provided.

[0165] As described above, in the plan view of the semiconductor layer 40 , the area of ​​the first wiring electrode exposed portion 71 is larger than the area of ​​the first opening 61 , and the area of ​​the second wiring electrode exposed portion 72 is larger than the area of ​​the second opening 62 .

[0166] Thus, in the plan view of the semiconductor layer 40, compared with the case where the area of ​​the first wiring electrode exposed portion 71 is not larger than the area of ​​the first opening portion 61 and the area of ​​the second wiring electrode exposed portion 72 is not larger than the area of ​​the second opening portion 62, the degree of freedom in the processing of opening a hole from the upper surface of the resin to the first wiring electrode exposed portion 71 and the processing of opening a hole from the upper surface of the resin to the second wiring electrode exposed portion 72 can be improved.

[0167] When the semiconductor device 1 is embedded in a mounting substrate for mounting, the semiconductor device 1 may receive stress and impact from the mounting substrate. If the thickness from the lower surface of the semiconductor layer 40 to the upper surface of the protective film 35 (hereinafter also referred to as "Si thickness") is too small relative to the area of ​​the semiconductor device 1 in the plan view of the semiconductor layer 40 (hereinafter also referred to as "chip area"), the semiconductor device 1 cannot obtain sufficient resistance to the stress and impact received from the mounting substrate.

[0168] The inventors have conducted experiments and studies on the relationship between the resistance of the semiconductor device 1 to stress and impact received from the mounting substrate and the shape of the semiconductor device 1 in the plan view of the semiconductor layer 40 and the Si thickness. As a result, the inventors have obtained the following knowledge: when the shape of the semiconductor device 1 in the plan view of the semiconductor layer 40 is 2 [mm] × 2 [mm], if the Si thickness is 0.1 mm or more, the semiconductor device 1 can obtain sufficient resistance to stress and impact received from the mounting substrate.

[0169] Based on this knowledge, the inventors have further conducted experiments and studies and have obtained the following knowledge: when the shape of the semiconductor device 1 in the plan view of the semiconductor layer 40 is smaller than 2 [mm] × 2 [mm], even if the chip area S [mm 2 ], the semiconductor device 1 can also obtain sufficient resistance to stress and impact from the mounting substrate by making the Si thickness h [mm] thinner in proportion to the chip area S [mm]; and when the shape of the semiconductor device 1 in the plan view of the semiconductor layer 40 is made larger than 2 [mm] × 2 [mm], 2 ] By increasing the Si thickness h [mm] in proportion to the value of FIG. 1 , the semiconductor device 1 can obtain sufficient resistance to stress and impact received from the mounting substrate.

[0170] Figure 6 This is a schematic diagram showing the relationship between the resistance of the semiconductor device 1 to stress and impact received from the mounting substrate and the shape of the semiconductor device 1 and the Si thickness in a plan view of the semiconductor layer 40 , which was obtained by the inventors through experiments and studies.

[0171] like Figure 6 As shown, if the chip area is set to S[mm 2 ], assuming that the Si thickness is [mm], then within the range where the relationship h / S≧0.025 holds true, the semiconductor device 1 can obtain sufficient resistance to stress and impact received from the mounting substrate.

[0172] Figure 7 The cross-sectional view of the semiconductor device 1 and the first peripheral structure 101 schematically shows an example of how the semiconductor device 1 is deformed due to a heat treatment process during resin sealing when the semiconductor device 1 is resin-sealed and face-up mounted on a mounting substrate.

[0173] As described above, the semiconductor device 1 includes the metal layer 30 on the back side which is thicker than the maximum thickness of the first wiring electrode 12, the maximum thickness of the second wiring electrode 52, the maximum thickness of the third wiring electrode 22, and the maximum thickness of the fourth wiring electrode 54. Generally, the metal constituting the metal layer 30 (for example, silver, copper, nickel, or an alloy thereof) has a larger thermal expansion coefficient than the semiconductor containing impurities (for example, silicon doped with impurities) constituting the semiconductor layer 40.

[0174] Therefore, if Figure 7 As shown in (b) of FIG. 1 , when the semiconductor device 1 is sealed in the mounting substrate with resin and heat-treated to cure the resin, the temperature of the semiconductor device 1 also rises, so that the back surface of the semiconductor device 1 is convexly warped. Figure 7 As shown in (a) and (b) of FIG. 1 , the inclination of the first wall surface 201 having an inverse tapered shape of the first outer peripheral structure 101 during the heat treatment is changed toward the upper side of the semiconductor device 1 compared to before the heat treatment.

[0175] Afterwards, when the heat treatment is completed and the temperature of the resin and the semiconductor device 1 is cooled (if it returns to room temperature), Figure 7 As shown in (c), the warping that causes the back surface of the semiconductor device 1 to bulge is alleviated. As a result, the inclination of the first wall surface 201 of the first peripheral structure 101 that has become an inverted cone after cooling is as shown in FIG. Figure 7 As shown in (b) and (c) of FIG. 1 , the temperature changes toward the lower side of the semiconductor device 1 compared to the heat treatment.

[0176] In this way, the inclination of the first wall surface 201 of the first peripheral structure 101 in the inverted tapered shape changes from the upper side to the lower side of the semiconductor device 1 as the warping of the semiconductor device 1 is relaxed when the heat treatment is completed and the temperature of the resin and the semiconductor device 1 is cooled. Due to this change, the first peripheral structure 101 is more firmly embedded in the resin compared to a structure without the first wall surface 201 in the inverted tapered shape.

[0177] Therefore, according to the semiconductor device 1 of the above-mentioned structure, the first peripheral structure 101 has a first wall surface 201 in the shape of an inverted cone, thereby playing the role of an anchor to more firmly fix the position of the semiconductor device 1 in the resin compared to the structure without the first wall surface 201. As a result, the resin peeling in the mounting substrate is further suppressed and the position of the semiconductor device 1 inside the mounting substrate is further stabilized.

[0178] In addition, based on the same reason, in the semiconductor device 1 according to the above-mentioned structure, the second peripheral structure 102 has a second wall surface in the shape of an inverted cone, which plays the role of anchoring to more firmly fix the position of the semiconductor device 1 in the resin compared to the structure without the second wall surface. As a result, the resin peeling in the mounting substrate is further suppressed and the position of the semiconductor device 1 inside the mounting substrate is further stabilized.

[0179] Furthermore, as described above, in the plan view of the semiconductor layer 40 , the first wall surface 201 is located inside the first tapered region 202 .

[0180] Thus, according to the semiconductor device 1 having the above structure, the first outer peripheral structure 101 is more firmly embedded in the resin than in a structure in which the first wall surface 201 is not located inside the first tapered region 202 .

[0181] Therefore, according to the semiconductor device 1 of the above structure, the first peripheral structure 101 serves as an anchor to more firmly fix the position of the semiconductor device 1 in the resin by locating the first wall 201 inside the first conical region 202 in the plan view of the semiconductor layer 40, compared with a structure in which the first wall 201 is not located inside the first conical region 202 in the plan view of the semiconductor layer 40. As a result, resin peeling in the mounting substrate is further suppressed and the position of the semiconductor device 1 inside the mounting substrate is further stabilized.

[0182] In addition, for the same reason, in the semiconductor device 1 according to the above-mentioned structure, the second peripheral structure 102 is located inside the second conical region in the plan view of the semiconductor layer 40, thereby acting as an anchor for more firmly fixing the position of the semiconductor device 1 in the resin, compared with a structure in which the second wall is not located inside the second conical region in the plan view of the semiconductor layer 40. As a result, resin peeling in the mounting substrate is further suppressed and the position of the semiconductor device 1 inside the mounting substrate is further stabilized.

[0183] However, in the plan view of the semiconductor layer 40 , the first wall surface 201 and the second wall surface in the inverted tapered shape may be in the surrounding inverted tapered shape along the periphery of the first wiring electrode 12 and the second wiring electrode 52 , or may be in the inverted tapered shape only partially along the periphery.

[0184] When only a portion of the first wall surface 201 and the second wall surface along the periphery is formed into an inverted tapered shape, it is preferable to provide the inverted tapered shape in a portion that matches the direction in which the warping of the semiconductor device 1 is the largest. For example, in a plan view of the semiconductor layer 40, when the semiconductor device 1 is a rectangle having a long side direction, the warping in the long side direction becomes the largest warping, and therefore it is preferable to provide the inverted tapered shape in a portion of the first wall surface 201 and the second wall surface that includes a position orthogonal to the long side direction of the semiconductor device 1.

[0185] Figure 8 The plan view of the semiconductor device 1 is a case where the area of ​​the first source electrode 13 is M1, the area of ​​the first opening 61 is S1, and the area of ​​the first wiring electrode exposed portion 71 is P1 in the plan view of the semiconductor layer 40, and the occupancy rate of the area of ​​the first opening 61 relative to the area of ​​the first source electrode 13 represented by S1 / M1 is greater than or equal to 0.5 and less than 1.0 (hereinafter also referred to as the "first case"). Figure 8 and the following Fig.10 The first wiring electrode exposed portion 71 is not shown in the figure, but the area P1 of the first wiring electrode exposed portion 71 in the plan view of the semiconductor layer 40 is Figure 8 and the following Fig.10 The area of ​​? is consistent with that of the first wiring electrode 12.

[0186] Fig. 9 is a cross-sectional view of the semiconductor device 1 in the first case, showing Figure 8 The cross section of III-III in FIG.

[0187] Fig.10 This is a plan view of the semiconductor device 1 in the case where the occupancy rate of the area of ​​the first opening portion 61 represented by S1 / M1 relative to the area of ​​the first source electrode 13 is greater than 0.9 and less than 1.0, and the occupancy rate of the area of ​​the first wiring electrode exposure portion 71 represented by P1 / M1 relative to the area of ​​the first source electrode 13 is greater than 0.5 (hereinafter also referred to as the "second case").

[0188] Fig.11 is a cross-sectional view of the semiconductor device 1 in the second case, showing Fig.10 The cross section of IV-IV in FIG.

[0189] Generally, in a semiconductor device that is face-down mounted using a bonding material such as solder, S1 / M1 is generally considered to be less than 0.5 in order to suppress the occurrence of mounting defects caused by voids in the bonding material.

[0190] In contrast, the semiconductor device 1 of the present invention is mounted face-up without using a bonding material such as solder, so there is no need to worry about poor mounting due to gaps in the bonding material. Therefore, from the perspective of reducing the on-resistance of the semiconductor device 1 and improving the heat dissipation characteristics of the semiconductor device 1, Figure 8 , Fig. 9 As in the example shown, in the semiconductor device 1 , S1 / M1 is preferably equal to or greater than 0.5, that is, S1 / M1 is preferably equal to or greater than 0.5 and less than 1.0.

[0191] The reason why S1 / M1 is preferably less than 1.0 is that, in the plan view of the semiconductor layer 30 , if the area S1 of the first opening 61 is larger than the area M1 of the first source electrode 13 , the first opening 61 is opened to the area of ​​the oxide film 34 not covered by the first source electrode 13 .

[0192] From the viewpoint of reducing the on-resistance of the semiconductor device 1 and improving the heat dissipation characteristics of the semiconductor device 1, further, Fig.10 , Fig.11 As shown in the example, in the semiconductor device 1, it is more preferable that S1 / M1 is greater than 0.9 and less than 1.0, and P1 / M1 is greater than 0.9 and less than 1.1. This is to reduce the on-resistance of the semiconductor device 1 and improve the heat dissipation characteristics of the semiconductor device 1, and to maximize the exposure of the first source electrode 13 to the outside.

[0193] In addition, Fig.10 , Fig.11 In the example shown, in the plan view of the semiconductor layer 40, when the area of ​​the first gate electrode 19 is set to M2, the area of ​​the second opening 62 is set to S2, and the area of ​​the second wiring electrode exposed portion 72 is set to P2, the occupancy rate of the area of ​​the second wiring electrode exposed portion 72 represented by P2 / M2 relative to the area of ​​the first gate electrode 19 is greater than 0.9 and less than 1.1.

[0194] like Fig.10 , Fig.11 As in the illustrated example, it is effective that the occupancy ratio of the area of ​​the second wiring electrode exposed portion 72 to the area of ​​the first gate electrode 19 represented by P2 / M2 is 0.9 or more and 1.1 or less.

[0195] In order to ensure that the second wiring electrode exposure portion 72 is well connected to the external wiring of the semiconductor device 1 via the hole opened in the resin that seals the semiconductor device 1, the area P2 of the second wiring electrode exposure portion 72 in the plan view of the semiconductor layer 40 is preferably larger than the area S2 of the second opening portion 62 in the plan view of the semiconductor layer 40.

[0196] Generally, the second opening 62 is often circular in a plan view of the semiconductor layer 40 . On the other hand, as described above, the semiconductor device 1 is rectangular in a plan view of the semiconductor layer 40 .

[0197] Therefore, when M2 is enlarged relative to S2, the second wiring electrode exposed portion 72 is preferably rectangular in the plan view of the semiconductor layer 40. In this case, the shape of the second wiring electrode exposed portion 72, which is a rectangle larger than S2, is a square circumscribed with the circular second opening 62 in the plan view of the semiconductor layer 40. Here, the square circumscribed with the circle is 1.27 times the area of ​​the circle.

[0198] Therefore, it can be said that the occupancy ratio of the area of ​​the second wiring electrode exposed portion 72 to the area of ​​the second opening 62 represented by P2 / S2 is preferably 1.27 or more.

[0199] In addition, in order to ensure that the first wiring electrode exposed portion 71 is well connected to the external wiring of the semiconductor device 1 via the hole opened in the resin that seals the semiconductor device 1, and to ensure that the second wiring electrode exposed portion 72 is well connected to the external wiring of the semiconductor device 1 via the hole opened in the resin that seals the semiconductor device 1, it is preferred that in the plan view of the semiconductor layer 40, the area of ​​the first wiring electrode 12 and the area of ​​the second wiring electrode 52 are as large as possible, and the shape of the first wiring electrode 12 is equal to the shape of the second wiring electrode 52.

[0200] Fig.12 1 is a plan view showing an example of the structure of the semiconductor device 1 in which the first wiring electrode 12 and the second wiring electrode 52 realize the above-mentioned desired shapes.

[0201] like Fig.12 As shown, in the plan view of the semiconductor layer 40, the shape of the first wiring electrode 12 and the shape of the second wiring electrode 52 are made linearly symmetrical with the center line as the axis of symmetry, and the center line is a shape that divides the semiconductor device 1 into two equal parts in area, thereby realizing the above-mentioned preferred shape of the semiconductor device 1.

[0202] (Implementation Method 2)

[0203] Hereinafter, a semiconductor device according to Embodiment 2 will be described in which the first peripheral structure 101 of the semiconductor device 1 according to Embodiment 1 is changed to the first peripheral structure according to Embodiment 2, and the second peripheral structure 102 is changed to the second peripheral structure according to Embodiment 2.

[0204] Here, regarding the semiconductor device according to the second embodiment, the same components as those of the semiconductor device 1 are given the same reference numerals as those already described, and detailed description thereof is omitted, and the description will focus on the differences from the semiconductor device 1 .

[0205] In addition, in Embodiment 1, it is explained that the protective film 35 of the semiconductor device 1 may be a single-layer structure or a multi-layer structure, but in Embodiment 2, the protective film 35 of the semiconductor device according to Embodiment 2 must be a multi-layer structure. Therefore, the protective film 35 of the semiconductor device according to Embodiment 2 is described below as a multi-layer structure (here, a two-layer structure) in which the first protective film layer 35A and the second protective film layer 35B are stacked.

[0206] <Structure>

[0207] Fig.13 It is a plan view showing an example of the structure of a semiconductor device 1A according to the second embodiment.

[0208] Fig.14 is a cross-sectional view showing an example of the structure of a semiconductor device 1A, showing Fig.14 The cross section at VV in .

[0209] like Fig.13 , 14 As shown, the semiconductor device 1A is configured by changing the first peripheral structure 101 of the semiconductor device 1 according to the first embodiment to a first peripheral structure 101A according to the second embodiment, and changing the second peripheral structure 102 to a second peripheral structure 102A according to the second embodiment.

[0210] More specifically, if Fig.14 As shown, in the semiconductor device 1A, in the peripheral part of the semiconductor layer 40 in the plan view of the first wiring electrode 12, a first peripheral structure 101A is formed in which the first source electrode 13, the first protective film layer 35A, the first wiring electrode 12 and the second protective film layer 35B are stacked in sequence, and in the peripheral part of the semiconductor layer 40 in the plan view of the second wiring electrode 52, a second peripheral structure 102A is formed in which the first gate electrode 19, the first protective film layer 35A, the second wiring electrode 52 and the second protective film layer 35B are stacked in sequence.

[0211] Here, the uppermost layer of the first peripheral structure 101A is the second protective film layer 35B, and the uppermost layer of the second peripheral structure 102A is the second protective film layer 35B.

[0212] Along with the above-mentioned changes, in the semiconductor device 1 involved in embodiment 1, the upper surface of the first wiring electrode 12 is exposed to the outside of the semiconductor device 1 as a whole, and the upper surface of the second wiring electrode 52 is exposed to the outside of the semiconductor device 1 as a whole. Conversely, in the semiconductor device 1A, the portion of the upper surface of the first wiring electrode 12 that is not included in the first peripheral structure 101A is exposed to the outside of the semiconductor device 1A, and the portion of the upper surface of the second wiring electrode 52 that is not included in the second peripheral structure 102A is exposed to the outside of the semiconductor device 1A.

[0213] As described above, in the present invention, the portion of the upper surface of the first wiring electrode 12 exposed to the outside of the semiconductor device 1A is defined as the first wiring electrode exposed portion 71, and the portion of the upper surface of the second wiring electrode 52 exposed to the outside of the semiconductor device 1A is defined as the second wiring electrode exposed portion 72.

[0214] Therefore, in the second embodiment, the first wiring electrode exposed portion 71 is a portion of the upper surface of the first wiring electrode 12 not included in the first peripheral structure 101A, and the second wiring electrode exposed portion 72 is a portion of the upper surface of the second wiring electrode 52 not included in the second peripheral structure 102A.

[0215] That is, in embodiment 2, a portion of the upper surface of the first wiring electrode 12 that is not included in the first peripheral structure 101A, i.e., a first wiring electrode exposed portion 71, is exposed to the outside of the semiconductor device 1A, and a portion of the upper surface of the second wiring electrode 52 that is not included in the second peripheral structure 102A, i.e., a second wiring electrode exposed portion 72, is exposed to the outside of the semiconductor device 1A.

[0216] In addition, in the semiconductor device 1A, similarly to the semiconductor device 1 involved in the first embodiment, in the plan view of the semiconductor layer 40, the area of ​​the first wiring electrode exposed portion 71 is larger than the area of ​​the first opening portion 61, and the area of ​​the second wiring electrode exposed portion 72 is larger than the area of ​​the second opening portion 62.

[0217] like Fig.14 As shown, the first peripheral structure 101A protrudes upward from the upper surface of the first wiring electrode exposure portion 71, and the second peripheral structure 102A protrudes upward from the upper surface of the second wiring electrode exposure portion 72. The top position of the semiconductor device 1A exists in the first peripheral structure 101A and / or the second peripheral structure 102A.

[0218] Here, in order to make the first peripheral structure 101A protrude further upward than the upper surface of the first wiring electrode exposed portion 71, if the thickness of the first wiring electrode 12 in the first peripheral structure 101A is set to the first thickness, and the thickness of the second protective film layer 35B in the first peripheral structure 101A is set to the second thickness, then the second thickness is preferably less than the first thickness.

[0219] This is because, if the second thickness exceeds the first thickness, the second protective film layer 35B uniformly covers the first wiring electrode 12 , and thus it is difficult to form the first peripheral structure 101A.

[0220] As the second thickness becomes larger than the first thickness, the tendency of the second protective film layer 35B to uniformly cover the first wiring electrode 12 increases. Therefore, it is preferable that at least the second thickness is equal to or smaller than the first thickness.

[0221] Similarly, in order to make the second peripheral structure 102A protrude further upward than the upper surface of the second wiring electrode exposed portion 72, if the thickness of the second wiring electrode 52 in the second peripheral structure 102A is set to the third thickness and the thickness of the second protective film layer 35B in the second peripheral structure 102A is set to the fourth thickness, it is preferred that the fourth thickness is less than the third thickness.

[0222] On the other hand, the inventors have repeatedly conducted experiments and studies on the height of the first peripheral structure 101A based on the upper surface of the first wiring electrode exposed portion 71 and the height of the second peripheral structure 102A based on the upper surface of the second wiring electrode exposed portion 72, which are required for the first peripheral structure 101A and the second peripheral structure 102A to be fully embedded in the resin when the semiconductor device 1A is resin-sealed in the mounting substrate and mounted face-up. As a result, the inventors have obtained the following knowledge: if the height of the first peripheral structure 101A based on the upper surface of the first wiring electrode exposed portion 71 is 50% of the thickness of the first wiring electrode 12 at the first opening 61, and the height of the second peripheral structure 102A based on the upper surface of the second wiring electrode exposed portion 72 is 50% of the thickness of the second wiring electrode 52 at the second opening 62, the first peripheral structure 101A and the second peripheral structure 102A can be fully embedded in the resin.

[0223] Here, sufficiently embedding the first peripheral structure 101A and the second peripheral structure 102A into the resin means embedding the first peripheral structure 101A and the second peripheral structure 102A embedded in the resin to a degree that functions as an anchor for fixing the position of the semiconductor device 1A in the resin.

[0224] That is, the inventors have found through experiments and studies that in order to enhance the penetration of the first outer peripheral structure 101A into the resin, if the penetration amount is 10% or more relative to the thickness of the resin, it is effective in obtaining a stable and strong anchoring effect.

[0225] As described later, the thickness of the first wiring electrode 12 must have a sufficient margin in the subsequent step of opening holes in the resin by laser processing or the like, and therefore is required to be at least about 1 / 3 of the thickness of the resin sealed directly thereon.

[0226] Therefore, the desired amount of sinking (the height of the first peripheral structure 101A based on the upper surface of the first wiring electrode exposed portion 71 and the height of the second peripheral structure 102A based on the upper surface of the second wiring electrode exposed portion 72) is at least 30% of the thickness of the first wiring electrode 12, but in the present invention, in order to obtain a more stable and firm anchoring effect, it is set to be more than 50% of the thickness of the first wiring electrode 12.

[0227] In addition, the inventors have reached the following insight: if the height of the first peripheral structure 101A based on the upper surface of the first wiring electrode exposed portion 71 is 50% of the thickness of the first wiring electrode 12 at the first opening 61, and the height of the second peripheral structure 102A based on the upper surface of the second wiring electrode exposed portion 72 is 50% of the thickness of the second wiring electrode 52 at the second opening 62, then protrusions reflecting the first peripheral structure 101A and the second peripheral structure 102A are formed on the upper surface of the resin that solidifies after encapsulating the semiconductor device 1A.

[0228] Therefore, the inventors set the second thickness of the semiconductor device 1A to be larger than half of the first thickness and smaller than the first thickness, and the fourth thickness to be larger than half of the third thickness and smaller than the third thickness.

[0229] However, the second protective film layer 35B is usually formed of viscous polyimide. Therefore, when the second protective film layer 35B is to be formed on a portion having a structure with a height difference such as the first peripheral structure 101A and the second peripheral structure 102A, the polyimide on the upper side of the height difference flows to the lower side of the height difference, so that the second protective film layer 35B of a desired shape may not be formed.

[0230] Therefore, the inventors have repeatedly conducted experiments and studies on the shape of the second protective film layer 35B that can suppress the flow of polyimide on the upper side of the height difference to the lower side of the height difference when forming the first peripheral structure 101A and the second peripheral structure 102A, and the shapes of the first peripheral structure 101A and the second peripheral structure 102A. As a result, the inventors have obtained the following insight, namely, if the minimum width of the portion of the second protective film layer 35B that overlaps with the first wiring electrode 12 in the plan view of the semiconductor layer 40 is greater than the thickness of the portion of the second protective film layer 35B that does not overlap with the first wiring electrode 12 or the second wiring electrode 52 in the plan view of the semiconductor layer 40, then when the first peripheral structure 101A is formed, the polyimide on the upper side of the height difference can be suppressed from flowing to the lower side of the height difference, and if the minimum width of the portion of the second protective film layer 35B that overlaps with the second wiring electrode 52 in the plan view of the semiconductor layer 40 is greater than the thickness of the portion of the second protective film layer 35B that does not overlap with the first wiring electrode 12 or the second wiring electrode 52 in the plan view of the semiconductor layer 40, then when the second peripheral structure 102A is formed, the polyimide on the upper side of the height difference can be suppressed from flowing to the lower side of the height difference.

[0231] Therefore, with respect to the semiconductor device 1A, the inventor believes that the minimum width of the portion overlapping with the first wiring electrode 12 in the plan view of the semiconductor layer 40 is greater than the thickness of the portion of the second protective film layer 35B that does not overlap with the first wiring electrode 12 or the second wiring electrode 52 in the plan view of the semiconductor layer 40, and the minimum width of the portion of the second protective film layer 35B that overlaps with the second wiring electrode 52 in the plan view of the semiconductor layer 40 is greater than the thickness of the portion of the second protective film layer 35B that does not overlap with the first wiring electrode 12 or the second wiring electrode 52 in the plan view of the semiconductor layer 40.

[0232] <Inspection>

[0233] According to the semiconductor device 1A of the above structure, similarly to the case of the semiconductor device 1 involved in embodiment 1, when the semiconductor device 1A is resin-sealed in the mounting substrate and mounted face up, the first peripheral structure 101A and the second peripheral structure 102A are embedded in the resin on the upper surface of the semiconductor device 1A.

[0234] Therefore, first peripheral structure 101A and second peripheral structure 102A sunken into the resin play an anchoring role to fix the position of semiconductor device 1A in the resin, thereby suppressing resin peeling in the mounting substrate and stabilizing the position of semiconductor device 1A inside the mounting substrate.

[0235] Further, similarly to the case of the semiconductor device 1 according to the first embodiment, protrusions reflecting the first peripheral structure 101A and the second peripheral structure 102A are formed on the upper surface of the resin that is cured after the semiconductor device 1A is sealed.

[0236] Therefore, when processing the resin to open a hole from the upper surface of the resin to the first wiring electrode exposed portion 71, the protrusion formed on the upper surface of the resin corresponding to the first peripheral structure 101A is used as a guide line, and the hole opening process is performed on the inner side of the protrusion. As a result, compared with the case where the protrusion does not exist, the hole opening from the upper surface of the resin to the first wiring electrode exposed portion 71 can be performed with higher precision.

[0237] Moreover, similarly, when the resin is processed to open a hole from the upper surface of the resin to the second wiring electrode exposed portion 72, the protrusion formed on the upper surface of the resin corresponding to the second peripheral structure 102A is used as a guide line to open a hole on the inner side of the protrusion, thereby allowing the hole from the upper surface of the resin to reach the second wiring electrode exposed portion 72 to be processed with higher precision compared to a case where the protrusion does not exist.

[0238] Thus, according to the semiconductor device 1A having the above-described structure, similarly to the case of the semiconductor device 1 according to the first embodiment, a semiconductor device having a structure suitable for the mounting method of embedding in a mounting substrate is provided.

[0239] As described above, in the plan view of the semiconductor layer 40 , the area of ​​the first wiring electrode exposed portion 71 is larger than the area of ​​the first opening 61 , and the area of ​​the second wiring electrode exposed portion 72 is larger than the area of ​​the second opening 62 .

[0240] Thus, similar to the case of the semiconductor device 1 involved in embodiment 1, in the plan view of the semiconductor layer 40, the degree of freedom in processing of opening a hole from the upper surface of the resin to the first wiring electrode exposed portion 71 and processing of opening a hole from the upper surface of the resin to the first wiring electrode exposed portion 71 can be improved compared to the case where the area of ​​the first wiring electrode exposed portion 71 is not larger than the area of ​​the first opening portion 61 and the area of ​​the second wiring electrode exposed portion 72 is not larger than the area of ​​the second opening portion 62.

[0241] In addition, similar to the case of the semiconductor device 1 involved in embodiment 1, in the semiconductor device 1A, S1 / M1 is preferably greater than or equal to 0.5, that is, S1 / M1 is preferably greater than or equal to 0.5 and less than 1.0. Furthermore, in the semiconductor device 1A, S1 / M1 is more preferably greater than or equal to 0.9 and less than 1.0, and P1 / M1 is more preferably greater than or equal to 0.9 and less than or equal to 1.1.

[0242] Further, similarly to the case of the semiconductor device 1 according to the first embodiment, in the semiconductor device 1A, it is effective that P2 / M2 is greater than or equal to 0.9 and less than or equal to 1.1.

[0243] Further, similarly to the case of the semiconductor device 1 according to the first embodiment, in the semiconductor device 1A, it can be said that P2 / S2 is preferably equal to or greater than 1.27.

[0244] In addition, similarly to the case of the semiconductor device 1 involved in Embodiment 1, in the semiconductor device 1A, in the plan view of the semiconductor layer 40, the shape of the first wiring electrode 12 and the shape of the second wiring electrode 52 are made line symmetrical with the center line as the axis of symmetry, and the center line is a shape that divides the semiconductor device 1A into two equal parts in area. As a result, the semiconductor device 1A can achieve a preferred shape in terms of enabling the first wiring electrode exposure portion 71 to be well connected to the external wiring of the semiconductor device 1A via the hole opened in the resin that seals the semiconductor device 1A, and enabling the second wiring electrode exposure portion 72 to be well connected to the external wiring of the semiconductor device 1A via the hole opened in the resin that seals the semiconductor device 1A.

[0245] In the second embodiment, the protective film 35 has been described as having a two-layer structure in which the first protective film layer 35A and the second protective film layer 35B are stacked. However, the protective film 35 may have a multi-layer structure in which three or more layers are stacked.

[0246] Fig.15 It is an enlarged cross-sectional view showing an example of the structure of the first outer peripheral structure 101A in the case where the protective film 35 has a three-layer structure.

[0247] like Fig.15 As shown, in the case where the protective film 35 has a three-layer structure, in addition to the first protective film layer 35A and the second protective film layer 35B, the third protective film layer 35C may be stacked between the first protective film layer 35A and the second protective film layer 35B.

[0248] Note that the logic described in the item <Consideration> in the second embodiment may not hold true when the thickness of the first wiring electrode 12 and the second wiring electrode 52 is too thin compared to 10 μm.

[0249] (Implementation method 3)

[0250] Hereinafter, a mounting substrate according to embodiment 3 is described in which the semiconductor device 1 according to embodiment 1 or the semiconductor device 1A according to embodiment 2, or a semiconductor device having the same structure as the semiconductor device 1 or the semiconductor device 1A in terms of the first wiring electrode 12, the second wiring electrode 52, and the protective film 35 (hereinafter also referred to as a "mounting semiconductor device") is mounted face up in an interlayer insulating film.

[0251] Here, regarding the mounting substrate according to the third embodiment, the components of the semiconductor device 1 are assumed to have been already described and are denoted by the same reference numerals, and detailed description thereof is omitted.

[0252] In the third embodiment, the case where the semiconductor device mounted on the mounting substrate of the third embodiment is the semiconductor device 1 is described, but the same is true when the semiconductor device mounted on the mounting substrate of the third embodiment is the semiconductor device 1A or a mounting semiconductor device.

[0253] Fig.16 FIG. 1 is a plan view showing an example of the structure of the mounting substrate 70 according to the third embodiment. Fig.16 As shown, the mounting substrate 70 is a shape having a long side direction. Fig.16 The X-axis direction in FIG. 7 is the long side direction of the mounting substrate 70 .

[0254] Fig.17 It is a cross-sectional view showing an example of the structure of the mounting substrate 70 . Fig.17 express Fig.16 The VI-VI cross section.

[0255] like Fig.16 , Fig.17 As shown, the mounting substrate 70 includes a first wiring layer 76 , an interlayer insulating film 78 , and a second wiring layer 77 , and is configured by stacking the first wiring layer 76 , the interlayer insulating film 78 , and the second wiring layer 77 in this order.

[0256] Here, the case where the mounting substrate 70 includes two wiring layers, the first wiring layer 76 and the second wiring layer 77 , is described. However, the mounting substrate 70 is not limited to the structure including the first wiring layer 76 and the second wiring layer 77 .

[0257] As another configuration example, the mounting substrate 70 may include one or more wiring layers on the lower layer side than the first wiring layer 76 and / or on the upper layer side than the second wiring layer 77 .

[0258] The mounting substrate 70 further includes the semiconductor device 1, the electronic component 81, and one or more first connection wirings 91 (herein, Fig.16 , Fig.17 The four first connection wirings 91A to 91D and the second connection wiring 92 in the second wiring layer 77 include first wiring 96 and second wiring 97 , and the electronic components 82 and 83 are provided on the second wiring layer 77 .

[0259] Here, the semiconductor device 1 is described as being a rectangle having a long side direction and the electronic component 83 is described as being a rectangle having a long side direction. Fig.16 The Y-axis direction in FIG. 1 is the long side direction of the semiconductor device 1. Fig.16 The X-axis direction in φ is the long side direction of the electronic component 83 .

[0260] In addition, Fig.16 , the semiconductor device 1, the electronic component 81, one or more first connecting wirings 91, the second connecting wirings 92, the first wiring electrode 12, and the second wiring electrode 52 are illustrated as being visually recognizable by dotted lines, but in reality, these components cannot be visually recognizable from the outside of the mounting substrate 70.

[0261] The first wiring layer 76 and the second wiring layer 77 are layers for forming wiring for electrically connecting components mounted on the mounting substrate 70 and / or components outside the mounting substrate 70 .

[0262] The interlayer insulating film 78 is an insulating film interposed between the first wiring layer 76 and the second wiring layer 77. Here, a case where the interlayer insulating film 78 is made of resin will be described.

[0263] The semiconductor device 1 is mounted face-up in the interlayer insulating film 78. At this time, the semiconductor device 1 is mounted face-up in the long side direction (here, Fig.16 The Y-axis direction in the figure) and the long side direction of the mounting substrate 70 (here Fig.16 The two components are installed in directions that are orthogonal to each other (the X-axis direction in FIG. 2 ).

[0264] The electronic component 81 is mounted in the interlayer insulating film 78 , and the electronic component 82 is mounted on the second wiring layer 77 .

[0265] The electronic component 83 is mounted on the second wiring layer 77. At this time, in the plan view of the mounting substrate 70, at least a portion of the electronic component 83 overlaps with the semiconductor device 1, and the long side direction (here, Fig.16 The X-axis direction in FIG. 1 and the long side direction in FIG. 1 (in this case, Fig.16 The Y-axis direction) is installed in a mutually orthogonal direction.

[0266] The first wiring 96 is formed in the second wiring layer 77 and is made of, for example, copper, silver, or an alloy thereof.

[0267] The second wiring 97 is formed in the second wiring layer 77 and is made of, for example, copper, silver, or an alloy thereof.

[0268] The one or more first connection wirings 91 are each connected to the first wiring 96 and the upper surface of the first wiring electrode 12 of the semiconductor device 1, and are arranged in a direction perpendicular to the mounting substrate 70 (in this case, Fig.16 , Fig.17 The wiring extending in the Z-axis direction) is made of copper.

[0269] The one or more first connecting wires 91 are each connected to the upper surface of the first wire electrode 12 at a portion of the first wire electrode 12 that does not overlap with the first peripheral structure 101 in a plan view of the semiconductor layer 40 .

[0270] For example, after the semiconductor device 1 is mounted face up in the interlayer insulating film 78, the interlayer insulating film 78 is processed by, for example, laser processing to form a hole that reaches the upper surface of the first wiring electrode 12 from the upper surface of the interlayer insulating film 78, and copper is filled in the hole, thereby forming one or more first connecting wirings 91.

[0271] Each of the one or more first connecting wirings 91 has a circular cross-section perpendicular to the direction in which each of the one or more first connecting wirings 91 extends.

[0272] In addition, here, it is assumed that the one or more first connection wirings 91 are the first connection wirings 91A to 91B.

[0273] Although four first connection wirings 91D are described, the number is not necessarily limited to four, and the number may be one or a plurality other than four.

[0274] If there are a plurality of at least one first connection wiring 91 , even if one of the plurality of first connection wirings 91 is disconnected, the connection between the first wiring electrode 12 and the first wiring 96 can be maintained through the other at least one first connection wiring 91 .

[0275] Furthermore, if there are multiple first connection wirings 91 , the resistance value in the first connection wirings 91 can be reduced and the heat dissipation through the first connection wirings 91 can be more efficient, compared with the case where there is only one first connection wiring 91 .

[0276] The second connection wiring 92 is a wiring that connects the second wiring 97 to the upper surface of the second wiring electrode 52 of the semiconductor device 1 and extends in a direction ( Fig.16 , Fig.17 The wiring extending in the Z-axis direction) is made of copper.

[0277] The second connecting wiring 92 is connected to the upper surface of the second wiring electrode 52 at a portion of the second wiring electrode 52 that does not overlap with the second outer peripheral structure 102 in a plan view of the semiconductor layer 40 .

[0278] The second connecting wiring 92 is formed, for example, by mounting the semiconductor device 1 face up in the interlayer insulating film 78, forming a hole in the interlayer insulating film 78 that reaches the upper surface of the second wiring electrode 52 from the upper surface of the interlayer insulating film 78 by laser processing, and filling the hole with copper.

[0279] Furthermore, at least one of the one or more first connection wirings 91 may have a larger cross section than a second connection wiring 92 described later. This is because, in the first vertical MOS transistor 10 , a current flowing through the first source electrode 13 is larger than a current flowing through the first gate electrode 19 .

[0280] Fig.18 This is an enlarged plan view showing an example of the structure of the mounting substrate 70 in a case where the semiconductor device 1 includes a plurality of first wiring electrodes 12 (here, six first wiring electrodes 12A to 12F).

[0281] In addition, Fig.18 In the figure, the semiconductor device 1, the first wiring electrode 12 (here, the first wiring electrode 12A to the first wiring electrode 12F), the second wiring electrode 52, the first connecting wiring 91 (here, the first connecting wiring 91E to the first connecting wiring 91J), the second connecting wiring 92, etc. are illustrated as being visually recognizable by dotted lines, but in fact, these components cannot be visually recognizable from the outside of the mounting substrate 70.

[0282] like Fig.18 As shown, when the semiconductor device 1 includes a plurality of first wiring electrodes 12, one or more first connection wirings 91 are a plurality of wirings corresponding to each of the plurality of first wiring electrodes 12 in pairs. In this case, each of the plurality of first connection wirings 91 is connected to the first wiring 96 via one of the plurality of first wiring electrodes 12 corresponding to the first connection wiring 91 in pairs.

[0283] At this time, the cross sections of the plurality of first connecting wirings 91 that are perpendicular to the directions in which the plurality of first connecting wirings 91 extend may be equal to each other.

[0284] This makes it possible to relatively easily manufacture the mounting substrate 70 .

[0285] <Inspection>

[0286] As described in the first embodiment, the semiconductor device 1 is a semiconductor device having a structure suitable for the mounting method of embedding and mounting the semiconductor device 1 in the mounting substrate 70 .

[0287] Therefore, according to the mounting substrate 70 having the above-described structure, there is provided a mounting substrate on which the semiconductor device 1 having a structure suitable for the mounting method of embedding the semiconductor device 1 in the mounting substrate 70 is mounted.

[0288] The same applies whether the semiconductor device mounted on the mounting substrate 70 is the semiconductor device 1A or the mounting semiconductor device.

[0289] As described above, in a plan view of the mounting substrate 70 , the mounting substrate 70 has a shape having a long side direction, and the semiconductor device 1 has a shape having a long side direction, and the long side direction of the mounting substrate 70 and the long side direction of the semiconductor device 1 are orthogonal to each other.

[0290] This can suppress the warping of the mounting substrate 70 and the warping of the semiconductor device 1 from mutually promoting each other, which are generated during the heat treatment in the manufacturing process of the mounting substrate 70 .

[0291] In addition, as described above, in the plan view of the mounting substrate 70, the electronic component 83 that at least partially overlaps with the semiconductor device 1 has a shape with a long side direction, and the semiconductor device 1 has a shape with a long side direction. The long side direction of the electronic component 83 is orthogonal to the long side direction of the semiconductor device 1.

[0292] This can suppress the warping of the electronic component 83 and the warping of the semiconductor device 1 from mutually promoting each other, which is generated during the heat treatment in the manufacturing process of the mounting substrate 70 .

[0293] In the mounting substrate 70 , the height to the uppermost position of the semiconductor device 1 based on the lowest position on the upper surface of the first wiring electrode 12 may be 15% or more of the length of one or more first connecting wirings 91 in a direction perpendicular to the mounting substrate 70 .

[0294] The length of the first connecting wiring 91 is equal to the thickness of the resin sealed just above the semiconductor device 1 .

[0295] The height to the uppermost position of the semiconductor device 1 based on the lowest position on the upper surface of the first wiring electrode 12 is the amount of penetration into the resin. In the present invention, it is assumed that 50% of the thickness of the first wiring electrode 12 is ensured.

[0296] As described above, since the thickness of the first wiring electrode 12 is 1 / 3 or more of the thickness of the resin, a sufficient anchoring effect can be obtained when the amount of depression is 1 / 3×0.5(50%)=1 / 6≈0.15 of the thickness of the resin, that is, 15% or more.

[0297] Thus, a protrusion reflecting the first peripheral structure 101 is formed on the upper surface of the interlayer insulating film 78, and during the formation of the first connecting wiring 91, by laser processing the mounting substrate 70, it is possible to ensure sufficient margin for the thickness of the first wiring electrode 12 when forming a hole reaching the upper surface of the first wiring electrode 12 from the upper surface of the interlayer insulating film 78.

[0298] (Replenish)

[0299] The semiconductor device and mounting substrate according to one embodiment of the present invention are described above based on Embodiments 1 to 3, but the present invention is not limited to these embodiments. As long as it does not deviate from the gist of the present invention, various modifications that can be thought of by those skilled in the art to these embodiments and combinations of constituent elements in different embodiments may also be included in the scope of one or more embodiments of the present invention.

[0300] [Industrial Applicability]

[0301] The present invention can be widely used in semiconductor devices, mounting substrates, and the like.

[0302] Explanation of symbols

[0303] 1. 1A semiconductor device

[0304] 10First vertical MOS transistor

[0305] 12, 12A, 12B, 12C, 12D, 12E, 12F first wiring electrodes

[0306] 13 first source electrode

[0307] 14First source region

[0308] 15 first gate conductor

[0309] 16 first gate insulating film

[0310] 18 First Body Region

[0311] 19 first gate electrode

[0312] 20 Second vertical MOS transistor

[0313] 22 third wiring electrode

[0314] 23 second source electrode

[0315] 24 Second source region

[0316] 25 second gate conductor

[0317] 26 second gate insulating film

[0318] 28 Second body region

[0319] 29 second gate electrode

[0320] 30 metal layers

[0321] 32Semiconductor substrate

[0322] 33 Low concentration impurity layer

[0323] 34 Oxide film

[0324] 35 protective film

[0325] 35A first protective film layer

[0326] 35B second protective film layer

[0327] 35C third protective film layer

[0328] 40 semiconductor layer

[0329] 52 second wiring electrode

[0330] 54 fourth wiring electrode

[0331] 61 first opening

[0332] 62 second opening

[0333] 63 Third opening

[0334] 64 Fourth opening

[0335] 70 Mounting Base Plate

[0336] 71 first wiring electrode exposed portion

[0337] 72 Second wiring electrode exposed portion

[0338] 76 First wiring layer

[0339] 77 Second wiring layer

[0340] 78 interlayer insulation film

[0341] 81, 82, 83 electronic parts

[0342] 91, 91A, 91B, 91C, 91D, 91E, 91F, 91G, 91H, 91I, 91J first connection wiring

[0343] 92 Second connection wiring

[0344] 96 First Wiring

[0345] 97 Second Wiring

[0346] 101, 101A first peripheral structure

[0347] 102, 102A Second peripheral structure

[0348] 201 First Wall

[0349] 202 first cone-shaped area

Claims

1. A semiconductor device, It is a semiconductor device of chip size package type that can be mounted face up and has: Semiconductor layer; A vertical MOS transistor is formed in the semiconductor layer, wherein the vertical MOS transistor is a vertical metal oxide semiconductor transistor; a protective film covering the upper surface of the vertical MOS transistor, having a first opening for exposing a source electrode of the vertical MOS transistor to the outside of the protective film, and a second opening for exposing a gate electrode of the vertical MOS transistor to the outside of the protective film; a first wiring electrode connected to the source electrode, mainly composed of copper, and seamlessly covering a portion of the source electrode in the first opening that is exposed to the outside of the protective film; and a second wiring electrode connected to the gate electrode, mainly composed of copper, and seamlessly covering a portion of the gate electrode exposed to the outside of the protective film in the second opening; In a plan view of the semiconductor layer, the semiconductor device is rectangular, A first peripheral structure in which the source electrode, the protective film, and the first wiring electrode are sequentially stacked is formed at the peripheral portion of the first wiring electrode in a plan view of the semiconductor layer. The uppermost layer of the first peripheral structure is the first wiring electrode, A second peripheral structure in which the gate electrode, the protective film, and the second wiring electrode are sequentially stacked is formed at the peripheral portion of the second wiring electrode in a plan view of the semiconductor layer. The uppermost layer of the second peripheral structure is the second wiring electrode, A first wiring electrode exposed portion, which is an upper surface of the first wiring electrode, is exposed to the outside of the semiconductor device. A second wiring electrode exposed portion, which is an upper surface of the second wiring electrode, is exposed to the outside of the semiconductor device. The first peripheral structure protrudes upward from the upper surface of a portion of the first wiring electrode exposed portion that is not included in the first peripheral structure. The second peripheral structure protrudes upward from the upper surface of a portion of the second wiring electrode exposed portion that is not included in the second peripheral structure. The uppermost position of the semiconductor device exists in the first peripheral structure and / or the second peripheral structure. In a plan view of the semiconductor layer, an area of ​​the first wiring electrode exposed portion is larger than an area of ​​the first opening portion, In a plan view of the semiconductor layer, the area of ​​the second wiring electrode exposed portion is larger than the area of ​​the second opening portion, When the area of ​​the semiconductor layer in a plan view of the semiconductor layer is set to S [mm 2 ], when the thickness from the lower surface of the semiconductor layer to the upper surface of the protective film is set to h [mm], the relationship of h / S≧0.025 holds.

2. The semiconductor device according to claim 1, further comprising a metal layer formed in contact with the lower surface of the semiconductor layer, The thickness of the metal layer is thicker than the maximum thickness of the first wiring electrode, In the outer peripheral portion of the semiconductor layer in a plan view, the first wiring electrode has a wall surface that is in an inversely tapered shape toward the outside of the first wiring electrode in a cross-sectional view of the semiconductor layer. The wall surface does not contact the protective film.

3. The semiconductor device according to claim 2, The protective film has a tapered region that tapers toward the first opening in the cross-sectional view in a portion surrounding the first opening in the plan view of the semiconductor layer. In a plan view of the semiconductor layer, the wall surface is located inside the tapered region.

4. A semiconductor device, It is a semiconductor device of chip size package type that can be mounted face up and has: Semiconductor layer; A vertical MOS transistor is formed in the semiconductor layer; a protective film covering the upper surface of the vertical MOS transistor, having a first opening for exposing a source electrode of the vertical MOS transistor to the outside of the protective film, and a second opening for exposing a gate electrode of the vertical MOS transistor to the outside of the protective film; a first wiring electrode connected to the source electrode, mainly composed of copper, and seamlessly covering a portion of the source electrode in the first opening that is exposed to the outside of the protective film; and a second wiring electrode connected to the gate electrode, mainly composed of copper, and seamlessly covering a portion of the gate electrode exposed to the outside of the protective film in the second opening; In a plan view of the semiconductor layer, the semiconductor device is rectangular, The protective film has a multilayer structure consisting of a plurality of protective film layers including a first protective film layer and a second protective film layer located above the first protective film layer. A first peripheral structure in which the source electrode, the first protective film layer, the first wiring electrode, and the second protective film layer are sequentially stacked is formed at the peripheral portion of the first wiring electrode in a plan view of the semiconductor layer. The uppermost layer of the first peripheral structure is the second protective film layer, A second peripheral structure in which the gate electrode, the first protective film layer, the second wiring electrode and the second protective film layer are sequentially stacked is formed at the peripheral portion of the second wiring electrode in a plan view of the semiconductor layer, The uppermost layer of the second peripheral structure is the second protective film layer, A first wiring electrode exposed portion, which is a portion of the upper surface of the first wiring electrode not included in the first peripheral structure, is exposed to the outside of the semiconductor device. A second wiring electrode exposed portion, which is a portion of the upper surface of the second wiring electrode not included in the second peripheral structure, is exposed to the outside of the semiconductor device. The first peripheral structure protrudes upward from the upper surface of the first wiring electrode exposed portion. The second peripheral structure protrudes upward from the upper surface of the second wiring electrode exposed portion. The uppermost position of the semiconductor device exists in the first peripheral structure and / or the second peripheral structure. If the thickness of the first wiring electrode in the first peripheral structure is set to a first thickness, and the thickness of the second protective film layer in the first peripheral structure is set to a second thickness, Then the second thickness is greater than half of the first thickness and less than the first thickness, and in the cross-sectional view In a plan view of the semiconductor layer, an area of ​​the first wiring electrode exposed portion is larger than an area of ​​the first opening portion, In a plan view of the semiconductor layer, an area of ​​the second wiring electrode exposed portion is larger than an area of ​​the second opening portion.

5. The semiconductor device according to claim 4, The minimum width of a portion of the second protective film layer that overlaps with the first wiring electrode in a plan view of the semiconductor layer is greater than the thickness of a portion of the second protective film layer that does not overlap with the first wiring electrode or the second wiring electrode in a plan view of the semiconductor layer, The minimum width of a portion of the second protective film layer that overlaps with the second wiring electrode in a plan view of the semiconductor layer is greater than the thickness of a portion of the second protective film layer that does not overlap with the first wiring electrode or the second wiring electrode in a plan view of the semiconductor layer.

6. The semiconductor device according to claim 4, The height of the first peripheral structure based on the upper surface of the first wiring electrode exposed portion is 50% or more of the thickness of the first wiring electrode in the first opening. The height of the second outer peripheral structure based on the upper surface of the second wiring electrode exposed portion is equal to or greater than 50% of the thickness of the second wiring electrode in the second opening.

7. The semiconductor device according to claim 1 or 4, When the area of ​​the source electrode in a plan view of the semiconductor layer is M1 and the area of ​​the first opening in a plan view of the semiconductor layer is S1, A first occupancy ratio, which is a ratio of an area of ​​the first opening in a plan view of the semiconductor layer to an area of ​​the source electrode in a plan view of the semiconductor layer, represented by S1 / M1, is 0.5 or more and less than 1.

0.

8. The semiconductor device according to claim 7, The first occupancy ratio is greater than or equal to 0.9 and less than 1.0, When the area of ​​the first wiring electrode exposed portion in a plan view of the semiconductor layer is denoted as P1, A second occupancy ratio, which is a ratio of the area of ​​the first wiring electrode exposed portion in a plan view of the semiconductor layer to the area of ​​the source electrode in a plan view of the semiconductor layer, represented by P1 / M1, is greater than or equal to 0.9 and less than or equal to 1.

1.

9. The semiconductor device according to claim 1 or 4, When the area of ​​the second opening in a plan view of the semiconductor layer is S2 and the area of ​​the second wiring electrode exposed portion in a plan view of the semiconductor layer is P2, A third occupancy ratio, which is a ratio of the area of ​​the second wiring electrode exposed portion in a plan view of the semiconductor layer to the area of ​​the second opening in a plan view of the semiconductor layer, represented by P2 / S2, is 1.27 or more.

10. The semiconductor device according to claim 9, In a plan view of the semiconductor layer, The shape of the first wiring electrode and the shape of the second wiring electrode are line symmetric with the center line as the axis of symmetry. The center line divides the semiconductor device into two equal parts in area.

11. A mounting substrate, A mounting substrate having a first wiring layer, an interlayer insulating layer, and a second wiring layer stacked in sequence, comprising: The semiconductor device according to claim 1 or 4, mounted face-up in the interlayer insulating layer; A first wiring is formed in the second wiring layer; and One or more first connecting wirings connect the first wiring to the upper surface of the first wiring electrode and extend in a direction orthogonal to the mounting substrate. The one or more first connecting wirings are connected to a portion of the upper surface of the first wiring electrode that does not overlap with the first peripheral structure in a plan view of the semiconductor layer.

12. The mounting substrate according to claim 11, further comprising: A second wiring is formed in the second wiring layer; and a second connecting wiring connecting the second wiring and the upper surface of the second wiring electrode, extending in a direction orthogonal to the mounting substrate, the second connecting wiring being connected to a portion of the upper surface of the second wiring electrode that does not overlap with the second peripheral structure in a plan view of the semiconductor layer, A cross section of each of the one or more first connection wirings perpendicular to the direction in which each of the one or more first connection wirings extends and a cross section of the second connection wiring perpendicular to the direction in which the second connection wiring extends are circular, A cross-section of at least one of the one or more first connecting wirings is larger than a cross-section of the second connecting wiring.

13. A mounting substrate, A mounting substrate having a first wiring layer, an interlayer insulating layer, and a second wiring layer stacked in sequence, comprising: a semiconductor device mounted face-up in the interlayer insulating layer and having a semiconductor layer, the semiconductor device having a first wiring electrode on an upper surface; A first wiring is formed in the second wiring layer; as well as one or more first connecting wirings, connecting the first wiring to the upper surface of the first wiring electrode and extending in a direction perpendicular to the mounting substrate, The semiconductor device has a first peripheral structure formed on a peripheral portion of the first wiring electrode in a plan view of the semiconductor layer. The first peripheral structure protrudes upward from a portion of the upper surface of the first wiring electrode that does not overlap with the first peripheral structure in a plan view of the semiconductor layer. The uppermost position of the semiconductor device is located in the first peripheral structure, At least a portion of the upper surface of the first wiring electrode that does not overlap with the first peripheral structure in a plan view of the semiconductor layer is exposed to the outside of the semiconductor device. The one or more first connecting wirings are connected to a portion of the upper surface of the first wiring electrode of the semiconductor device that does not overlap with the first peripheral structure in a plan view of the semiconductor layer.

14. The mounting substrate according to claim 11 or 13, The one or more first connecting wirings are plural in number.

15. The mounting substrate according to claim 11 or 13, A height from the lowest position on the upper surface of the first wiring electrode to the uppermost position of the semiconductor device is equal to or greater than 15% of a length of the one or more first connecting wirings in a direction perpendicular to the mounting substrate.

16. The mounting substrate according to claim 11 or 13, There are a plurality of first wiring electrodes, The one or more first connecting wirings are a plurality of wirings corresponding to each of the plurality of first wiring electrodes in pairs. Each of the plurality of first connecting wirings is connected to the first wiring through one of the plurality of first wiring electrodes corresponding to the first connecting wiring in a pair. The cross sections of the plurality of first connecting wirings that are perpendicular to the directions in which the plurality of first connecting wirings extend are equal to each other.

17. The mounting substrate according to claim 11 or 13, In a plan view of the mounting substrate, The mounting substrate has a shape having a long side direction, The semiconductor device has a shape having a long side direction, The longitudinal direction of the mounting substrate and the longitudinal direction of the semiconductor device are orthogonal to each other.

18. The mounting substrate according to claim 11 or 13, further comprising an electronic component disposed above the interlayer insulating layer, In a plan view of the mounting substrate, The electronic component has a shape with a long side direction, The semiconductor device has a shape having a long side direction, At least a portion of the electronic component overlaps with the semiconductor device, The longitudinal direction of the electronic component and the longitudinal direction of the semiconductor device are orthogonal to each other.

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