Small-profile packaged integrated circuit testing device and use method thereof

Abstract

The invention provides a small-profile packaged integrated circuit testing device and a using method thereof, and belongs to the technical field of integrated circuit testing. The small-profile packaged integrated circuit testing device comprises a testing probe assembly, a substrate and a cover plate. The test probe assembly comprises a plurality of test probes and a probe fixing block. Each test probe comprises a probe contact, a probe extension needle, a probe guide needle and a probe contact. The probe contact is connected with the probe extension needle, the tail end of the probe extension needle is connected with the probe guide needle, the probe guide needle is connected with the probe contact, and the plurality of test probes are designed according to an upper and lower layer layout and are divided into an upper layer test probe and a lower layer test probe through the probe fixing block. The problems that in the prior art, in the integrated circuit finished product testing process, the number of mistakenly-tested products is large in the first-time testing process, and the testing yield is low in the first-time testing process are solved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit testing, and in particular relates to a small-outline package integrated circuit testing device and a use method thereof. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, the integration of integrated circuits is getting higher and higher, and the functions are becoming more and more complex. In the production process of integrated circuits, testing is an important link to ensure the quality and performance of integrated circuits. The final test is to use the combination of testers (ATE), handlers (Handler), test boards (DUT) and test probes (Finger) to test each integrated circuit product. The resources of the tester test the integrated circuit product. First, the gold finger of the test board is connected to one end of the test probe, and the other end of the test probe is directly in contact with the pin of the integrated circuit product, and then the integrated circuit product is tested.

[0003] However, in the manufacturing process of integrated circuit packaging, due to the differences in packaging process technology, the soldering plane of the packaged integrated circuit pins is reduced, there are differences in the height difference between each pin and the bottom of the plastic package, and the characteristics of the electroplating process are different, which not only leads to poor contact between the probe and the integrated circuit pins, but also leads to a large number of mistested products and a low test yield in the first test during the integrated circuit finished product test (Final Test, FT). Summary of the invention

[0004] The purpose of the present invention is to provide a small-outline package integrated circuit testing device and a method of using the same, which are used to solve the problems of a large number of mistested products and a low test yield during the first test in the process of testing integrated circuit finished products in the prior art.

[0005] In order to achieve the above object, the present invention adopts the following technical solution: In a first aspect, the present invention provides a small outline package integrated circuit test device, including a test probe assembly, a substrate and a cover plate; The test probe assembly includes a plurality of test probes and a probe fixing block, each test probe includes a probe contact, a probe extension needle, a probe guide needle and a probe contact, the probe contact is connected to the probe extension needle, the end of the probe extension needle is connected to the probe guide needle, and the probe guide needle is connected to the probe contact, and the plurality of test probes are designed according to an upper and lower layer layout, and are divided into an upper layer test probe and a lower layer test probe by the probe fixing block, wherein an upper layer test probe and a lower layer test probe form a group of test probes; The test probe assembly is arranged on a base plate, the upper surface of the base plate is provided with a sinking groove corresponding to the cover plate, the base plate is provided with a plurality of test probe guide grooves, and the cover plate is provided with a plurality of corresponding probe contact limiting grooves.

[0006] A further improvement of the present invention is that the upper surface of the substrate is also provided with screw through holes corresponding to the cover plate.

[0007] A further improvement of the present invention is that a plurality of positioning through holes are also provided on the upper surface of the substrate.

[0008] A further improvement of the present invention is that the lower surface of the cover plate is also provided with protrusions corresponding to the substrate.

[0009] A further improvement of the present invention is that the probe contact is provided with a probe contact contact blade surface.

[0010] A further improvement of the present invention is that insulating material is filled between each group of test probes.

[0011] A further improvement of the present invention is that the insulating material is peek material, insulating glue or mica sheet. In a second aspect, the present invention provides a method for using a small outline package integrated circuit test device, comprising the following steps: Prepare small outline package integrated circuit test equipment and integrated circuit products to be tested; placing the integrated circuit product to be tested on the small outline package integrated circuit test device; Adjust the position of the probe tip so that the probe tip is in close contact with the integrated circuit product to be tested; Starting the tester to perform the test, applying a test signal to the integrated circuit product to be tested through the small outline package integrated circuit test device, and receiving a response signal from the integrated circuit product to be tested; Analyzing the test results according to the response signal of the integrated circuit product to be tested; Determine whether the performance of the tested integrated circuit meets the preset standard according to the test results; If the integrated circuit product to be tested does not meet the preset standard, the testing of the integrated circuit product to be tested is stopped.

[0012] A further improvement of the present invention is that the probe contact (1) is provided with a probe contact contact blade surface.

[0013] A further improvement of the present invention is that the integrated circuit product is an integrated circuit product of a SOT series small outline package.

[0014] Compared with the prior art, the present invention has the following beneficial effects: The present invention belongs to an improved invention. Compared with the existing small-profile packaged integrated circuit test device, the small-profile packaged integrated circuit test device proposed by the present invention is designed with a test probe assembly, a substrate and a cover plate. The test probe assembly includes a plurality of test probes and a probe fixing block, and each test probe includes a probe contact, a probe extension needle, a probe guide needle and a probe contact. The test probe in the small-profile packaged integrated circuit test device of the present invention has a long service life and a relatively low cost. The test probe contact can pierce the pins of the integrated circuit product to achieve good contact. The probe extension needle provides support for the probe contact, and the probe guide needle provides continuous pressure for the probe extension contact and the pins of the integrated circuit product, so that the probe contact and the pins of the integrated circuit product achieve good contact under the pressure of the elasticity of the probe extension needle, thereby reducing the problem of contact failure between the probe contact and the pins of the integrated circuit product, thereby not only improving the accuracy of product testing, but also improving the qualified rate of the product, thereby effectively solving the problem of a large number of mistested products and a low test yield in the first test during the test of the integrated circuit finished product in the prior art.

[0015] Furthermore, the present invention also discloses that the probe contact is provided with a probe contact blade surface. During testing, the probe contact is embedded into the inside of the integrated circuit product pin through the probe contact blade surface to achieve contact. The probe guide needle can increase the contact pressure between the probe contact and the integrated circuit product pin, thereby increasing the effective contact area between the probe contact and the integrated circuit product pin, thereby improving the accuracy of integrated circuit product testing.

[0016] Furthermore, the present invention also discloses that insulating materials are filled between each group of test probes, which can effectively ensure that insulation is formed between each group of test probes. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a three-dimensional schematic diagram of the overall structure of the small outline package integrated circuit testing device of the present invention; Figure 2 It is a schematic plan view of the overall structure of the small outline package integrated circuit test device of the present invention; Figure 3 It is a three-dimensional schematic diagram of the assembly structure of the substrate and the test probe assembly in the small outline package integrated circuit test device of the present invention; Figure 4 It is a three-dimensional schematic diagram of a substrate, a cover plate and a probe fixing block in a small outline package integrated circuit test device of the present invention; Figure 5 It is a schematic diagram of the structure of a test probe assembly in a small outline package integrated circuit test device of the present invention; Figure 6 It is a schematic diagram of the structure of three groups of test probes in the small outline package integrated circuit test device of the present invention; Figure 7 It is a schematic diagram of the structure of the first group of test probes in the small outline package integrated circuit test device of the present invention; Figure 8 It is a schematic diagram of the structure of the second group of test probes in the small outline package integrated circuit test device of the present invention; Fig. 9 It is a schematic diagram of the structure of the third group of test probes in the small outline package integrated circuit test device of the present invention; Fig.10 A schematic diagram of a guide for installing a test probe in a small outline package integrated circuit test device of the present invention; Fig.11 It is a schematic diagram of the structure of the probe contact in the small outline package integrated circuit test device of the present invention; Fig.12 It is a schematic diagram of the probe contact structure in the small outline package integrated circuit test device of the present invention; Fig.13 It is a schematic diagram of the structure of the probe contact in the small outline package integrated circuit test device of the present invention contacting the integrated circuit product pin; In the figure: 1. probe contact; 2. probe extension needle; 3. probe guide needle; 4. probe contact; 5. substrate; 6. cover plate; 7. sink groove; 8. bump; 9. positioning through hole; 10. screw through hole; 11. third group of test probes; 12. second group of test probes; 13. first group of test probes; 14. integrated circuit product pins; 15. guide groove; 16. limit groove; 17. probe fixing block. DETAILED DESCRIPTION

[0018] In order to further understand the content of the present invention, the present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the embodiments are only for explaining the present invention and are not intended to limit it.

[0019] The small-outline packaged integrated circuit test device proposed by the present invention is designed. Compared with the prior art, the present invention effectively solves the problems of many mistested products and low test yield in the first test during the test of finished integrated circuits in the prior art.

[0020] Embodiment 1: This embodiment discloses a small-outline package integrated circuit test device. The three-dimensional schematic diagram and the planar schematic diagram of the overall structure of the small-outline package integrated circuit test device of this embodiment are shown in FIG. Figure 1 and Figure 2 As shown, the technical solution of this embodiment is specifically described as follows: The small outline package integrated circuit test device of this embodiment includes a test probe assembly, a substrate 5 and a cover plate 6. A three-dimensional schematic diagram of the assembly structure of the substrate and the test probe assembly is shown in FIG. Figure 3As shown. The test probe assembly includes a plurality of test probes (the test probe assembly in this embodiment includes 6 test probes) and a probe fixing block 17, each test probe includes a probe contact 1, a probe extension needle 2, a probe guide needle 3 and a probe contact 4. The plurality of test probes are designed according to the upper and lower layer layout, and are divided into upper layer test probes and lower layer test probes by the probe fixing block 17, wherein one upper layer test probe and one lower layer test probe constitute a group of test probes. The three-dimensional structures of the substrate 5, the cover plate 6 and the probe fixing block 17 are respectively as shown in Figure 4 a. Figure 4 b and Figure 4 c. The structure of the test probe assembly is shown in Figure 5 shown.

[0021] The probe fixing block 17 divides the plurality of test probes into upper test probes and lower test probes, and fixes them into three rows. The test probes of this embodiment specifically include three rows of test probes (also called three groups of test probes, and the structure of the overall three groups of test probes is as follows: Figure 6 As shown, the structures of each group of test probes are as follows Figure 7 , Figure 8 and Fig. 9 As shown in the figure, each row of test probes includes lower test probes and upper test probes, which will not affect the electrical signal during the integrated circuit test process. Each row of test probes serves as a group of FORCE test probes and SENSE test probes for the integrated circuit pin test. The schematic diagram of the test probe guide for the small package integrated circuit test device is shown in the figure. Fig.10 shown.

[0022] The probe contact 1 includes two groups of front and rear probe contacts, which serve as the FORCE end and the SENSE end of the Kelvin test respectively. During the test, when the integrated circuit is pressed down to the probe contact 1, the FORCE end and the SENSE end will not be short-circuited. On the contact pin probe contact 1, the probe contact 1 is set to be in the shape of a knife edge. When the integrated circuit contacts the probe contact 1, it can pierce the plating of the integrated circuit pin and contact the inside of the integrated circuit pin to achieve good contact. The structural schematic diagram of the probe contact 1 is shown in FIG. Fig.11 shown.

[0023] One end of the probe extension needle 2 is connected to the probe contact 1, and the other end of the probe extension needle 2 is connected and fixed to the probe guide needle 3. The structure consists of an upper and lower layer of probes, and the upper and lower layers serve as the FORCE end and SENSE end of the Kelvin test respectively. During the test, when the integrated circuit is pressed down to the probe contact 1, the FORCE end and the SENSE end will not be short-circuited.

[0024] One end of the probe guide pin 3 is connected to the probe extension pin 2, and the other end of the probe guide pin 3 is connected to the probe contact 4, which is fixed inside the probe fixing block 17. After the six test probes extend out of the probe guide block, they extend and bend to the six guide points respectively. After the test board is fixed to the small outline package integrated circuit test device, the probe contact 4 sinks, and under the limiting effect of the substrate 5, a good contact between the probe contact 4 and the test board is achieved.

[0025] The probe contact 4 is connected to one end of the probe guide pin 3. After the test board is fixed to the test structure, good surface-to-surface contact between the test board and the test probe is achieved. Moreover, under the action of a 10 ampere (A) pulse current, good testing of the integrated circuit signal can be achieved. The structural diagram of the probe contact 4 is shown in FIG. Fig.12 shown.

[0026] The relevant dimensions of the probe contact 1, the probe extension needle 2, the probe guide needle 3 and the probe contact 4 of this embodiment are specifically described as follows: The dimensions of the probe contact 1 are 1.3mm in height, 0.6mm in needle width, 0.35mm in bottom thickness, and 0.1mm in top thickness. The dimensions of the probe extension needle 2 are 5.2mm in length, 0.6mm in needle width, and 0.35mm in thickness. The dimensions of the probe guide needle 3 are 5.2mm in length, 0.6mm in needle width, and 0.35mm in thickness. The dimensions of the probe contact 4 are 1.5mm in length, 1.5mm in width, and 0.8mm in thickness. The probe contact 4 protrudes 0.2mm from the probe cover.

[0027] The test probe assembly is arranged on the substrate 5 , and the upper surface of the substrate 5 is provided with a sinking groove corresponding to the cover plate 6 (in this embodiment, the upper surface of the substrate 5 is specifically provided with 4 sinking grooves corresponding to the cover plate 6 ) to achieve an inlay connection with the cover plate 6 . Several test probe guide grooves are arranged on the substrate 5 (in this embodiment, six test probe guide grooves 15 are arranged on the substrate 5). The probe guide grooves are divided into two layers, the upper layer probe guide needles and the lower layer probe guide needles are used as the FORCE and SENSE end probes of the Kelvin test respectively.

[0028] The cover plate 6 is provided with a plurality of corresponding probe contact limiting grooves (in this embodiment, the cover plate 6 is specifically provided with six corresponding probe contact limiting grooves 16). When the test board is fixed to the small form factor package integrated circuit test device, the probe contact 4 sinks, and under the limiting and supporting effect of the cover plate 6, a good contact between the probe contact 4 and the test board is achieved.

[0029] The upper surface of the substrate 5 is also provided with screw through holes corresponding to the cover plate 6 (in this embodiment, the upper surface of the substrate 5 is specifically provided with three 1.5 mm screw through holes corresponding to the cover plate 6), so as to realize the fixed connection between the test board, the small form factor package integrated circuit test device and the test base. The test base is used to fix the test board, and the small form factor package integrated circuit test device is fixed on the test board.

[0030] The upper surface of the substrate 5 is also provided with a plurality of positioning through holes (in this embodiment, the upper surface of the substrate 5 is specifically provided with two 1 mm and two 1.5 mm positioning through holes) to realize the positioning connection of the test board, the small outline package integrated circuit test device and the test base.

[0031] The lower surface of the cover plate 6 is further provided with protrusions 8 corresponding to the substrate 5 (in this embodiment, the lower surface of the cover plate 6 is specifically provided with four protrusions 8 corresponding to the substrate 5 ) to achieve an inlay connection with the substrate 5 .

[0032] The probe contact 1 is provided with a probe contact blade. During testing, the probe contact 1 is embedded into the integrated circuit product pin 14 through the probe contact blade to achieve contact. The probe guide needle 3 can increase the contact pressure between the probe contact 1 and the integrated circuit product pin 14, thereby increasing the effective contact area between the probe contact 1 and the integrated circuit product pin 14. The probe contact 1 is embedded into the integrated circuit product pin 14 through the probe contact blade, which can also solve the problem of increased contact resistance of the test probe caused by oxidation of the integrated circuit plating and tin or foreign matter on the test probe. The three-dimensional schematic diagram and planar schematic diagram of the probe contacting the integrated circuit product pin 14 are shown in Fig.13 a and Fig.13 As shown in b.

[0033] Insulating materials are filled between each group of test probes to ensure insulation between each group of test probes (the first group of test probes 13, the second group of test probes 12 and the third group of test probes 11). The insulating materials are peek materials, insulating glue or mica sheets. In order to verify the contact quality between the small form factor package integrated circuit test device proposed by the present invention and the integrated product to be tested and the test board, the present embodiment also performs a Kelvin test. The specific description of the Kelvin test is as follows: The Kelvin test is not only an important basis for checking whether the contact between the IC product pin 14 and the test probe is good, but also the key to subsequent telecommunication function testing. The Kelvin test improves the reliability of IC testing by changing the contact scheme between the IC pin and the test probe. The process of the Kelvin test is described as follows: Two traces are drawn from the pins of the integrated circuit, and these two traces are called the FORCE terminal and the SENSE terminal. The FORCE terminal is used for input or output, and the SENSE terminal is used to measure the current value or voltage value of the integrated circuit pin. Under the premise of good contact, each pin of the integrated circuit is pressed on the corresponding FORCE terminal and SENSE terminal, and each pin of the integrated circuit will contact with two test probes. When a pin of the integrated circuit is not in good contact with the two corresponding test probes, the resistance between the two test probes will increase, so the resistance value can be used to reflect whether the integrated circuit is placed well.

[0034] Embodiment 2: This embodiment discloses a method for using a small outline package integrated circuit test device. The method for using the small outline package integrated circuit test device of this embodiment includes the following steps: Prepare small outline package integrated circuit test equipment and integrated circuit products to be tested; Placing the integrated circuit product to be tested on a small outline package integrated circuit test device, wherein the integrated circuit product to be tested is an integrated circuit product of a SOT series small outline package; Adjust the position of the probe contact 1 so that the probe contact 1 is in close contact with the integrated circuit product to be tested; Starting the tester to perform the test, applying a test signal to the integrated circuit product to be tested through the small outline package integrated circuit test device, and receiving a response signal from the integrated circuit product to be tested; Analyzing the test results according to the response signal of the integrated circuit product to be tested; Determine whether the performance of the tested integrated circuit meets the preset standard according to the test results; If the integrated circuit product to be tested does not meet the preset standard, the detection of the integrated circuit product to be tested is stopped. The preset standard is a limit range set based on the voltage, current, resistance and frequency of the integrated circuit product to be tested.

[0035] The small outline package integrated circuit test device of this embodiment includes a test probe assembly, a substrate 5 and a cover plate 6. The test probe assembly includes a plurality of test probes (the test probe assembly of this embodiment includes 6 test probes) and a probe fixing block 17, and each test probe includes a probe contact 1, a probe extension needle 2, a probe guide needle 3 and a probe contact 4. The plurality of test probes are designed according to the upper and lower layer layout, and are divided into an upper layer test probe and a lower layer test probe by the probe fixing block 17, wherein one upper layer test probe and one lower layer test probe constitute a group of test probes.

[0036] The probe fixing block 17 divides the plurality of test probes into upper test probes and lower test probes, and fixes them into three rows. The test probes in this embodiment specifically include three rows of test probes (also called three groups of test probes), each row of test probes includes lower test probes and upper test probes, respectively, and will not cause influence on electrical signals during the integrated circuit test process. Each row of test probes serves as a group of FORCE test probes and SENSE test probes for integrated circuit pin testing.

[0037] The probe contact 1 includes two groups of front and rear probe contacts, which are used as the FORCE end and the SENSE end of the Kelvin test respectively. During the test, when the integrated circuit is pressed down to the probe contact 1, the FORCE end and the SENSE end will not be short-circuited. On the contact pin probe contact 1, the probe contact 1 is set to be in the shape of a knife edge. When the integrated circuit contacts the probe contact 1, it can pierce the plating of the integrated circuit pin and contact the inside of the integrated circuit pin to achieve good contact.

[0038] One end of the probe extension needle 2 is connected to the probe contact 1, and the other end of the probe extension needle 2 is connected and fixed to the probe guide needle 3. The structure consists of an upper and lower layer of probes, and the upper and lower layers serve as the FORCE end and SENSE end of the Kelvin test respectively. During the test, when the integrated circuit is pressed down to the probe contact 1, the FORCE end and the SENSE end will not be short-circuited.

[0039] One end of the probe guide pin 3 is connected to the probe extension pin 2, and the other end of the probe guide pin 3 is connected to the probe contact 4, which is fixed inside the probe fixing block 17. After the six test probes extend out of the probe guide block, they extend and bend to the six guide points respectively. After the test board is fixed to the small outline package integrated circuit test device, the probe contact 4 sinks, and under the limiting effect of the substrate 5, a good contact between the probe contact 4 and the test board is achieved.

[0040] The probe contact 4 is connected to one end of the probe guide pin 3. After the test board is fixed to the test structure, good surface-to-surface contact between the test board and the test probe is achieved, and under the action of a large pulse current of 10 amperes (A), good testing of the integrated circuit signal can be achieved.

[0041] The relevant dimensions of the probe contact 1, the probe extension needle 2, the probe guide needle 3 and the probe contact 4 of this embodiment are specifically described as follows: The dimensions of the probe contact 1 are 1.3mm in height, 0.6mm in needle width, 0.35mm in bottom thickness, and 0.1mm in top thickness. The dimensions of the probe extension needle 2 are 5.2mm in length, 0.6mm in needle width, and 0.35mm in thickness. The dimensions of the probe guide needle 3 are 5.2mm in length, 0.6mm in needle width, and 0.35mm in thickness. The dimensions of the probe contact 4 are 1.5mm in length, 1.5mm in width, and 0.8mm in thickness. The probe contact 4 protrudes 0.2mm from the probe cover.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A small outline package integrated circuit test device, characterized in that: It comprises a test probe assembly, a substrate (5) and a cover plate (6); The test probe assembly comprises a plurality of test probes and a probe fixing block (17), each test probe comprising a probe contact (1), a probe extension needle (2), a probe guide needle (3) and a probe contact (4), the probe contact (1) being connected to the probe extension needle (2), the end of the probe extension needle (2) being connected to the probe guide needle (3), and the probe guide needle (3) being connected to the probe contact (4), the plurality of test probes being designed according to an upper and lower layer layout, and being divided into an upper layer test probe and a lower layer test probe by the probe fixing block (17), wherein one upper layer test probe and one lower layer test probe constitute a group of test probes; The test probe assembly is arranged on a base plate (5); a sinking groove corresponding to the cover plate (6) is arranged on the upper surface of the base plate (5); a plurality of test probe guide grooves are arranged on the base plate (5); and a corresponding plurality of probe contact limit grooves are arranged on the cover plate (6).

2. The small outline package integrated circuit test device according to claim 1, characterized in that: The upper surface of the base plate (5) is also provided with screw through holes corresponding to the cover plate (6).

3. The small outline package integrated circuit test device according to claim 1, characterized in that: The upper surface of the substrate (5) is also provided with a plurality of positioning through holes.

4. The small outline package integrated circuit test device according to claim 1, characterized in that: The lower surface of the cover plate (6) is also provided with convex points (8) corresponding to the base plate (5).

5. The small outline package integrated circuit test device according to claim 1, characterized in that: The probe contact (1) is provided with a probe contact contact blade surface.

6. The small outline package integrated circuit test device according to claim 1, characterized in that: Insulating material is filled between each set of test probes.

7. The small outline package integrated circuit test device according to claim 6, characterized in that: The insulating material is peek material, insulating glue or mica sheet.

8. A method for using the small outline package integrated circuit test device according to any one of claims 1 to 7, characterized in that: The following steps are involved: Prepare small outline package integrated circuit test equipment and integrated circuit products to be tested; placing the integrated circuit product to be tested on the small outline package integrated circuit test device; Adjusting the position of the probe contact (1) so that the probe contact (1) is in close contact with the integrated circuit product to be tested; Starting the tester to perform the test, applying a test signal to the integrated circuit product to be tested through the small outline package integrated circuit test device, and receiving a response signal from the integrated circuit product to be tested; Analyzing the test results according to the response signal of the integrated circuit product to be tested; Determine whether the performance of the tested integrated circuit meets the preset standard according to the test results; If the integrated circuit product to be tested does not meet the preset standard, the testing of the integrated circuit product to be tested is stopped.

9. The method for using the small outline package integrated circuit test device according to claim 8, characterized in that: The probe contact (1) is provided with a probe contact contact blade surface.

10. The method for using the small outline package integrated circuit test device according to claim 8, characterized in that: The integrated circuit product is an integrated circuit product of the SOT series small outline package.

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