Serial-in serial-out data bubble sorting method based on FPGA

Abstract

The invention belongs to the technical field of aviation electrical, and discloses a serial-in serial-out data bubble sorting method based on an FPGA (Field Programmable Gate Array), the FPGA adopts a state machine mode to carry out operation, a state jump pointer is set, and at the end of each step of operation, the state jump pointer is set to point to the state to which the next step wants to jump; the sorting method comprises the following steps of: 1, initializing; step 2, taking a value; 3, comparing the last two bits; 4, performing cycle comparison; and 5, outputting data. According to the method, analog quantity bubbling sorting filtering is completed in the FPGA, for some small systems, the use of a CPU can be omitted, the cost is saved, meanwhile, the transmission time of data between the CPU and the FPGA is shortened, the rate is increased, and meanwhile the system stability is not affected.

Description

Technical Field

[0001] The invention belongs to the field of aviation electrical technology and relates to a serial-in serial-out data bubble sorting method based on FPGA. Background Art

[0002] As the degree of integration and intelligence of airborne equipment is gradually improved, the application of FPGA in airborne equipment is becoming more and more extensive. When using FPGA to collect external analog data, how to ensure the accuracy of the collected data without jitter becomes particularly critical. The application of the serial-in and serial-out data bubble sorting algorithm in the present invention can well solve the problem of occasional jitter of the external analog quantity collected in the actual application process of the product, which leads to the erroneous output of the control signal. Summary of the invention

[0003] (I) Purpose of the invention

[0004] The purpose of the present invention is to provide a serial-in serial-out data bubble sorting method based on FPGA, which uses FPGA to perform data bubble sorting comparison, so that the system can accurately complete data acquisition filtering without the participation of CPU, ensure the stability of acquisition, save costs, improve the system operation rate, and ensure that the system stability is not affected.

[0005] (II) Technical solution

[0006] In order to solve the above technical problems, the present invention provides a serial-in serial-out data bubble sorting method based on FPGA. The FPGA uses a state machine to perform calculations and sets a state jump pointer. At the end of each step of operation, the state jump pointer is set to point to the state to be jumped to in the next step. The sorting method includes the following steps:

[0007] Step 1: Initialization

[0008] Assign initial values ​​to the two registers to be used, assign a value of 2 to the comparison bit register, and assign an initial value of the remaining data amount register to the total number of data. After initialization is completed, point the state jump pointer to "value";

[0009] Step 2: Get the value

[0010] Assign the data to be compared to the comparison register array. The purpose of this step is to prevent new data input from affecting the comparison result during the comparison process. After the assignment is completed, the state jump pointer points to "the last two digits are compared";

[0011] Step 3: Compare the last two digits

[0012] Compare the last bit and the second to last bit of the comparison register array, swap the smaller data to the last bit, and reduce the value of the remaining data register by 1. After the comparison is completed, point the state jump pointer to "loop comparison";

[0013] Step 4: Cycle comparison

[0014] After entering this step, the "remaining data amount register" and the "comparison bit register" are first compared, and branch processing is performed according to the comparison result;

[0015] Step 5: Data Output

[0016] The data in the comparison register array that has completed the comparison is assigned to the output array in sequence. The purpose of this step is to prevent the output of erroneous results of unfinished comparison during the comparison process. After the assignment is completed, the state jump pointer points to "initialization" and a new round of data comparison can be started after the next clock edge arrives.

[0017] In the fourth step, if the "comparison bit register" is not greater than the "remaining data amount register", the data comparison will continue. The compared digits are the data bit corresponding to the "remaining data amount register" and its previous bit in the comparison register array. The smaller data will be exchanged to the data bit corresponding to the "remaining data amount register", and the value of the "remaining data amount register" will be reduced by 1. After the comparison is completed, the state jump pointer will point to the "loop comparison".

[0018] In the fourth step, if the "comparison bit register" is greater than the "remaining data amount register" and the "comparison bit register" is less than the total number of data, the "comparison bit register" is assigned a value plus 1, and the "remaining data amount register" is initialized to the total number of data. After the assignment is completed, the state jump pointer points to "loop comparison".

[0019] In the fourth step, if the "comparison bit register" is greater than the "remaining data amount register" and the "comparison bit register" is not less than the total number of data, it indicates that the loop comparison has been completed and the state jump pointer points to "data output".

[0020] Among them, the minimum operating cycle of the FPGA logic is the clock edge of the crystal oscillator. When each clock edge arrives, the state jump pointer address is read, and then the corresponding step is jumped to perform data processing according to the state jump pointer address.

[0021] Among them, the total number of comparisons is n (n-1) , that is, n is required (n-1) The clock cycle completes the data comparison, and n is the number of data.

[0022] Among them, bubble sort is not affected by the bit width of the input data and is suitable for analog quantities with a width of 8, 16 or 32 bits.

[0023] Among them, the external data refresh time is less than the time interval T of bubble data acquisition.

[0024] Among them, 2V1000 is used as the core FPGA, and AD conversion chip AD7656 is used as the analog input source.

[0025] (III) Beneficial effects

[0026] The FPGA-based serial-in and serial-out data bubble sorting method provided by the above technical solution completes analog bubble sort filtering inside the FPGA. For some smaller systems, it can save the use of the CPU and save costs. At the same time, it reduces the previous data transmission time between the CPU and FPGA, improves the rate, and does not affect the system stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Flow chart of the method of the present invention.

[0028] Figure 2 Graph showing simulation results in an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below in conjunction with the drawings and examples.

[0030] Reference Figure 1 As shown, in the serial-in serial-out data bubble sorting method based on FPGA in this embodiment, FPGA uses a state machine to perform calculations and sets a state jump pointer. At the end of each step of operation, the state jump pointer is set to point to the state to be jumped to in the next step; the serial-in serial-out data bubble sorting method includes the following steps:

[0031] Step 1: Initialization

[0032] Assign initial values ​​to the two registers to be used, assign a value of 2 to the comparison bit register, and assign an initial value of the remaining data amount register to the total number of data. After initialization is completed, point the state jump pointer to "value";

[0033] Step 2: Get the value

[0034] Assign the data to be compared to the comparison register array. The purpose of this step is to prevent new data input from affecting the comparison result during the comparison process. After the assignment is completed, the state jump pointer points to "the last two digits are compared";

[0035] Step 3: Compare the last two digits

[0036] Compare the last bit and the second to last bit of the comparison register array, swap the smaller data to the last bit, and reduce the value of the remaining data register by 1. After the comparison is completed, point the state jump pointer to "loop comparison";

[0037] Step 4: Cycle comparison

[0038] After entering this step, the "remaining data amount register" and the "comparison bit register" are first compared, and branch processing is performed according to the comparison result:

[0039] 1) If the "Comparison Bit Register" is not greater than the "Remaining Data Quantity Register", the data comparison will continue. The compared digits are the data bit corresponding to the "Remaining Data Quantity Register" and its previous bit in the comparison register array. The smaller data will be exchanged to the data bit corresponding to the "Remaining Data Quantity Register", and the value of the "Remaining Data Quantity Register" will be reduced by 1. After the comparison is completed, the state jump pointer will point to the "loop comparison".

[0040] 2) If the "Comparison Bit Register" is greater than the "Remaining Data Quantity Register" and the "Comparison Bit Register" is less than the total number of data, the "Comparison Bit Register" is assigned a value plus 1, and the "Remaining Data Quantity Register" is assigned an initial value of the total number of data. After the assignment is completed, the state jump pointer points to "Circular Comparison".

[0041] 3) If the "Comparison Bit Register" is greater than the "Remaining Data Amount Register" and the "Comparison Bit Register" is not less than the total number of data, it indicates that the loop comparison has been completed and the state jump pointer points to "Data Output";

[0042] Step 5: Data Output

[0043] The data in the comparison register array that has completed the comparison is assigned to the output array in sequence. The purpose of this step is to prevent the output of erroneous results of unfinished comparison during the comparison process. After the assignment is completed, the state jump pointer points to "initialization" and a new round of data comparison can be started after the next clock edge arrives.

[0044] In this embodiment, the minimum operation cycle of the FPGA logic is the clock edge of the crystal oscillator. When each clock edge arrives, the state jump pointer address is read, and then the corresponding step is jumped to perform data processing according to the state jump pointer address;

[0045] In this embodiment, the total number of comparisons required is n. (n-1) , that is, n is required (n-1) Data comparison can be completed in one clock cycle;

[0046] In this embodiment, regardless of the influence of the input data bit width, the bubble sort can be completed accurately regardless of the analog quantity with a width of 8 bits, 16 bits or 32 bits.

[0047] In this embodiment, it should be noted that the external data refresh time should be less than T to ensure that the algorithm execution is meaningful.

[0048] Example 1

[0049] Use 2V1000 as the core FPGA, use AD conversion chip AD7656 as the analog input source, the data width is 16 bits, the AD acquisition frequency is 200KHz, take the AD data every 0.2ms, for 8 consecutive times, and take A[4] output after bubble sorting. Write the simulation code and simulate. The input data is assigned the following initial value:

[0050] data_1 = 16'h1234;

[0051] data_2 = 16'h0123;

[0052] data_3 = 16'hc156;

[0053] data_4 = 16'hd378;

[0054] data_5 = 16' HF456;

[0055] data_6 = 16'hb367;

[0056] data_7 = 16'ha234;

[0057] data_8 = 16'h1258;

[0058] data_9 = 16'h3468;

[0059] After running the simulation, the comparison results are shown in the attached Figure 2 .

[0060] The comparison result output is correct, which proves that the method is reasonable and effective.

[0061] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A serial-in and serial-out data bubble sorting method based on FPGA, characterized in that: FPGA uses a state machine to perform calculations and sets a state jump pointer. At the end of each step, the state jump pointer is set to point to the state to be jumped to in the next step. The sorting method includes the following steps: Step 1: Initialization Assign initial values ​​to the two registers to be used, assign a value of 2 to the comparison bit register, and assign an initial value of the remaining data amount register to the total number of data. After initialization is completed, point the state jump pointer to "value"; Step 2: Get the value Assign the data to be compared to the comparison register array. The purpose of this step is to prevent new data input from affecting the comparison result during the comparison process. After the assignment is completed, the state jump pointer points to "the last two digits are compared"; Step 3: Compare the last two digits Compare the last bit and the second to last bit of the comparison register array, swap the smaller data to the last bit, and reduce the value of the remaining data register by 1. After the comparison is completed, point the state jump pointer to "loop comparison"; Step 4: Cycle comparison After entering this step, the "remaining data amount register" and the "comparison bit register" are first compared, and branch processing is performed according to the comparison result; Step 5: Data Output The data in the comparison register array that has completed the comparison is assigned to the output array in sequence. The purpose of this step is to prevent the output of erroneous results of unfinished comparison during the comparison process. After the assignment is completed, the state jump pointer points to "initialization" and a new round of data comparison can be started after the next clock edge arrives.

2. The FPGA-based serial-in, serial-out data bubble sorting method as claimed in claim 1, characterized in that: In the fourth step, if the "comparison bit register" is not greater than the "remaining data amount register", the data comparison will continue. The compared digits are the data bit corresponding to the "remaining data amount register" and its previous bit in the comparison register array. The smaller data will be exchanged to the data bit corresponding to the "remaining data amount register", and the value of the "remaining data amount register" will be reduced by 1. After the comparison is completed, the state jump pointer will point to the "loop comparison".

3. The FPGA-based serial-in, serial-out data bubble sorting method as claimed in claim 2, characterized in that: In the fourth step, if the "comparison bit register" is greater than the "remaining data amount register" and the "comparison bit register" is less than the total number of data, the "comparison bit register" is assigned a value plus 1, and the "remaining data amount register" is initialized to the total number of data. After the assignment is completed, the state jump pointer points to the "loop comparison".

4. The FPGA-based serial-in, serial-out data bubble sorting method as claimed in claim 3, characterized in that: In the fourth step, if the "comparison bit register" is greater than the "remaining data amount register" and the "comparison bit register" is not less than the total number of data, it indicates that the loop comparison has been completed and the state jump pointer points to "data output".

5. The FPGA-based serial-in, serial-out data bubble sorting method as claimed in claim 4, characterized in that: The minimum operating cycle of the FPGA logic is the clock edge of the crystal oscillator. When each clock edge arrives, the state jump pointer address is read, and then the corresponding step is jumped to perform data processing according to the state jump pointer address.

6. The FPGA-based serial-in, serial-out data bubble sorting method as claimed in claim 5, characterized in that: The total number of comparisons is n (n-1) , that is, n is required (n-1) The clock cycle completes the data comparison, and n is the number of data.

7. The FPGA-based serial-in, serial-out data bubble sorting method as claimed in claim 6, characterized in that: Bubble sort is not affected by the bit width of the input data and is suitable for analog quantities with a width of 8, 16, or 32 bits.

8. The FPGA-based serial-in, serial-out data bubble sorting method as claimed in claim 7, characterized in that: The external data refresh time is less than the time interval T of bubble data acquisition.

9. The FPGA-based serial-in, serial-out data bubble sorting method according to any one of claims 1 to 8, characterized in that: Use 2V1000 as the core FPGA and AD conversion chip AD7656 as the analog input source.

10. An application of the FPGA-based serial-in, serial-out data bubble sorting method according to any one of claims 1 to 8 in aviation electrical technology.

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