Firmware updating method, circuit and equipment of electronic equipment and storage medium

Abstract

The invention discloses a firmware updating method, circuit and equipment of electronic equipment and a storage medium, and relates to the technical field of electronic circuits. The method comprises the steps that when connection is established through a connecting line base and a universal connecting line, power is supplied to a capacitor module through a power module, and current is transmitted to a first triode through the capacitor module, so that the first triode is changed into a conducting state from a cut-off state; if the system switch of the power supply module is closed before the first triode is changed from the on state to the off state, current is transmitted to the second triode through the power supply module, so that the second triode is changed from the off state to the on state; voltage is transmitted to the main control chip through the second triode, so that the current voltage of a connecting pin of the main control chip and the second triode is high level, and firmware updating is triggered. According to the technical scheme, the firmware updating is triggered by using the universal connecting line, the production cost is reduced, and the workload of a user for storing and managing the special connecting line is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of electronic circuit technology, in particular to the field of interface control logic technology, and specifically to a firmware update method, circuit, device and storage medium for an electronic device. Background Art

[0002] Some of the existing electronic devices need to have firmware written to them in order to work properly. At the same time, these electronic devices can update their firmware to correct defects, update functions, optimize performance, etc.

[0003] Some of these electronic devices are connected to a computer using a dedicated USB (Universal Serial Bus) cable to update the firmware. This requires providing a dedicated USB cable for the device, which increases production costs. During user use, if the dedicated USB cable is lost or damaged, the user needs to contact the supplier to obtain it again, which adds an extra burden to the user. In addition, since the USB connector used by the dedicated USB cable is the same as the connector of the universal USB cable, it is easy to confuse it. Once it is plugged in incorrectly, it may damage the device and cause greater losses. Summary of the invention

[0004] The present application provides a firmware update method, circuit, device and storage medium for an electronic device, so as to trigger the firmware update using a universal connection line and reduce production costs.

[0005] According to one aspect of the present application, a method for updating the firmware of an electronic device is provided, and the method is applied to a firmware update circuit of a target electronic device; the firmware update circuit includes a connection line base, a main control chip, a power module, a capacitor module, a first transistor and a second transistor; the capacitor module includes at least a target capacitor; the negative electrode of the target capacitor is grounded through a resistor; the negative electrode of the target capacitor is connected to the first transistor through a resistor; the first transistor and the second transistor are connected through a resistor; the second transistor and the main control chip are connected through a resistor; the method includes:

[0006] When the connection is established with the universal connection line through the connection line base, the power supply module supplies power to the capacitor module, and the capacitor module transmits current to the first transistor, so that the first transistor changes from a cut-off state to a conducting state;

[0007] If the system switch of the power module is closed before the first transistor changes from the on state to the off state, current is transmitted to the second transistor through the power module to change the second transistor from the off state to the on state; wherein the first transistor changes from the on state to the off state means that the negative electrode voltage of the target capacitor continues to drop to less than or equal to the base on voltage of the first transistor;

[0008] The voltage is transmitted to the main control chip through the second transistor, so that the current voltage of the connecting pin between the main control chip and the second transistor is at a high level, thereby triggering the firmware update.

[0009] According to another aspect of the present application, a firmware update circuit of an electronic device is provided, the circuit comprising a connection line base, a main control chip, a power module, a capacitor module, a first transistor and a second transistor; the capacitor module at least comprises a target capacitor; the negative electrode of the target capacitor is grounded through a resistor; the negative electrode of the target capacitor is connected to the first transistor through a resistor; the first transistor and the second transistor are connected through a resistor; the second transistor and the main control chip are connected through a resistor;

[0010] The power supply module is used to supply power to the capacitor module when a connection is established with the universal connection line through the connection line base;

[0011] The capacitor module is used to transmit current to the first transistor, so that the first transistor changes from a cut-off state to a conducting state;

[0012] The power module is further configured to transmit current to the second transistor when the system switch of the power module is closed before the first transistor changes from the on state to the off state, so that the second transistor changes from the off state to the on state; wherein the first transistor changes from the on state to the off state means that the negative electrode voltage of the target capacitor continues to drop to a value less than or equal to the base on-voltage of the first transistor;

[0013] The second transistor is used to transmit voltage to the main control chip, so that the current voltage of the connection pin between the main control chip and the second transistor is high level, thereby triggering firmware update.

[0014] According to another aspect of the present application, an electronic device is provided, the electronic device comprising:

[0015] one or more processors;

[0016] A memory for storing one or more programs;

[0017] When the one or more programs are executed by the one or more processors, the one or more processors implement any one of the firmware update methods for electronic devices provided in the embodiments of the present application.

[0018] According to another aspect of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the program is executed by a processor, the firmware update method of any electronic device provided in the embodiments of the present application is implemented.

[0019] According to another aspect of the present application, a computer program product is provided, including a computer program, which, when executed by a processor, implements the firmware update method of any electronic device provided in the embodiments of the present application.

[0020] When the present application establishes a connection with the universal connecting line through the connecting line base, power is supplied to the capacitor module through the power module, and current is transmitted to the first triode through the capacitor module, so that the first triode changes from the cut-off state to the on state; if the system switch of the power module is closed before the first triode changes from the on state back to the cut-off state, current is transmitted to the second triode through the power module, so that the second triode changes from the cut-off state to the on state; wherein, the first triode changes from the on state back to the cut-off state means that the negative voltage of the target capacitor continues to drop to less than or equal to the base conduction voltage of the first triode; and voltage is transmitted to the main control chip through the second triode, so that the current voltage of the connecting pin between the main control chip and the second triode is a high level, thereby triggering a firmware update. The above technical solution can use a universal USB cable to implement firmware update of electronic devices, reduce costs, and avoid damage to electronic devices caused by incorrect use of dedicated USB cables. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1a is a flowchart of a firmware update method for an electronic device provided according to Embodiment 1 of the present application;

[0022] Figure 1b It is a circuit diagram of a firmware update circuit of an electronic device provided according to Embodiment 1 of the present application;

[0023] Figure 2 is a flowchart of a firmware update method for an electronic device provided according to Embodiment 2 of the present application;

[0024] Figure 3 It is a structural schematic diagram of a firmware update circuit of an electronic device provided according to Embodiment 3 of the present application;

[0025] Figure 4 It is a structural diagram of an electronic device that implements the firmware update method of the electronic device of the fourth embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] In addition, it should be noted that the collection, storage, use, processing, transmission, provision and disclosure of relevant data such as the cut-off state and the on-state involved in the technical solution of this application are in compliance with the relevant laws and regulations and do not violate public order and good morals.

[0029] Embodiment 1

[0030] Figure 1a This is a flowchart of a firmware update method for an electronic device provided in accordance with the first embodiment of the present application. This embodiment is applicable to the case where the firmware of an electronic device is updated using a universal USB cable. The firmware update circuit of the electronic device can be implemented in the form of hardware. The firmware update circuit of the electronic device can be configured in the firmware update circuit of the target electronic device, for example. Figure 1b The circuit shown in FIG. 1 is a circuit diagram of a firmware update circuit, comprising a connection line base, a main control chip, a power module, a capacitor module, a first transistor and a second transistor; the capacitor module comprises at least a target capacitor; the negative electrode of the target capacitor is grounded through a resistor; the negative electrode of the target capacitor is connected to the first transistor through a resistor; the first transistor is connected to the second transistor through a resistor; and the second transistor is connected to the main control chip through a resistor. Figure 1a As shown, the method includes:

[0031] S110. When a connection is established with the universal connection line through the connection line base, power is supplied to the capacitor module through the power supply module, and current is transmitted to the first transistor through the capacitor module, so that the first transistor changes from a cut-off state to a conduction state.

[0032] In this embodiment, the connection line base refers to the connection interface part of the electronic device, which is used to connect other devices or cables; the connection line base can specifically refer to Figure 1b The Micro-USB (Micro-Universal Serial Bus) base shown. Universal connection cable refers to a connection cable that meets universal standards (such as a USB cable) that can connect different devices for data transmission or power supply. The power module refers to a circuit module that provides power, transferring electrical energy from a power source (such as a battery or an external power source) to other circuit parts to ensure the normal operation of the device. The capacitor module refers to a circuit module composed of capacitors, resistors, etc., which is used to store electrical energy, adjust voltage, or play a role in filtering and denoising in the circuit. A transistor refers to an electronic component that can amplify signals or switch circuits; in this application, the first and second transistors act as switches to control the on and off of current; it should be noted that the first transistor in this application refers to an NPN (Negative-Positive-Negative, negative-positive-negative) transistor, and the second transistor refers to a PNP (Positive-Negative-Positive, positive-negative-positive) transistor. The cut-off state means that no current flows through the transistor, which is equivalent to the switch being in the off state and the circuit is not conducting. The on state means that the switch of the transistor is turned on, allowing current to flow and the circuit is turned on.

[0033] Optionally, the power module may include at least one of a power pin in a connecting wire base and a power conversion module; accordingly, when a connection is established with a universal connecting wire through the connecting wire base, power is supplied to the capacitor module through the power pin in the connecting wire base in the power module, and current is transmitted to the first transistor through the capacitor module to change the first transistor from a cut-off state to a conducting state.

[0034] For example, Figure 1b Taking the circuit diagram shown as an example, the power pin in the base of the connecting cable can be a Vbus (Voltage Bus) pin; when a universal Micro-USB cable is used to connect a computer and a device, the voltage of the positive electrode of the target capacitor C1 to the ground instantly rises to the Vbus pin voltage, that is, 5V; since the voltage across the capacitor cannot jump, the voltage of the negative electrode of the target capacitor C1 to the ground also instantly rises to 5V, and since it is higher than the base conduction voltage of the first transistor Q1 0.7V, a current is generated to pass through the first bias resistor R4 and the base of the first transistor Q1, so that the first transistor Q1 is turned on.

[0035] In an alternative embodiment, see Figure 1b , this application also optimizes the ID (Identification) pin of the Micro-USB base, and sets the ID pin of the Micro-USB base to a null pin.

[0036] It is understandable that setting the ID pin of the Micro-USB base as a free pin allows the electronic device to update the firmware using a universal USB cable without changing the appearance and function of the system.

[0037] S120: If the system switch of the power module is closed before the first transistor changes from the on state to the off state, current is transmitted to the second transistor through the power module to change the second transistor from the off state to the on state.

[0038] In this embodiment, the first transistor changes from the on state to the off state when the negative electrode voltage of the target capacitor continues to drop to less than or equal to the base on voltage of the first transistor; wherein the base on voltage refers to when the base voltage of the transistor exceeds a certain threshold, the transistor starts to conduct, and this voltage is usually a specific value to ensure that the transistor is in a working state; the target capacitor refers to a specific capacitor used to store or release electrical energy in a circuit, and the target capacitor can specifically refer to Figure 1b Capacitor C1 is shown.

[0039] Specifically, if the system switch of the voltage conversion module in the power module is closed before the first transistor changes from the on state to the off state, current is transmitted to the second transistor through the power module to change the second transistor from the off state to the on state.

[0040] For example, Figure 1b Taking the circuit diagram shown as an example, before the first transistor changes from the on state to the off state, the first transistor Q1 is in the on state, the equivalent resistance from the collector to the emitter of the first transistor Q1 is very small, the second bias resistor R5 is connected to one end of the collector of the first transistor Q1 and is pulled down to about 0.1V, and the emitter of the second transistor Q2, i.e., the e-pole, is connected to Vbus, so Q2 is turned on.

[0041] S130, transmitting voltage to the main control chip through the second transistor, so that the current voltage of the connecting pin between the main control chip and the second transistor is high level, thereby triggering firmware update.

[0042] In this embodiment, the main control chip refers to the core processing unit of the entire circuit or system, which is responsible for coordinating, controlling and managing the work of each subsystem or module. Firmware update refers to upgrading or changing the firmware of the embedded device to enhance functions or fix vulnerabilities. High level refers to the state of higher voltage in the circuit, usually representing the "on" state, and the signal is at 1. Low level refers to the state of lower voltage in the circuit, usually representing the "off" state, and the signal is at 0.

[0043] It should be noted that the present application is applicable to the case where the main control chip uses a specific pin DET for firmware update. When the main control chip is powered on, it determines the level of the pin to choose normal startup or enter the firmware update mode.

[0044] For example, Figure 1b Taking the circuit diagram shown as an example, when the second transistor Q2 is turned on, the emitter-to-collector resistance of the second transistor Q2 becomes very small, and the end of the first voltage-dividing resistor R6 connected to the collector of the second transistor Q2 is pulled up to about 5V-0.1V=4.9V. After the voltage is divided by the first voltage-dividing resistor R6 and the second voltage-dividing resistor R7, the voltage of the DET (Detection) pin of the main control chip is 4.9V×R7 / (R6+R7). By setting reasonable resistance values ​​of R6 and R7, it can be ensured that the voltage of the DET pin is at a high level at this time. For example, when VCC is 3.3V, R6 is 10KΩ, and R7 is 20KΩ. Then, the voltage of the DET pin is 4.9V×20KΩ / (10KΩ+20KΩ)=3.266V, that is, a high level, and the system enters the firmware update mode.

[0045] Optional, see Figure 1b The second transistor Q2 is connected to the main control chip through the first voltage-dividing resistor R6 and the second voltage-dividing resistor R7; the second transistor Q2, the first voltage-dividing resistor R6 and the second voltage-dividing resistor R7 are connected in series; the connecting pin DET is connected in parallel with the second voltage-dividing resistor R7.

[0046] Optional, continue to see Figure 1b , the negative electrode of the target capacitor C1 is grounded through the grounding resistor R3; the grounding resistor R3 is connected in parallel with the first transistor Q1; the negative electrode of the target capacitor C1 is connected in series with the grounding resistor R3; the negative electrode of the target capacitor C1 is connected in series with the first transistor Q1 through the resistor R4.

[0047] Furthermore, the grounding resistance of the grounding resistor R3 and the capacitance of the target capacitor C1 can be adjusted according to the supply voltage of the power module to control the time length for the first transistor Q1 to change from the off state to the on state and from the on state back to the off state.

[0048] In this embodiment, the grounding resistance value refers to the resistance value of the grounding resistor, which determines the degree of obstruction encountered when the current passes through the resistor; the larger the resistance, the greater the obstruction to the current passing through, and the smaller the current; usually, we control the current or voltage division by the resistance value. The capacitance value refers to the ability of the target capacitor C1 to store charge; the capacitor plays the role of filtering, coupling, decoupling and timing in the circuit; the larger the capacitance, the more charge is stored and the slower the voltage changes.

[0049] Optionally, the time when Q1 changes from the off state to the on state is marked as T0, and the time when Q1 changes from the on state back to the off state is marked as T1; the time setting from T0 to T1 can be achieved by the following formula:

[0050]

[0051] in, A function that represents the voltage on a capacitor as a function of time. represents the input voltage (in volts). t represents the charging time (in seconds). R represents the resistance of the grounding resistor R3 (in ohms). C represents the capacitance of the capacitor C1 (in farads). e is the base of the natural logarithm, which is approximately equal to 2.71828.

[0052] For example, Figure 1b Take the circuit diagram shown in the figure as an example, V0=5V, when the voltage of the negative electrode of C1 to the ground drops to 0.7V, Q1 starts to be in the cut-off state, and the voltage across C1 is 5V-0.7V=4.3V, that is, V(t)=0.86 , substituting into the RC charging formula, we get: 1-e^(-t / RC)=0.86, and after calculation, we get: RC=t / 1.966. Just set the appropriate values ​​of R3 and C1 to get the desired time length from T0 to T1. For example, if you want the time length from T0 to T1 to be 3 seconds, then RC=3 / 1.966=1.526, and you can set C1 to 100uF, then the resistance of R3 is 1.526 / (100×0.000001)=15260Ω.

[0053] It should be noted that the above is only a rough calculation. Because the negative electrode of the target capacitor C1 is also connected to the first bias resistor R4, and the other end of the first bias resistor R4 is connected to the base of the first transistor Q1, there will be a certain current in the first bias resistor R4 during the conduction of the first transistor Q1, and this current will have a certain impact on the above calculation results. In addition, the voltage of the negative electrode of the target capacitor C1 to the ground needs to be higher than the conduction voltage of the base of the first transistor Q1, so that the current flowing through the first bias resistor R4 and the base of the first transistor Q1 can be large enough to generate enough current after two-stage amplification by the first transistor Q1 and the second transistor Q2, so as to pull the DET pin of the main control chip to a high level.

[0054] For further information, see Figure 1b , the negative electrode of the target capacitor C1 is connected in series with the base of the first transistor Q1 through the first bias resistor R4; the collector of the first transistor Q1 is connected in series with the base of the second transistor Q2 through the second bias resistor R5; the grounding resistor R3 is connected in parallel with the first bias resistor R4 and the first transistor Q1; the first bias resistor R4, the second bias resistor R5, the first voltage divider resistor R6 or the second voltage divider resistor R7 can be adjusted to reduce the error of the time setting from T0 to T1.

[0055] Exemplarily, R4 is set to be larger to reduce the current flowing through R4 and the base of Q1, thereby reducing the impact on the calculation results; R5 is set to be smaller to increase the current flowing through the base of Q2, that is, to increase the collector current of Q2 in the amplified state; R6 and R7 are set to be larger to reduce the current that needs to flow through R6 and R7 while ensuring that the DET pin can be pulled to a high level; actual measurements can also be used to adjust the parameters of the above components, especially R3 and C1, in an actual circuit environment to achieve the desired time length from T0 to T1.

[0056] Optional, continue to see Figure 1b The capacitor module also includes a discharge resistor R8 and a discharge diode D1; the target capacitor C1, the discharge resistor R8 and the discharge diode D1 are connected in series.

[0057] It should be noted that the discharge diode may specifically refer to a germanium diode.

[0058] Furthermore, when the connection line base is disconnected from the universal connection line, current is transmitted to the discharge resistor and the discharge diode through the positive electrode of the target capacitor to form a discharge loop to discharge the target capacitor.

[0059] For example, when the USB cable is unplugged, since C1 is in a charged state, if the charge in it is not released in time, it will still be in a charged state when the USB cable is plugged in again next time, causing Q1 to be unable to conduct, so that the DET pin will not be pulled high, that is, the firmware update mode cannot be entered. R8 and D1 play a discharging role in this circuit. When the USB cable is unplugged, Vbus fails. Since C1 is in a charged state, the voltage across it acts on the series circuit composed of R8 and D1, and the voltage direction is the same as the conduction direction of D1, that is, C1, R8 and D1 form a discharge circuit, and C1 is discharged through the discharge circuit. Since D1 uses a germanium diode, its conduction voltage is relatively low, about 0.1V, and the discharge law of the entire discharge circuit is similar to the RC discharge law.

[0060] In order to simplify the explanation, the common practice in engineering is adopted here, that is, the concept of the time constant RC of the RC charging and discharging circuit is quoted, R is the resistance value, and C is the capacitance value. According to public data, during discharge, after 1RC time, the voltage across the capacitor drops to 0.37 times the initial voltage, after 2RC time, the voltage across the capacitor drops to 0.14 times the initial voltage, and after 3RC time, the voltage across the capacitor drops to 0.05 times the initial voltage. In the circuit of this application, when the voltage across the capacitor drops to 5V×0.05=0.25V after 3RC time, it can be considered to be fully discharged. Parameter calculation example: For example, if you want to fully discharge within 1 second, that is, 3RC=1, you can set C=100uF, then: R=1 / (3×C)=1 / (3×100×0.000001)=3333Ω; C and R here correspond to C1 and R8 in the circuit.

[0061] When the embodiment of the present application establishes a connection with the universal connecting line through the connecting line base, power is supplied to the capacitor module through the power module, and current is transmitted to the first transistor through the capacitor module, so that the first transistor changes from the cut-off state to the on state; if the system switch of the power module is closed before the first transistor changes from the on state back to the cut-off state, current is transmitted to the second transistor through the power module, so that the second transistor changes from the cut-off state to the on state; wherein, the first transistor changes from the on state back to the cut-off state means that the negative voltage of the target capacitor continues to drop to less than or equal to the base conduction voltage of the first transistor; voltage is transmitted to the main control chip through the second transistor, so that the current voltage of the connecting pin between the main control chip and the second transistor is a high level, thereby triggering a firmware update. The above technical solution can use a universal USB cable to implement firmware update of electronic devices, reduce costs, and avoid damage to electronic devices caused by incorrect use of dedicated USB cables.

[0062] See also Figure 1b In order to facilitate the understanding of the solution of this application, this application Figure 1bThe related application of the circuit shown is further explained. In the improved circuit of the present application, the ID pin in the Micro-USB base is an empty pin. An NPN transistor Q1, a PNP transistor Q2, a germanium diode D1, a capacitor C1, and resistors R3, R4, R5, R6, R7, and R8 are added.

[0063] When the power is turned off, that is, the power switch K1 is not closed and the USB cable is not connected, C1 is not charged, the voltages at both ends of it to ground are 0, the base currents through R4 and Q1 are 0, and the currents through R5 and the base of Q2 are also 0, that is, Q1 and Q2 are both in the cut-off state.

[0064] When a universal Micro-USB cable is used to connect a computer and a device, the voltage of the positive electrode of C1 to ground instantly rises to Vbus, i.e., 5V. Since the voltage across the capacitor cannot jump, the voltage of the negative electrode of C1 to ground also instantly rises to 5V. Since it is higher than the base conduction voltage of Q1, 0.7V, a current is generated through R4 and the base of Q1, turning on Q1. For ease of explanation, this moment is marked as T0. Starting from T0, the positive electrode of C1 is connected to the 5V power supply, the negative electrode of C1 is connected to the ground through R3, and then to the base of Q1 and the emitter through R4. The circuit continues to charge the capacitor C1, and the voltage across its two ends continues to rise, that is, the voltage of the negative electrode of C1 to ground continues to drop. After a period of time, when the voltage of the negative electrode of C1 drops to near the base conduction voltage of Q1, this moment is marked as T1. Starting from T1, since the voltage of the negative electrode of C1 to the ground is less than or equal to the base conduction voltage of Q1, the current flowing through R4 and the base of Q1 drops to 0, and Q1 begins to be in the cut-off state. From the above analysis, it can be seen that Q1 is in the on state after T0 and before T1, and Q1 is in the cut-off state after T1. When the power is turned on, that is, K1 is closed, the system power supply VCC begins to take effect, that is, it quickly rises from 0V to the voltage value set by the power module, and then the main control chip starts to run. Since the time required for this process is relatively short, it can be ignored.

[0065] The circuit designed for this application has the following three power-on conditions:

[0066] The first startup situation: when the built-in battery is used to power the system instead of the USB cable, since Q2 is in the cut-off state, the DET pin of the main control chip will be pulled to a low level by R7, and the system starts normally.

[0067] The second startup situation: startup after T0 and before T1. At this time, Q1 is in the on state, and the equivalent resistance from the collector to the emitter of Q1 is very small. The end of R5 connected to the collector of Q1 is pulled down to about 0.1V. Since the emitter of Q2, i.e. the e-pole, is connected to Vbus, Q2 is turned on, and the resistance from the emitter to the collector of Q2 becomes very small. The end of R6 connected to the collector of Q2 is pulled up to about 5V-0.1V=4.9V. After the voltage is divided by R6 and R7, the voltage of the DET pin is 4.9V×R7 / (R6+R7). By setting reasonable resistance values ​​of R6 and R7, it can be ensured that the voltage of the DET pin is at a high level at this time. For example, when VCC is 3.3V, R6 is 10KΩ and R7 is 20KΩ, then the voltage of the DET pin is 4.9V×20KΩ / (10KΩ+20KΩ)=3.266V, i.e. high level, and the system enters the firmware update mode.

[0068] The third startup situation: Start after T1. At this time, Q1 is in the cut-off state, the current flowing through R5 and the base of Q1 is 0, Q2 is also in the cut-off state, the DET pin of the main control chip is pulled to a low level by R7, and the system starts normally.

[0069] It is understandable that when using a universal USB cable, the system is turned on after T0 and before T1 to enter the firmware update mode, and it is turned on normally in other cases. That is, the present application achieves the purpose of using a universal USB cable and allowing the user to choose whether to enter the firmware update mode without changing the appearance and function of the system, such as adding buttons. Moreover, the present circuit only adds two transistors, a germanium diode, a capacitor, and several resistors, and has the advantages of low cost, simple circuit, not easy to damage, and less space occupied.

[0070] Embodiment 2

[0071] Figure 2 This is a flow chart of a firmware update method for an electronic device provided in accordance with the second embodiment of the present application. Based on the technical solutions of the above embodiments, this embodiment refines "transmitting current to the main control chip through the second transistor so that the current voltage of the connecting pin between the main control chip and the second transistor is a high level" into "transmitting voltage to the first voltage-dividing resistor through the collector of the second transistor, and after voltage division through the first voltage-dividing resistor, transmitting the voltage to the connecting pin and the second voltage-dividing resistor respectively; controlling the current voltage of the connecting pin by setting the resistance values ​​of the first voltage-dividing resistor and the second voltage-dividing resistor so that the current voltage of the connecting pin is a high level". It should be noted that for the parts not described in detail in the embodiments of the present application, please refer to the relevant statements of other embodiments. Figure 2 As shown, the method includes:

[0072] S210. When a connection is established with the universal connection line through the connection line base, power is supplied to the capacitor module through the power supply module, and current is transmitted to the first transistor through the capacitor module, so that the first transistor changes from a cut-off state to a conduction state.

[0073] S220: If the system switch of the power module is closed before the first transistor changes from the on state to the off state, current is transmitted to the second transistor through the power module to change the second transistor from the off state to the on state.

[0074] S230, transmitting a voltage to the first voltage-dividing resistor through the collector of the second transistor, and after dividing the voltage through the first voltage-dividing resistor, transmitting the voltage to the connecting pin and the second voltage-dividing resistor respectively.

[0075] In this embodiment, the first voltage-dividing resistor and the second voltage-dividing resistor refer to resistors used to divide the collector voltage of the second transistor; the resistance values ​​of the first voltage-dividing resistor and the second voltage-dividing resistor determine the voltage distribution ratio; selecting different resistance values ​​can control the voltage of the connecting pin connected between the first voltage-dividing resistor and the second voltage-dividing resistor. The connecting pin is an interface point of a circuit board or an integrated circuit, which is usually used for the transmission of electrical signals or connection with an external circuit; the pin here is used to receive a specific voltage signal to trigger a firmware update.

[0076] For example, Figure 1b Taking the circuit diagram shown as an example, the voltage is transmitted to the first voltage-dividing resistor R6 through the collector c of the second transistor Q2, and after voltage division by R6, the voltage is transmitted to the connecting pin DET and the second voltage-dividing resistor R7 respectively.

[0077] S240, controlling the current voltage of the connection pin by setting the resistance values ​​of the first voltage-dividing resistor and the second voltage-dividing resistor so that the current voltage of the connection pin is a high level, thereby triggering a firmware update.

[0078] In this embodiment, a high level refers to a relatively high voltage state, for example, in a digital circuit, it indicates a logic "1" or an on state; in this application, a high level voltage signal is used to trigger a firmware update.

[0079] Optionally, the resistance values ​​of the first voltage-dividing resistor and the second voltage-dividing resistor are pre-configured according to the system voltage of the power supply module to control the current voltage of the connecting pin to be a high level; wherein the current voltage is determined by calculating the collector voltage of the collector of the first transistor, the resistance values ​​of the first voltage-dividing resistor and the second voltage-dividing resistor via a series-parallel circuit.

[0080] In this embodiment, the series-parallel circuit includes at least one of a series circuit and a parallel circuit; a series circuit refers to a plurality of elements connected in sequence, with the same current and voltage distributed among the elements; a parallel circuit refers to a plurality of elements connected side by side, with the same voltage and current distributed among the elements.

[0081] Exemplarily, the current voltage of the connection pin may be determined by the following series voltage division formula:

[0082]

[0083] in, Refers to the current voltage at the connected pin. Refers to the collector voltage of the first transistor collector. R6 refers to the resistance value of the first voltage-dividing resistor. R7 refers to the resistance value of the second voltage-dividing resistor.

[0084] It is understood that the connection pins (such as Figure 1b The resistance to ground of the DET pin shown in the figure is very large. When calculating the voltage of R7, only the series effect of R6 and R7 needs to be considered, and the connecting pin is regarded as an open circuit.

[0085] For example, Figure 1b Taking the circuit shown as an example, when the second transistor Q2 is turned on, the emitter-to-collector resistance of the second transistor Q2 becomes very small, and the end of the first voltage-dividing resistor R6 connected to the collector of the second transistor Q2 is pulled up to about 5V-0.1V=4.9V. After the voltage is divided by the first voltage-dividing resistor R6 and the second voltage-dividing resistor R7, the voltage of the DET (Detection) pin of the main control chip is 4.9V×R7 / (R6+R7). By setting reasonable resistance values ​​of R6 and R7, it can be ensured that the voltage of the DET pin is at a high level at this time. For example, when VCC is 3.3V, R6 is 10KΩ, and R7 is 20KΩ. Then, the voltage of the DET pin is 4.9V×20KΩ / (10KΩ+20KΩ)=3.266V, that is, a high level, and the system enters the firmware update mode.

[0086] It should be noted that the resistance to ground of the DET pin of the main control chip is very large, and the current flowing through this pin can be ignored, that is, only the voltage-dividing effect of R6 and R7 in series needs to be considered.

[0087] When the embodiment of the present application establishes a connection with the universal connecting line through the connecting line base, power is supplied to the capacitor module through the power module, and current is transmitted to the first triode through the capacitor module, so that the first triode changes from the cut-off state to the on state; if the system switch of the power module is closed before the first triode changes from the on state back to the cut-off state, current is transmitted to the second triode through the power module, so that the second triode changes from the cut-off state to the on state; wherein, the first triode changes from the on state back to the cut-off state means that the negative voltage of the target capacitor continues to drop to less than or equal to the base conduction voltage of the first triode; the voltage is transmitted to the first voltage-dividing resistor through the collector of the second triode, and after the voltage is divided by the first voltage-dividing resistor, the voltage is transmitted to the connecting pin and the second voltage-dividing resistor respectively; the current voltage of the connecting pin is controlled by setting the resistance values ​​of the first voltage-dividing resistor and the second voltage-dividing resistor, so that the current voltage of the connecting pin is high level, thereby triggering the firmware update. The above technical scheme can use a universal USB line to implement firmware update of electronic equipment, reduce costs, and avoid damage to electronic equipment caused by incorrect use of a dedicated USB line.

[0088] Embodiment 3

[0089] Figure 3 This is a schematic diagram of a firmware update circuit of an electronic device according to the third embodiment of the present application, which can be applied to the case where the firmware of an electronic device is updated using a universal USB cable. The firmware update circuit of the electronic device can be implemented in the form of hardware and can be configured in a target electronic device, such as a USB base. Figure 3 As shown, the circuit includes a connecting wire base 10, a main control chip 20, a power module 30, a capacitor module 40, a first transistor 50 and a second transistor 60; the capacitor module 40 includes at least a target capacitor; the negative electrode of the target capacitor is grounded through a resistor; the negative electrode of the target capacitor is connected to the first transistor 50 through a resistor; the first transistor 50 and the second transistor 60 are connected through a resistor; the second transistor 60 and the main control chip 20 are connected through a resistor;

[0090] The power module 30 is used to supply power to the capacitor module 40 when a connection is established with the universal connection line through the connection line base 10;

[0091] The capacitor module 40 is used to transmit current to the first transistor 50 so as to change the first transistor 50 from a cut-off state to a conducting state;

[0092] The power module 30 is also used for transmitting current to the second transistor 60 when the system switch of the power module 30 is closed before the first transistor 50 changes from the on state to the off state, so that the second transistor 60 changes from the off state to the on state; wherein the first transistor 50 changes from the on state to the off state means that the negative electrode voltage of the target capacitor continues to decrease to less than or equal to the base conduction voltage of the first transistor;

[0093] The second transistor 60 is used to transmit voltage to the main control chip 20, so that the current voltage of the connection pin between the main control chip 20 and the second transistor 60 is high, thereby triggering firmware update.

[0094] When the embodiment of the present application establishes a connection with the universal connecting line through the connecting line base, power is supplied to the capacitor module through the power module, and current is transmitted to the first transistor through the capacitor module, so that the first transistor changes from the cut-off state to the on state; if the system switch of the power module is closed before the first transistor changes from the on state back to the cut-off state, current is transmitted to the second transistor through the power module, so that the second transistor changes from the cut-off state to the on state; wherein, the first transistor changes from the on state back to the cut-off state means that the negative voltage of the target capacitor continues to drop to less than or equal to the base conduction voltage of the first transistor; voltage is transmitted to the main control chip through the second transistor, so that the current voltage of the connecting pin between the main control chip and the second transistor is a high level, thereby triggering a firmware update. The above technical solution can use a universal USB cable to implement firmware update of electronic devices, reduce costs, and avoid damage to electronic devices caused by incorrect use of dedicated USB cables.

[0095] Optionally, the second transistor 60 is connected to the main control chip 20 via a first voltage-dividing resistor and a second voltage-dividing resistor; the second transistor 60, the first voltage-dividing resistor and the second voltage-dividing resistor are connected in series; the connecting pin is connected in parallel with the second voltage-dividing resistor;

[0096] The collector of the second triode is used to transmit voltage to the first voltage-dividing resistor;

[0097] The first voltage-dividing resistor is used to transmit the voltage to the connecting pin and the second voltage-dividing resistor respectively after voltage division;

[0098] The resistance values ​​of the first voltage-dividing resistor and the second voltage-dividing resistor are used to control the current voltage of the connecting pin so that the current voltage of the connecting pin is a high level.

[0099] Optionally, the first voltage-dividing resistor and the second voltage-dividing resistor are specifically used for:

[0100] The resistance values ​​of the first voltage-dividing resistor and the second voltage-dividing resistor are pre-configured through the system voltage of the power module 30 to control the current voltage of the connection pin to be a high level; wherein the current voltage is determined by calculating the collector voltage of the collector, the resistance values ​​of the first voltage-dividing resistor and the second voltage-dividing resistor via a series-parallel circuit.

[0101] Optionally, the negative electrode of the target capacitor is grounded through a grounding resistor; the grounding resistor is connected in parallel with the first transistor 50; the negative electrode of the target capacitor is connected in series with the grounding resistor; the negative electrode of the target capacitor is connected in series with the first transistor 50 through a resistor; the grounding resistor and the target capacitor are used for:

[0102] According to the supply voltage of the power module, the grounding resistance of the grounding resistor and the capacitance of the target capacitor are adjusted to control the time length for the first transistor to change from the off state to the on state and from the on state to the off state.

[0103] Optionally, the negative electrode of the target capacitor is connected in series with the base of the first transistor 50 through a first bias resistor; the collector of the first transistor 50 is connected in series with the base of the second transistor 60 through a second bias resistor; and the grounding resistor is connected in parallel with the first bias resistor and the first transistor 50.

[0104] Optionally, the capacitor module 40 further includes a discharge resistor and a discharge diode; the target capacitor, the discharge resistor and the discharge diode are connected in series;

[0105] The target capacitor is used to transmit current to the discharge resistor and the discharge diode through the positive electrode when the connection line base is disconnected from the universal connection line, so as to form a discharge loop to discharge the target capacitor.

[0106] The firmware update circuit of the electronic device provided in the embodiment of the present application can execute the firmware update method of the electronic device provided in any embodiment of the present application, and has the corresponding functional modules and beneficial effects for executing the firmware update method of each electronic device.

[0107] According to an embodiment of the present application, the present application also provides an electronic device, a readable storage medium and a computer program product.

[0108] Embodiment 4

[0109] Figure 44 is a schematic diagram of the structure of an electronic device 410 that implements the firmware update method of the electronic device of the embodiment of the present application. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present application described and / or required herein.

[0110] like Figure 4 As shown, the electronic device 410 includes at least one processor 411, and a memory connected to the at least one processor 411 in communication, such as a read-only memory (ROM) 412, a random access memory (RAM) 413, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 411 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 412 or the computer program loaded from the storage unit 418 to the random access memory (RAM) 413. In RAM413, various programs and data required for the operation of the electronic device 410 can also be stored. The processor 411, ROM412 and RAM413 are connected to each other via a bus 414. An input / output (I / O) interface 415 is also connected to the bus 414.

[0111] Multiple components in the electronic device 410 are connected to the I / O interface 415, including: an input unit 416, such as a keyboard, a mouse, etc.; an output unit 417, such as various types of displays, speakers, etc.; a storage unit 418, such as a disk, an optical disk, etc.; and a communication unit 419, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 419 allows the electronic device 410 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0112] The processor 411 may be a variety of general and / or dedicated processing components with processing and computing capabilities. Some examples of the processor 411 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 411 performs the various methods and processes described above, such as a firmware update method for an electronic device.

[0113] In some embodiments, the firmware update method of the electronic device may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 418. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 410 via the ROM 412 and / or the communication unit 419. When the computer program is loaded into the RAM 413 and executed by the processor 411, one or more steps of the firmware update method of the electronic device described above may be performed. Alternatively, in other embodiments, the processor 411 may be configured as a firmware update method for the electronic device in any other appropriate manner (e.g., by means of firmware).

[0114] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0115] The computer programs for implementing the methods of the present application may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a firmware update device of a general-purpose computer, a special-purpose computer, or other programmable electronic device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine as a stand-alone software package and partially on a remote machine, or entirely on a remote machine or server.

[0116] In the context of the present application, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, device, or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0117] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0118] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0119] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0120] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this application can be executed in parallel, sequentially or in different orders, as long as the expected results of the technical solution of this application can be achieved, and this document is not limited here.

[0121] The above specific implementations do not constitute a limitation on the protection scope of this application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this application should be included in the protection scope of this application.

Claims

1. A method for updating the firmware of an electronic device, characterized in that: A firmware update circuit applied to a target electronic device; the firmware update circuit comprises a connection line base, a main control chip, a power module, a capacitor module, a first transistor and a second transistor; the capacitor module comprises at least a target capacitor; the negative electrode of the target capacitor is grounded through a resistor; the negative electrode of the target capacitor is connected to the first transistor through a resistor; The first transistor and the second transistor are connected via a resistor; the second transistor and the main control chip are connected via a resistor; the method comprises: When the connection is established with the universal connection line through the connection line base, the power supply module supplies power to the capacitor module, and the capacitor module transmits current to the first transistor, so that the first transistor changes from a cut-off state to a conducting state; If the system switch of the power module is closed before the first transistor changes from the on state to the off state, current is transmitted to the second transistor through the power module to change the second transistor from the off state to the on state; wherein the first transistor changes from the on state to the off state means that the negative electrode voltage of the target capacitor continues to drop to less than or equal to the base on voltage of the first transistor; The voltage is transmitted to the main control chip through the second transistor, so that the current voltage of the connecting pin between the main control chip and the second transistor is at a high level, thereby triggering the firmware update.

2. The method according to claim 1, characterized in that The second triode is connected to the main control chip through a first voltage-dividing resistor and a second voltage-dividing resistor; the second triode, the first voltage-dividing resistor and the second voltage-dividing resistor are connected in series; the connecting pin is connected in parallel with the second voltage-dividing resistor; accordingly, a voltage is transmitted to the main control chip through the second triode so that the current voltage of the connecting pin between the main control chip and the second triode is a high level, including: transmitting a voltage to the first voltage-dividing resistor through the collector of the second transistor, and after dividing the voltage through the first voltage-dividing resistor, transmitting the voltage to the connecting pin and the second voltage-dividing resistor respectively; The current voltage of the connecting pin is controlled by setting the resistance values ​​of the first voltage-dividing resistor and the second voltage-dividing resistor, so that the current voltage of the connecting pin is a high level.

3. The method according to claim 2, characterized in that Controlling the current voltage of the connection pin by setting the resistance values ​​of the first voltage-dividing resistor and the second voltage-dividing resistor includes: By pre-configuring the resistance values ​​of the first voltage-dividing resistor and the second voltage-dividing resistor according to the system voltage of the power module, so as to control the current voltage of the connecting pin to be a high level; The current voltage is determined by calculating the collector voltage of the collector, the resistance values ​​of the first voltage-dividing resistor and the second voltage-dividing resistor via a series-parallel circuit.

4. The method according to claim 1, characterized in that: The negative electrode of the target capacitor is grounded through a grounding resistor; the grounding resistor is connected in parallel with the first transistor; the negative electrode of the target capacitor is connected in series with the grounding resistor; the negative electrode of the target capacitor is connected in series with the first transistor through a resistor; accordingly, the method further includes: The grounding resistance of the grounding resistor and the capacitance of the target capacitor are adjusted according to the supply voltage of the power module to control the time length for the first transistor to change from the off state to the on state and from the on state back to the off state.

5. The method according to claim 4, characterized in that The negative electrode of the target capacitor is connected in series with the base of the first transistor through a first bias resistor; the collector of the first transistor is connected in series with the base of the second transistor through a second bias resistor; the grounding resistor is connected in parallel with the first bias resistor and the first transistor.

6. The method according to claim 1, characterized in that The capacitor module further includes a discharge resistor and a discharge diode; the target capacitor, the discharge resistor and the discharge diode are connected in series; accordingly, the method further includes: When the connection line base is disconnected from the universal connection line, current is transmitted to the discharge resistor and the discharge diode through the positive electrode of the target capacitor to form a discharge loop to discharge the target capacitor.

7. A firmware update circuit for an electronic device, characterized in that: The circuit includes a connecting wire base, a main control chip, a power module, a capacitor module, a first transistor and a second transistor; the capacitor module includes at least a target capacitor; the negative electrode of the target capacitor is grounded through a resistor; the negative electrode of the target capacitor is connected to the first transistor through a resistor; the first transistor and the second transistor are connected through a resistor; the second transistor and the main control chip are connected through a resistor; The power supply module is used to supply power to the capacitor module when a connection is established with the universal connection line through the connection line base; The capacitor module is used to transmit current to the first transistor so that the first transistor changes from a cut-off state to a conducting state; The power module is further configured to transmit current to the second transistor when the system switch of the power module is closed before the first transistor changes from the on state to the off state, so that the second transistor changes from the off state to the on state; wherein the first transistor changes from the on state to the off state means that the negative electrode voltage of the target capacitor continues to drop to a value less than or equal to the base on-voltage of the first transistor; The second transistor is used to transmit voltage to the main control chip, so that the current voltage of the connection pin between the main control chip and the second transistor is high level, thereby triggering firmware update.

8. An electronic device, characterized in that: include: one or more processors; A memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the firmware update method for an electronic device as described in any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the firmware updating method of the electronic device as described in any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the firmware update method for an electronic device according to any one of claims 1 to 6.

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