Memory system and method for transmitting data through command address bus

Abstract

The invention relates to a memory system and a method for transmitting data through a command address bus. A memory system includes a memory controller and a memory device. One of the memory controller and the memory device is configured to transmit data to the other of the memory controller and the memory device through the command address bus.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Application No. 10-2023-0144611 filed on October 26, 2023, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Various embodiments relate generally to integrated circuit technology, and more particularly, to a memory system. Background Art

[0004] An electronic device includes many electronic components, and a computer system as an electronic device includes many semiconductor devices each configured by a semiconductor. The semiconductor device constituting the computer system may include a processor or a memory controller and a memory device or a storage device. The processor or the memory controller may work as a master device, and the memory device or the storage device may work as a slave device. The master device may provide a command address signal to the slave device, and the slave device may perform various operations in response to the command address signal. In addition, the master device and the slave device may transmit data to each other.

[0005] In a NAND flash memory system, a NAND flash memory device can communicate with a memory controller through various interface schemes. According to the NAND interface scheme, a command address signal and data can be transmitted through the same input / output bus. As the operating frequency of the NAND flash memory system increases, the NAND interface scheme may cause the performance of the NAND flash memory to decrease due to the increase in command overhead. According to the serial command address (SCA) interface scheme, the command address signal and data can be transmitted through different input / output buses. The command address signal can be transmitted through the command address bus, and the data can be transmitted through the data bus. The SCA interface scheme has the advantages of reducing some command overheads and controlling multiple memory devices to operate in parallel. However, since the transmission cycle of the command address signal is shorter than the transmission cycle of the data, the command address bus may be in an idle state without any action during the long period of time when the data is transmitted through the data bus. Summary of the invention

[0006] In an embodiment, a memory system may include a memory controller and a memory device. The memory device may be coupled to the memory controller via a data bus and a command address bus. One of the memory controller and the memory device may be configured to transmit data to the other of the memory controller and the memory device via the command address bus.

[0007] In an embodiment, a method for operating a memory system including a memory controller and a memory device may include the memory controller transmitting one of a data input command signal and a data output command signal to the memory device via a command address bus. The method may include one of the memory controller and the memory device transmitting a first portion of data to the other of the memory controller and the memory device via a data bus. The method may include the memory controller transmitting a mode command signal to the memory device via the command address bus. And the method may include one of the memory controller and the memory device transmitting a second portion of data to the other of the memory controller and the memory device via the command address bus.

[0008] In an embodiment, a memory system may include: a memory controller; and a memory device connected to the memory controller via a data bus and a command address bus, the data bus being configured to transmit data to be programmed into the memory device, the command address bus being configured to transmit a command address signal, wherein the memory controller is configured to transmit a first portion of the data to be programmed into the memory device to the memory device via the command address bus, and wherein the memory controller is configured to transmit a second portion of the data to be programmed into the memory device to the memory device via the data bus.

[0009] In an embodiment, a memory system may include: a memory controller; and a memory device connected to the memory controller via a data bus and a command address bus, the data bus being configured to transmit data to be read from the memory device, the command address bus being configured to transmit a command address signal, wherein the memory controller is configured to transmit a first portion of the data to be read from the memory device to the memory controller via the command address bus, and wherein the memory controller is configured to transmit a second portion of the data to be read from the memory device to the memory controller via the data bus.

[0010] In an embodiment, a method for operating a memory system including a memory controller and a memory device may be provided, the method comprising: transmitting a command address signal through a command address bus; transmitting a first portion of data to be programmed into the memory device to the memory device through the command address bus; and transmitting a second portion of data to be programmed into the memory device to the memory device through a data bus.

[0011] In an embodiment, a method for operating a memory system including a memory controller and a memory device may be provided, the method comprising: transmitting a command address signal through a command address bus; transmitting a first portion of data to be read from the memory device to the memory controller through the command address bus; and transmitting a second portion of data to be read from the memory device to the memory controller through a data bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram showing a configuration of a memory system according to an embodiment.

[0013] Figure 2 is a timing diagram illustrating the operation of the memory system according to the embodiment.

[0014] Figure 3 is a timing diagram illustrating a data input operation of a memory system according to an embodiment.

[0015] Figure 4 is a timing diagram illustrating a data output operation of a memory system according to an embodiment.

[0016] Figure 5 is a diagram showing a configuration of a memory device according to an embodiment.

[0017] Figure 6 It is shown Figure 5 A diagram of the configuration of an embodiment of a command address buffer is shown.

[0018] Figure 7 It is shown Figure 5 A diagram showing a configuration of an embodiment of a second data input / output circuit shown.

[0019] Fig. 8A and Figure 8B It is shown Figure 7 A timing diagram of an embodiment of the operation of the second data input / output circuit is shown.

[0020] Fig. 9 is a diagram showing a configuration of a memory controller according to an embodiment.

[0021] Fig.10 It is shown Fig. 9 A diagram showing a configuration of an embodiment of a second data input / output circuit shown. DETAILED DESCRIPTION

[0022] Figure 1 is a block diagram showing a configuration of a memory system 100 according to an embodiment. Figure 1, the memory system 100 may include a memory controller 110 and a memory device 120. The memory controller 110 may provide various control signals for the operation of the memory device 120 to the memory device 120. Based on the control signals provided from the memory controller 110, the memory device 120 may perform various operations. The memory device 120 may perform data input and data output operations using the memory controller 110. The data input operation may be an operation of transferring data from the memory controller 110 to the memory device 120. The data output operation may be an operation of transferring data from the memory device 120 to the memory controller 110. For example, the memory device 120 may be a flash memory device, the data input operation may be a random data input operation, and the data output operation may be a random data output operation. The memory device 120 may include a plurality of memory dies 121 and 122. Each of the plurality of memory dies 121 and 122 may independently perform a data input operation and a data output operation.

[0023] The memory controller 110 may be coupled to the memory device 120 via a plurality of buses. The plurality of buses may be signal transmission paths, links or channels for transmitting signals. The plurality of buses may include a command address bus 101, a command clock bus 102, a data bus 103, a data strobe bus 104 and a chip enable bus 105. The chip enable bus 105 may be a unidirectional bus from the memory controller 110 to the memory device 120. Each of the command address bus 101, the command clock bus 102, the data bus 103 and the data strobe bus 104 may be a bidirectional bus. The memory controller 110 may provide a command address signal CA<0:1> to the memory device 120 via the command address bus 101. The command address signal CA<0:1> may include a command signal and an address signal. The command signal may include command information indicating an operation to be performed by the memory device 120. The address signal may include address information for accessing storage areas of a plurality of memory dies 121 and 122 in the memory device 120. For example, the memory controller 110 may provide a command address signal CA<0:1> including a data input command signal, a data output command signal, and a mode command signal. In an embodiment, the mode command signal may include a first mode command signal and a second mode command signal. In each unit cycle, the memory controller 110 may transmit a 2-bit signal to the memory device 120 through the command address bus 101. The command address signal CA<0:1> transmitted in multiple cycles may constitute a single command address signal set.

[0024] The memory controller 110 may provide the command clock signal CCK to the memory device 120 through the command clock bus 102. The memory device 120 may provide the command clock signal CCK to the memory controller 110 through the command clock bus 102. The command clock bus 102 may be a signal synchronized with a signal transmitted through the command address bus 101, and may be a signal defining a time period during which the memory device 120 may receive the signal transmitted through the command address bus 101 as a valid signal. For example, during a time interval during which the command clock signal CCK switches, the memory device 120 may sample the signal transmitted from the memory controller 110 through the command address bus 101 as a valid signal. The memory controller 110 may sample the signal transmitted from the memory device 120 through the command address bus 101 as a valid signal. Through the data bus 103, the memory controller 110 may provide the data signal DQ<0:7> to the memory device 120, or receive the data signal DQ<0:7> from the memory device 120. For example, the data signal DQ<0:7> may include 8 bits, and the 8-bit data signal DQ<0:7> may be transmitted through the data bus 103 in each unit cycle. The data signal DQ<0:7> transmitted in multiple cycles may constitute a data set. The memory controller 110 may transmit the data strobe signal DQS to the memory device 120 through the data strobe bus 104. The memory device 120 may transmit the data strobe signal DQS to the memory controller 110 through the data strobe bus 104.

[0025] The memory controller 110 may transmit the chip enable signal CE# to the memory device 120 through the chip enable bus 105. The number of bits included in the chip enable signal CE# may vary according to the number of memory dies and / or memory chips included in the memory device 120. For example, when the memory device 120 includes two (2) memory dies or memory chips, the chip enable signal CE# may include 1 bit or 2 bits. When the memory device 120 includes four (4) memory dies or memory chips, the chip enable signal CE# may include 2 bits or 4 bits. The memory controller 110 may provide the chip enable signal CE# to the memory device 120 through the chip enable bus 105. The chip enable signal CE# may be used as a signal to identify a memory die among a plurality of memory dies included in the memory device 120 to perform an operation in response to the command address signal CA<0:1>.

[0026] Figure 2 1 is a timing diagram showing the operation of the memory system 100 according to an embodiment. Figure 1 and Figure 2, the memory controller 110 may provide a command address signal CA<0:1> to the memory device 120 through the command address bus 101, the command address signal CA<0:1> including a data input command signal CMD1 or a data output command signal CMD2 for a data input operation or a data output operation. After providing the data input command signal CMD1 or the data output command signal CMD2, data DOUT or DIN may be transmitted through the data bus 103. When the memory controller 110 provides the data input command signal CMD1, a data input operation may be performed, and the memory controller 110 may transmit the data DIN to the memory device 120 by transmitting the data signal DQ<0:7> through the data bus 103 in a plurality of unit cycles. When the memory controller 110 provides the data output command signal CMD2, a data output operation may be performed, and the memory device 120 may transmit the data DOUT to the memory controller 110 by transmitting the data signal DQ<0:7> through the data bus 103 in a plurality of unit cycles. The total number of bits of the data input command signal CMD1 or the data output command signal CMD2 may be less than the total number of bits of the data DIN and DOUT, and the time interval for transmitting the command address signal CA<0:1> may be shorter than the time interval for transmitting the data signal DQ<0:7>. Therefore, during the time interval for transmitting the data signal DQ<0:7>, the command address bus 101 may remain idle and may not transmit any information. In addition, when all data is transmitted through the data bus 103, the time interval for transmitting the data DIN and DOUT may not be shortened. In order to effectively use the command address bus 101 that remains idle, the memory system 100 according to the embodiment may transmit the data signal through the command address bus 101. In an embodiment, by transmitting the data signal via the command address bus 101, the memory system 100 can reduce the time interval for transmitting the data DIN and DOUT, can increase the speed of the data input / output (input and output) operation, and can improve the performance of the memory system 100.

[0027] Figure 3 1 is a timing diagram showing a data input operation of the memory system 100 according to an embodiment. Figure 1 and Figure 3, the memory controller 110 may provide the command address signal CA<0:1> including the data input command signal CMD1 for the data input operation to the memory device 120 through the command address bus 101. Together with the command address signal CA<0:1>, the memory controller 110 may provide the command clock signal CCK synchronized with the command address signal CA<0:1>. During the data input operation after providing the data input command signal CMD1, the memory controller 110 may provide the data DIN1 to DIN3 as the data signal DQ<0:7> to the memory device 120 through the data bus 103, which is the first part of the data DIN1 to DIN4. Together with the data DIN1 to DIN3 or the first part of the data DIN1 to DIN4, the memory controller 110 may provide the data strobe signal DQS synchronized with the data DIN1 to DIN3. After providing the data input command signal CMD1, the memory controller 110 may provide the command address signal CA<0:1> including the mode command signal MCMD to the memory device 120 through the command address bus 101. Together with the command address signal CA<0:1>, the memory controller 110 may provide a command clock signal CCK synchronized with the command address signal CA<0:1>. Upon receiving the data input command signal CMD1 and the mode command signal MCMD, the memory device 120 may enable the first data mode signal CBDI to activate the data input / output (input and output) mode. Once the data input / output mode is activated, the command address bus 101 may be ready to transmit data signals. In one embodiment, the mode command signal MCMD may be replaced by the first mode command signal CMD3, and the memory device 120 may enable the first data mode signal CBDI upon receiving the command address signal CA<0:1> including the first mode command signal CMD3. After providing the mode command signal MCMD or the first mode command signal CMD3, the memory controller 110 may provide the data DIN4 or the second part of the data DIN1 to DIN4 to the memory device 120 through the command address bus 101. Together with the data DIN4 or the second part of the data DIN1 to DIN4, the memory controller 110 may provide the memory device 120 with the command clock signal CCK synchronized with the data DIN4. Once the transmission of the data DIN1 to DIN4 is completed, the memory controller 110 may provide the chip enable signal CE# to the memory device 120. The pulse width of the chip enable signal CE# may be greater than the predetermined pulse width. Upon receiving the chip enable signal CE#, the memory device 120 may generate a reset signal CBRST based on the chip enable signal CE#. The memory device 120 may detect the pulse width of the chip enable signal CE# to generate the reset signal CBRST.When the pulse width is greater than the predetermined pulse width, the memory device 120 may enable the reset signal CBRST. Based on the reset signal CBRST, the memory device 120 may disable the first data mode signal CBDI and may disable the data input / output mode. When the data input / output mode is disabled, the command address bus 101 may be ready to transmit the command address signal CA<0:1>. In an embodiment, when data DIN1 to DIN4 are transmitted simultaneously through both the data bus 103 and the command address bus 101 during a data input operation, the time interval for transmitting the data signal DQ<0:7> through the data bus 103 may be reduced, and the amount of time required for the data input operation may be reduced. The word "predetermined" used herein with respect to a parameter (e.g., a predetermined pulse width) refers to a value of a parameter determined before the parameter is used in a process or algorithm. For some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0028] Figure 4 is a timing diagram showing a data output operation of the memory system 100 according to an embodiment. Figure 1 and Figure 4, the memory controller 110 may provide the command address signal CA<0:1> including the data output command signal CMD2 for the data output operation to the memory device 120 through the command address bus 101. Together with the command address signal CA<0:1>, the memory controller 110 may provide the command clock signal CCK synchronized with the command address signal CA<0:1>. During the data output operation after the memory controller 110 provides the data output command signal CMD2, the memory device 120 may provide the data DOUT1 to DOUT3 to the memory controller 110 as the data signal DQ<0:7> through the data bus 103, which DOUT1 to DOUT3 are the first part of the data DOUT1 to DOUT4. Together with the data DOUT1 to DOUT3 or the first part of the data DOUT1 to DOUT4, the memory device 120 may provide the data strobe signal DQS synchronized with the data DOUT1 to DOUT3. After providing the data output command signal CMD2, the memory controller 110 may provide the command address signal CA<0:1> including the mode command signal MCMD to the memory device 120 through the command address bus 101. Together with the command address signal CA<0:1>, the memory controller 110 may provide a command clock signal CCK synchronized with the command address signal CA<0:1>. Upon receiving the data output command signal CMD2 and the mode command signal MCMD, the memory device 120 may enable the second data mode signal CBDO to activate the data input / output mode. Once the data input / output mode is activated, the command address bus 101 may be ready to transmit the data signal. In one embodiment, the mode command signal MCMD may be replaced by the second mode command signal CMD4, and the memory device 120 may enable the second data mode signal CBDO upon receiving the command address signal CA<0:1> including the second mode command signal CMD4. After receiving the mode command signal MCMD or the second mode command signal CMD4, the memory device 120 may provide the data DOUT4 or the second part of the data DOUT1 to DOUT4 to the memory controller 110 through the command address bus 101. Together with the data DOUT4 or the second part of the data DOUT1 to DOUT4, the memory device 120 may provide a command clock signal CCK synchronized with the data DOUT4. Once the transmission of the data DOUT1 to DOUT4 is completed, the memory controller 110 may provide the chip enable signal CE# having a pulse width greater than a predetermined pulse width to the memory device 120. Upon receiving the chip enable signal CE#, the memory device 120 may generate a reset signal CBRST based on the chip enable signal CE#. Based on the reset signal CBRST, the memory device 120 may disable the second data mode signal CBDO and may deactivate the data input / output mode.When the data input / output mode is disabled, the command address bus 101 may be ready to transmit the command address signal CA<0:1>. In an embodiment, when data DOUT1 to DOUT4 are simultaneously transmitted through both the data bus 103 and the command address bus 101 during a data output operation, a time interval for transmitting the data signal DQ<0:7> through the data bus 103 may be reduced, and the amount of time required for the data output operation may be reduced.

[0029] Figure 5 2 is a diagram showing a configuration of a memory device 200 according to an embodiment. The memory device 200 may be used as Figure 1 At least one of the plurality of memory dies 121 and 122 of the memory device 120 shown in FIG. 1 is applied. Figure 1 , Figure 3 , Figure 4 and Figure 5 , the memory device 200 may include a command address buffer 210, a command control circuit 220, a first data input / output (input and output) circuit 230, and a second data input / output (input and output) circuit 240. The command address buffer 210 may be connected to the command address bus 101. The command address buffer 210 may receive a signal transmitted through the command address bus 101, and may generate an internal command address signal ICA<0:1>. The command address buffer 210 may buffer a signal transmitted through the command address bus 101 to generate an internal command address signal ICA<0:1>. The command address buffer 210 may receive the internal command address signal ICA<0:1>, may buffer the internal command address signal ICA<0:1>, and may output the buffered signal to the command address bus 101. The command address buffer 210 may receive a read enable signal REN. The read enable signal REN may be generated based on the command address signal CA<0:1>, and may be used when the memory device 200 performs various information including data output to Figure 1is enabled when the operation of the memory controller 110 is enabled. When the read enable signal REN is disabled, the command address buffer 210 may buffer the signal transmitted through the command address bus 101 to generate the internal command address signal ICA<0:1>. When the read enable signal REN is disabled and the data input / output mode is deactivated, the command address buffer 210 may buffer the command address signal CA<0:1> transmitted through the command address bus 101 to generate the internal command address signal ICA<0:1>. When the read enable signal REN is disabled and the data input / output mode is activated, the command address buffer 210 may buffer the data signal transmitted through the command address bus 101 to generate the internal command address signal ICA<0:1>. When the read enable signal REN is enabled, the command address buffer 210 may drive the command address bus 101 based on the internal command address signal ICA<0:1>.

[0030] The command control circuit 220 may be coupled to the command address buffer 210 and may receive an internal command address signal ICA<0:1>. Based on the internal command address signal ICA<0:1>, the command control circuit 220 may generate a first data mode signal CBDI and a second data mode signal CBDO. When receiving the internal command address signal ICA<0:1> including the data input command signal CMD1 and the mode command signal MCMD, the command control circuit 220 may enable the first data mode signal CBDI. When receiving the internal command address signal ICA<0:1> including the data output command signal CMD2 and the mode command signal MCMD, the command control circuit 220 may enable the second data mode signal CBDO. In one embodiment, the command control circuit 220 may enable the first data mode signal CBDI when receiving the internal command address signal ICA<0:1> including the first mode command signal CMD3, and may enable the second data mode signal CBDO when receiving the internal command address signal ICA<0:1> including the second mode command signal CMD4. The command control circuit 220 may receive a chip enable signal CE#. Based on the chip enable signal CE#, the command control circuit 220 may disable the first data pattern signal CBDI and the second data pattern signal CBDO. The command control circuit 220 may detect the pulse width of the chip enable signal CE# to disable the first data pattern signal CBDI and the second data pattern signal CBDO.

[0031] The command control circuit 220 may include a command decoding circuit 221 and a reset circuit 222. The command decoding circuit 221 may receive an internal command address signal ICA<0:1>, and may decode the internal command address signal ICA<0:1> to generate various internal command signals. The command decoding circuit 221 may also receive a command clock signal CCK through the command clock bus 102, and may latch the internal command address signal ICA<0:1> based on the command clock signal CCK. The command decoding circuit 221 may decode the latched internal command address signal ICA<0:1> to generate various internal command signals. When the internal command address signal ICA<0:1> includes the data output command signal CMD2, the command decoding circuit 221 may generate a read enable signal REN. When the internal command address signal ICA<0:1> includes the mode command signal MCMD, the command decoding circuit 221 may enable one of the first data mode signal CBDI and the second data mode signal CBDO. When the data input command signal CMD1 is received before the mode command signal MCMD, the command decoding circuit 221 may enable the first data mode signal CBDI. When the data output command signal CMD2 is received before the mode command signal MCMD, the command decoding circuit 221 may enable the second data mode signal CBDO. In one embodiment, when the internal command address signal ICA<0:1> including the first mode command signal CMD3 is received, the command decoding circuit 221 may enable the first data mode signal CBDI. When the internal command address signal ICA<0:1> including the second mode command signal CMD4 is received, the command decoding circuit 221 may enable the second data mode signal CBDO. The command decoding circuit 221 may receive a reset signal CBRST generated by the reset circuit 222. When the reset signal CBRST is enabled, the command decoding circuit 221 may disable the first data mode signal CBDI and the second data mode signal CBDO.

[0032] The reset circuit 222 may receive the chip enable signal CE# and may generate a reset signal CBRST. The reset circuit 222 may detect the pulse width of the chip enable signal CE# to generate the reset signal CBRST. When the pulse width of the chip enable signal CE# is equal to or greater than a predetermined pulse width, the reset circuit 222 may enable the reset signal CBRST. For example, the reset circuit 222 may include a counter, may use an arbitrary clock signal to count the enable duration of the chip enable signal CE#, and may enable the reset signal CBRST when the result of the count becomes a threshold value or greater.

[0033] The first data input / output circuit 230 may be coupled to the data bus 103 and the data strobe bus 104. During a data input operation, the first data input / output circuit 230 may receive a data signal DQ<0:7> transmitted from the memory controller 110 through the data bus 103. During a data output operation, the first data input / output circuit 230 may output the data signal DQ<0:7> to the memory controller 110 through the data bus 103. During a data input operation, the first data input / output circuit 230 may receive a data strobe signal DQS transmitted from the memory controller 110 through the data strobe bus 104. During a data output operation, the first data input / output circuit 230 may output the data strobe signal DQS to the memory controller 110 through the data strobe bus 104. During a data input operation, the first data input / output circuit 230 may receive the data signal DQ<0:7> and may generate memory data MD1 to MD3 as a first portion of the memory data MD1 to MD4. The memory data MD1 to MD4 may include a first memory data signal MD1, a second memory data signal MD2, a third memory data signal MDR3, and a fourth memory data signal MD4. The memory data MD1 to MD3 as the first part of the memory data MD1 to MD4 may include a first memory data signal MD1, a second memory data signal MD2, and a third memory data signal MD3. The memory device 200 may include a plurality of memory banks, each of which is a unit of a memory cell array that can independently perform a programming operation and a read operation. For example, the memory device 200 may include four memory banks. The first memory data signal MD1 may represent data of the first memory bank BK1.

[0034] The first memory data signal MD1 may be data stored in the first memory bank BK1 .

[0035] The first memory data signal MD1 may be data retrieved from the first memory bank BK1. The second memory data signal MD2 may represent data of the second memory bank BK2. The second memory data signal MD2 may be data stored in the second memory bank BK2. The second memory data signal MD2 may be data retrieved from the second memory bank BK2. The third memory data signal MD3 may represent data of the third memory bank BK3. The third memory data signal MD3 may be data stored in the third memory bank BK3. The third memory data signal MD3 may be data retrieved from the third memory bank BK3. The fourth memory data signal MD4 may represent data of the fourth memory bank BK4. The fourth memory data signal MD4 may be data stored in the fourth memory bank BK4. The fourth memory data signal MD4 may be data retrieved from the fourth memory bank BK4. The first data input / output circuit 230 may generate the first memory data signal MD1, the second memory data signal MD2, and the third memory data signal MD3 according to the data signal DQ<0:7> transmitted through the data bus 103. The first data input / output circuit 230 may generate a first data clock signal DCK1, a second data clock signal DCK2, and a third data clock signal DCK3 according to a data strobe signal DQS provided together with the data signal DQ<0:7>. The first data input / output circuit 230 may output a first memory data signal MD1 together with the first data clock signal DCK1, may output a second memory data signal MDR2 together with the second data clock signal DCK2, and may output a third memory data signal MD3 together with the third data clock signal DCK3. During a data output operation, the first data input / output circuit 230 may receive memory data MD1 to MD3 as a first portion of memory data MD1 to MD4 to generate a data signal DQ<0:7>. The first data input / output circuit 230 may receive a first memory data signal MD1, a second memory data signal MD2, and a third memory data signal MD3, and may output the first to third memory data signals MD1 to MD3 as data signals DQ<0:7> through the data bus 103. The first data input / output circuit 230 may receive the first to third data clock signals DCK1, DCK2, and DCK3 and the first to third memory data signals MD1 to MD3. The first data input / output circuit 230 may output the first to third data clock signals DCK1, DCK2, and DCK3 as a data strobe signal DQS through the data strobe bus 104.

[0036] The second data input / output circuit 240 may be coupled to an internal bus providing an internal command address signal ICA<0:1> and the data bus 103. The second data input / output circuit 240 may also be coupled to the command clock bus 102 and the data strobe bus 104. The second data input / output circuit 240 may receive a first data mode signal CBDI and a second data mode signal CBDO. According to the first data mode signal CBDI and the second data mode signal CBDO, the second data input / output circuit 240 may be selectively coupled to one of the data bus 103 and the internal bus providing the internal command address signal ICA<0:1>. According to the first data mode signal CBDI and the second data mode signal CBDO, the second data input / output circuit 240 may be selectively coupled to the data bus 103 or the data strobe bus 104. When the first data mode signal CBDI and the second data mode signal CBDO are disabled, the second data input / output circuit 240 may be coupled to both the data bus 103 and the data strobe bus 104. The second data input / output circuit 240 may receive the data signal DQ<0:7> through the data bus 103, or may output the data signal DQ<0:7> through the data bus 103. The second data input / output circuit 240 may receive the data strobe signal DQS through the data strobe bus 104, or may output the data strobe signal DQS through the data strobe bus 104.

[0037] When the first data mode signal CBDI or the second data mode signal CBDO is enabled, the second data input / output circuit 240 may be connected to the command clock bus 102 and the internal bus providing the internal command address signal ICA<0:1>. When the first data mode signal CBDI is enabled, the second data input / output circuit 240 may receive the internal command address signal ICA<0:1>, and may generate the fourth memory data signal MD4 as the second part of the memory data MD1 to MD4 according to the internal command address signal ICA<0:1>. The second data input / output circuit 240 may also receive the command clock signal CCK through the command clock bus 102, and may generate the fourth data clock signal DCK4 according to the command clock signal CCK. When the second data mode signal CBDO is enabled, the second data input / output circuit 240 may receive the fourth memory data signal MD4, and may generate the internal command address signal ICA<0:1> according to the fourth memory signal MD4. The second data input / output circuit 240 may also receive a fourth data clock signal DCK4, may generate a command clock signal CCK according to the fourth data clock signal DCK4, and may output the command clock signal CCK through the command clock bus 102. The second data input / output circuit 240 may further receive a read enable signal REN. When the read enable signal REN is disabled, the second data input / output circuit 240 may output a fourth memory data signal MD4 and a fourth data clock signal DCK4. When the read enable signal REN is enabled, the second data input / output circuit 240 may receive a fourth memory data signal MD4 and a fourth data clock signal DCK4.

[0038] The memory device 200 may further include a cache latch circuit 250. The cache latch circuit 250 may be coupled to the first data input / output circuit 230 and the second data input / output circuit 240 and the plurality of memory banks BK1, BK2, BK3, and BK4. During a data input operation, the cache latch circuit 250 may receive the first to third memory data signals MD1, MD2, and MD3 and the first to third data clock signals DCK1, DCK2, and DCK3 from the first data input / output circuit 230. During a data output operation, the cache latch circuit 250 may provide the first to third memory data signals MD1, MD2, and MD3 and the first to third data clock signals DCK1, DCK2, and DCK3 to the first data input / output circuit 230. During a data input operation, the cache latch circuit 250 may receive the fourth memory data signal MD4 and the fourth data clock signal DCK4 from the second data input / output circuit 240. During a data output operation, the cache latch circuit 250 may provide the fourth memory data signal MD4 and the fourth data clock signal DCK4 to the second data input / output circuit 240 .

[0039] The cache latch circuit 250 may include a plurality of latch circuits. For example, the number of latch circuits may correspond to the number of memory data signals and / or the number of memory banks. The cache latch circuit 250 may include a first latch circuit 251, a second latch circuit 252, a third latch circuit 253, and a fourth latch circuit 254. During a data input operation, the first latch circuit 251 may store a first memory data signal MD1 output from the first data input / output circuit 230 according to a first data clock signal DCK1. The stored data may be programmed into the first memory bank BK1 during a programming operation. During a read operation, the first latch circuit 251 may store data output from the first memory bank BK1. During a data output operation, the first latch circuit 251 may provide the first data input / output circuit 230 with stored data as the first memory data signal MD1 according to the first data clock signal DCK1. During a data input operation, the second latch circuit 252 may store a second memory data signal MD2 from the first data input / output circuit 230 according to a second data clock signal DCK2. The stored data may be programmed into the second memory bank BK2 during a programming operation. During a read operation, the second latch circuit 252 may store data output from the second memory bank BK2. During a data output operation, the second latch circuit 252 may provide the stored data as the second memory data signal MD2 to the first data input / output circuit 230 according to the second data clock signal DCK2. During a data input operation, the third latch circuit 253 may store the third memory data signal MD3 from the first data input / output circuit 230 according to the third data clock signal DCK3. The stored data may be programmed into the third memory bank BK3 during a programming operation. During a read operation, the third latch circuit 253 may store data output from the third memory bank BK3. During a data output operation, the third latch circuit 253 may provide the stored data as the third memory data signal MD3 to the first data input / output circuit 230 according to the third data clock signal DCK3. During the data input operation, the fourth latch circuit 254 can store the fourth memory data signal MD4 from the second data input / output circuit 240 according to the fourth data clock signal DCK4. The stored data can be programmed into the fourth memory bank BK4 during the programming operation. During the read operation, the fourth latch circuit 254 can store the data output from the fourth memory bank BK4. During the data output operation, the fourth latch circuit 254 can provide the stored data as the fourth memory data signal MD4 to the second data input / output circuit 240 according to the fourth data clock signal DCK4.

[0040] Figure 6 It is shown Figure 5FIG. 2 is a diagram showing a configuration of the command address buffer 210. Figure 6 , the command address buffer 210 may include a first buffer 310, a first control buffer 320, a second buffer 330, and a second control buffer 340. The first buffer 310 may be coupled to the command address bus 101, and may buffer a signal transmitted through the command address bus 101. Based on the second data mode signal CBDO, the first control buffer 320 may selectively output a signal output from the first buffer 310 as an internal command address signal ICA<0:1>. The first control buffer 320 may receive an inverted signal of the second data mode signal CBDO. When the second data mode signal CBDO is disabled, the first control buffer 320 may couple the first buffer 310 to an internal bus providing the internal command address signal ICA<0:1>, and an output signal from the first buffer 310 may be provided as the internal command address signal ICA<0:1>. When the second data mode signal CBDO is enabled, the first control buffer 320 may disconnect the first buffer 310 from the internal bus providing the internal command address signal ICA<0:1>. The third buffer 330 may receive the internal command address signal ICA<0:1> and may buffer the internal command address signal ICA<0:1>. The second control buffer 340 may receive the second data pattern signal CBDO and may selectively output an output signal from the second buffer 330 to the command address bus 101 based on the second data pattern signal CBDO. When the second data pattern signal CBDO is enabled, the second control buffer 340 may couple the second buffer 330 to the command address bus 101 and may output an output signal from the second buffer 330 to the command address bus 101. When the second data pattern signal CBDO is disabled, the second control buffer 340 may disconnect the second buffer 330 from the command address bus 101.

[0041] The command address buffer 210 may further include an OR gate 351 and an inverter 352, and may further receive a feature data output signal FDO and an identification information output signal RID. The memory device 200 may output feature data and identification information of the memory device 200 through the command address bus 101. When the memory device 200 performs an operation of outputting feature data, the feature data output signal FDO may be enabled. When the memory device 200 performs an operation of outputting identification information, the identification information output signal RID may be enabled. The OR gate 351 may receive a second data mode signal CBDO, a feature data output signal FDO, and an identification information output signal RID. The signal output from the OR gate 351 may be provided as a control signal of the second control buffer 340. The second control buffer 340 may be modified to selectively connect the command address bus 101 and the second buffer 330 to each other based on the output signal from the OR gate 351. The inverter 352 may invert the output signal from the OR gate 351. The signal output from the inverter 352 may be provided as a control signal of the first control buffer 320. The first control buffer 320 may be modified to selectively couple the internal bus providing the internal command address signal ICA<0:1> and the first buffer 310 to each other based on the output signal of the inverter 352 .

[0042] Figure 7 It is shown Figure 5 FIG. 2 is a diagram showing a configuration of the second data input / output circuit 240. Figure 7, the second data input / output circuit 240 may include a first converter 411, a first selection circuit 412, a second selection circuit 413, and a second converter 414. The first converter 411 may receive an internal command address signal ICA<0:1>. The first converter 411 may generate an input conversion data signal CDIN<0:7> according to the internal command address signal ICA<0:1>. The first converter 411 may convert a plurality of internal command address signals ICA<0:1> into an input conversion data signal CDIN<0:7>. For example, the first converter 411 may receive four (4) 2-bit signals of the internal command address signal ICA<0:1>, and may generate a single input conversion data signal CDIN<0:7>. The first converter 411 may be a 2-bit to 8-bit converter. The first selection circuit 412 may be coupled to the first converter 411 and the data bus 103, and may receive a first data mode signal CBDI. Based on the first data mode signal CBDI, the first selection circuit 412 may output one of the signals transmitted through the data bus 103 and the input conversion data signal CDIN<0:7> output from the first converter 411. The output signal from the first selection circuit 412 may be provided as a fourth memory data signal MD4. When the first data mode signal CBDI is disabled, the first selection circuit 412 may output the data signal DQ<0:7> transmitted through the data bus 103 as the fourth memory data signal MD4. When the first data mode signal CBDI is enabled, the first selection circuit 412 may output the input conversion data signal CDIN<0:7> as the fourth memory data signal MD4. The second selection circuit 413 may be coupled to the data bus 103 and the second converter 414, and may receive the fourth memory data signal MD4 and the second data mode signal CBDO. Based on the second data mode signal CBDO, the second selection circuit 413 may output the fourth memory data signal MD4 to one of the data bus 103 and the second converter 414. When the second data mode signal CBDO is disabled, the second selection circuit 413 may output the fourth memory data signal MD4 to the data bus 103, and the fourth memory data signal MD4 may be transmitted as the data signal DQ<0:7> through the data bus 103. When the second data mode signal CBDO is enabled, the second selection circuit 413 may output the fourth memory data signal MD4 to the second converter 414. The second converter 414 may receive the output signal from the second selection circuit 413, and may convert the output signal from the second selection circuit 413 into the internal command address signal ICA<0:7>.The second converter 414 may convert the fourth memory data signal MD4, which is a single signal of 8 bits, into four (4) 2-bit signals of internal command address signals ICA<0:1>, and may sequentially output the four (4) 2-bit signals of internal command address signals ICA<0:1>. The second converter 414 may be an 8-bit to 2-bit converter.

[0043] The second data input / output circuit 240 may further include a first path selection circuit 415. The first path selection circuit 415 may be coupled between the fourth memory data signal MD4 and the first selection circuit 412 and the second selection circuit 413. The first path selection circuit 415 may receive a read enable signal REN, and may couple a line providing the fourth memory data signal MD4 to one of the first selection circuit 412 and the second selection circuit 413 based on the read enable signal REN. When the read enable signal REN is disabled, the first path selection circuit 415 may couple the first selection circuit 412 to the line providing the fourth memory data signal MD4, and may provide a signal output from the first selection circuit 414 as the fourth memory data signal MD4. When the read enable signal REN is enabled, the first path selection circuit 415 may couple the second selection circuit 413 to the line providing the fourth memory data signal MD4, and may provide the fourth memory signal MD4 as a signal to be input to the second selection circuit 413. The first path selection circuit 415 may include a first buffer 415-1 and a second buffer 415-2. The first buffer 415-1 may receive a complementary signal RENB of a read enable signal REN. When the complementary signal RENB is enabled, that is, when the read enable signal REN is disabled, the first buffer 415-1 may buffer an output signal from the first selection circuit 412 to generate a fourth memory data signal MD4. The second buffer 415-2 may receive the read enable signal REN. When the read enable signal REN is enabled, the second buffer 415-2 may buffer the fourth memory data signal MD4 and may provide the buffered signal to the second selection circuit 413.

[0044] The second data input / output circuit 240 may further include a first clock generator 421, a third selection circuit 422, a fourth selection circuit 423, and a second clock generator 424. The first clock generator 421 may be a clock frequency division circuit. The first clock generator 421 may divide the frequency of the command clock signal CCK to generate a divided clock signal VCK. For example, the first clock generator 421 may divide the frequency of the command clock signal CCK into one-fourth (1 / 4), and may create a divided clock signal VCK having a frequency corresponding to one-fourth (1 / 4) of the frequency of the command clock signal CCK. The third selection circuit 422 may be coupled to the first clock generator 421 and the data strobe bus 104, and may receive the first data mode signal CBDI. The third selection circuit 422 may output one of the data strobe signal DQS transmitted through the data strobe bus 104 and the divided clock signal VCK generated by the first clock generator 421 based on the first data mode signal CBDI. The signal output from the third selection circuit 422 may be provided as the fourth data clock signal DCK4. When the first data mode signal CBDI is disabled, the third selection circuit 422 may output the data strobe signal DQS transmitted through the data strobe bus 104 as the fourth data clock signal DCK4. When the first data mode signal CBDI is enabled, the third selection circuit 422 may output the divided clock signal VCK as the fourth data clock signal DCK4. The fourth selection circuit 423 may be coupled to the data strobe bus 104 and the second clock generator 424, and may receive the fourth data clock signal DCK4 and the second data mode signal CBDO. The fourth selection circuit 423 may output the fourth data clock signal DCK4 to one of the data strobe bus 104 and the second clock generator 424 based on the second data mode signal CBDO. When the second data mode signal CBDO is disabled, the fourth selection circuit 423 may output the fourth data clock signal DCK4 to the data strobe bus 104, and may output the fourth data clock signal DCK4 as the data strobe signal DQS through the data strobe bus 104. When the second data mode signal CBDO is enabled, the fourth selection circuit 423 may output the fourth data clock signal DCK4 to the second clock generator 424. The second clock generator 424 may receive the output signal from the fourth selection circuit 423, and may convert the output signal from the fourth selection circuit 423 into the command clock signal CCK. The second clock generator 424 may be a clock multiplication circuit. The second clock generator 424 may multiply the frequency of the output signal from the fourth selection circuit 423 to generate the command clock signal CCK. For example, the second clock generator 424 may generate the command clock signal CCK, the frequency of which is four times the frequency of the output signal from the fourth selection circuit 423.

[0045] The second data input / output circuit 240 may further include a second path selection circuit 425. The second path selection circuit 425 may be connected between the fourth data clock signal DCK4, the third selection circuit 422, and the fourth selection circuit 423. The second path selection circuit 425 may receive a read enable signal REN, and may connect a line providing the fourth data clock signal DCK4 to one of the third selection circuit 422 and the fourth selection circuit 423 based on the read enable signal REN. When the read enable signal REN is disabled, the second path selection circuit 425 may connect the third selection circuit 422 to the line providing the fourth data clock signal DCK4, and may provide a signal output from the third selection circuit 422 as the fourth data clock signal DCK4. When the read enable signal REN is enabled, the second path selection circuit 425 may connect the fourth selection circuit 423 to the line providing the fourth data clock signal DCK4, and may provide the fourth data clock signal DCK3 as a signal to be input to the fourth selection circuit 423. The second path selection circuit 425 may include a third buffer 425-1 and a fourth buffer 425-2. The third buffer 425-1 may receive a complementary signal RENB of the read enable signal REN. When the complementary signal RENB is enabled, that is, when the read enable signal REN is disabled, the third buffer 425-1 may buffer the output signal from the third selection circuit 422 to generate a fourth data clock signal DCK4. The fourth buffer 425-2 may receive the read enable signal REN. When the read enable signal REN is enabled, the fourth buffer 425-2 may buffer the fourth data clock signal DCK4, and may provide the buffered signal to the fourth selection circuit 423.

[0046] Fig. 8A and Figure 8B It is shown Figure 7 2 is a timing diagram of the operation of the second data input / output circuit 240 shown in FIG. Fig. 8A 2 shows the operation of the second data input / output circuit 240 during the data input operation. Figure 5 , Figure 7 and Fig. 8A, when a data input operation is performed and the first data mode signal CBDI is enabled, the read enable signal REN may be disabled. The first path selection circuit 415 may connect the first selection circuit 412 to a line providing a fourth memory data signal MD4, and the second path selection circuit 425 may connect the third selection circuit 422 to a line providing a fourth data clock signal DCK4. The first converter 411 may receive an internal command address signal ICA<0:1>, and may generate an input conversion data signal CDIN<0:7>. Synchronously with the command clock signal CCK, the 2-bit internal command address signal ICA<0:1> may be input to the first converter 411, and the first converter 411 may convert the four (4) 2-bit signals of the internal command address signal ICA<0:1> into one 8-bit input conversion data signal CDIN<0:7>. Each time the first converter 411 receives the four (4) 2-bit signals of the internal command address signal ICA<0:1>, the first converter 411 may generate an 8-bit input conversion data signal CDIN<0:7>. For example, the first converter 411 may generate four (4) 8-bit input conversion data signals CDIN<0:7> based on the sixteen (16) 2-bit internal command address signals ICA<0:1>. The first converter 411 may convert the first to fourth internal command address signals (01, 10, 01, 10) into the first input conversion data signal (01100110), may convert the fifth to eighth internal command address signals (01, 11, 01, 11) into the second input conversion data signal (01110111), may convert the ninth to twelfth internal command address signals (11, 10, 11, 10) into the third input conversion data signal (11101110), and may convert the thirteenth to sixteenth internal command address signals (00, 10, 00, 11) into the fourth input conversion data signal (00100011). The first selection circuit 412 may output the input conversion data signal CDIN<0:7> as the fourth memory data signal MD4. The first clock generator 421 can divide the command clock signal CCK to generate a divided clock signal VCK. The third selection circuit 422 can output the divided clock signal VCK as the fourth data clock signal DCK4. The fourth latch circuit 254 in the cache latch circuit 250 can receive the fourth memory data signal MD4 and the fourth data clock signal DCK4. Synchronous with the edge of the fourth data clock signal DCK4, the fourth latch circuit 254 can store the fourth memory data signal MD4. When the first data mode signal CBDI is disabled, the first selection circuit 412 can connect the data bus 103 to the line providing the fourth memory data signal MD4, and the third selection circuit 422 can connect the data selection bus 104 to the line providing the fourth data clock signal DCK4.The data signal DQ<0:7> transmitted through the data bus 103 may be provided as the fourth memory data signal MD4, and the data strobe signal DQS transmitted through the data strobe bus 104 may be provided as the fourth data clock signal DCK4. In synchronization with the fourth data clock signal DCK4, the fourth latch circuit 254 may store the fourth memory data signal MD4.

[0047] Figure 8B 2 shows the operation of the second data input / output circuit 240 during the data output operation. Figure 5 , Figure 7 and Figure 8B, when a data output operation is performed and the second data mode signal CBDO is enabled, the read enable signal REN may be enabled. The first path selection circuit 415 may connect the second selection circuit 413 to a line providing a fourth memory data signal MD4, and the second path selection circuit 425 may connect the fourth selection circuit 423 to a line providing a fourth data clock signal DCK4. In synchronization with the edge of the fourth data clock signal DCK4, the fourth latch circuit 254 within the cache latch circuit 250 may output the fourth memory data signal MD4. The second selection circuit 412 may output the fourth memory data signal MD4 to the second converter 414, and the fourth selection circuit 423 may output the fourth data clock signal DCK4 to the second clock generator 424. The second converter 414 may generate a 2-bit internal command address signal ICA<0:1> based on the fourth memory data signal MD4 having 8 bits. The second converter 414 may generate four (4) 2-bit signals of the internal command address signal ICA<0:1> based on one 8-bit fourth memory data signal MD4. The second converter 414 may generate sixteen (16) 2-bit internal command address signals ICA<0:1> based on the four (4) 8-bit fourth memory data signals MD4. For example, the second converter 414 may convert the first provided fourth memory data signal (01100110) into the first to fourth internal command address signals (01, 10, 01, 10), may convert the second provided fourth memory data signal (01110111) into the fifth to eighth internal command address signals (01, 11, 01, 11), may convert the third provided fourth memory data signal (11101110) into the ninth to twelfth internal command address signals (11, 10, 11, 10), and may convert the fourth provided fourth memory data signal (00100011) into the thirteenth to sixteenth internal command address signals (00, 10, 00, 11). The second clock generator 424 may apply multiplication to the frequency of the fourth data clock signal DCK4 to generate the command clock signal CCK. When the second data mode signal CBDO is disabled, the second selection circuit 413 may connect the data bus 103 to the line providing the fourth memory data signal MD4, and the fourth selection circuit 423 may connect the data strobe bus 104 to the line providing the fourth data clock signal DCK4. The fourth latch circuit 254 may output the fourth memory data signal MD4 having 8 bits and the fourth data clock signal DCK4 having the same frequency as the data strobe signal DQS. The fourth memory data signal MD4 may be transmitted as the data signal DQ<0:7> through the data bus 103, and the fourth data clock signal DCK4 may be transmitted as the data strobe signal DQS through the data strobe bus 104.

[0048] Fig. 9 is a diagram showing a configuration of a memory controller 500 according to an embodiment. The memory controller 500 may be used as Figure 1 The memory controller 110 shown in FIG. 1 is applied. Figure 1 and Fig. 9 , the memory controller 500 may include a clock generation circuit 510, a command address generation circuit 520, a first data input / output (input and output) circuit 530, a path setting circuit 540, and a second data input / output (input and output) circuit 550. The clock generation circuit 510 may generate a command clock signal CCK and a data clock signal DCK. The clock generation circuit 510 equipped with a clock generator such as an oscillator, a phase-locked loop circuit, etc. may generate a command clock signal CCK and a data clock signal DCK. The clock generation circuit 510 may output the command clock signal CCK through the command clock bus 102. The clock generation circuit 510 may provide the command clock signal CCK to the command address generation circuit 520, and provide the data clock signal DCK to the first data input / output circuit 530.

[0049] The command address generation circuit 520 may receive a request REQ and may generate a command address signal CA<0:1> based on the request REQ. According to the request REQ, the command address generation circuit 520 may generate a command address signal CA<0:1> including a data input command signal, a data output command signal, a mode command signal, or a first and second mode command signal. The command address generation circuit 520 may receive a command clock signal CCK and may output the command address signal CA<0:1> in synchronization with the command clock signal CCK. The command address signal CA<0:1> may be output to the path setting circuit 540. After outputting the command address signal CA<0:1> including the mode command signal, the command address generation circuit 520 may generate a path setting signal CBDIO. After generating the command address signal CA<0:1> including the mode command signal and outputting the command address signal CA<0:1>, the command address generation circuit 520 may enable the path setting signal CBDIO. Based on the request REQ, the command address generation circuit 520 may further generate a chip enable signal CE#. The command address generation circuit 520 may transmit the chip enable signal CE# to the memory device 120 through the chip enable bus 105. The command address generation circuit 520 may generate the chip enable signal CE# having a pulse width greater than or equal to a predetermined pulse width based on the mode command signal to deactivate the activated data input / output mode.

[0050] The first data input / output circuit 530 may be coupled to the data bus 103 and the data strobe bus 104. During a data input operation, the first data input / output circuit 530 may provide the first parts CD1, CD2, and CD3 of the controller data CD1, CD2, CD3, and CD4 to the memory device 120 through the data bus 103 as the data signal DQ<0:7>. The first parts CD1, CD2, and CD3 of the controller data CD1, CD2, CD3, and CD4 may include the first controller data signal CD1, the second controller data signal CD2, and the third controller data signal CD3. The first data input / output circuit 530 may receive the data clock signal DCK, and may output the first parts CD1, CD2, and CD3 of the controller data CD1, CD2, CD3, and CD4 to the data bus 103 in synchronization with the data clock signal DCK. The first data input / output circuit 530 may generate a data strobe signal DQS based on the data clock signal DCK, and may transmit the data strobe signal DQS to the memory device 120 through the data strobe bus 104. During the data output operation, the first data input / output circuit 530 may receive the data signal DQ<0:7> transmitted from the memory device 120 through the data bus 103. The first data input / output circuit 530 may receive the data strobe signal DQS transmitted from the memory device 120 through the data strobe bus 104. The first data input / output circuit 530 may receive the data signal DQ<0:7> in synchronization with the data strobe signal DQS, and may generate first to third controller data signals CD1, CD2, and CD3 according to the data signal DQ<0:7>.

[0051] The path setting circuit 540 may be coupled between the command address generation circuit 520, the second data input / output circuit 550, and the command address bus 101. The path setting circuit 540 may receive a path setting signal CBDIO, and may couple one of the command address generation circuit 520 and the second data input / output circuit 550 to the command address bus 101 based on the path setting signal CBDIO. When the path setting signal CBDIO is disabled, the path setting circuit 540 may couple the command address generation circuit 520 to the command address bus 101. When the path setting signal CBDIO is enabled, the path setting circuit 540 may couple the second data input / output circuit 550 to the command address bus 101.

[0052] The second data input / output circuit 550 may be coupled to the data bus 103 and the path setting circuit 540. The second data input / output circuit 550 may receive a path setting signal CBDIO. The second data input / output circuit 550 may be coupled to the data bus 103 or the path setting circuit 540 according to the path setting signal CBDIO. When the path setting signal CBDIO is disabled, the second data input / output circuit 550 may be coupled to the data bus 103. During a data input operation, the second data input / output circuit 550 may provide a second portion CD4 of the controller data CD1, CD2, CD3, and CD4 to the memory device 120 through the data bus 103 as a data signal DQ<0:1>. The second portion CD4 of the controller data CD1, CD2, CD3, and CD4 may include a fourth controller data signal CD4. During a data output operation, the second data input / output circuit 550 may receive a data signal DQ<0:7> transmitted through the data bus 103, and may generate fourth controller data CD4. When the path setting signal CBDIO is enabled, the second data input / output circuit 550 may be coupled to the path setting circuit 540 and the command address bus 101. During a data input operation, the second data input / output circuit 550 may receive the fourth controller data CD4, may convert the fourth controller data CD4 into an output conversion data signal, and may output the output conversion data signal to the path setting circuit 540. During a data output operation, the second data input / output circuit 550 may receive a signal transmitted through the command address bus 101 through the path setting circuit 540, and may generate a fourth controller data signal CD4 based on the received signal.

[0053] Fig.10 It is shown Fig. 9 FIG. 5 is a diagram showing a configuration of the second data input / output circuit 550. Fig.10, the second data input / output circuit 550 may include a first path selection circuit 610, a data register 620, a first converter 630, and a second converter 640. The first path selection circuit 610 may receive a path setting signal CBDIO, and may be connected to the data bus 103, the data register 620, and a line providing a fourth controller data signal CD4. Based on the path setting signal CBDIO, the first path selection circuit 610 may selectively connect the data bus 103 or the data register 620 to the line providing the fourth controller data signal CD4. When the path setting signal CBDIO is disabled, the first path selection circuit 610 may connect the data bus 103 to the line providing the fourth controller data signal CD4. When the path setting signal CBDIO is enabled, the first path selection circuit 610 may connect the data register 620 to the line providing the fourth controller data signal CD4. The data register 620 may be connected to the fourth controller data signal CD4 through the first path selection circuit 610, and may be connected to the first converter 630 and the second converter 640. The data register 620 may receive the fourth controller data signal CD4 through the first path selection circuit 610 and may store the fourth controller data signal CD4. During a data input operation, the data register 620 may output the fourth controller data signal CD4 to the first converter 630. During a data output operation, the data register 620 may store a data signal output from the second converter 640. The data register 620 may output the stored data as the fourth controller data signal CD4 through the first path selection circuit 610.

[0054] The first converter 630 may receive the data signal stored in the data register 620, and may convert the received data signal into an output conversion data signal CDOUT<0:1>. The first converter 630 may convert the 8-bit data signal stored in the data register 620 into a 2-bit output conversion data signal CDOUT<0:1>. The first converter 630 may generate four (4) 2-bit output conversion data signals CDOUT<0:1> from a single data signal output from the data register 620. The first converter 630 may output the output conversion data signal CDOUT<0:1> to Fig. 9The path setting circuit 540 shown. The output conversion data signal CDOUT<0:1> output from the first converter 630 can be transmitted to the memory device 120 as a data signal through the command address bus 101. The first converter 630 may include an 8-bit to 2-bit converter. The second converter 640 may receive the signal transmitted through the command address bus 101 and the path selection circuit 540. The second converter 640 may convert the received signal into a storage conversion data signal CDS<0:7>. The second converter 640 may generate a storage conversion data signal CDS<0:7> based on the signal of four (4) 2-bit signals transmitted through the command address bus 101. The second converter 640 may provide the storage conversion data signal CDS<0:7> to the data register 620, and the data register 620 may store the storage conversion data signal CDS<0:7>. The second converter 640 may include a 2-bit to 8-bit converter.

[0055] The second data input / output circuit 550 may further include a second path selection circuit 650. The second path selection circuit 650 may receive a read enable signal REN. The read enable signal REN may be generated by the command address generation circuit 520. For example, the command address generation circuit 520 may generate the read enable signal REN after generating the data output command signal CMD2. When the read enable signal REN is disabled, the second path selection circuit 650 may couple the first converter 630 to the path setting circuit 540. Therefore, the output conversion data signal CDOUT<0:1> output from the first converter 630 may be transmitted as a data signal through the command address bus 101. When the read enable signal REN is enabled, the second path selection circuit 650 may couple the second converter 640 to the path setting circuit 540, and the signal transmitted through the command address bus 101 may be input to the second converter 640.

[0056] Although certain embodiments have been described above, it will be appreciated by those skilled in the art that the described embodiments are merely examples. Therefore, the memory system and the method for transmitting data via a command address bus should not be limited by the described embodiments. On the contrary, the memory system and the method for transmitting data via a command address bus described herein should only be limited to the claims understood in conjunction with the above description and the accompanying drawings.

Claims

1. A memory system, comprising: Memory controller; as well as A memory device coupled to the memory controller via a data bus and a command address bus, One of the memory controller and the memory device transmits data to the other of the memory controller and the memory device through the command address bus.

2. The memory system according to claim 1, wherein: The data transmitted by the memory controller to the memory device is data to be programmed into the memory device, and the data transmitted by the memory device to the memory controller is data to be read from the memory device.

3. The memory system according to claim 1, wherein: One of the memory controller and the memory device transmits a first portion of the data to the other of the memory controller and the memory device through the data bus, and transmits a second portion of the data to the other of the memory controller and the memory device through the command address bus.

4. The memory system according to claim 3, wherein: A first portion of the data transmitted through the data bus is synchronized with a data strobe signal, and a second portion of the data transmitted through the command address bus is synchronized with a command clock signal.

5. A method for operating a memory system, the memory system comprising a memory controller and a memory device, the method comprising: The memory controller transmits one of a data input command signal and a data output command signal to the memory device through a command address bus; One of the memory controller and the memory device transmits a first portion of data to the other of the memory controller and the memory device via a data bus, and the memory controller transmits a mode command signal to the memory device via the command address bus; as well as One of the memory controller and the memory device transmits a second portion of the data to the other of the memory controller and the memory device through the command address bus.

6. The operating method according to claim 5, wherein: Transmitting the first portion of the data includes one of the memory controller and the memory device transmitting a data strobe signal to the other of the memory controller and the memory device, the data strobe signal being synchronized with the first portion of the data.

7. The operating method according to claim 5, wherein: Transmitting the second portion of the data includes one of the memory controller and the memory device transmitting a command clock signal to the other of the memory controller and the memory device, the command clock signal being synchronized with the second portion of the data.

8. The operating method according to claim 5, further comprising: After transmitting the mode command signal, a data input and output mode, i.e., a data input / output mode, is activated, and Wherein, after the data input and output mode is activated, the second part of the data is transmitted.

9. The operating method according to claim 8, further comprising: After transmitting the second portion of the data, the memory controller transmits a chip enable signal to the memory device; as well as The data input and output modes are disabled according to the chip enable signal.

10. The operating method according to claim 9, wherein: Disabling the data input / output mode includes the memory device detecting a pulse width of the chip enable signal to disable the data input and output mode.

11. A memory system comprising: Memory controller; as well as A memory device coupled to the memory controller via a data bus and a command address bus, wherein the memory controller transmits data to be stored in the memory device to the memory device through the data bus and the command address bus during a data input operation, and During a data output operation, the memory device transmits data read from the memory device to the memory controller through the data bus and the command address bus.

12. The memory system according to claim 11, wherein: The memory device comprises: a command address buffer, generating an internal command address signal according to a signal transmitted through the command address bus, or outputting the internal command address signal through the command address bus; a command control circuit that generates a first data mode signal and a second data mode signal based on the internal command address signal; and The first data input and output circuit generates a first memory data signal according to the internal command address signal based on the first data pattern signal, and generates the internal command address signal according to the first memory data signal based on the second data pattern signal.

13. The memory system according to claim 12, wherein: The command address buffer: When the second data mode signal is disabled, buffering a signal transmitted through the command address bus to generate the internal command address signal, and When the second data mode signal is enabled, the internal command address signal is buffered to output the buffered internal command address signal through the command address bus.

14. The memory system according to claim 13, wherein: The command control circuit: When the internal command address signal including a data input command signal and a mode command signal is received, the first data mode signal is enabled, and When the internal command address signal including a data output command signal and the mode command signal is received, the second data mode signal is enabled.

15. The memory system according to claim 13, wherein: The mode command signal includes a first mode command signal and a second mode command signal, and The command control circuit: When an internal command address signal corresponding to the first mode command signal is received, the first data mode signal is enabled, and When an internal command address signal corresponding to the second mode command signal is received, the second data mode signal is enabled.

16. The memory system according to claim 12, wherein: The command control circuit comprises: a command decoding circuit that decodes the internal command address signal to enable the first data mode signal and the second data mode signal, and disables the first data mode signal and the second data mode signal according to a reset signal; and The reset circuit generates the reset signal according to the chip enable signal.

17. The memory system of claim 16, wherein: The reset circuit generates the reset signal by detecting a pulse width of the chip enable signal.

18. The memory system according to claim 12, wherein: The first data input and output circuit comprises: a first converter, generating a converted input data signal according to the internal command address signal; a first selection circuit, outputting one of the converted input data signal and the data signal transmitted through the data bus as the first memory data signal according to the first data mode signal; and a second selection circuit, outputting the first memory data signal to the data bus or to the second converter according to the second data mode signal, and The second converter generates the internal command address signal according to the first memory data signal.

19. The memory system of claim 18, wherein: The first data input and output circuit further comprises a path selection circuit, wherein: When the read enable signal is disabled, a line providing an output signal of the first selection circuit is coupled to a line providing the first memory data signal, and When the read enable signal is enabled, a line providing the first memory data signal is coupled to a line providing an input signal of the second selection circuit.

20. The memory system of claim 12, wherein: The first data input and output circuit comprises: a first clock generator, which divides the frequency of the command clock signal to generate a divided clock signal; a third selection circuit, outputting one of the divided clock signal and the data strobe signal as a data clock signal according to the first data mode signal; and a fourth selection circuit, outputting the data clock signal as one of the data selection signal and an input signal to be input to the second clock generator according to the second data mode signal, and The second clock generator applies multiplication to the frequency of the data clock signal to generate the command clock signal.

21. The memory system of claim 12, further comprising: A second data input and output circuit, wherein the second data input and output circuit: generating a second memory data signal according to a data signal transmitted through the data bus in synchronization with the data strobe signal, The second memory data signal is output through the data bus in synchronization with the data strobe signal.

22. The memory system of claim 12, wherein: The memory controller comprises: A command address generating circuit generates a command address signal; First data input and output circuit: When the path setting signal is disabled, connecting a line providing a first controller data signal to the first data bus, When the path setting signal is enabled, an output conversion data signal is generated according to the first controller data signal, and generating the first controller data signal according to a signal transmitted through the command address bus; and A path setting circuit connects the command address bus to one of the command address generation circuit and the first data input and output circuit according to the path setting signal.

23. The memory system of claim 22, wherein: The first data input and output circuit comprises: a first path selection circuit, connecting a line providing the first controller data signal to one of the data bus and the data register according to the path setting signal; a first converter, generating the output conversion data signal according to the data signal stored in the data register; a second converter, generating a storage conversion data signal according to a signal transmitted through the command address bus to provide the storage conversion data signal to the data register; and The second path selection circuit couples the path setting circuit to one of the first converter and the second converter according to a read enable signal.

24. The memory system of claim 22, wherein: The memory controller further includes a second data input and output circuit, wherein the second data input and output circuit: generating a second controller data signal according to a data signal transmitted through the data bus in synchronization with the data strobe signal, and The second controller data signal is output through the data bus in synchronization with the data strobe signal.

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