Reconfigurable systolic array method, device and equipment based on network-on-chip and medium

Abstract

The invention relates to a network-on-chip-based reconfigurable systolic array method, device and equipment and a medium, and the method comprises the steps: obtaining a relative position relation between input data and output data; if the relative position relationship is a parallel relationship, determining an input data row from the first to Nth row nodes, and determining a first output data row from the first to Nth row nodes, determining a destination node of each input data row node in the input data rows in the first output data row according to the row number of the first output data rows and the row number of each input data row, and performing multiplication and / or additive operation by using the reconfigurable systolic array circuit based on input data of each input data row node, and outputting the data at the destination node of the first output data row. Therefore, the problems of low energy efficiency and area efficiency of matrix operation are solved, and the method has relatively high energy efficiency and area efficiency.

Description

Technical Field

[0001] The present application relates to the technical field of on-chip networks, and in particular to a method, device, equipment and medium for a reconfigurable systolic array based on an on-chip network. Background Art

[0002] Artificial intelligence and other algorithms usually involve large-scale matrix multiplication operations, that is, each element of each row (or column) of a matrix is ​​multiplied and added with each element of each column (or row) of another matrix to obtain a new matrix. Matrix multiplication naturally has the characteristics of parallel computing, and all the multiplication operations it contains can be calculated simultaneously, and the addition operations can also be calculated simultaneously.

[0003] In the central processing unit (CPU) of a traditional computer, matrix multiplication is performed serially, that is, each multiplication and addition operation is performed in sequence, which is very inefficient. In contrast, in the graphics processing unit (GPU) used on a large scale for algorithms such as artificial intelligence, multiple computing cores calculate in parallel, greatly accelerating matrix multiplication. In addition, application-specific integrated circuits (ASICs) such as tensor processing units (TPUs) use large-scale pulsating arrays to accelerate matrix multiplication, which improves energy efficiency and area efficiency at the expense of a certain degree of versatility.

[0004] Related technologies usually perform matrix operations through the following means: (1) CPU is used to implement matrix multiplication operations, and multiplication and addition operations are performed serially, which is slow and inefficient; (2) GPU is used to implement matrix multiplication operations, and multiplication and addition operations are performed in parallel, but multiplication and addition operations are not performed synchronously and need to be controlled by instructions, which increases the area of ​​the control circuit, and the movement of data between computing units increases energy consumption; (3) TPU is used to implement matrix multiplication operations, and multiplication and addition operations are performed with a fixed systolic array and data stream, which is not suitable for on-chip network architecture. Summary of the invention

[0005] The present application provides a reconfigurable systolic array method, device, electronic device and storage medium based on an on-chip network to solve the problems of slow matrix operation speed, low efficiency, low energy efficiency and area efficiency, and low versatility. While retaining high energy efficiency and area efficiency, the versatility and flexibility of matrix multiplication operations are improved through a reconfigurable manner.

[0006] A first aspect of the present application provides a reconfigurable systolic array method based on an on-chip network. The method uses a reconfigurable systolic array circuit. The reconfigurable systolic array circuit includes first to Nth row nodes and first to Mth column nodes, where N and M are both integers. The method includes the following steps:

[0007] Obtain the relative position relationship between input data and output data;

[0008] If the relative position relationship is a parallel relationship, determining an input data row from the first to Nth rows of nodes, and determining a first output data row from the first to Nth rows of nodes;

[0009] The destination node of each input data row node in the input data row is determined according to the number of the first output data row and the number of each input data row, and based on the input data of each input data row node, the reconfigurable systolic array circuit is used to perform multiplication and / or addition operations to output data at the destination node of the first output data row.

[0010] Optionally, in some embodiments, determining the destination node of each input data row node in the input data row in the first output data row according to the number of rows of the first output data row and the number of rows of each input data row includes:

[0011] Determining a first dividing line according to the number of the input data row and the center line of the row above the input data row;

[0012] If the number of the first output data row is above the first dividing line, the column number corresponding to each input data row node at the destination node of the first output data row is equal to that of each input data row node;

[0013] And, if the number of rows of the first output data row is below the first dividing line, then the first sum of the row number and the column number corresponding to each input data row node is calculated, and the second sum of the total number of rows and the first preset value is calculated, and the second sum and the first sum corresponding to each input data row node are respectively calculated to obtain the destination node of each input data row node in the input data row in the first output data row.

[0014] Optionally, in some embodiments, determining the destination node of each input data row node in the input data row in the first output data row according to the number of rows of the first output data row and the number of rows of each input data row includes:

[0015] Determine a second dividing line according to the number of the input data row and the center line of the row below the input data row;

[0016] If the number of the first output data row is below the first dividing line, the column number corresponding to each input data row node at the destination node of the first output data row is equal to that of each input data row node;

[0017] And, if the number of rows of the first output data row is above the first dividing line, then the third sum of the row number and the column number corresponding to each input data row node is calculated, and the fourth sum of the total number of rows and the first preset value is calculated, and the fourth sum and the third sum corresponding to each input data row node are respectively calculated to obtain the destination node of each input data row node in the input data row in the first output data row.

[0018] Optionally, in some embodiments, after obtaining the relative position relationship between the input data and the output data, the method further includes:

[0019] If the relative position relationship is a vertical relationship, an input data column is determined from the first to M-th column nodes, and a second output data row is determined from the first to N-th row nodes;

[0020] The data transmission time of each input data column node in the input data column is determined, and the reconfigurable systolic array circuit is used to perform multiplication and / or addition operations according to the data transmission time to output data in the second output data row.

[0021] A second aspect of the present application provides a reconfigurable systolic array device based on an on-chip network, wherein the device adopts a reconfigurable systolic array circuit, wherein the reconfigurable systolic array circuit includes first to Nth row nodes and first to Mth column nodes, where N and M are both integers, and wherein the device includes:

[0022] An acquisition module is used to acquire the relative position relationship between input data and output data;

[0023] a determination module, configured to determine an input data row from the first to Nth row nodes, and determine a first output data row from the first to Nth row nodes, when the relative position relationship is a parallel relationship;

[0024] an output module, for determining the destination node of each input data row node in the input data row at the first output data row according to the number of rows of the first output data row and the number of rows of each input data row, and performing multiplication and / or addition operations using the reconfigurable systolic array circuit based on the input data of each input data row node, so as to output data at the destination node of the first output data row.

[0025] Optionally, in some embodiments, the output module includes:

[0026] A first determining unit, configured to determine a first dividing line according to the number of the input data lines and the center line of the line above the input data line;

[0027] A second determining unit, if the number of rows of the first output data row is above the first dividing line, then the column number corresponding to each input data row node at the destination node of the first output data row is equal to that of each input data row node;

[0028] A first calculation unit is used to calculate a first sum of the row number and the column number corresponding to each input data row node when the number of rows of the first output data row is below the first dividing line, and calculate a second sum of the total number of rows and a first preset value, and respectively calculate the second sum and the first sum corresponding to each input data row node to obtain a destination node of each input data row node in the input data row in the first output data row.

[0029] Optionally, in some embodiments, the output module includes:

[0030] A third determining unit, configured to determine a second dividing line according to the number of the input data line and the center line of the line below the input data line;

[0031] a fourth determining unit, if the number of rows of the first output data row is below the first dividing line, then the column number corresponding to each input data row node at the destination node of the first output data row is equal to that of each input data row node;

[0032] A second calculation unit is used to calculate the third sum of the row number and the column number corresponding to each input data row node when the number of rows of the first output data row is above the first dividing line, and calculate the fourth sum of the total number of rows and the first preset value, and respectively calculate the fourth sum and the third sum corresponding to each input data row node to obtain the destination node of each input data row node in the input data row in the first output data row.

[0033] Optionally, in some embodiments, after obtaining the relative position relationship between the input data and the output data, the obtaining module further includes:

[0034] a fifth determining unit, configured to determine an input data column from the first to M-th column nodes, and determine a second output data row from the first to N-th row nodes when the relative position relationship is a vertical relationship;

[0035] A sixth determining unit is used to determine the data transmission time of each input data column node in the input data column, and use the reconfigurable systolic array circuit to perform multiplication and / or addition operations according to the data transmission time to output data in the second output data row.

[0036] A third aspect of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement a reconfigurable systolic array method based on an on-chip network as described in the above embodiment.

[0037] A fourth aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, the program being executed by a processor to implement a reconfigurable systolic array method based on an on-chip network as described in the above embodiments.

[0038] Thus, by obtaining the relative position relationship between the input data and the output data, if the relative position relationship is a parallel relationship, the input data row is determined from the first to Nth row nodes, and the first output data row is determined from the first to Nth row nodes, and the destination node of each input data row node in the input data row is determined according to the number of rows of the first output data row and the number of rows of each input data row, and based on the input data of each input data row node, a reconfigurable systolic array circuit is used to perform multiplication and / or addition operations to output data at the destination node of the first output data row. Thus, the problems of slow matrix operation speed, low efficiency, low energy efficiency and area efficiency, and low versatility are solved, and while retaining high energy efficiency and area efficiency, the versatility and flexibility of matrix multiplication operations are improved through a reconfigurable manner.

[0039] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0041] Figure 1 A schematic diagram of a network on chip;

[0042] Figure 2 A flowchart of a reconfigurable systolic array method based on an on-chip network provided according to an embodiment of the present application;

[0043] Figure 3 A schematic diagram of the principle of a reconfigurable systolic array method for parallel input and output data and left-side startup longitudinal accumulation according to an embodiment of the present application;

[0044] Figure 4 A schematic diagram of the principle of a reconfigurable systolic array method for vertically starting longitudinal accumulation of input data and output data on the left side according to an embodiment of the present application;

[0045] Figure 5 A schematic diagram of a non-leftmost node of a reconfigurable systolic array circuit with parallel input data and output data and left-side startup longitudinal accumulation according to an embodiment of the present application;

[0046] Figure 6 A schematic diagram of the leftmost node of a reconfigurable systolic array circuit with parallel input data and output data and left-side startup of longitudinal accumulation according to one embodiment of the present application;

[0047] Figure 7 A schematic diagram of a non-leftmost node of a reconfigurable systolic array circuit for vertically starting longitudinal accumulation of input data and output data provided by one embodiment of the present application;

[0048] Figure 8 A schematic diagram of the leftmost node of a reconfigurable systolic array circuit for vertically starting longitudinal accumulation of input data and output data according to one embodiment of the present application;

[0049] Fig. 9 A block diagram of a reconfigurable systolic array device based on a network on chip provided according to an embodiment of the present application;

[0050] Fig.10 It is a schematic diagram of the structure of an electronic device provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0051] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0052] Before introducing the reconfigurable systolic array method based on on-chip network according to the embodiment of the present application, the on-chip network is first introduced.

[0053] On-chip network refers to a network architecture in which each functional node on a chip achieves interconnected communication in some way. For the sake of simplicity in design and feasibility of back-end layout and routing, each node is often aligned with each other in the horizontal and vertical directions, and is directly connected only to the four adjacent nodes above, below, left, and right of the node. When a node communicates with a node that is not adjacent to it, it needs to cross multiple intermediate nodes, that is, the communication data is first sent to the adjacent node. If the adjacent node is adjacent to the destination node, the communication data is sent directly to the destination node, otherwise the above steps are repeated until it is sent to the destination node.

[0054] like Figure 1 The figure shows a schematic diagram of an on-chip network, in which when node 1 sends data to node 2, the two nodes are adjacent and can be sent directly. When node 1 sends data to node 5, since the two nodes are not adjacent, node 1 sends the data to 5 through intermediate node 3 or 4.

[0055] In the on-chip network, since storage units such as static random access memory (SRAM) are scattered in various nodes, the input data and output data of matrix multiplication operations are also scattered in various nodes, making it impossible to use fixed systolic arrays and data streams to accelerate matrix multiplication operations like TPU.

[0056] In view of the problems of slow matrix operation speed, low efficiency, low energy efficiency and area efficiency, and weak versatility in the above-mentioned background technology, the present application provides a reconfigurable systolic array method based on an on-chip network. In the method, by obtaining the relative position relationship between input data and output data, if the relative position relationship is a parallel relationship, the input data row is determined from the first to Nth row nodes, and the first output data row is determined from the first to Nth row nodes, and the destination node of each input data row node in the input data row is determined according to the number of rows of the first output data row and the number of rows of each input data row, and based on the input data of each input data row node, a reconfigurable systolic array circuit is used to perform multiplication and / or addition operations to output data at the destination node of the first output data row. Thus, the problems of slow matrix operation speed and low efficiency are solved by parallel computing, the problems of low energy efficiency and area efficiency of matrix operation are solved by the advantages of high energy efficiency and high area efficiency of systolic array, and the problems of low versatility and flexibility of matrix operation are overcome by the characteristics of distributed and reconfigurable.

[0057] Specifically, Figure 1 A flowchart of a reconfigurable systolic array method based on an on-chip network provided in an embodiment of the present application.

[0058] The reconfigurable systolic array method based on an on-chip network in an embodiment of the present application adopts a reconfigurable systolic array circuit, and the reconfigurable systolic array circuit includes first to Nth row nodes and first to Mth column nodes, where N and M are both integers.

[0059] like Figure 1 As shown, the reconfigurable systolic array method based on on-chip network includes the following steps:

[0060] In step S101, the relative position relationship between input data and output data is obtained.

[0061] Among them, the relative position relationship can include a parallel relationship and a vertical relationship.

[0062] Specifically, when the input data is stored in any row and the output data is stored in any row, and the input data row is different from the output data row, the relative position relationship between the input data and the output data is a parallel relationship; when the input data is stored in any column and the output data is stored in any row, the relative position relationship between the input data and the output data is a vertical relationship.

[0063] In step S102, if the relative position relationship is a parallel relationship, an input data row is determined from the first to Nth row nodes, and a first output data row is determined from the first to Nth row nodes.

[0064] Specifically, input data can be stored in any row, and output data can also be stored in any row. It takes a fixed unit of time for data to move from any node to an adjacent node, such as Figure 3 As shown in the figure, a 4x4 on-chip network is illustrated, in which the input data is stored in the second row and the output data is stored in the third row.

[0065] In step S103, the destination node of each input data row node in the input data row is determined according to the number of rows of the first output data row and the number of rows of each input data row, and based on the input data of each input data row node, a multiplication operation and / or an addition operation is performed using a reconfigurable systolic array circuit to output data at the destination node of the first output data row.

[0066] Optionally, in some embodiments, the destination node of each input data row node in the input data row in the first output data row is determined according to the number of rows of the first output data row and the number of rows of each input data row, including: determining the first dividing line according to the number of rows of the input data row and the center line of the row above the input data row; if the number of rows of the first output data row is above the first dividing line, the destination node of each input data row node in the first output data row is equal to the column number corresponding to each input data row node; if the number of rows of the first output data row is below the first dividing line, calculating the first sum of the row number and the column number corresponding to each input data row node, and calculating the second sum of the total number of rows and the first preset value, and respectively calculating the second sum and the first sum corresponding to each input data row node to obtain the destination node of each input data row node in the input data row in the first output data row.

[0067] It can be understood that when the relative position relationship between the input data and the output data is parallel, each node in the row where the input data is located must send the input data to a destination node in the first column to start calculation, and different nodes in the row where the input data is located correspond to different destination nodes.

[0068] In the embodiment of the present application, there are two ways to determine the destination node of each node in the row where the input data is located. Here, the first way to determine the destination node of each node in the row where the input data is located is introduced.

[0069] The dividing line is the center line of the row where the input data is located and the row above it. The row number of the destination node above the dividing line is equal to the column number of the corresponding node where the input data is located, that is, the node where the input data corresponds to the destination node in the first row is located in the first column; the sum of the row number of the destination node below the dividing line and the column number of the corresponding node where the input data is located is equal to the number of rows (or columns) plus 2, that is, the node where the input data corresponds to the destination node in the second row is located in the fourth column, the node where the input data corresponds to the destination node in the third row is located in the third column, and the node where the input data corresponds to the destination node in the fourth row is located in the second column.

[0070] Optionally, in some embodiments, the destination node of each input data row node in the input data row in the first output data row is determined according to the number of rows of the first output data row and the number of rows of each input data row, including: determining the second dividing line according to the number of rows of the input data row and the center line of the row below the input data row; if the number of rows of the first output data row is below the first dividing line, the destination node of each input data row node in the first output data row is equal to the column number corresponding to each input data row node; if the number of rows of the first output data row is above the first dividing line, calculating the third sum of the row number and the column number corresponding to each input data row node, and calculating the fourth sum of the total number of rows and the first preset value, and respectively calculating the fourth sum and the third sum corresponding to each input data row node to obtain the destination node of each input data row node in the input data row in the first output data row.

[0071] Here we introduce the second method of determining the destination node of each node in the row where the input data is located.

[0072] Specifically, in the second method, the center line of the row where the input data is located and the row below it is used as the dividing line, and the row number of the destination node above the dividing line is equal to the column number of the corresponding node where the input data is located, that is, the node where the input data corresponding to the destination node in the first row is located in the first column, and the node where the input data corresponding to the destination node in the second row is located in the second column; the sum of the row number of the destination node below the dividing line and the column number of the corresponding node where the input data is located is equal to the number of rows (or columns) plus 2, that is, the node where the input data corresponding to the destination node in the third row is located in the third column, and the node where the input data corresponding to the destination node in the fourth row is located in the second column.

[0073] In the actual implementation process, Figure 3 As shown, Figure 3 A schematic diagram of a reconfigurable systolic array method with parallel input and output data and left-side startup and longitudinal accumulation is provided, in which the number of rows and columns of the on-chip network is equal.

[0074] During the movement process, the input data must follow the order of moving vertically to the row where the destination node is located first, and then moving horizontally to the destination node. After the calculation is started, each input data needs to be moved from the leftmost node to the rightmost node. When it reaches the rightmost node, the life cycle of the input data will also end. In the process of moving from left to right, the input data needs to be calculated at each node (including the leftmost node and the rightmost node) passed through to obtain the cumulative sum, and the cumulative sum is sent vertically to the corresponding node in the row where the output data is located. In the process of vertical movement of the cumulative sum, the nodes passed through must also participate in the process of calculating the new cumulative sum at the node. After obtaining the cumulative sum, the node in the row where the output data is located does not need to be transmitted vertically, and the cumulative sum is directly stored in the current node as output data. It takes a fixed unit of time for each node to calculate the cumulative sum.

[0075] The node where the input data is located stores multiple input data, and sends out one data per unit time until all the input data are sent. The number of input data stored in each node where the input data is located is equal. The time when each node where the input data is located starts to send input data is not exactly the same. It is necessary to ensure that the cumulative sum generated by the input data at the same position in each node arrives at the corresponding output data node at the same time point. For example, the cumulative sum corresponding to the first data in each node must arrive at the corresponding output data node at the same time point. In this example, the node in the first column of the second row and the third column of the second row needs to start sending input data first. The time point at this time is 0, then the node in the second column of the second row and the fourth column of the second row needs to start sending input data at time point 1, so that the cumulative sum corresponding to the first input data of the four input data nodes can be generated at the node where the output data is located in the first column of the third row at time point 4, and generated at the nodes where the output data is located in the second column of the third row, the third column of the third row, and the fourth column of the third row at time point 5, time point 6, and time point 7, respectively. Figure 2 The numbers in the second row indicate the time when the input data starts to be sent, and the numbers in the third row indicate the time when the output data is generated.

[0076] According to the principle of symmetry, Figure 3 The method shown is also applicable to a reconfigurable systolic array method in which the right side starts longitudinal accumulation, the upper side starts lateral accumulation, and the lower side starts lateral accumulation.

[0077] Optionally, in some embodiments, after obtaining the relative position relationship between the input data and the output data, it also includes: if the relative position relationship is a vertical relationship, determining the input data column from the first to Mth column nodes, and determining the second output data row from the first to Nth row nodes; determining the data sending time of each input data column node in the input data column, and using a reconfigurable systolic array circuit to perform multiplication and / or addition operations according to the data sending time to output data in the second output data row.

[0078] Specifically, Figure 4 As shown, Figure 4 An example diagram of a reconfigurable systolic array method for vertically accumulating input data and output data and starting longitudinally from the left is provided. In this method, the number of rows and columns of a row of an on-chip network is not necessarily equal. Input data can be stored in any column, and output data can also be stored in any row. It takes a fixed unit of time for data to move from any node to an adjacent node. The figure illustrates a 3x4 on-chip network, in which input data is stored in the second column and output data is stored in the second row.

[0079] In this example, each node in the column where the input data is located must send the input data to the destination node in the first column of the same row to start the calculation. After the calculation is started, each input data needs to move from the leftmost node to the rightmost node. When it reaches the rightmost node, the life cycle of the input data will also end. In the process of the input data moving from left to right, it is necessary to calculate the cumulative sum at each node passed through (including the leftmost node and the rightmost node), and send the cumulative sum vertically to the corresponding node in the row where the output data is located. In the process of the cumulative sum moving vertically, the nodes passed through must also participate in the process of calculating the new cumulative sum at the node. After obtaining the cumulative sum, the node in the row where the output data is located does not need to transmit it vertically, and directly stores the cumulative sum as output data in the current node. It takes a fixed unit of time for each node to calculate the cumulative sum.

[0080] Multiple input data are stored in each node where the input data is located, and a data is sent out every time a unit of time passes until all the input data are sent. The number of input data stored in each node where the input data is located is equal. The time when each node in the column where the input data is located starts to send input data is not exactly the same. It is necessary to ensure that the cumulative sum corresponding to the input data at the same position in each node arrives at the corresponding output data node at the same time point, such as the cumulative sum generated by the first data in each node to arrive at the corresponding output data node at the same time point. In an embodiment of the present application, the nodes in the second column of the first row and the second column of the third row need to start sending input data first, and the time point at this time is recorded as 0, then the nodes in the second row and the second column need to start sending input data at time point 1, so that the cumulative sum corresponding to the first input data of the nodes where the three input data are located can be generated at the node where the output data of the first column of the second row is located at time point 3 at the same time, and generated at the nodes where the output data of the second row and the second column, the second row and the third column, and the second row and the fourth column are located at time points 4, 5, and 6, respectively. Figure 3 The numbers in the second column indicate the time when input data starts to be sent, the numbers in the second row indicate the time when output data starts to be generated, the numbers on the left side of the second column and second row indicate the time when input data starts to be sent, and the numbers on the right side of the second column and second row indicate the time when output data starts to be generated.

[0081] According to the principle of symmetry, Figure 4 The method shown is also applicable to a reconfigurable systolic array method in which the right side starts longitudinal accumulation, the upper side starts lateral accumulation, and the lower side starts lateral accumulation.

[0082] In order to enable relevant technical personnel in the art to further understand the reconfigurable systolic array method based on on-chip network according to the embodiment of the present application, it is described in detail below in conjunction with specific embodiments.

[0083] like Figure 5 As shown, Figure 5 Provided is a schematic diagram of a reconfigurable systolic array circuit node (except the leftmost node) with parallel input and output data and left-side startup of longitudinal accumulation. Figure 5 It contains the entire structure of a node, the partial structures of the nodes around it, and the interconnection relationship between the nodes. Each node consists of an upward register, a downward register, a left register, a right register, a three-way selector, a multiplier register, a multiplication and addition unit, an accumulation and sum register, an input data memory, and an output data memory. For the topmost, rightmost, and bottommost nodes, if there is no adjacent node in a certain direction, there is no data input and output arrow in that direction. Figure 6 This is a schematic diagram of the leftmost node. Compared with the non-leftmost nodes, the leftmost node does not have a three-way selector and a right row register.

[0084] According to the on-chip network-based reconfigurable systolic array method provided in an embodiment of the present application, the input data memory sends the input data together with the start computing node address and the row number of the output data to the upstream register, the downstream register or the left row register according to the relationship between the node where the input data is located and its corresponding start computing node.

[0085] The three-way gate decides which register's data to send to the left-row register of the left node according to the start computation node addresses in the upper register, lower register, and left-row register. For example, the three-way gate in the third-row node will send the data of the start computation node in the third row and the first column to the left-row register of the left node. If there is no qualified data in the three registers, the three-way gate sends invalid data to the left node. If the data in more than one register meets the conditions, the three-way gate selects any one data and sends it to the left node.

[0086] Except for the leftmost node, the up register will automatically send data to the three-way gate of the current node and the up register of the node above, the down register will automatically send data to the three-way gate of the current node and the down register of the node below, the left register will automatically send data to the three-way gate of the current node, and the right register will automatically send data to the multiplication and addition unit of the current node and the right register of the node to the right. For the leftmost node, the up register will automatically send data to the up register of the node above, the down register will automatically send data to the down register of the node below, and the left register will automatically send data to the multiplication and addition unit of the current node and the right register of the node to the right.

[0087] The multiplier register stores the multiplier for multiplication operation in advance. The input data from the right row register of the non-leftmost node or the left row register of the leftmost node will first be multiplied with the multiplier in the multiplier register in the multiplication-addition unit, and the obtained product will be determined whether to be added to the data in the cumulative sum register of the upper node and the cumulative sum register of the lower node according to the row number of the output data brought by the input data. If the row where the output data is located is the row where the current node is located, the obtained product is added to the data in the cumulative sum register of the upper node and the cumulative sum register of the lower node at the same time; if the row where the output data is located is above the row where the current node is located, the obtained product is only added to the data in the cumulative sum register of the lower node; if the row where the output data is located is below the row where the current node is located, the obtained product is only added to the data in the cumulative sum register of the upper node. The sum obtained by addition is written to the cumulative sum register of the current node. If the row where the output data is located is the row where the current node is located, the cumulative sum register will write the data to the output data memory, otherwise it will not be written to the output data memory.

[0088] According to the principle of symmetry, Figure 5 , Figure 6The circuit shown is also applicable to a reconfigurable systolic array circuit in which the right side starts the longitudinal accumulation, the upper side starts the lateral accumulation, and the lower side starts the lateral accumulation.

[0089] In another embodiment of the present application, Figure 7 As shown, Figure 7 Provided is a schematic diagram of a reconfigurable systolic array circuit node (except the leftmost node) with vertical input and output data and vertical accumulation started on the left. Figure 7 It contains the entire structure of a node, the partial structures of the nodes around it, and the interconnection relationship between nodes. Each node consists of a left row register, a right row register, a multiplier register, a multiplication and addition unit, an accumulation and sum register, an input data memory, and an output data memory. For the topmost, rightmost, and bottommost nodes, if there is no adjacent node in a certain direction, there is no data input and output arrow in that direction. Figure 8 The diagram shows a schematic diagram of the leftmost node. Compared with non-leftmost nodes, the leftmost node does not have a right row register inside.

[0090] According to the reconfigurable systolic array method based on on-chip network provided by the embodiment of the present application, the input data memory sends the input data together with the row number of the output data to the left row register. Except for the leftmost node, the left row register automatically sends the data to the left row register of the left node, and the right row register automatically sends the data to the multiplication and addition unit of the current node and the right row register of the right node. For the leftmost node, the left row register automatically sends the data to the multiplication and addition unit of the current node and the right row register of the right node.

[0091] The multiplier register stores the multiplier for multiplication operation in advance. The input data from the right row register of the non-leftmost node or the left row register of the leftmost node will first be multiplied with the multiplier in the multiplier register in the multiplication-addition unit, and the obtained product will be determined whether to be added to the data in the cumulative sum register of the upper node and the cumulative sum register of the lower node according to the row number of the output data brought by the input data. If the row where the output data is located is the row where the current node is located, the obtained product is added to the data in the cumulative sum register of the upper node and the cumulative sum register of the lower node at the same time; if the row where the output data is located is above the row where the current node is located, the obtained product is only added to the data in the cumulative sum register of the lower node; if the row where the output data is located is below the row where the current node is located, the obtained product is only added to the data in the cumulative sum register of the upper node. The sum obtained by addition is written to the cumulative sum register of the current node. If the row where the output data is located is the row where the current node is located, the cumulative sum register will write the data to the output data memory, otherwise it will not be written to the output data memory.

[0092] According to the principle of symmetry, Figure 7 , Figure 8The circuit shown is also applicable to a reconfigurable systolic array circuit in which the right side starts the longitudinal accumulation, the upper side starts the lateral accumulation, and the lower side starts the lateral accumulation.

[0093] According to the reconfigurable systolic array method based on the on-chip network proposed in the embodiment of the present application, the relative position relationship between the input data and the output data is obtained. If the relative position relationship is a parallel relationship, the input data row is determined from the first to Nth row nodes, and the first output data row is determined from the first to Nth row nodes. The destination node of each input data row node in the input data row is determined according to the number of rows of the first output data row and the number of rows of each input data row, and based on the input data of each input data row node, a reconfigurable systolic array circuit is used to perform multiplication and / or addition operations to output data at the destination node of the first output data row. Thus, the problem of slow matrix operation speed and low efficiency is solved through parallel computing, the problem of low energy efficiency and area efficiency of matrix operation is solved through the advantages of high energy efficiency and high area efficiency of the systolic array, and the problem of low versatility and flexibility of matrix operation is overcome through the characteristics of distributed and reconfigurable.

[0094] Next, a reconfigurable systolic array device based on a network on a chip proposed in accordance with an embodiment of the present application will be described with reference to the accompanying drawings.

[0095] Fig. 9 It is a block diagram of a reconfigurable systolic array device based on an on-chip network according to an embodiment of the present application.

[0096] The reconfigurable systolic array device based on an on-chip network in the embodiment of the present application adopts a reconfigurable systolic array circuit, and the reconfigurable systolic array circuit includes first to Nth row nodes and first to Mth column nodes, where N and M are both integers.

[0097] like Fig. 9 As shown, the reconfigurable systolic array device 10 based on the network on chip includes: an acquisition module 100 , a determination module 200 and an output module 300 .

[0098] The acquisition module 100 is used to acquire the relative position relationship between the input data and the output data.

[0099] The determination module 200 is used to determine the input data row from the first to Nth row nodes and determine the first output data row from the first to Nth row nodes when the relative position relationship is a parallel relationship.

[0100] The output module 300 is used to determine the destination node of each input data row node in the input data row at the first output data row according to the number of rows of the first output data row and the number of rows of each input data row, and to perform multiplication and / or addition operations based on the input data of each input data row node using a reconfigurable systolic array circuit to output data at the destination node of the first output data row.

[0101] Optionally, in some embodiments, the output module 300 includes: a first determination unit, a second determination unit and a first calculation unit.

[0102] The first determining unit is used to determine the first dividing line according to the number of the input data lines and the center line of the line above the input data line.

[0103] The second determining unit is configured such that, if the number of rows of the first output data row is above the first dividing line, the column number corresponding to each input data row node at the destination node of the first output data row is equal to that of each input data row node.

[0104] The first calculation unit is used to calculate the first sum of the row number and the column number corresponding to each input data row node when the number of rows of the first output data row is below the first dividing line, and calculate the second sum of the total number of rows and the first preset value, and respectively calculate the second sum and the first sum corresponding to each input data row node to obtain the destination node of each input data row node in the input data row in the first output data row.

[0105] Optionally, in some embodiments, the output module 300 includes: a third determination unit, a fourth determination unit and a second calculation unit.

[0106] The third determining unit is used to determine the second dividing line according to the number of the input data rows and the center line of the row below the input data row.

[0107] The fourth determining unit is configured to, if the number of rows of the first output data row is below the first dividing line, have the column numbers corresponding to the destination node of each input data row node and each input data row node be equal.

[0108] The second calculation unit is used to calculate the third sum of the row number and the column number corresponding to each input data row node when the row number of the first output data row is above the first dividing line, and calculate the fourth sum of the total number of rows and the first preset value, and respectively calculate the fourth sum and the third sum corresponding to each input data row node to obtain the destination node of each input data row node in the input data row in the first output data row.

[0109] Optionally, in some embodiments, after obtaining the relative position relationship between the input data and the output data, the obtaining module 100 further includes: a fifth determining unit and a sixth determining unit.

[0110] The fifth determining unit is used to determine the input data column from the first to the Mth column nodes and determine the second output data row from the first to the Nth row nodes when the relative position relationship is a vertical relationship;

[0111] The sixth determining unit is used to determine the data transmission time of each input data column node in the input data column, and use the reconfigurable systolic array circuit to perform multiplication and / or addition operations according to the data transmission time to output data in the second output data row.

[0112] It should be noted that the above explanation of the embodiment of the method for a reconfigurable systolic array based on a network on chip is also applicable to the reconfigurable systolic array device based on a network on chip of this embodiment, and will not be repeated here.

[0113] According to the reconfigurable systolic array device based on the on-chip network proposed in the embodiment of the present application, the relative position relationship between the input data and the output data is obtained. If the relative position relationship is a parallel relationship, the input data row is determined from the first to Nth row nodes, and the first output data row is determined from the first to Nth row nodes. The destination node of each input data row node in the input data row is determined according to the number of rows of the first output data row and the number of rows of each input data row, and based on the input data of each input data row node, a multiplication operation and / or addition operation is performed using a reconfigurable systolic array circuit to output data at the destination node of the first output data row. Thus, the problem of slow matrix operation speed and low efficiency is solved through parallel computing, the problem of low energy efficiency and area efficiency of matrix operation is solved through the advantages of high energy efficiency and high area efficiency of the systolic array, and the problem of low versatility and flexibility of matrix operation is overcome through the characteristics of distributed and reconfigurable.

[0114] Fig.10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device may include:

[0115] A memory 1001 , a processor 1002 , and a computer program stored in the memory 1001 and executable on the processor 1002 .

[0116] When the processor 1002 executes the program, the reconfigurable systolic array method based on on-chip network provided in the above embodiment is implemented.

[0117] Furthermore, the electronic device further comprises:

[0118] The communication interface 1003 is used for communication between the memory 1001 and the processor 1002 .

[0119] The memory 1001 is used to store computer programs that can be executed on the processor 1002 .

[0120] The memory 1001 may include a high-speed RAM (Random Access Memory) memory, and may also include a non-volatile memory, such as at least one disk memory.

[0121] If the memory 1001, the processor 1002 and the communication interface 1003 are implemented independently, the communication interface 1003, the memory 1001 and the processor 1002 can be connected to each other through a bus and communicate with each other. The bus can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.10 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0122] Optionally, in a specific implementation, if the memory 1001, the processor 1002 and the communication interface 1003 are integrated on a chip, the memory 1001, the processor 1002 and the communication interface 1003 can communicate with each other through an internal interface.

[0123] The processor 1002 may be a CPU (Central Processing Unit), or an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present application.

[0124] An embodiment of the present application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-mentioned reconfigurable systolic array method based on an on-chip network.

[0125] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0126] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0127] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0128] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiment, the N steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array, a field programmable gate array, etc.

[0129] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0130] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A reconfigurable systolic array method based on a network on chip, characterized in that: The method adopts a reconfigurable systolic array circuit, the reconfigurable systolic array circuit includes first to Nth row nodes and first to Mth column nodes, N and M are both integers, wherein the method includes the following steps: Obtain the relative position relationship between input data and output data; If the relative position relationship is a parallel relationship, determining an input data row from the first to Nth rows of nodes, and determining a first output data row from the first to Nth rows of nodes; The destination node of each input data row node in the input data row is determined according to the number of the first output data row and the number of each input data row, and based on the input data of each input data row node, the reconfigurable systolic array circuit is used to perform multiplication and / or addition operations to output data at the destination node of the first output data row.

2. The method according to claim 1, characterized in that The determining, according to the number of the first output data rows and the number of each input data row, the destination node of each input data row in the input data row in the first output data row comprises: Determining a first dividing line according to the number of the input data row and the center line of the row above the input data row; If the number of the first output data row is above the first dividing line, the column number corresponding to each input data row node at the destination node of the first output data row is equal to that of each input data row node; And, if the number of rows of the first output data row is below the first dividing line, then the first sum of the row number and the column number corresponding to each input data row node is calculated, and the second sum of the total number of rows and the first preset value is calculated, and the second sum and the first sum corresponding to each input data row node are respectively calculated to obtain the destination node of each input data row node in the input data row in the first output data row.

3. The method according to claim 1, characterized in that The determining, according to the number of the first output data rows and the number of each input data row, the destination node of each input data row in the input data row in the first output data row comprises: Determine a second dividing line according to the number of the input data row and the center line of the row below the input data row; If the number of the first output data row is below the second dividing line, the column number corresponding to each input data row node at the destination node of the first output data row is equal to that of each input data row node; And, if the number of rows of the first output data row is above the second dividing line, then the third sum of the row number and the column number corresponding to each input data row node is calculated, and the fourth sum of the total number of rows and the first preset value is calculated, and the fourth sum and the third sum corresponding to each input data row node are respectively calculated to obtain the destination node of each input data row node in the input data row in the first output data row.

4. The method according to claim 1, characterized in that: After obtaining the relative position relationship between the input data and the output data, it also includes: If the relative position relationship is a vertical relationship, an input data column is determined from the first to M-th column nodes, and a second output data row is determined from the first to N-th row nodes; The data transmission time of each input data column node in the input data column is determined, and the reconfigurable systolic array circuit is used to perform multiplication and / or addition operations according to the data transmission time to output data in the second output data row.

5. A reconfigurable systolic array device based on a network on chip, characterized in that: The device adopts a reconfigurable systolic array circuit, the reconfigurable systolic array circuit includes first to Nth row nodes and first to Mth column nodes, N and M are both integers, wherein the device includes: An acquisition module is used to acquire the relative position relationship between input data and output data; a determination module, configured to determine an input data row from the first to Nth row nodes, and determine a first output data row from the first to Nth row nodes, when the relative position relationship is a parallel relationship; an output module, for determining the destination node of each input data row node in the input data row at the first output data row according to the number of rows of the first output data row and the number of rows of each input data row, and performing multiplication and / or addition operations using the reconfigurable systolic array circuit based on the input data of each input data row node, so as to output data at the destination node of the first output data row.

6. The device according to claim 5, characterized in that The output module comprises: A first determining unit, configured to determine a first dividing line according to the number of the input data lines and the center line of the line above the input data line; A second determining unit, if the number of rows of the first output data row is above the first dividing line, then the column number corresponding to each input data row node at the destination node of the first output data row is equal to that of each input data row node; A first calculation unit is used to calculate a first sum of the row number and the column number corresponding to each input data row node when the number of rows of the first output data row is below the first dividing line, and calculate a second sum of the total number of rows and a first preset value, and respectively calculate the second sum and the first sum corresponding to each input data row node to obtain a destination node of each input data row node in the input data row in the first output data row.

7. The device according to claim 5, characterized in that The output module comprises: A third determining unit, configured to determine a second dividing line according to the number of the input data line and the center line of the line below the input data line; a fourth determining unit, if the number of rows of the first output data row is below the second dividing line, then the column number corresponding to each input data row node at the destination node of the first output data row is equal to that of each input data row node; A second calculation unit is used to calculate the third sum of the row number and the column number corresponding to each input data row node when the number of rows of the first output data row is above the second dividing line, and calculate the fourth sum of the total number of rows and the first preset value, and respectively calculate the fourth sum and the third sum corresponding to each input data row node to obtain the destination node of each input data row node in the input data row in the first output data row.

8. The device according to claim 5, characterized in that After obtaining the relative position relationship between the input data and the output data, the obtaining module further includes: a fifth determining unit, configured to determine an input data column from the first to M-th column nodes, and determine a second output data row from the first to N-th row nodes when the relative position relationship is a vertical relationship; A sixth determining unit is used to determine the data transmission time of each input data column node in the input data column, and use the reconfigurable systolic array circuit to perform multiplication and / or addition operations according to the data transmission time to output data in the second output data row.

9. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the on-chip network-based reconfigurable systolic array method according to any one of claims 1 to 4.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement the on-chip network-based reconfigurable systolic array method as described in any one of claims 1 to 4.

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