Chip pin processing method and device, storage medium and electronic equipment

Abstract

The embodiment of the invention provides a chip pin processing method and device, a storage medium and electronic equipment, and relates to the field of computers.The chip pin processing method comprises the steps that a first array composed of attribute information of all pins in a first set of pins of a target chip is obtained, and a set of signal lines which are not connected with wires exist around the target chip; based on the first array and a second array formed by signal attributes of all signal lines in the group of signal lines, determining a second group of pins of which the network names are to be replaced from the first group of pins; according to a region division rule, attribute information of each pin in the second group of pins is stored in a target array corresponding to a target region, and the target region is obtained by dividing a region occupied by the target chip; and on the basis of the first position information of the signal line of the target pin in the target array, replacing the network name of the predetermined candidate pin with the target network name of the target pin.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computers, and more specifically, to a chip pin processing method and device, a storage medium, and an electronic device. Background Art

[0002] With the development of cloud computing applications, people's work and life have put forward higher requirements on the computing speed, storage capacity and management efficiency of servers. In order to meet these requirements, the number of pins of chips in servers has increased, making the PCB (Printed Circuit Board) board design increasingly complex.

[0003] During the PCB board design process, considering the signal routing length, the layer number limit of the PCB board, etc., it is usually necessary to change the pin signal name of the chip. In the related technology, Allegro software is usually used to realize the replacement of the pin network name. For example, first find an empty pin on the chip, and then click the corresponding replacement command to replace the network name of the current pin to the empty pin, and then repeat the replacement command to replace other network names to the current pin.

[0004] However, as the scale of chips becomes larger and the number of pins increases, this method of relying on manual replacement of network names is prone to duplication or omission of network names, resulting in low accuracy in the process of replacing the network names of chip pins.

[0005] In the related art, there is a problem of low accuracy in the process of changing the network name of the chip pin, and no effective solution has been proposed yet. Summary of the invention

[0006] The embodiments of the present application provide a chip pin processing method and device, a storage medium and an electronic device to at least solve the problem of low accuracy in the process of changing the network name of the chip pin.

[0007] According to an embodiment of the present application, a chip pin processing method is provided, comprising: obtaining a first array consisting of attribute information of each pin in a first group of pins of a target chip, wherein there is a group of signal lines with unconnected routing around the target chip, and the first array includes description information of each pin on multiple attributes; based on the first array and a second array consisting of signal attributes of each signal line in a group of signal lines, determining a second group of pins whose network names are to be replaced from the first group of pins; according to an area division rule, saving the attribute information of each pin in the second group of pins to a target array corresponding to a target area, wherein the target area is obtained by dividing the area occupied by the target chip; based on the first position information of the signal line of the target pin in the target array, replacing the network name of the predetermined candidate pin with the target network name of the target pin.

[0008] In an exemplary embodiment, the above-mentioned method of determining a second group of pins whose network names are to be replaced from the first group of pins based on the first array and the second array composed of signal attributes of each signal line in a group of signal lines includes: filtering out attribute information of power pins from the first array based on the pin type of each pin; constructing a third array based on the remaining attribute information in the first array except the attribute information of the power pin; determining at least some signal lines whose network names are the same as the network names of at least some pins in the third array from each signal line by traversing the second array; constructing a fourth array based on the signal attributes of at least some signal lines and the attribute information of at least some pins, wherein the fourth array includes description information of multiple element attribute lines, one of the multiple element attribute lines is a virtual connection line between a breakpoint of one of the at least some signal lines and one of the at least some pins, and a signal line has the same network name as a pin; and obtaining the second group of pins whose network names are to be replaced by traversing the fourth array.

[0009] In an exemplary embodiment, the above-mentioned obtaining a second group of pins of the network name to be replaced by traversing the fourth array includes: obtaining the chip area occupied by each pin in the target chip; dividing the chip area into a preset number of sub-areas by a first dividing line and a second dividing line, wherein the preset number of sub-areas include the target area; obtaining the second group of pins of the network name to be replaced by traversing the description information of multiple element attribute lines in the fourth array.

[0010] In an exemplary embodiment, the second group of pins of the network name to be replaced is obtained by traversing the description information of multiple element attribute lines in the fourth array, including: obtaining the description information of each element attribute line in turn from the description information of multiple element attribute lines as the description information of a current element attribute line; when the current element attribute line intersects with at least one of the first dividing line and the second dividing line, determining a current pin on the current element attribute line as a pin in the second group of pins.

[0011] In an exemplary embodiment, the above-mentioned area division rule is followed to save the attribute information of each pin in the second group of pins into a target array corresponding to the target area, including: dividing the chip area into a preset number of sub-areas by a first dividing line and a second dividing line, wherein the first dividing line and the second dividing line are two diagonal lines on the closed area formed by the chip area; obtaining each pin from the second group of pins in turn as a current pin; when the signal attribute line of a current signal on the current pin first passes through a current sub-area of ​​a preset number of sub-areas, saving the current attribute information of the current pin into a current array corresponding to the current sub-area, wherein the current array is the target array.

[0012] In an exemplary embodiment, the above-mentioned method of replacing the network name of a predetermined candidate pin with the target network name of the target pin based on the first position information of the signal line of the target pin in the target array includes: when the first position information of the signal line of the target pin indicates that the target pin is located on the surface layer of the target chip, determining the candidate pin from the pin set outside the target chip; replacing the network name of the candidate pin with the target network name; or when the first position information of the signal line of the target pin indicates that the layer where the target pin is located is inconsistent with the surface layer of the target chip, determining the candidate pin from the pin set outside the target chip; obtaining the position of the target signal line connecting the target pin and the target via that the candidate pin needs to pass through; connecting the signal line of the target pin to the candidate pin through the target via.

[0013] In an exemplary embodiment, after replacing the network name of the predetermined candidate pin with the target network name of the target pin based on the first position information of the signal line of the target pin in the target array, the above method also includes: in the case where the chip area is divided into multiple sub-areas, sequentially obtaining each sub-area from the multiple sub-areas as a current sub-area; backing up the element information of the current group of pins in the current sub-area to the current backup array; based on the network name, comparing the target array after the network name is updated with the current backup array to obtain a first comparison result; when the first comparison result indicates that the target array after the network name is updated is consistent with the network name in the current backup array, determining that the target network name of the target pin has been accurately replaced ; or in the case where the chip area is divided into multiple sub-areas, updated element information of multiple groups of pins is obtained, wherein the updated element information of the multiple groups of pins represents the element information of each pin in the multiple sub-areas after the network name is changed, and the multiple sub-areas have a corresponding relationship with the multiple groups of pins; based on the updated element information of the multiple groups of pins, the target array is updated to obtain an updated target array; the network name in the updated target array is compared with the network name of each pin in the second group of pins to obtain a second comparison result, wherein the second group of pins is a plurality of groups of pins in the plurality of sub-areas; when the second comparison result indicates that the network name in the updated target array is consistent with the network name of each pin in the second group of pins, it is determined that the target network name of the target pin has been accurately replaced.

[0014] According to another embodiment of the embodiment of the present application, a chip pin processing device is also provided, including: a first acquisition unit, used to acquire a first array composed of attribute information of each pin in a first group of pins of a target chip, wherein there is a group of signal lines with unconnected routing around the target chip, and the first array includes description information of each pin on multiple attributes; a first processing unit, used to determine a second group of pins whose network names are to be replaced from the first group of pins based on the first array and a second array composed of signal attributes of each signal line in a group of signal lines; a second processing unit, used to save the attribute information of each pin in the second group of pins to a target array corresponding to the target area according to the area division rule, wherein the target area is obtained by dividing the area occupied by the target chip; a third processing unit, used to replace the network name of a predetermined candidate pin with the target network name of the target pin based on the first position information of the signal line of the target pin in the target array.

[0015] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0016] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0017] According to another embodiment of the present application, a computer program product is provided. The computer program product includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0018] Through the above-mentioned embodiment provided by the present application, according to the attribute information of all pins in the target chip and a group of signal lines that are not connected to the routing around the target chip, the second group of pins that need to optimize the routing layout (replace the network name) are determined. Then, according to the regional division rules, the second group of pins that need to change the network name are divided into different areas respectively, and according to the first position information of the signal line of the pin in each area in the target chip, it is automatically determined to change the network name of the pin in each area to the candidate pin closest to the signal line. In other words, the above-mentioned replacement method is adopted, which not only realizes the optimal connection between the signal line and the pin, but also avoids the omission and duplication of the pin network name, and improves the accuracy in the process of changing the network name of the chip pin. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0020] Figure 1 It is a hardware structure block diagram of a server device of a chip pin processing method according to an embodiment of the present application;

[0021] Figure 2 is a flow chart of an optional chip pin processing method according to an embodiment of the present application;

[0022] Figure 3 It is a schematic diagram of the signal routing of the chip pins in the related art;

[0023] Figure 4 is a schematic diagram of an optional element attribute line and a group of signal lines according to an embodiment of the present application;

[0024] Figure 5 is a schematic diagram of optionally dividing a chip area into multiple sub-areas according to an embodiment of the present application;

[0025] Figure 6 is an overall flow chart of an optional chip pin processing method according to an embodiment of the present application;

[0026] Figure 7 is a structural block diagram of a chip pin processing device according to an embodiment of the present application;

[0027] Figure 8 It is a schematic diagram of the structure of an optional electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0030] The chip pin processing method embodiment provided in the embodiment of the present application can be executed in a server device or a similar computing device. Taking running on a server device as an example, Figure 1 1 is a hardware structure block diagram of a server device of a chip pin processing method according to an embodiment of the present application. Figure 1 As shown, the server device may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the server device may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above server device. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0031] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the chip pin processing method in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the server device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0032] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the server device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0033] The chip pin processing method in the embodiment of the present application can be applied to, but not limited to, the optimization scenario of signal routing in the PCB board design process of the chip in the server, such as Figure 3 Therefore, the routing of traditional chip pins is seriously crossed and the routing is relatively chaotic. If the signal routing cannot be connected to the inside of the chip, it is usually necessary to increase the number of chip layers or change the network naming of the chip pins to achieve it.

[0034] Among them, PCB board routing can be but not limited to copper wires distributed at various levels with a certain width and thickness, which are divided into strip lines and microstrip lines. Among them, strip lines refer to strip lines that run on the inner layer of the PCB board and are buried inside the PCB. It is embedded between two layers of conductors, so it is not easy to receive external radiation interference; microstrip lines refer to strip lines attached to the surface of the PCB in the surface layer. It is not exposed to the air, and the other side is distributed in the insulating medium of the PCB, so it is easy to receive surrounding radiation interference.

[0035] If the number of layers is increased only to solve the problem of chip pins, it will inevitably cause waste, and the more layers there are, the higher the cost and the greater the processing difficulty, which does not meet the needs of cost optimization. Therefore, consider changing the chip pin network name to solve the problem of serious signal routing crossing.

[0036] In order to solve the above problems existing in the related art, a chip pin processing method is provided in this embodiment, and its execution subject includes but is not limited to a software system for automatically changing the network name of the chip pin, such as Figure 2 As shown, the process includes the following steps S202-S208:

[0037] Step S202: obtaining a first array consisting of attribute information of each pin in a first group of pins of a target chip, wherein there is a group of signal lines with no connected routing around the target chip, and the first array includes description information of each pin on multiple attributes;

[0038] Step S204: determining a second group of pins whose network names are to be changed from the first group of pins based on the first array and a second array consisting of signal attributes of each signal line in a group of signal lines;

[0039] Step S206: according to the area division rule, the attribute information of each pin in the second group of pins is saved in a target array corresponding to the target area, wherein the target area is obtained by dividing the area occupied by the target chip;

[0040] Step S208: Based on the first position information of the signal line of the target pin in the target array, the network name of the predetermined candidate pin is replaced with the target network name of the target pin.

[0041] In the embodiment of the present application, the PCB can be designed using, but is not limited to, Allegro software, and the software supports secondary development by users, providing a good software foundation for the method of quickly replacing chip pins or chip pin networks.

[0042] Among them, Allegro software, as a PCB design tool, provides comprehensive design and simulation tools, enabling developers to design and route complex PCBs with high speed, high density, and multiple layers. Depending on the complexity of the circuit design, the PCB board can include different numbers of layers. The layer used for chip routing is also called the signal layer, which can transmit electrical signals. The point-to-point paths (also known as traces) on the PCB board connect the pins of the chip to achieve electrical connections between the internal circuits of the chip and the external circuits. These traces transmit electrical signals, power, and bottom lines to ensure that the chip can work properly.

[0043] It should be noted that the PCB board may include a signal layer, a power layer, a ground layer, etc., wherein a plurality of signal layers may be included.

[0044] After selecting the target chip whose network needs to be replaced, create a first array corresponding to the original pin signal attributes of the target chip M whose network needs to be replaced, wherein the first array can be but is not limited to a one-dimensional or multi-dimensional array, specifically including pin number, coordinates, material number, network name, and layer, etc.

[0045] As shown in case 2, there are multiple circular connection points distributed on the left circuit board, indicating the connection points between the chip pins and other components, and the right area marks a group of signal lines with unconnected traces around the target chip. The signal attributes of a group of signal lines are saved in the second array, and then the second group of pins whose network names need to be changed are determined based on the first array and the second array. The implementation method of determining the second group of pins will be described in detail below in conjunction with a specific embodiment.

[0046] After the second group of pins is determined, the area where the target chip is located is divided into a preset number of sub-areas, for example Figure 5 As shown, it is divided into 4 sub-areas M1 to M4 in total. According to the first-come-first-served principle, the second group of pins are stored in 4 arrays A1 to A4 corresponding to the 4 sub-areas.

[0047] Specifically, by traversing each pin in the second group of pins, it is determined which sub-area of ​​the four sub-areas M1 to M4 the signal routing of each pin passes through first, and then the current pin is stored in the sub-area that is passed through first. The reason is that the signal routing in the sub-area that is passed through first is the shortest and has fewer windings. The purpose is to optimize the routing layout, reduce unnecessary windings, and reduce the crossing between signal routings.

[0048] After all the pins are stored in 4 sub-areas, 4 arrays A1 to A4 corresponding to the 4 sub-areas are created, wherein array A1 stores the attribute information of the pins stored in the first sub-area M1, for example, including the above-mentioned pin serial number, coordinates, material number, network name, and layer, etc. Array A2 stores the attribute information of the pins stored in the second sub-area M2, and so on, to create arrays A3 and A4.

[0049] After determining the area division of the second group of pins, the network name replacement strategy will be executed according to the signal routing position information in each sub-area (each target area). Specifically, the algorithm will analyze whether the signal routing of each pin in each sub-area is located at the same level as the target chip, for example, whether it is located on the upper surface layer of the target chip or on the lower surface layer of the target chip. If so, the network name of the current pin will be replaced to a candidate pin on the first or second row of pins on the outside of the target chip.

[0050] In an optional example, the system can find the candidate pins closest to the signal line by calculating the distance from the signal line to the external pins of the chip, but is not limited to it. These candidate pins are usually the first and second rows of pins outside the chip, because they can be directly connected to the signal line without passing through VIA (vias), which effectively reduces the length of the line and the winding. The system will automatically replace the network name of the candidate pin with the target network name of the target pin, achieving the optimal connection between the signal line and the pin. In addition, the system will automatically check the network names before and after the replacement to ensure that there are no omissions or duplications, thereby improving the accuracy and consistency of the design.

[0051] The above method not only simplifies the pin network replacement work in PCB design and improves design efficiency, but also ensures the optimization of signal line connection and reduces costs. It is an important innovation in the field of server chip design. Through automated processing, it not only reduces the workload of designers, but also significantly improves the accuracy and quality of design.

[0052] In an exemplary embodiment, the method of determining a second group of pins whose network names are to be replaced from the first group of pins based on the first array and the second array consisting of signal attributes of each signal line in a group of signal lines includes:

[0053] Based on the pin type of each pin, filter out the attribute information of the power pin from the first array;

[0054] constructing a third array based on the remaining attribute information in the first array except the attribute information of the power pin;

[0055] By traversing the second array, determining from each signal line at least some of the signal lines whose network names are the same as the network names of at least some of the pins in the third array;

[0056] Based on the signal attributes of at least some of the signal lines and the attribute information of at least some of the pins, a fourth array is constructed, wherein the fourth array includes description information of a plurality of element attribute lines, one of the plurality of element attribute lines is a virtual connection line between a breakpoint of a signal line in at least some of the signal lines and one of the pins in at least some of the pins, and a signal line and a pin have the same network name;

[0057] By traversing the fourth array, a second group of pins whose network names are to be replaced is obtained.

[0058] After obtaining the attribute information of all pins on the target chip, it is necessary to filter out the attribute information of non-power network pins and save it in the third array. In other words, the power pins and ground pins that do not need to participate in the optimization process of signal line connection are separated from the first array to improve the overall processing efficiency.

[0059] Combined with the description of the above embodiment, it can be known that the second array contains the attribute information of the signal lines that are not connected to the routing around the target chip. By traversing the second array and comparing it with the third array, it is possible to identify which signal lines have the same network names as the pin network names in the third array. These same network names represent potential connection requirements between signal lines and pins, but they cannot be directly connected due to routing length or layer restrictions. Therefore, after identifying these signal lines and pins, these pins are determined as pins that may need to change network names.

[0060] Among them, by traversing the second array and comparing it with the third array, while identifying that the network name of the signal line is the same as the pin network name in the third array, it is also necessary to determine whether the attribute display is a disconnected signal line, and then store the network name that is the same as the network name in the third array and the attribute of the disconnected signal line in the fourth array, and determine this part of the signal line as a signal that needs to exchange networks. In this way, the signals that appear on the surface without punching and directly connect to the pull-up and pull-down resistors can be eliminated, reducing the workload caused by replacing the pin network.

[0061] The fourth array contains virtual connection line information (which can also be logically regarded as element attribute lines). These connection lines connect the signal line breakpoints and the pins with the same network name. The construction of this virtual connection line provides an intuitive data structure for the subsequent network name replacement strategy, which helps to more accurately understand and process the connection relationship between signal lines and pins.

[0062] In this embodiment, the screening process of network name replacement is further optimized. Not only is the network of signal lines and pins considered for matching, but a more intuitive data structure is provided through the construction of virtual connection lines, ensuring that the connection requirements between signal lines and pins can be more effectively identified and processed, thereby improving the accuracy of screening pins that need to change network names.

[0063] In an exemplary embodiment, the second group of pins whose network names are to be changed are obtained by traversing the fourth array, including:

[0064] Get the chip area occupied by each pin in the target chip;

[0065] Dividing the chip area into a preset number of sub-areas by a first dividing line and a second dividing line, wherein the preset number of sub-areas include the target area;

[0066] By traversing the description information of multiple element attribute lines in the fourth array, a second group of pins of the network name to be replaced is obtained.

[0067] In this embodiment, it is assumed that the area occupied by the target chip is Figure 5 The square area shown is then divided into 4 sub-areas M1 to M4 by introducing a first dividing line L1 and a second dividing line L2, and then a second group of pins whose network names need to be changed are determined by traversing multiple element attribute lines in the fourth array.

[0068] It should be noted that the fourth array includes but is not limited to two parts of content. One part is the attribute information related to the network name that is the same as the network name in the third array and the attribute is displayed as a disconnected signal line. The other part is the description information of multiple element attribute lines, where the element attribute lines include but are not limited to the following: Figure 4 The connection lines between the pins in the target chip and the breakpoints of the signal lines that are not connected to the surrounding traces are shown. Obviously, the net name of the pin connected by each element attribute line is the same as the net name of a signal line corresponding to the breakpoint.

[0069] In addition, the first cutting line L1 and the second cutting line L2 may be, but are not limited to, two diagonal lines of a square corresponding to the chip area. Obviously, L1 and L2 are only examples and are not limited thereto.

[0070] By introducing the preset first dividing line and the second dividing line in the embodiment of the present application, the chip area can be divided into multiple sub-areas. This area division strategy aims to more finely manage the connection relationship between the signal line and the pin, ensure that the signal line can be connected to the pin as directly as possible, reduce unnecessary routing length and winding, and improve the efficiency and accuracy of PCB design.

[0071] In an exemplary embodiment, the second group of pins whose network names are to be replaced are obtained by traversing the description information of multiple element attribute lines in the fourth array, including:

[0072] Obtain each element attribute line from the multiple element attribute lines in turn as the current element attribute line;

[0073] When a current element attribute line intersects at least one of the first segmentation line and the second segmentation line, a current pin on the current element attribute line is determined as a pin in the second group of pins.

[0074] By traversing the description information of all element attribute lines in the fourth array, it is determined whether each element attribute line intersects with the first dividing line L1 or the second dividing line L2. If so, the pin connected to the element attribute line is determined as the pin whose network name needs to be changed, and the attribute information of the pin is stored in the fifth array.

[0075] If an element attribute line intersects both the first dividing line L1 and the second dividing line L2, the pin network name connected to the element attribute line also needs to be changed. Similarly, the attribute information of the pin is stored in the fifth array.

[0076] The above-mentioned element attribute line intersects with the first dividing line and the second dividing line, indicating that the routing path of the signal line crosses the boundary of the chip area, which means that there are routing length or layer limitations for direct connection to the internal pins of the chip. Therefore, the pins that intersect with the dividing lines need to change the network names to optimize the connection of the signal lines.

[0077] Through the pin screening strategy of this embodiment, it is ensured that the system can accurately identify the pins whose network names need to be changed, avoid unnecessary network name change operations, and improve processing accuracy and processing efficiency.

[0078] In an example, the above-mentioned saving the attribute information of each pin in the second group of pins into the target array corresponding to the target area according to the area division rule includes:

[0079] Dividing the chip area into a preset number of sub-areas by a first dividing line and a second dividing line, wherein the first dividing line and the second dividing line are two diagonal lines on a closed area formed by the chip area;

[0080] Get each pin from the second group of pins in turn as the current pin;

[0081] When a signal attribute line of a current signal on a current pin first passes through a current sub-region among a preset number of sub-regions, the current attribute information of the current pin is saved in a current array corresponding to the current sub-region, wherein the current array is a target array.

[0082] After determining the second group of pins whose network names need to be changed by the method in the above embodiment, these pins are further analyzed one by one. Specifically, according to the first dividing line and the second dividing line, the chip area is divided into 4 sub-areas M1 to M4, and then it is determined in turn which sub-area of ​​the 4 sub-areas the signal line of each pin in the second group of pins passes through first.

[0083] According to the first-pass principle, the signal attribute line of each pin in the second group of pins is determined in turn to first pass through one of the four sub-areas, and then the pin is stored in one of the sub-areas, and the attribute information of the pin is saved in one of the arrays corresponding to one of the sub-areas.

[0084] For example, when the signal attribute line of pin 1 first passes through sub-area M1, the attribute information of pin 1 is saved in array A1 corresponding to sub-area M1; when the signal attribute line of pin 2 first passes through sub-area M2, the attribute information of pin 2 is saved in array A2 corresponding to sub-area M2.

[0085] By adopting this embodiment, the classification and storage process of pin attribute information is further refined, ensuring the optimal execution of the subsequent network name replacement strategy. This method not only significantly improves the efficiency of PCB design and reduces the design cost, but also effectively reduces the routing length and winding, and improves the performance and stability of signal transmission.

[0086] In addition, through the above method, designers can quickly and accurately complete the replacement and optimization of the chip pin network, solve the problem of inconsistent designs among multiple people, improve the uniformity of the design, reduce the design error rate, and improve the overall quality of PCB design, providing strong technical support for the high performance and low-cost design of server equipment.

[0087] In an exemplary embodiment, the method of replacing the network name of the predetermined candidate pin with the target network name of the target pin based on the first position information of the signal line of the target pin in the target array includes:

[0088] In a case where the first position information of the signal line of the target pin indicates that the target pin is located on a surface layer of the target chip, determining a candidate pin from a set of pins outside the target chip;

[0089] Replace the candidate pin's net name with the target net name; or

[0090] When the first position information of the signal line of the target pin indicates that the layer where the target pin is located is inconsistent with the surface layer of the target chip, determining the candidate pin from the pin set outside the target chip;

[0091] Obtain the location of the target signal line connecting the target pin and the target via that the candidate pin needs to pass through;

[0092] Connect the signal line of the target pin to the candidate pin through the target via.

[0093] In this embodiment, the strategy for changing the network name can be determined based on but is not limited to the first position information of the signal line of the target pin. If the signal routing line of the target pin is located on the surface layer of the target chip, that is, the first position information and the surface layer of the target chip (including the upper surface layer and the lower surface layer) are on the same level, then the network name of the signal line is exchanged to the first and second rows of pins on the outside of the target chip.

[0094] That is to say, when the signal routing is located on the surface of the target chip, the pin outside the chip closest to the signal line will be selected as the candidate pin, and the network name of the candidate pin will be directly replaced with the target network name of the target pin, thereby optimizing the signal transmission path.

[0095] When the signal line of the target pin is located in a non-surface layer, that is, the layer where the first position information is located is different from the surface layer of the target chip, since the pins inside the target chip need to be drilled with VIA (via), the signal line of the target pin is connected to the first or second row of pins on the outside of the chip through the target via.

[0096] Obviously, it is easy to understand that after the target network name of the target pin is replaced with the candidate pin, according to the above replacement strategy, the network names of other pins will also be replaced with the target pin.

[0097] By determining whether the signal line of the target pin is located in the same layer as the surface layer of the target chip, different methods are used to select candidate pins, fully considering the routing restrictions of the signal line at different levels. Through intelligent pin selection and optimized use of vias, the shortest path for signal transmission is ensured, the crossing between signals is reduced, and the performance and stability of signal transmission are improved.

[0098] In addition, this embodiment not only takes into account the network name matching problem between the signal line and the pin, but also deeply analyzes the specific routing position and level of the signal line on the PCB board, ensuring the optimal execution of the network name replacement strategy, while also improving the work efficiency of designers, reducing the design error rate, and improving the overall quality of PCB design, thereby achieving the flexibility and adaptability of the network name replacement strategy.

[0099] In an exemplary embodiment, after replacing the network name of the predetermined candidate pin with the target network name of the target pin based on the first position information of the signal line of the target pin in the target array, the method further includes:

[0100] In the case where the chip area is divided into a plurality of sub-areas, each sub-area is sequentially obtained from the plurality of sub-areas as a current sub-area;

[0101] Back up the element information of the current group of pins in the current sub-area to the current backup array;

[0102] Based on the network name, compare the target array after the network name is updated with a current backup array to obtain a first comparison result;

[0103] When the first comparison result indicates that the target array after the network name is updated is consistent with the network name in the current backup array, determining that the target network name of the target pin is accurately replaced; or

[0104] In the case where the chip area is divided into multiple sub-areas, updated element information of multiple groups of pins is obtained, wherein the updated element information of the multiple groups of pins represents element information of each pin in the multiple sub-areas after the network name is changed, and the multiple sub-areas have a corresponding relationship with the multiple groups of pins;

[0105] Based on the update element information of the multiple groups of pins, the target array is updated to obtain an updated target array;

[0106] Compare the network name in the updated target array with the network name of each pin in the second group of pins to obtain a second comparison result, wherein the second group of pins is a plurality of groups of pins in a plurality of sub-areas;

[0107] When the second comparison result indicates that the network name in the updated target array is consistent with the network name of each pin in the second group of pins, it is determined that the target network name of the target pin is accurately replaced.

[0108] In order to ensure the accuracy of the pin network name replacement result, in this embodiment, two checking methods are provided to check whether there is omission or duplication of network names.

[0109] The first is for Figure 5 The pins in each of the four sub-areas M1 to M4 are checked respectively, and based on the inspection results of each sub-area, it is determined whether the replacement result is accurate. Specifically, arrays A1 to A4 corresponding to the four sub-areas M1 to M4 are obtained, and an array A is selected from arrays A1 to A4 respectively. i , array A i The element information in is backed up to a backup array, where i is a positive integer greater than or equal to 1 and less than or equal to 4.

[0110] Judge array A i Check whether the signal routing of each pin is at the same level as the target chip. If so, swap the network name of the signal line to the first and second rows of pins on the outside of the chip. If not, connect the pins inside the chip to the first and second rows of pins on the outside of the chip through the target vias, thereby achieving the replacement of the network name.

[0111] In realizing A i After changing the network names of each pin in array A, compare i The element information in the backup array is compared with the element information in the backup array. For example, compare array A i The network name in the backup array is exactly the same as the network name in the backup array. If they are exactly the same, determine the Mth i There are no omissions or duplications in the network names of all pins in the sub-areas.

[0112] According to the above method, the element information in the array corresponding to each sub-region is backed up one by one, and then the above-mentioned network name replacement strategy is executed based on each sub-region. By comparing the element information in the array after replacement of each sub-region with the element information in the backup array, it is ensured that the replacement result of the network name of the pins used in the sub-region is accurate.

[0113] It is easy to understand that each of the above sub-regions corresponds to an array (for example, A1) containing element information of all pins in the sub-region and a backup array.

[0114] The second is to Figure 5 The pins in all areas of the four sub-areas M1 to M4 shown are checked uniformly, and specifically, the above-mentioned network name replacement strategy is executed for the array corresponding to each sub-area. During the replacement process, the network name in each array A1 to A4 is updated to obtain the updated array A′1 to A′4, and then all elements in the array A′1 to A′4 are merged into an array F (which can also be understood as the updated target array).

[0115] By comparing the network names in array F with the network names of each pin in the second group of pins, if the two are completely consistent, it is determined that there are no omissions or duplications.

[0116] It should be noted that after the inspection process is completed, the array composed of the element information of the second group of pins and the element information in array F can also be printed into a table, which includes the chip position number, chip pin number, network name before replacement (or network name), network name after replacement, etc., and output to an Excel table so that the chip pin network name can be replaced in the schematic diagram.

[0117] In order to understand the above technical solution more clearly, Figure 6 The overall flow chart shown further describes the processing method of the above chip pins.

[0118] S602, selecting a chip whose network name needs to be changed;

[0119] S604, creating an array A of original pin signal attributes of the target chip;

[0120] That is, for each pin on the target chip, the element information in multiple dimensions such as the pin number, coordinates, material number, network name and layer is recorded to obtain array A, where array A can be a one-dimensional array or a multi-dimensional array.

[0121] S606, filtering out element information of non-power or non-ground pins from array A to obtain array B;

[0122] S608, storing the array C consisting of the signal attributes of the surrounding unconnected routing lines and the signal line attributes with the same network name in the array B into the array D;

[0123] like Figure 4As shown, there is a group of signal lines with unconnected routing around the target chip, and the attribute information of some signal lines in the group of signal lines whose network names are the same as those in array B and whose attributes are displayed as disconnected are stored in array D.

[0124] S610, determining whether an element attribute line in array D intersects with a first cutting line and / or a second cutting line;

[0125] Among them, element attribute lines include but are not limited to Figure 4 The connection lines between the pins in the target chip and the breakpoints of the signal lines that are not connected to the surrounding traces are shown. Obviously, the net name of the pin connected by each element attribute line is the same as the net name of a signal line corresponding to the breakpoint.

[0126] In addition, the first cutting line L1 and the second cutting line L2 may be, but are not limited to, two diagonal lines of a square corresponding to the chip area. Obviously, L1 and L2 are only examples and are not limited thereto.

[0127] If the element attribute line intersects at least one of L1 and L2, step S612 is executed; otherwise, the network name is not changed.

[0128] S612, determining a pin connected to at least one of L1 and L2 that has an intersecting element attribute line as a pin that needs to have its network name changed, and storing the attribute information of the pin in array E;

[0129] S614, according to the first-come-first-served principle, the element information in array E is stored in arrays A1 to A4 respectively;

[0130] For example, suppose the signal attribute line connected to a pin in array E first passes through Figure 5 A sub-region M1 among the four sub-regions shown, and then the pins are stored in the M1 region, and the attribute information of the pins is saved in an array A1 corresponding to the M1 sub-region.

[0131] Similarly, when the signal attribute line of pin 2 first passes through the sub-region M2, the attribute information of pin 2 is saved in the array A2 corresponding to the sub-region M2, and so on.

[0132] S616, executing a network name exchange process for each array in A1-A4;

[0133] For example, for the signal line of each pin in the A1 array, determine whether its layer is on the same layer as the target chip. If so, swap the network name of the pin to the first and second rows of pins on the outside of the target chip; if not, connect the pins inside the chip to the first and second rows of pins on the outside of the chip through the target vias.

[0134] For the above A2 to A4, you can refer to the replacement process of each pin in the above array A1, change their network names respectively, and then get the array A1 to A4 after the network names are changed.

[0135] S618, respectively comparing each array after the network name is changed with the network name in the preset backup array to obtain 4 comparison results;

[0136] For example, assuming that the array A1 after the network name is changed is recorded as array A′1, then the element information in array A1 is backed up in advance to an array N1, and the network names in array A′1 and backup array N1 are compared to obtain a second comparison result. If the first comparison result indicates that all network names are completely consistent, it is determined that the network name replacement process of the pins in sub-area M1 is accurate.

[0137] Similarly, assuming that the array A2 after the network name is changed is recorded as array A′2, then the element information in array A2 is backed up in advance to an array N2, and the network names in array A′2 and backup array N2 are compared to obtain a second comparison result. The comparison process of the remaining two arrays can refer to the execution process in the above-mentioned array A1 and array A2 after the network name is changed, which will not be repeated here.

[0138] S620, when the four comparison results all indicate that the network name in the backup array is consistent with the network name in the array corresponding to the network name after replacement, it is determined that there is no duplication or omission of the network name during the replacement process;

[0139] S622, for the signal line of each pin in the array A1, the network name is changed, and the element information after the name change is merged into the array F;

[0140] S624, comparing the network names in array F and array E;

[0141] The array F includes element information of each pin after the network name is changed.

[0142] S626, when the network names in array F and array E are consistent, determine that there are no duplicate or missing pins or network names.

[0143] In another optional embodiment, the chip pin processing method may be implemented by, but not limited to, the following steps:

[0144] S11, loading a program for realizing automatic network name change in the command window;

[0145] At S12, the program will automatically pop up a window to prompt the developer to change the network chip currently selected;

[0146] S13, the program automatically creates an array of original pin signal attributes of the chip that needs to replace the network;

[0147] S14, the software provides a window to fill in the pin number of the network that cannot be swapped;

[0148] S15, the software automatically selects the signal that needs to change the network;

[0149] S16, the software automatically executes the automatic switching network strategy;

[0150] For details, please refer to the description in the above implementation, which will not be repeated here.

[0151] S17, the software automatically outputs the final excel table of chip exchange pin network names, and uses the table to replace the chip pin network names in the schematic diagram.

[0152] Through the above-mentioned method, the above-mentioned method for quickly replacing the chip pin network provided by the present application can realize that the chip automatically matches the most suitable network according to the direction of the signal line, completes the network naming replacement of all pins, and verifies with the original network naming. After checking whether there are omissions or duplications, the corresponding table of exchange pin network names is output, and the chip pin network naming replacement is completed quickly and accurately, and a table in a unified format is output, without the need for manual matching and inspection. Improve efficiency and accuracy, and avoid repeated exchange of chip pin network names.

[0153] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0154] In this embodiment, a chip pin processing device is also provided to implement the above-mentioned embodiments and preferred implementation modes, which have been described and will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the modules described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0155] Figure 7 : is a structural block diagram of a chip pin processing device according to an embodiment of the present application, the device comprising:

[0156] A first acquisition unit 702 is used to acquire a first array consisting of attribute information of each pin in a first group of pins of a target chip, wherein there is a group of signal lines with no connected wiring around the target chip, and the first array includes description information of each pin on multiple attributes;

[0157] A first processing unit 704 is used to determine a second group of pins whose network names are to be replaced from the first group of pins based on the first array and a second array consisting of signal attributes of each signal line in a group of signal lines;

[0158] The second processing unit 706 is used to save the attribute information of each pin in the second group of pins into a target array corresponding to the target area according to the area division rule, wherein the target area is obtained by dividing the area occupied by the target chip;

[0159] The third processing unit 708 is used to replace the network name of the predetermined candidate pin with the target network name of the target pin based on the first position information of the signal line of the target pin in the target array.

[0160] In an exemplary embodiment, the first processing unit 704 includes:

[0161] A first processing module, configured to filter out attribute information of power pins from a first array based on pin types of respective pins;

[0162] A second processing module, configured to construct a third array based on the remaining attribute information in the first array except the attribute information of the power pin;

[0163] A third processing module, configured to determine, from each signal line, at least some of the signal lines whose network names are the same as the network names of at least some of the pins in the third array by traversing the second array;

[0164] a fourth processing module, configured to construct a fourth array based on the signal attributes of at least some of the signal lines and the attribute information of at least some of the pins, wherein the fourth array includes description information of a plurality of element attribute lines, one of the plurality of element attribute lines is a virtual connection line between a breakpoint of a signal line of at least some of the signal lines and one of the pins of at least some of the pins, and a signal line and a pin have the same network name;

[0165] The fifth processing module is used to obtain a second group of pins whose network names are to be replaced by traversing the fourth array.

[0166] In an exemplary embodiment, the fifth processing module includes:

[0167] A first acquisition submodule is used to acquire the chip area occupied by each pin in the target chip;

[0168] A first dividing submodule, used to divide the chip area into a preset number of sub-areas through a first dividing line and a second dividing line, wherein the preset number of sub-areas include a target area;

[0169] The first processing submodule is used to obtain a second group of pins of the network name to be replaced by traversing the description information of multiple element attribute lines in the fourth array.

[0170] In an exemplary embodiment, the fifth processing module includes:

[0171] A second acquisition submodule is used to sequentially acquire the description information of each element attribute line from the description information of the plurality of element attribute lines as the description information of the current element attribute line;

[0172] The second processing submodule determines a current pin on the current element attribute line as a pin in the second group of pins when the current element attribute line intersects at least one of the first segmentation line and the second segmentation line.

[0173] In an exemplary embodiment, the second processing unit 706 includes:

[0174] A first dividing module, used to divide the chip area into a preset number of sub-areas by a first dividing line and a second dividing line, wherein the first dividing line and the second dividing line are two diagonal lines on a closed area formed by the chip area;

[0175] A first acquisition module, used for sequentially acquiring each pin from the second group of pins as a current pin;

[0176] A saving module is used to save the current attribute information of a current pin to a current array corresponding to a current sub-area when a signal attribute line of a current signal on a current pin first passes through a current sub-area in a preset number of sub-areas, wherein the current array is a target array.

[0177] In an exemplary embodiment, the third processing unit 708 includes:

[0178] A fifth processing module, configured to determine a candidate pin from a set of pins outside the target chip when the first position information of the signal line of the target pin indicates that the target pin is located on a surface layer of the target chip;

[0179] Replace the candidate pin's net name with the target net name; or

[0180] When the first position information of the signal line of the target pin indicates that the layer where the target pin is located is inconsistent with the surface layer of the target chip, determining the candidate pin from the pin set outside the target chip;

[0181] Obtain the location of the target signal line connecting the target pin and the target via that the candidate pin needs to pass through;

[0182] Connect the signal line of the target pin to the candidate pin through the target via.

[0183] In an exemplary embodiment, the above device further includes:

[0184] a fourth processing unit, configured to, after replacing the predetermined network name of the candidate pin with the target network name of the target pin based on the first position information of the signal line of the target pin in the target array, sequentially acquire each sub-region from the multiple sub-regions as a current sub-region when the chip region is divided into multiple sub-regions;

[0185] Back up the element information of the current group of pins in the current sub-area to the current backup array;

[0186] Based on the network name, compare the target array after the network name is updated with a current backup array to obtain a first comparison result;

[0187] When the first comparison result indicates that the target array after the network name is updated is consistent with the network name in the current backup array, determining that the target network name of the target pin is accurately replaced; or

[0188] In the case where the chip area is divided into multiple sub-areas, updated element information of multiple groups of pins is obtained, wherein the updated element information of the multiple groups of pins represents element information of each pin in the multiple sub-areas after the network name is changed, and the multiple sub-areas have a corresponding relationship with the multiple groups of pins;

[0189] Based on the update element information of the multiple groups of pins, the target array is updated to obtain an updated target array;

[0190] Compare the network name in the updated target array with the network name of each pin in the second group of pins to obtain a second comparison result, wherein the second group of pins is a plurality of groups of pins in a plurality of sub-areas;

[0191] When the second comparison result indicates that the network name in the updated target array is consistent with the network name of each pin in the second group of pins, it is determined that the target network name of the target pin is accurately replaced.

[0192] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0193] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0194] Optionally, in this embodiment, the computer program may be configured to perform the following steps by means of the computer program:

[0195] S1, after replacing the predetermined network name of the candidate pin with the target network name of the target pin based on the first position information of the signal line of the target pin in the target array;

[0196] S2, determining a second group of pin information of the network name to be replaced from the first group of pins based on the first array and a second array consisting of signal attributes of each signal line in a group of signal lines;

[0197] S3, according to the area division rule, respectively saving the attribute information of each pin in the second group of pins into a target array corresponding to the target area, wherein the target area is obtained by dividing the area occupied by the target chip;

[0198] S4, based on the first position information of the signal line of the target pin in the target array, replacing the network name of the predetermined candidate pin with the target network name of the target pin.

[0199] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0200] The embodiment of the present application also provides an electronic device, such as Figure 8 As shown, the electronic device includes a memory 802 and a processor 804. The memory 802 stores a computer program, and the processor 804 is configured to execute the steps in any of the above method embodiments through the computer program.

[0201] Optionally, in this embodiment, the processor 804 may be configured to perform the following steps through a computer program: S1, after replacing the network name of the predetermined candidate pin with the target network name of the target pin based on the first position information of the signal line of the target pin in the target array;

[0202] S2, determining a second group of pin information of the network name to be replaced from the first group of pins based on the first array and a second array consisting of signal attributes of each signal line in a group of signal lines;

[0203] S3, according to the area division rule, respectively saving the attribute information of each pin in the second group of pins into a target array corresponding to the target area, wherein the target area is obtained by dividing the area occupied by the target chip;

[0204] S4, based on the first position information of the signal line of the target pin in the target array, replacing the network name of the predetermined candidate pin with the target network name of the target pin.

[0205] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0206] Alternatively, a person skilled in the art may understand that: Figure 8 The structure shown is for illustration only. Figure 8 The structure of the electronic device is not limited. For example, the electronic device may also include Figure 8 More or fewer components (such as network interfaces, etc.) as shown in, or with Figure 8 Different configurations shown.

[0207] Among them, the memory 802 can be used to store software programs and modules, such as the program instructions / modules corresponding to the chip pin processing method and the alarm information blowing device in the embodiment of the present application. The processor 804 executes various functional applications and data processing by running the software programs and modules stored in the memory 802, that is, realizing the above-mentioned chip pin processing method. The memory 802 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 802 may further include a memory remotely arranged relative to the processor 804, and these remote memories may be connected to the terminal via a network. Examples of the above-mentioned networks include but are not limited to the Internet, corporate intranets, local area networks, mobile communication networks and combinations thereof. Among them, the memory 802 can be specifically but not limited to being used to store first location information, target network name and other information. As an example, such as Figure 8As shown, the memory 802 may include, but is not limited to, the first acquisition unit 702, the first processing unit 704, the second processing unit 706, and the third processing unit 708 in the chip pin processing device. In addition, it may also include, but is not limited to, other module units in the verification device of the soft decoding function, which will not be repeated in this example.

[0208] Optionally, the transmission device 806 is used to receive or send data via a network. Specific examples of the network may include wired networks and wireless networks. In one example, the transmission device 806 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices and routers via a network cable so as to communicate with the Internet or a local area network. In one example, the transmission device 806 is a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0209] In addition, the electronic device mentioned above further includes: a display 808; and a connection bus 810, which is used to connect various module components in the electronic device mentioned above.

[0210] In other embodiments, the electronic device may be a node in a distributed system, wherein the distributed system may be a blockchain system, and the blockchain system may be a distributed system formed by connecting the multiple nodes in the form of network communication. Among them, the nodes may form a peer-to-peer (P2P) network, and any form of computing device, such as a server, terminal, or other electronic device, may become a node in the blockchain system by joining the peer-to-peer network.

[0211] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0212] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0213] The embodiments of the present application also provide a computer program, which includes computer instructions, which are stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps of any one of the above method embodiments.

[0214] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0215] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A chip pin processing method, characterized in that: include: Acquire a first array consisting of attribute information of each pin in a first group of pins of a target chip, wherein there is a group of signal lines with no connected routing wires around the target chip, and the first array includes description information of each pin on multiple attributes; Based on the first array and a second array consisting of signal attributes of each signal line in the group of signal lines, determining a second group of pins whose network names are to be replaced from the first group of pins; According to the area division rule, the attribute information of each pin in the second group of pins is respectively saved in a target array corresponding to a target area, wherein the target area is obtained by dividing the area occupied by the target chip; Based on the first position information of the signal line of the target pin in the target array, the network name of the predetermined candidate pin is replaced with the target network name of the target pin.

2. The method according to claim 1, characterized in that The determining a second group of pins whose network names are to be replaced from the first group of pins based on the first array and a second array consisting of signal attributes of each signal line in the group of signal lines comprises: Based on the pin types of the respective pins, the attribute information of the power pins is filtered out from the first array; based on the remaining attribute information in the first array except the attribute information of the power pins, a third array is constructed; By traversing the second array, determining from the respective signal lines at least some of the signal lines whose network names are the same as the network names of at least some of the pins in the third array; Based on the signal attributes of the at least part of the signal lines and the attribute information of the at least part of the pins, a fourth array is constructed, wherein the fourth array includes description information of a plurality of element attribute lines, one of the plurality of element attribute lines is a virtual connection line between a breakpoint of a signal line among the at least part of the signal lines and one of the at least part of the pins, and the network name of the one signal line is the same as that of the one pin; The second group of pins whose network names are to be changed is obtained by traversing the fourth array.

3. The method according to claim 2, characterized in that The step of obtaining the second group of pins whose network names are to be replaced by traversing the fourth array includes: Obtaining the chip area occupied by each pin in the target chip; Dividing the chip area into a preset number of sub-areas by a first dividing line and a second dividing line, wherein the preset number of sub-areas include a target area; The second group of pins of the network name to be replaced is obtained by traversing the description information of the plurality of element attribute lines in the fourth array.

4. The method according to claim 3, characterized in that The step of obtaining the second group of pins of the network name to be replaced by traversing the description information of the plurality of element attribute lines in the fourth array includes: sequentially acquiring description information of each element attribute line from the description information of the plurality of element attribute lines as description information of a current element attribute line; When the current element attribute line intersects at least one of the first segmentation line and the second segmentation line, a current pin on the current element attribute line is determined as a pin in the second group of pins.

5. The method according to claim 1, characterized in that The step of saving the attribute information of each pin in the second group of pins into a target array corresponding to the target area according to the area division rule comprises: Dividing the chip area into a preset number of sub-areas by a first dividing line and a second dividing line, wherein the first dividing line and the second dividing line are two diagonal lines on a closed area formed by the chip area; sequentially acquiring each pin from the second group of pins as a current pin; When the signal attribute line of the current signal on the current pin first passes through the current sub-region among the preset number of sub-regions, the current attribute information of the current pin is saved in the current array corresponding to the current sub-region, wherein the current array is the target array.

6. The method according to claim 1, characterized in that The replacing the predetermined network name of the candidate pin with the target network name of the target pin based on the first position information of the signal line of the target pin in the target array includes: In a case where the first position information of the signal line of the target pin indicates that the target pin is located on a surface layer of the target chip, determining the candidate pin from a set of pins outside the target chip; Replace the network name of the candidate pin with the target network name; or In the case where the first position information of the signal line of the target pin indicates that the layer where the target pin is located is inconsistent with the surface layer of the target chip, determining the candidate pin from the pin set outside the target chip; obtaining the position of the target via through which the target signal line connecting the target pin and the candidate pin passes; The signal line of the target pin is connected to the candidate pin through the target via.

7. The method according to any one of claims 1 to 6, characterized in that After replacing the predetermined network name of the candidate pin with the target network name of the target pin based on the first position information of the signal line of the target pin in the target array, the method further includes: In the case where the chip area is divided into a plurality of sub-areas, sequentially acquiring each sub-area from the plurality of sub-areas as a current sub-area; Backing up the element information of the current group of pins in the current sub-region to the current backup array; based on the network name, comparing the target array after the network name is updated with the current backup array to obtain a first comparison result; In the case where the first comparison result indicates that the target array after the network name is updated is consistent with the network name in the current backup array, determining that the target network name of the target pin is accurately replaced; or in the case where the chip area is divided into multiple sub-areas, obtaining updated element information of multiple groups of pins, wherein the updated element information of the multiple groups of pins represents the element information of each pin in the multiple sub-areas after the network name is replaced, and the multiple sub-areas have a corresponding relationship with the multiple groups of pins; Based on the update element information of the plurality of groups of pins, the target array is updated to obtain an updated target array; Comparing the network name in the updated target array with the network name of each pin in the second group of pins to obtain a second comparison result, wherein the second group of pins is a plurality of groups of pins in the plurality of sub-areas; When the second comparison result indicates that the network name in the updated target array is consistent with the network name of each pin in the second group of pins, it is determined that the target network name of the target pin is accurately replaced.

8. A chip pin processing device, characterized in that: include: A first acquisition unit is used to acquire a first array consisting of attribute information of each pin in a first group of pins of a target chip, wherein there is a group of signal lines that are not connected to the target chip around the target chip, and the first array includes description information of each pin on multiple attributes; A first processing unit, configured to determine a second group of pins whose network names are to be replaced from the first group of pins based on the first array and a second array consisting of signal attributes of each signal line in the group of signal lines; A second processing unit is used to save the attribute information of each pin in the second group of pins into a target array corresponding to a target area according to an area division rule, wherein the target area is obtained by dividing an area occupied by the target chip; The third processing unit is used to replace the network name of the predetermined candidate pin with the target network name of the target pin based on the first position information of the signal line of the target pin in the target array.

9. A computer-readable storage medium, characterized in that: The computer readable storage medium stores a computer program, wherein the computer program is executed by the processor. When executed, the steps of the method described in any one of claims 1 to 7 are implemented.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 7 are implemented.

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