Display device

Abstract

The embodiment of the invention provides a display device which comprises a backlight assembly, a plurality of gate lines, a plurality of data lines, a power line and a plurality of sub-pixel circuits are arranged on the backlight assembly, each sub-pixel circuit comprises a pixel driving circuit and a light-emitting element, the pixel driving circuit comprises a light-emitting duration driving circuit and a light-emitting control circuit, and the light-emitting duration driving circuit is connected with the light-emitting control circuit. The first capacitor is connected in series between the power signal transmission circuit and the first end of the third transistor, and the third transistor can adjust the conduction state of the third transistor according to the obtained first power signal, the control power change signal and the light-emitting duration driving data compensated by the threshold voltage of the third transistor, so that the light-emitting control circuit controls the light-emitting element to emit light. According to the circuit structure, the accuracy of the light-emitting duration of the light-emitting element is guaranteed through threshold value compensation, the process that a power line transmitting high level continuously transmits electric energy to a power line transmitting low level is avoided due to the arrangement of the first capacitor, and energy consumption generated in the light-emitting duration regulation and control process is reduced.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of display technology, and in particular, to a display device. Background Art

[0002] In recent years, due to the advantages of micro-LEDs over AMOLEDs (Active-matrix organic light emitting diodes), such as smaller device size, faster response speed, higher luminous efficiency, stronger stability and longer service life, the display application field based on micro-LEDs has developed rapidly and has become a research hotspot for display devices.

[0003] The pixel driving circuit of the micro LED can drive the micro LED to emit light through pulse width modulation (PWM) + pulse amplitude modulation (PAM), that is, the pixel driving circuit controls the conduction state of the PWM driving transistor according to the PWM signal and the changing ramp signal it obtains, so as to regulate the time when the pixel driving circuit generates the driving signal, that is, the light-emitting time of the micro transistor in each frame display cycle; and then determine the current value in the driving signal according to the PAM signal to determine the light intensity of the micro transistor during the light-emitting process, thereby determining the brightness of the micro LED in each frame display cycle.

[0004] However, in the circuit for pulse width modulation within the pixel driving circuit, two transistors are connected to both ends of the PWM driving transistor. When the luminous time is adjusted, the PWM driving transistor and the two transistors will be turned on at the same time, and the power line transmitting a high level will transmit an electrical signal to the power line transmitting a low level through the two turned-on transistors and the PWM driving transistor, resulting in high energy consumption when the luminous duration is adjusted by using the on-state of the PWM driving transistor. Summary of the invention

[0005] The present application provides a display device for solving the technical problem of high energy consumption when adjusting the light emission duration by using the on-state of a PWM driving transistor.

[0006] An embodiment of the present application provides a display device, including:

[0007] A backlight assembly, on which a power line, a plurality of gate lines, a plurality of data lines and a plurality of sub-pixel circuits are arranged;

[0008] Each of the sub-pixel circuits includes a pixel driving circuit and a light-emitting element;

[0009] The pixel driving circuit includes: a light-emitting duration driving circuit and a light-emitting control circuit, and the light-emitting duration driving circuit includes: a first capacitor, a third transistor, and a power signal transmission circuit;

[0010] The power signal transmission circuit is electrically connected to the power line and the gate line, and is configured to obtain a first power signal and a light-emitting control signal, and its conduction state is controlled by the light-emitting control signal, outputs the first power signal when it is turned on, and stops outputting the first power signal when it is turned off;

[0011] The first end of the first capacitor is electrically connected to the power signal transmission circuit and the control end of the third transistor, and the second end of the first capacitor is electrically connected to the first end of the third transistor, and is configured to store the light emission duration driving data compensated by the threshold voltage of the third transistor when the power signal transmission circuit is turned off and the first end of the first capacitor obtains the light emission duration driving data;

[0012] The first end of the third transistor is electrically connected to the power line, and the control end thereof is electrically connected to the power signal transmission circuit, and is configured to obtain a control power change signal and the first power signal, and adjust the conduction state of the third transistor according to the control power change signal, the first power signal, the threshold voltage of the third transistor and the compensated light emission duration driving data thereof;

[0013] The light emitting control circuit is electrically connected to the second end of the third transistor, and is configured to control the light emitting element to emit light when the third transistor is turned on during the display phase of each display cycle; and to control the light emitting element to stop emitting light during other time periods of the display cycle.

[0014] In the above technical solution, a pixel driving circuit is provided, including a light-emitting duration driving circuit and a light-emitting control circuit. In the light-emitting duration driving circuit, the first end of the first capacitor is electrically connected to the power signal transmission circuit, and the second end is electrically connected to the first end of the third transistor. The third transistor can adjust the conduction state of the third transistor according to the first power signal obtained at its control end, the control power change signal obtained at its first end, and the light-emitting duration driving data compensated by the threshold voltage of the third transistor stored in the first capacitor, so that the light-emitting control circuit controls the light-emitting element to emit light. The above circuit structure can perform threshold compensation on the light-emitting duration driving data to ensure the accuracy of the light-emitting duration of the light-emitting element, and the first capacitor is connected in series between the first transistor and the third transistor, thereby avoiding the process in which the power line transmitting a high level continuously transmits electrical energy to the power line transmitting a low level, reducing the energy consumption generated in the process of adjusting the light-emitting duration, thereby reducing the loss generated in the process of driving the light-emitting element.

[0015] In a feasible implementation manner, the light-emitting duration driving circuit further includes a second capacitor;

[0016] The first end of the second capacitor is electrically connected to the power line, and the second end of the second capacitor is electrically connected to the second end of the fourth capacitor. The second capacitor is configured to obtain a second power signal from its first end, and determine the control power change signal according to the change in the second power signal and the capacitance of the second capacitor and the capacitance of the first capacitor.

[0017] In the above technical solution, a second capacitor is set in the display device so that the change in the potential of the first end of the third transistor is a control power change signal determined after the coupling change of the second capacitor and the first capacitor to the change in the second power signal, and the change in the control power change signal is smaller than the change in the second power signal, so that in the process of adjusting the conduction state of the third transistor by using the change in the potential of the first end of the third transistor, the second power signal has a larger control range, so that the second power signal does not need to meet a higher control accuracy can also meet the control requirements of the third transistor.

[0018] The display device provided in the embodiment of the present application includes a backlight component, on which a plurality of gate lines, a plurality of data lines, a power line and a plurality of sub-pixel circuits are arranged, each sub-pixel circuit includes a pixel driving circuit and a light-emitting element, in the pixel driving circuit, including a light-emitting duration driving circuit and a light-emitting control circuit, in the light-emitting duration driving circuit, the first end of the first capacitor is electrically connected to the power signal transmission circuit, and the second end is electrically connected to the first end of the third transistor, the third transistor can adjust the conduction state of the third transistor according to the first power signal obtained by its control end, the control power change signal obtained by its first end, and the light-emitting duration driving data compensated by the threshold voltage of the third transistor stored in the first capacitor, so that the light-emitting control circuit controls the light-emitting element to emit light, the above-mentioned circuit structure ensures the accuracy of the light-emitting duration of the light-emitting element through threshold compensation, and the first capacitor is connected in series between the first transistor and the third transistor, so as to avoid the process of the power line transmitting a high level continuously transmitting electric energy to the power line transmitting a low level, thereby reducing the energy consumption generated in the process of regulating the light-emitting duration, thereby reducing the loss generated in the process of driving the light-emitting element. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0020] Figure 1 This is an application scenario diagram of a display device provided by the present application according to an exemplary embodiment;

[0021] Figure 2 This is a schematic diagram of the structure of a display device provided according to an exemplary embodiment of the present application;

[0022] Figure 3 A schematic diagram of the structure of a display provided by the present application according to an exemplary embodiment;

[0023] Figure 4 A schematic diagram of the structure of a display provided according to another exemplary embodiment of the present application;

[0024] Figure 5 A circuit structure diagram of a conventional pixel driving circuit provided by the present application according to an exemplary embodiment;

[0025] Figure 6 A schematic diagram of the structure of a P-type pixel driving circuit provided by the present application according to an exemplary embodiment;

[0026] Figure 7 A driving signal timing diagram of a P-type pixel driving circuit provided by the present application according to an exemplary embodiment;

[0027] Figure 8 This is a schematic structural diagram of an N-type pixel driving circuit provided by the present application according to an exemplary embodiment;

[0028] Fig. 9 This is a driving signal timing diagram of an N-type pixel driving circuit provided by the present application according to an exemplary embodiment.

[0029] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0030] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0031] It should be noted that, in this article, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "include one..." do not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, the parts, features, and elements with the same names in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context in the specific embodiment. It should be further understood that the terms "include", "comprise" indicate the existence of features, steps, operations, elements, components, projects, types, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, types, and / or groups.

[0032] In the description of the present disclosure, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The terms "or" and "and / or" are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way.

[0033] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0034] The display device provided in the embodiments of the present application may have various implementation forms, for example, it may be a smart TV, a laser projection device, a monitor, an electronic bulletin board, an electronic table, etc. Figure 1 This is a specific implementation of the display device of the present application.

[0035] Figure 1 is a schematic diagram of an operation scenario between a display device and a control device according to an embodiment, such as Figure 1As shown, the user can operate the display device 200 through the smart device 1003 or the control device 1005.

[0036] In some embodiments, the control device 1005 may be a remote controller, and the communication between the remote controller and the display device 200 includes infrared protocol communication or Bluetooth protocol communication, and other short-range communication methods, and the display device 200 is controlled wirelessly or wired. The user can input user commands through buttons on the remote controller, voice input, control panel input, etc. to control the display device 200.

[0037] In some embodiments, a smart device 1003 (such as a mobile terminal, a tablet computer, a computer, a laptop computer, etc.) may also be used to control the display device 200. For example, the display device 200 is controlled using an application running on the smart device.

[0038] In some embodiments, the display device 200 may not use the above-mentioned smart device or control device to receive instructions, but may receive user control through gestures or the like.

[0039] In some embodiments, the display device 200 can also be controlled in a manner other than the control device 1005 and the smart device 1003. For example, the user's voice command control can be directly received through a module for obtaining voice commands configured inside the display device 200, or the user's voice command control can be received through a voice control device set outside the display device 200.

[0040] In some embodiments, the display device 200 also communicates data with the server 1004. The display device 200 may be allowed to communicate via a local area network (LAN), a wireless local area network (WLAN), and other networks. The server 1004 may provide various content and interactions to the display device 200. The server 1004 may be a cluster or multiple clusters, and may include one or more types of servers.

[0041] Figure 2 A schematic diagram showing the structure of a display device in an example is shown in FIG. Figure 2 The display device 200 includes at least one of a tuner and demodulator 210 , a communicator 220 , a detector 230 , an external device interface 240 , a controller 250 , a display 260 , an audio output interface 270 , a memory 290 , a power supply 280 , and a user interface 291 .

[0042] In some embodiments, the controller includes a processor, a video processor, an audio processor, a graphics processor, a RAM, a ROM, and a first interface to an nth interface for input / output.

[0043] The display 260 includes a display screen component for presenting images, and a driving component for driving image display, which is used to receive image signals output from the controller, and display video content, image content, and menu control interface components and user control UI interface.

[0044] The display 260 may be a liquid crystal display, an OLED display, or a projection display, and may also be a projection device and a projection screen.

[0045] The communicator 220 is a component for communicating with an external device or server according to various communication protocol types. For example, the communicator may include at least one of a Wifi module, a Bluetooth module, a wired Ethernet module, and other network communication protocol chips or near field communication protocol chips, and an infrared receiver. The display device 200 can establish transmission and reception of control signals and data signals with the external control device 100 or the server 400 through the communicator 220.

[0046] The power supply 290 may be used to provide the controller 250 and its related components with the required power supply electrical signals.

[0047] The user interface 291 may be used to receive a control signal from the control device 100 (eg, an infrared remote controller, etc.).

[0048] The detector 230 is used to collect signals from the external environment or the external interaction. For example, the detector 230 includes a light receiver, a sensor for collecting the intensity of ambient light; or, the detector 230 includes an image collector, such as a camera, which can be used to collect external environment scenes, user attributes or user interaction gestures; or, the detector 230 includes a sound collector, such as a microphone, etc., for receiving external sounds.

[0049] The external device interface 240 may include, but is not limited to, any one or more of the following: a high-definition multimedia interface (HDMI), an analog or digital high-definition component input interface (component), a composite video input interface (CVBS), a USB input interface (USB), an RGB port, etc. It may also be a composite input / output interface formed by the above multiple interfaces.

[0050] The tuner-demodulator 210 receives broadcast television signals via wired or wireless reception, and demodulates audio and video signals, such as EPG data signals, from a plurality of wireless or wired broadcast television signals.

[0051] In some embodiments, the controller 250 and the tuner-demodulator 210 may be located in different separate devices, that is, the tuner-demodulator 210 may also be located in an external device of the main device where the controller 250 is located, such as an external set-top box.

[0052] The controller 250 controls the operation of the display device and responds to user operations through various software control programs stored in the memory 290. The controller 250 controls the overall operation of the display device 200. For example, in response to receiving a user command for selecting a UI object to be displayed on the display 260, the controller 250 can perform operations related to the object selected by the user command.

[0053] In some embodiments, the controller includes a central processing unit (CPU), a video processor, an audio processor, a graphics processing unit (GPU), RAM Random Access Memory (RAM), ROM (Read-Only Memory, ROM), a first interface to an nth interface for input / output, a communication bus (Bus), etc.

[0054] The user may input a user command through a graphical user interface (GUI) displayed on the display 260, and the user input interface receives the user input command through the graphical user interface (GUI). Alternatively, the user may input a user command through a specific sound or gesture, and the user input interface recognizes the sound or gesture through a sensor to receive the user input command.

[0055] "User interface" is the medium interface for interaction and information exchange between applications or operating systems and users. It realizes the conversion between the internal form of information and the form acceptable to users. The commonly used form of user interface is the Graphical User Interface (GUI), which refers to the user interface related to computer operation displayed in a graphical way. It can be an interface element such as an icon, window, control, etc. displayed on the display screen of an electronic device, where the control can include icons, buttons, menus, tabs, text boxes, dialog boxes, status bars, navigation bars, widgets, etc.

[0056] The display 260 includes a display panel and a backlight assembly configured to provide backlight.

[0057] The display panel is placed in front of the backlight assembly and includes a plurality of liquid crystal display units. The display panel drives and adjusts the state of its internal imaging structure according to the display data obtained, and displays the picture when the backlight is obtained. The display data is the data obtained from the main control system of the display.

[0058] The backlight assembly includes a diaphragm, a diffusion plate, a reflection plate, a lamp board and a back board from top to bottom, and micro diodes distributed in an array are arranged in the lamp board.

[0059] The circuit structure diagram of the backlight assembly and its control device is shown in Figure 3 As shown, the backlight assembly 40 includes a control circuit 250, a data driving circuit 20, a gate driving circuit 30, a backlight assembly 40, and a power supply circuit 280. The control circuit 250 and the data driving circuit 20 are electrically connected, the control circuit 250 and the gate driving circuit 30 are electrically connected, and the backlight assembly 40 and the data driving circuit 20, the gate driving circuit 30, and the power supply circuit 280 are electrically connected.

[0060] The backlight assembly 40 includes a display area AA where a plurality of pixel units 80 are arranged and a non-display area NA outside the display area. In the display area AA, a power line 90, a plurality of gate lines 60 and a plurality of data lines 50 are arranged. The plurality of pixel units 80 are arranged in an array in the display area AA, and each pixel unit 80 is located in an area where the gate line 60 and the data line 50 intersect.

[0061] The gate drive circuit 30 is electrically connected to the gate line 60. The gate drive circuit 30 is configured to obtain a clock signal and a trigger signal from the control circuit 250, and generate a gate drive signal based on the clock signal and the trigger signal, and transmit the gate drive signal to the corresponding pixel unit 80 through the gate line 60 to control the transistor in the pixel unit 80 to be turned on or off.

[0062] More specifically, the gate driver circuit 30 can be made into a separate gate driver integrated circuit (GDIC), and the gate driver circuit 30 can also be integrated in the backlight assembly. The way of integrating the gate driver circuit 30 in the backlight assembly is called gate-in-panel (GIP). In some cases, the GDIC can be electrically connected to the backlight assembly 40 through the COG process (Chip on Glass), and the GDIC can be electrically connected to the backlight assembly 40 through the COF process (Chipon Film). In the COF process, the component is electrically connected to the backlight assembly 40 through a flexible printed circuit (FPC).

[0063] The data driving circuit 20 is a circuit for driving the data line 50, and is configured to obtain display data from the control circuit 250, convert it into an analog data voltage (Vdata), and transmit the data analog voltage to the corresponding pixel unit 80 through the data line 50, so that the light-emitting element 813 in the pixel unit 80 emits light according to the analog data voltage. The magnitude of the analog data voltage determines the light-emitting brightness of the light-emitting element 813.

[0064] The data driving circuit 20 may include one or more source driver integrated circuits (SDICs). Each source driver integrated circuit SDIC may include a shift register, a latch circuit, a digital-to-analog converter, an output buffer, and the like.

[0065] The power circuit 280 is a circuit for providing stable electrical signals, and is configured to provide corresponding required power signals to the backlight assembly 40 , the control circuit 250 , the data driving circuit 20 , and the gate driving circuit 30 .

[0066] In one case, each pixel unit 80 includes three sub-pixel circuits 810, which are respectively used to display red light, blue light, and green light. In another case, each pixel unit 80 includes four sub-pixel circuits 810, which are respectively used to display red light, blue light, green light, and white light. This is not specifically limited here.

[0067] The luminous color of each pixel unit 80 is determined by the properties of the luminous element 813. The luminous element 813 can be any luminous device, including but not limited to OLED and micro LED.

[0068] Micro LED refers to a micro light emitting body made of inorganic semiconductor layers. Micro LEDs can generally include a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. The structure of such micro LEDs can be diverse, such as vertical, horizontal, flip-chip, etc., and is not particularly limited to a specific structure.

[0069] More specifically, if Figure 4 As shown, a sub-pixel circuit 810 includes a pixel driving circuit 814 and a light-emitting element 813. The pixel driving circuit 814 is electrically connected to the light-emitting element 813, and the pixel driving circuit 814 is configured to drive the light-emitting element 813 to emit light. The signals required by the pixel driving circuit 814 include a driving signal, a scanning signal (Scan), and an emission control signal (Emission, referred to as: EM control signal).

[0070] The driving signal may be generated by the control circuit 250 or obtained from the outside. It includes but is not limited to a start pulse signal, a clock signal, and an enable signal. The light-emitting control signal may be a global signal provided by the control circuit 250 or a signal generated by the gate drive circuit 30, which is not specifically limited here. The scanning signal is a successive displacement signal generated by the gate drive circuit 30.

[0071] If the EM control signal is a global signal generated by the control circuit 250 , the gate driving circuit 30 obtains the EM control signal from the control circuit 250 , and transmits the EM control signal to the corresponding pixel driving circuit 814 through the gate line 60 .

[0072] If both the EM control signal and the scan signal are generated by the gate driving circuit 30, the gate driving circuit 30 includes a scan signal generating circuit 301 and an EM control signal generating circuit 302. The scan signal generating circuit 301 outputs the scan signal, and the EM control signal generating circuit 302 outputs the EM control signal.

[0073] Figure 5 It is a circuit structure diagram of a traditional pixel driving circuit provided in the present application according to an exemplary embodiment, including a PWM driving circuit 803 and a PAM driving circuit 804 .

[0074] The PWM driving circuit 803 is configured to obtain the lighting duration driving data PWMD and the power signal SWEEP, and adjust the level of the first lighting control signal generated by it according to the lighting duration driving data PWMD and the power signal SWEEP, and the level of the lighting control signal is the first level or the second level.

[0075] The PAM driving circuit 804 is electrically connected to the PWM driving circuit 803 and the light emitting element LED, and is configured to obtain the first light emitting control signal and the current brightness driving data PAMD, and generate a driving signal according to the first light emitting control signal and the current brightness driving data PAMD to drive the light emitting element LED to emit light. The first light emitting control signal is used to adjust the light emitting time of the light emitting element LED, and the current brightness driving data PAMD is used to adjust the magnitude of the current passing through the light emitting element LED.

[0076] The PWM driving circuit 803 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a second capacitor C2.

[0077] The circuit structure and principle of the PWM driving circuit 803 are explained below based on the case where all transistors in the conventional pixel driving circuit are P-type transistors.

[0078] The first transistor T1 has a first terminal electrically connected to the power line 90, a control terminal electrically connected to the gate line 60, and is configured to obtain a reset signal RESET from its control terminal, obtain a reference power signal REF from its first terminal, and be turned on when the reset signal RESET is at a low level, and output the reference power signal REF from its second terminal. The reference power signal REF is a low level signal.

[0079] The first end of the sixth transistor T6 is electrically connected to the data line 50, and the control end is electrically connected to the gate line 60. It is configured to obtain a scan signal SN from its control end, obtain light-emitting duration driving data PWMD from its first end, turn on when the scan signal SN is at a low level, and output the light-emitting duration driving data PWMD from its second end.

[0080] The control end of the third transistor T3 is electrically connected to the second end of the first transistor T1, and the first end is electrically connected to the second end of the sixth transistor T6, and is configured to be short-circuited between its control end and the second end, and when its first end obtains the light-emitting duration driving data PWMD, the light-emitting duration driving data after threshold voltage compensation is determined from its control end.

[0081] The control end of the fourth transistor T4 is electrically connected to the gate line 60, the first end is electrically connected to the control end of the third transistor T3, and the second end is electrically connected to the second end of the third transistor T3. The fourth transistor T4 is configured to obtain a scan signal SN from its control end, and is turned on when the scan signal SN is at a low level, so as to short-circuit the control end and the second end of the third transistor T3.

[0082] The first end of the second capacitor C1 is electrically connected to the power line 90, and the second end is electrically connected to the control end of the third transistor T3. The second capacitor C1 is configured such that its first end obtains the second power signal SWEEP from the power line 90, and its second end is used to store the threshold voltage compensated light-emitting duration driving data generated by the control end of the third transistor T3, and is also used to follow the voltage change of its first end to adjust the voltage value of its second end.

[0083] The first end of the second transistor T2 is electrically connected to the power line 90, the second end is electrically connected to the first end of the third transistor T3, and the control end is electrically connected to the gate line 60. The second transistor T2 is configured to obtain a high-level first power signal VGH from its first end, obtain a light-emitting control signal EM from its control end, turn on when the light-emitting control signal EM is at a low level, and transmit the first power signal VGH obtained at its first end to the first end of the third transistor T3.

[0084] The second end of the fifth transistor T5 is electrically connected to the second end of the third transistor T3, the first end is electrically connected to the power line 90, and the control end is electrically connected to the gate line 60. The fifth transistor T5 is configured to obtain a low-level third power signal VGL from its first end, obtain a light-emitting control signal EM from its control end, turn on when the light-emitting control signal EM is at a low level, and transmit the third power signal VGL obtained at its first end to the second end.

[0085] The third transistor T3 is also configured to be turned on when the difference between the electric signal generated at the second end of the second capacitor C2 obtained at the control end and the potential value of the first end thereof is less than a preset threshold value when the control end and the second end thereof are disconnected, and to be turned off when the electric signal generated at the second end of the first capacitor C1 obtained at the control end and the potential value of the first end thereof are greater than or equal to the preset threshold value.

[0086] When the third transistor T3 is turned on, since the size of the third transistor T3 is larger than that of the fifth transistor T5, the potential value of its second end is determined by the electrical signal obtained at its first end, which is a low level; when the third transistor T3 is turned off, the potential value of the second end of the third transistor T3 is determined by the fifth transistor T5 electrically connected to this point, which is a high level.

[0087] The PAM driving circuit 804 adjusts the time period for generating the driving signal according to the level state provided by the second end of the sixth transistor T6, that is, when the second end of the third transistor T3 is at a high level, the driving signal is generated, and the light-emitting element LED emits light; when the second end of the third transistor T3 is at a low level, no driving signal is generated, and the light-emitting element LED does not emit light.

[0088] Because when the third transistor T3 is turned on, the second transistor T2 and the fifth transistor T5 are also turned on, the power line providing the first power signal VGH transmits the electrical signal to the power line providing the third power signal VGL through the turned-on second transistor T2, the third transistor T3 and the fifth transistor T5, and a cross-charging phenomenon occurs in the third transistor T3, consuming a large amount of power.

[0089] In order to solve the above problems, the present application provides a display device to solve the technical problem of high energy consumption when adjusting the light-emitting duration by using the conduction state of a PWM driving transistor. The technical concept of the present application is: in a light-emitting duration driving circuit in a pixel driving circuit, the first end of the first capacitor is electrically connected to the power signal transmission circuit, and the second end is electrically connected to the first end of the third transistor. The third transistor can adjust the conduction state of the third transistor according to the first power signal obtained by its control end, the control power change signal obtained by its first end, and the light-emitting duration driving data compensated by the threshold voltage of the third transistor stored in the first capacitor, so that the light-emitting control circuit controls the light-emitting element to emit light. The above circuit structure can perform threshold compensation on the light-emitting duration driving data to ensure the accuracy of the light-emitting duration of the light-emitting element, and the first capacitor is connected in series between the first transistor and the third transistor, avoiding the process of the power line transmitting a high level continuously transmitting electric energy to the power line transmitting a low level, reducing the energy consumption generated in the process of adjusting the light-emitting duration, thereby reducing the loss generated in the process of driving the light-emitting element.

[0090] The pixel driving circuit proposed in this application is explained in detail below. Figure 6The schematic diagram of the structure of a pixel driving circuit provided by the present application according to an exemplary embodiment is shown in FIG.

[0091] like Figure 6 As shown, the pixel driving circuit provided in the present application includes a light-emitting duration driving circuit 803, a light-emitting control circuit 804 and a light-emitting element LED.

[0092] The light emission duration driving circuit 803 is configured to obtain light emission duration driving data and generate a light emission duration control signal according to the light emission duration driving data.

[0093] The light emitting control circuit 804 is electrically connected to the light emitting duration driving circuit 803 , and is configured to obtain a light emitting duration control signal and light emitting brightness driving data, and generate a driving signal.

[0094] The light emitting element LED is electrically connected to the light emitting control circuit 804 and is configured to emit light according to a driving signal.

[0095] The light-emitting duration driving circuit 803 includes: a threshold compensation circuit, a power signal transmission circuit, a data input circuit and an initialization circuit.

[0096] The threshold compensation circuit includes a third transistor T3 and a first capacitor C1, the power signal transmission circuit includes a first transistor T1 and a fifth transistor T5, the data input circuit includes a sixth transistor T6 and a second capacitor C2, and the initialization circuit includes a second transistor T2.

[0097] The initialization circuit is electrically connected to the gate line 60 and the power line 90 and is configured to obtain a reset signal RESET and a first power signal VGH. Its conduction state is controlled by the reset signal RESET and the first power signal VGH is output from its output terminal when it is turned on.

[0098] The power signal transmission circuit is electrically connected to the gate line 60 and the power line 90, and is configured to obtain a light-emitting control signal EM, a first power signal VGH and a third power signal VGL. Its conduction state is controlled by the light-emitting control signal EM. When it is turned on, the first power signal VGH and the third power signal VGL are output from its output end.

[0099] The data input circuit is electrically connected to the gate line 60 and the data line 50, and is configured to obtain the light-emitting duration driving data PWMD and the scanning signal SN. Its conduction state is controlled by the scanning signal SN. When it is turned on, the light-emitting duration driving data PWMD is output from its output end.

[0100] The threshold compensation circuit is electrically connected to the initialization circuit, the power signal transmission circuit, and the data input circuit, and is configured to be initialized according to the first power signal VGH transmitted by the initialization circuit, and when the light-emitting duration driving data PWMD transmitted by the data input circuit is obtained, the light-emitting duration driving data PWMD compensated for the threshold voltage Vth of the transistor therein is generated.

[0101] The data input circuit is also electrically connected to the power line 90 and is configured to obtain and provide a second power signal SWEEP to the threshold compensation circuit. The second power signal SWEEP is a ramp signal in a display phase of each display cycle.

[0102] The threshold compensation circuit is configured to control its conduction state according to the light-emission duration driving data PWMD and the third power signal SWEEP compensated by the threshold voltage Vth generated by it. When it is turned on, the light-emission duration control signal output from its output end is the same as the level state of the first power signal VGH; when it is turned off, the light-emission duration control signal output from its output end is the same as the level state of the second power signal VGL.

[0103] In the initialization circuit, the first end of the second transistor T2 is electrically connected to the power line 90, the second end thereof is electrically connected to the first end of the third transistor T3, the control end thereof is electrically connected to the gate line 60, and is configured to obtain the first power signal VGH from its first end and the reset signal RESET from its control end, and its conduction state is controlled by the reset signal RESET.

[0104] The second transistor T2 is turned on when the reset signal RESET is at a low level, and outputs the first power signal VGH obtained at its first end from its second end; and is turned off when the reset signal RESET is at a high level, and stops outputting the first power signal VGH from its second end.

[0105] In the data input circuit, the first end of the sixth transistor T6 is electrically connected to the data line 50, the second end thereof is electrically connected to the control end of the third transistor T3, and the control end thereof is electrically connected to the gate line 60. It is configured to obtain the light-emitting duration driving data PWMD from its input end, obtain the scanning signal SN from its control end, and control its conduction state by the scanning signal SN, and output the light-emitting duration driving data PWMD from its second end when it is turned on.

[0106] The sixth transistor T6 is turned on when the scanning signal SN is at a low level, and outputs the light emission duration driving data PWMD obtained at its first end from its second end, and is turned off when the scanning signal SN is at a high level, and stops transmitting the light emission duration driving data PWMD.

[0107] The first end of the second capacitor C2 is electrically connected to the power line 90, and the second end thereof is electrically connected to the second end of the first capacitor C1. The second capacitor C2 is configured to obtain a second power signal SWEEP from its first end, and determine a control power change signal according to a change in the second power signal SWEEP and the capacitance of the second capacitor C2 and the capacitance of the first capacitor C1, wherein the control power change signal is a change in the potential value at point S.

[0108] More specifically, the change in the potential value at point S is: Wherein, ΔS is the change in potential of the second end (point S) of the second capacitor C2, ΔSWEEP is the change in potential of the second power signal SWEEP, c1 is the capacitance of the first capacitor C1, and c2 is the capacitance of the second capacitor C2.

[0109] In the power signal transmission circuit, the first end of the first transistor T1 is electrically connected to the power line 90, the control end thereof is electrically connected to the gate line 60, and the second end thereof is electrically connected to the first end of the first capacitor C1. The first transistor T1 is configured to obtain a light emitting control signal EM from its control end and a first power signal VGH from its first end, and its conduction state is controlled by the light emitting control signal EM, and the first power signal VGH is output from its second end when the first transistor T1 is turned on.

[0110] The first transistor T1 is turned on when the light emitting control signal EM is at a low level, and outputs the first power signal VGH obtained at its first end from its second end, and is turned off when the light emitting control signal EM is at a high level, and stops the transmission of the first power signal VGH.

[0111] The fifth transistor T5 has a first end electrically connected to the power line 90, a second end electrically connected to the second end of the third transistor T3, and a control end electrically connected to the gate line 60. The fifth transistor T5 is configured to obtain a third power signal VGL from its first end and a light emitting control signal EM from its control end, and its conduction state is controlled by the light emitting control signal EM.

[0112] The fifth transistor T5 is turned on when the light emitting control signal EM is at a low level, and transmits the third power signal VGL obtained from its first end to its second end, and is turned off when the light emitting control signal EM is at a high level, and stops outputting the third power signal VGL from its second end.

[0113] In the threshold compensation circuit, the first end of the first capacitor C1 is electrically connected to the second end of the first transistor T1 and the control end of the third transistor T3, and the second end of the first capacitor C1 is electrically connected to the first end of the third transistor T3 and the second end of the second transistor T2. The first capacitor C1 is configured to reset the potential value of the second end of the first capacitor C1 using the first power signal VGH transmitted by the second transistor T2 when the first transistor T1 is turned off and the second transistor T2 is turned on, and at the same time determine the potential value of the first end of the third transistor T3 to be the potential value of the first power signal VGH.

[0114] The first capacitor C1 is further configured to reset the potential value of its first end using the first power signal VGH transmitted by the first transistor T1 when the first transistor T1 is turned on and the second transistor T2 is turned off, and adjust the potential value of the control end of the third transistor T3 to the potential value of the first power signal VGH.

[0115] The first end of the third transistor T3 is electrically connected to the second end of the first capacitor C1 and the second end of the second capacitor C2, and the control end thereof is electrically connected to the second end of the sixth transistor T6. The third transistor T3 is configured such that when the first end thereof obtains the first power supply signal VGH and the control end thereof obtains the light emission duration driving data PWMD, its state is adjusted from the on state to the off state following the decrease of the potential value of the first end thereof. When the third transistor T3 is off, the potential value of the first end thereof is determined to be the difference between the light emission duration driving data PAMD and its threshold voltage.

[0116] The first capacitor C1 stores the threshold voltage of the third transistor T3 via the potential difference between its two terminals.

[0117] The third transistor T3 is also configured to adjust its conduction state according to the control power change signal and the source voltage signal provided by the first capacitor C1 when the control terminal thereof obtains the first power signal VGH and the first terminal thereof obtains the control power change signal. The source voltage signal provided by the first capacitor C1 is a signal generated by the first capacitor C1 according to the light emission duration driving data and the power change signal stored therein that are compensated for the threshold voltage of the third transistor T3.

[0118] The control power change signal is Wherein, ΔS is the change in potential of the second end (point S) of the second capacitor C2, ΔSWEEP is the change in potential of the second power signal SWEEP, c1 is the capacitance of the first capacitor C1, and c2 is the capacitance of the second capacitor C2.

[0119] Then the potential value of the source voltage signal obtained at the first end of the third transistor T3 is adjusted to At this time, the potential value of the control terminal of the third transistor T3 is VGH, and the third transistor T3 is turned on when the potential difference between the control terminal and the first terminal thereof is greater than the threshold voltage, that is, When the potential difference between the control terminal and the first terminal of the third transistor T3 is less than or equal to the threshold voltage, the third transistor T3 is turned on; when the potential difference between the control terminal and the first terminal of the third transistor T3 is less than or equal to the threshold voltage, the third transistor T3 is turned off. When , the third transistor T3 is turned off, in the above formula for determining on and off, the threshold voltage can be eliminated, thereby avoiding the influence of the threshold voltage on the on and off states of the third transistor T3.

[0120] Since the electric signal obtained by the control terminal of the third transistor T3 is at a high level, in order to keep the third transistor T3 turned on, the potential value of the first terminal of the third transistor T3 must be greater than the potential value of the control terminal. Therefore, when the third transistor T3 is turned on, the potential of its first terminal is at a high level, and since the size of the third transistor T3 is greater than that of the fifth transistor T5, when the third transistor T3 is turned on, the potential value of its second terminal is determined by the potential value of its first terminal, which is a high level; when the third transistor T3 is turned off, the potential value of its second terminal is determined by the third power supply signal VGL outputted from the second terminal of the fifth transistor, which is a low level.

[0121] In addition, the light-emitting duration driving circuit 803 also includes a third capacitor C3, a first end of the third capacitor C3 is electrically connected to the second end of the third transistor T3, and a second end of the third capacitor C3 is electrically connected to the power line 90, and is configured to store and maintain the potential value of the light-emitting duration control signal output by the second end of the third transistor T3.

[0122] The light emitting control circuit 804 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a fourth capacitor C4, a tenth transistor T10 and a driving transistor T11.

[0123] The first end of the seventh transistor T7 is electrically connected to the power line 90, and the control end is electrically connected to the gate line 60. The seventh transistor T7 is configured to obtain a light emitting control signal EM from its control end and a first power signal VGH from its first end, and its conduction state is controlled by the light emitting control signal EM.

[0124] The seventh transistor T7 is turned on when the light emitting control signal EM is at a low level, and outputs the first power signal VGH from its second end; and is turned off when the light emitting control signal EM is at a high level, and stops the transmission of the first power signal VGH.

[0125] The first end of the eighth transistor T8 is electrically connected to the second end of the seventh transistor T7, and the control end is electrically connected to the output end of the third transistor T3. The eighth transistor T8 is configured to obtain a light-emitting duration control signal from its control end and a first power supply signal VGH from its first end, and its conduction state is controlled by the light-emitting duration control signal.

[0126] The eighth transistor T8 is turned on when the light emission time control signal is at a low level, and outputs the first power signal VGH from its second end; and is turned off when the light emission time control signal is at a high level, and stops the transmission of the first power signal VGH.

[0127] The ninth transistor T9 has a first terminal electrically connected to the data line 50 and a control terminal electrically connected to the gate line 60. The ninth transistor T9 is configured to obtain a scan signal SN from its control terminal and a light emitting brightness driving data PAMD from its first terminal, and its conduction state is controlled by the scan signal SN.

[0128] The ninth transistor T9 is turned on when the scan signal SN is at a low level, and outputs the luminous brightness driving data PAMD obtained at its first end from its second end; and is turned off when the scan signal SN is at a high level, and stops the transmission of the luminous brightness driving data PAMD.

[0129] The first end of the tenth transistor T10 is electrically connected to the power line 90, and the control end is electrically connected to the gate line 60. The tenth transistor T10 is configured to obtain a fourth power signal VDD from its first end and a light emitting control signal EM from its control end, and its conduction state is controlled by the light emitting control signal EM. The fourth power signal VDD is a high level.

[0130] The tenth transistor T10 is turned on when the light emitting control signal EM is at a low level, and outputs the fourth power signal VDD from its second end; and is turned off when the light emitting control signal EM is at a high level, and stops the transmission of the fourth power signal VDD.

[0131] The first end of the driving transistor T11 is electrically connected to the second end of the tenth transistor T10, the control end is electrically connected to the second end of the eighth transistor T8 and the second end of the ninth transistor T9, and the second end is electrically connected to the positive electrode of the light-emitting element LED. It is configured to generate a driving signal to drive the light-emitting element LED to emit light when the light-emitting brightness driving data PAMD is obtained at its control end and the eighth transistor T8 is turned off; when the eighth transistor T8 is turned on, no driving signal is generated and the light-emitting element LED does not emit light.

[0132] The fourth capacitor C4 has a first terminal electrically connected to the power line 90 , a second terminal electrically connected to the control terminal of the driving transistor T11 , and is configured to store and maintain an electrical signal obtained by the control terminal of the driving transistor T11 .

[0133] It is worth noting that Figure 6 In the embodiment shown, the light-emitting control circuit 804 is only a circuit structure of PAM driving. The combination of other light-emitting control circuits 804 for compensating the threshold voltage Vth of the driving transistor T11 and the light-emitting duration driving circuit 803 provided in the present application also falls within the scope of protection of the present application and will not be described in detail here.

[0134] Figure 6 The circuit structure shown is composed of Figure 7 Drive according to the driving signal timing diagram shown.

[0135] Below Figure 6 The circuit structure shown is used to explain the circuit operation in a display cycle. A display cycle T includes a reset phase T1, a data writing phase T2 and a display phase T3 in sequence.

[0136] In the period corresponding to the reset phase T1 in the driving signal timing diagram, the reset signal RESET is at a low level, and the scanning signal SN and the light emitting control signal EM are at a high level.

[0137] Since the reset signal RESET is at a low level, the second transistor T2 is turned on, and the first power signal VGH obtained at the first end thereof is transmitted to the S point.

[0138] Since the first power signal VGH is at a low level, the signal obtained by the control end of the third transistor T3 is at a low level, the second end of the first capacitor C1 and the second end of the second capacitor C2 are reset according to the first power signal VGH and the level value of the control end of the third transistor T3 is maintained.

[0139] In the period corresponding to the data writing phase T2 in the driving signal timing diagram, the scanning signal SN is at a low level, and the reset signal RESET and the light emitting control signal EM are at a high level.

[0140] Since the reset signal RESET is at a high level, the second transistor T2 is turned off, and stops transmitting the first power signal VGH to each capacitor.

[0141] Since the scanning signal SN is at a low level, the sixth transistor T6 is turned on, and the light-emission duration driving data PWMD obtained at its first end is transmitted to the control end of the third transistor T3 and the first end of the first capacitor C1. The first power signal VGH is set to be greater than the sum of the light-emission duration driving data PWMD and the threshold voltage of the third transistor T3.

[0142] Since the first power signal VGH is greater than the sum of the light emitting duration driving data PWMD and the threshold voltage of the third transistor T3 , the third transistor T3 is turned on.

[0143] As the light-emitting duration driving data PWMD transmits an electrical signal to the first capacitor C1, the potential value of the second end of the first capacitor C1 decreases, and the potential of the first end of the third transistor T3 decreases. When the difference between the potential values ​​of the control end and the first end of the third transistor T3 is equal to the threshold voltage of the third transistor T3, the third transistor T3 is turned off. At this time, the potential value of the first end of the third transistor T3 is PWMD-Vth.

[0144] Then the potential value of the first end of the first capacitor C1 is PWMD, the potential value of the second end is PAMD+Vth, and the potential difference between the two ends is the threshold voltage of the third transistor T3.

[0145] Since the scanning signal SN is at a low level, the ninth transistor T9 is turned on, and transmits the light emitting brightness driving data PAMD obtained at its first end to the control end of the driving transistor T11.

[0146] The fourth capacitor C4 stores the light emitting brightness driving data PAMD.

[0147] Since the light emitting control signal EM is at a high level, the tenth transistor T10 is turned off and does not transmit the fourth power signal VDD, and the driving transistor T11 does not generate a driving signal, and the light emitting element LED does not emit light.

[0148] In the period corresponding to the light emitting stage T3 in the driving signal timing diagram, the light emitting control signal EM is at a low level, the scanning signal SN and the reset signal RESET are at high levels, and the third power signal SWEEP is a ramp signal adjusted from a high level to a low level.

[0149] Since the scanning signal SN is at a high level, the sixth transistor T6 is turned off, and stops transmitting the light emitting duration driving data PWMD to the control terminal of the third transistor T3.

[0150] Since the light emitting control signal EM is at a low level, the first transistor T1 is turned on, and the first power signal VGH obtained at the first end thereof is transmitted to the first end of the third transistor T3 and the first end of the first capacitor C1.

[0151] Since the light emitting control signal EM is at a low level, the fifth transistor T5 is turned on, and the third power signal VGL obtained at the first end thereof is transmitted to the second end of the third transistor T3.

[0152] The first capacitor C1 adjusts the potential value of its second end to be

[0153] The second capacitor C2 adjusts the potential value of its second end to be The potential value of this point is also the potential value of the first end of the third transistor T3.

[0154] Since the potential difference between the control terminal and the first terminal of the third transistor T3 is greater than the threshold voltage, the third transistor T3 is turned on. Since the size of the third transistor T3 is larger than the fifth transistor T5, the potential value of the second terminal of the third transistor T3 is the same as the potential of the first power signal VGH.

[0155] As the potential value of the third power signal SWEEP decreases, the potential value of the control terminal of the third transistor T3 decreases, and the potential value is

[0156] When the difference between the potential values ​​of the control terminal and the first terminal of the third transistor T3 is less than or equal to the threshold voltage, the third transistor T3 is turned off, and the potential value of the second terminal thereof is adjusted to the same potential value as the second power signal VGL.

[0157] Since the light emitting control signal EM is at a low level, the seventh transistor T7 is turned on, and the first power signal VGH obtained at the first end thereof is transmitted to the first end of the eighth transistor T8.

[0158] Since the light emitting control signal EM is at a low level, the tenth transistor T10 is turned on, and the fourth power signal VDD obtained at the first end thereof is transmitted to the first end of the driving transistor T11 .

[0159] When the third transistor T3 is turned on and the light emission duration control signal outputted from its second terminal is at a high level, the eighth transistor T8 is turned off and stops transmitting the first power supply signal VGH obtained from its first terminal to the control terminal of the driving transistor T11.

[0160] The potential difference between the control terminal and the first terminal of the driving transistor T11 is greater than the threshold voltage of the driving transistor T11, and the driving transistor T11 is turned on to generate a driving signal according to the light emitting brightness driving data PAMD to drive the light emitting element LED to emit light.

[0161] When the third transistor T3 is turned off and the light emission duration control signal outputted from the second end thereof is at a low level, the eighth transistor T8 is turned on to transmit the first power supply signal VGH obtained from the first end thereof to the control end of the driving transistor T11.

[0162] The luminous brightness driving data PAMD stored in the fourth capacitor C4 is covered by the first power signal VGH. The potential difference between the control end and the first end of the driving transistor T11 is less than the threshold voltage, the driving transistor T11 is turned off, the generation of the driving signal stops, and the light-emitting element LED stops emitting light.

[0163] Figure 8 Schematic diagram of the structure of an N-type pixel driving circuit provided by the present application according to an exemplary embodiment, in which each transistor in the pixel driving circuit is an N-type transistor. Figure 6 The circuit structure shown is Figure 8 The circuit structure shown is briefly explained.

[0164] Compared to Figure 6 The circuit structure shown is different in that:

[0165] Each transistor is turned on when a high level is obtained and turned off when a low level is obtained;

[0166] The first power signal VGL obtained from the power line 90 by the first end of the first transistor T1, the first end of the second transistor T2, and the first end of the seventh transistor T7 is a low level signal, the third power signal VGH obtained from the power line 90 by the first end of the fifth transistor T5 is a high level signal, the second end of the driving transistor T11 is electrically connected to the cathode of the light emitting element LED, the fourth power signal VSS obtained from the power line 90 by the first end of the fourth capacitor C4 and the first end of the tenth transistor T10 is a low level signal, and the second power signal SWEEP obtained by the first end of the second capacitor C2 is a ramp signal adjusted from a low level to a high level in the display stage of the display cycle, and is a low level signal in other stages.

[0167] Other circuit connections and Figure 6 The circuit structure shown is the same and will not be repeated here.

[0168] Fig. 9 The circuit structure shown is composed of Figure 8 Drive according to the driving signal timing diagram shown.

[0169] In the period corresponding to the reset phase T1 in the driving signal timing diagram, the reset signal RESET is at a high level, and the scanning signal SN and the light emitting control signal EM are at a low level.

[0170] The second transistor T2 is turned on according to the reset signal RESET, and transmits the first power signal VGL obtained at its first end to the second end of the first capacitor C1, the second end of the second capacitor C2 and the first end of the third transistor T3 to perform a reset operation.

[0171] In the period corresponding to the data writing phase T2 in the driving signal timing diagram, the scanning signal SN is at a high level, and the reset signal RESET and the light emitting control signal EM are at a low level.

[0172] The sixth transistor T6 is turned on according to the scanning signal SN, and transmits the light-emitting duration driving data PWMD to the control end of the third transistor T3. As the data is transmitted, the third transistor T3 gradually adjusts from the on state to the off state, and obtains the light-emitting duration driving data compensated by the threshold voltage from its first end.

[0173] The ninth transistor T9 is turned on according to the scan signal SN, and transmits the light emitting brightness driving data PAMD to the control end of the driving transistor T11, and stores the data at the first end of the fourth capacitor C4.

[0174] In the period corresponding to the light emitting stage T3 in the driving signal timing diagram, the light emitting control signal EM is at a high level, the scanning signal SN and the reset signal RESET are at a low level, and the third power signal SWEEP is a ramp signal adjusted from a low level to a high level.

[0175] Since the light emitting control signal EM is at a high level, the first transistor T1 , the fifth transistor T5 , the seventh transistor T7 and the tenth transistor T10 are turned on, and transmit the electrical signals obtained at the first ends thereof to the second ends.

[0176] The potential value of the control terminal of the third transistor T3 follows the change of the potential value obtained by the first terminal thereof, the change of the potential value of the second power signal SWEEP, the capacitance of the first capacitor C1 and the capacitance of the second capacitor C2, and is: When the potential difference between the control terminal and the first terminal is greater than a preset threshold, the third transistor T3 is turned on to output the low-level first power signal VGL obtained at the first terminal.

[0177] The eighth transistor T8 is turned off according to the low-level first power signal VGL, and does not transmit the first power signal VGL obtained at its first end to the second end. The driving transistor T11 can generate a driving signal according to the luminous brightness driving data PAMD obtained at its control end and the fourth power signal VSS obtained at the first end to drive the light-emitting element LED to emit light.

[0178] As the potential value of the control terminal of the third transistor T3 changes, the third transistor T3 is turned off, and the potential value outputted by the second terminal thereof is the potential value of the second power signal VGH.

[0179] The eighth transistor T8 is turned on according to the high-level second power signal VGL, and transmits the first power signal VGL obtained at its first end to the second end, and the driving transistor T11 is turned off, the generation of the driving signal is stopped, and the light-emitting element LED stops emitting light.

[0180] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0181] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A display device, comprising: A backlight assembly, on which a power line, a plurality of gate lines, a plurality of data lines and a plurality of sub-pixel circuits are arranged; Each of the sub-pixel circuits includes a pixel driving circuit and a light-emitting element; Characterized in that the pixel driving circuit comprises: a light-emitting duration driving circuit and a light-emitting control circuit, and the light-emitting duration driving circuit comprises: a first capacitor, a third transistor, and a power signal transmission circuit; The power signal transmission circuit is electrically connected to the power line and the gate line, and is configured to obtain a first power signal and a light-emitting control signal, and its conduction state is controlled by the light-emitting control signal, outputs the first power signal when it is turned on, and stops outputting the first power signal when it is turned off; The first end of the first capacitor is electrically connected to the power signal transmission circuit and the control end of the third transistor, and the second end of the first capacitor is electrically connected to the first end of the third transistor, and is configured to store the light emission duration driving data compensated by the threshold voltage of the third transistor when the power signal transmission circuit is turned off and the first end of the first capacitor obtains the light emission duration driving data; The first end of the third transistor is electrically connected to the power line, and the control end thereof is electrically connected to the power signal transmission circuit, and is configured to obtain a control power change signal and the first power signal, and adjust the conduction state of the third transistor according to the control power change signal, the first power signal, the threshold voltage of the third transistor and the compensated light emission duration driving data thereof; The light emitting control circuit is electrically connected to the second end of the third transistor, and is configured to control the light emitting element to emit light when the third transistor is turned on during the display phase of each display cycle; and to control the light emitting element to stop emitting light during other time periods of the display cycle.

2. The display device according to claim 1, characterized in that The first capacitor is also configured to obtain the control power change signal from its second end, and output a source voltage signal from its first end after adjusting the light emission duration driving data of the threshold voltage compensation of the third transistor stored therein using the control power change signal.

3. The display device according to claim 2, characterized in that The third transistor is configured to obtain the first power supply signal from its control terminal and the source voltage signal from its first terminal, to be turned on when the source voltage signal and the first power supply signal meet the turn-on condition of the third transistor, and to be turned off when the source voltage signal and the first power supply signal do not meet the turn-on condition of the third transistor.

4. The display device according to claim 2, characterized in that: The light-emitting duration driving circuit further includes a second capacitor; The first end of the second capacitor is electrically connected to the power line, and the second end of the second capacitor is electrically connected to the second end of the first capacitor. The second capacitor is configured to obtain a second power signal from its first end, and determine the control power change signal based on the change in the second power signal and the capacitance of the second capacitor and the capacitance of the first capacitor.

5. The display device according to claim 1, characterized in that The power signal transmission circuit includes a first transistor; The first end of the first transistor is electrically connected to the power line, the control end is electrically connected to the gate line, and the second end is electrically connected to the first end of the first capacitor. The first transistor is configured to obtain a light-emitting control signal from its control end and a first power signal from its first end, and to control its conduction state by the light-emitting control signal, and to output the first power signal from its second end when it is turned on.

6. The display device according to claim 1 or 5, characterized in that: The power signal transmission circuit further includes a fifth transistor; The first end of the fifth transistor is electrically connected to the power line, the control end is electrically connected to the gate line, and the second end is electrically connected to the second end of the third transistor. The fifth transistor is configured to obtain the light-emitting control signal from its control end and the third power signal from its first end, and its conduction state is controlled by the light-emitting control signal, and the third power signal is output from its second end when it is turned on.

7. The display device according to claim 1, characterized in that The light emission duration driving circuit further includes a sixth transistor; The first end of the sixth transistor is electrically connected to the data line, the second end thereof is electrically connected to the control end of the third transistor, and the control end thereof is electrically connected to the gate line. The sixth transistor is configured to obtain the light emission duration driving data from its input end and obtain a scanning signal from its control end, and its conduction state is controlled by the scanning signal. When the sixth transistor is turned on, the light emission duration driving data is output from its second end.

8. The display device according to claim 1, characterized in that: The light emission duration driving circuit further includes a second transistor; The first end of the second transistor is electrically connected to the power line, the control end is electrically connected to the gate line, and the second end is electrically connected to the second end of the first capacitor. The second transistor is configured to obtain a reset signal from its control end and a first power signal from its first end, and its conduction state is controlled by the reset signal. When it is turned on, the first power signal is output from its second end.

9. The display device according to claim 1, characterized in that: The display cycle includes a reset phase, a data writing phase and a display phase in sequence; In the reset stage, the reset signal is at a first level, and the scan signal and the light-emitting control signal are at a second level; The second transistor is turned on according to the reset signal, and transmits the first power signal obtained at the first end thereof to the second end of the first capacitor; The first capacitor adjusts the potential of the second end thereof according to the first power signal.

10. The display device according to claim 9, characterized in that: In the data writing stage, the scanning signal is at a first level, and the reset signal and the light emitting control signal are at a second level; The sixth transistor is turned on according to the scanning signal, and transmits the light emitting duration driving data obtained at the first end thereof to the first end of the first capacitor; The first capacitor adjusts the potential of the first end thereof according to the light emitting duration driving data; The third transistor is turned on when the difference between the potential value of the first end and the potential value of the control end meets the turn-on condition of the third transistor, and the first capacitor adjusts the potential value of the second end through the turned-on third transistor until the third transistor is turned off; When the third transistor is turned off, the first capacitor determines that the potential value of the second end thereof is the light emitting duration driving data compensated by the threshold voltage of the third transistor.

11. The display device according to claim 10, characterized in that: In the display stage, the light emitting control signal is at a first level, the reset signal and the scanning signal are at a second level, and the second power supply signal is a ramp signal adjusted from the second level to the first level; The first transistor is turned on according to the light emitting control signal, and transmits the first power signal obtained at its first end to the control end of the third transistor; The fifth transistor is turned on according to the light emitting control signal, and transmits the third power supply signal obtained at the first end thereof to the second end of the third transistor; The second capacitor adjusts the potential value of the first end of the third transistor according to the change amount of the second power signal obtained at the first end thereof, the capacitance of the second capacitor, the capacitance of the first capacitor, and the light emission duration driving data compensated by the threshold voltage of the third transistor; The third transistor is turned on when the potential difference between the control terminal and the first terminal satisfies the corresponding turn-on condition, and is turned off when the potential difference between the control terminal and the first terminal does not satisfy the turn-on condition of the third transistor; The light emission control circuit controls the light emitting element to emit light when the third transistor is turned on, and controls the light emitting element to stop emitting light when the third transistor is turned off.

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