Method for forming reduced size features

Abstract

The invention relates to a method for forming reduced-size features. A method for forming features on a wafer includes forming a first opening in a first layer over a carbon-containing layer; and removing the material of the carbon-containing layer through the first opening to form a cavity. The method includes forming a spacer material on sidewalls of the carbon-containing layer in the cavity using a material forming process, wherein the spacer material is inhibited from being formed on a bottom surface portion of the cavity during the material forming process. The spacer material formed forms a spacer defining a second opening, the second opening having a lateral dimension in a first lateral direction that is smaller than the first opening.

Description

Technical Field

[0001] The present invention generally relates to a method for forming features of reduced size by forming a spacer material on the sidewalls of a carbon-containing layer. Background Art

[0002] Semiconductor device manufacturing involves forming openings and structures on a wafer using a photolithography process. In the photolithography process, a patterned photoresist layer is used to define the edges of the opening or structure. The critical dimension of a semiconductor manufacturing process is the smallest dimension that can be defined photolithographically given the capabilities of the processing equipment for the process. Over the years, semiconductor processing technology has improved and the achievable critical dimensions have decreased. Currently, some advanced processes have critical dimensions of less than 5nm. Summary of the invention

[0003] Features specifically shown or described with respect to one embodiment set forth herein may be implemented in other embodiments set forth herein.

[0004] In one embodiment, a method includes: forming a carbon-containing layer over a substrate including a semiconductor material; forming a first layer over the carbon-containing layer; and forming a first opening in the first layer. The first opening has a first lateral dimension in a first lateral direction. The method includes: removing material of the carbon-containing layer through the first opening to form a cavity in the carbon-containing layer; and forming a sidewall spacer structure. The forming of the sidewall spacer structure includes performing a material forming process that forms a sidewall spacer material on a sidewall of the carbon-containing layer of the cavity. The sidewall spacer material is inhibited from forming on a bottom surface portion of the cavity during the material forming process. The sidewall spacer structure defines a second opening that exposes a bottom surface portion. The second opening has a second lateral dimension in the first lateral direction that is less than the first lateral dimension.

[0005] Illustratively, the carbon-containing layer includes amorphous carbon.

[0006] Illustratively, the sidewall spacer material includes at least one of the group consisting of: TiN, TiO2, HfO2, Ru, Pt, Al2O3.

[0007] Illustratively, the material formation process is characterized as an atomic layer deposition process.

[0008] Illustratively, the method further comprises:

[0009] After performing the material forming process, a second material is formed in the second opening.

[0010] Illustratively, the second material is characterized as a conductive material.

[0011] Illustratively, the second material is characterized as a semiconductor material.

[0012] Illustratively, the second material is characterized as a transistor control electrode material.

[0013] Illustratively, the bottom surface portion is a portion of the carbon-containing layer that is treated with hydrogen after the forming of the cavity.

[0014] Illustratively, after the forming of the sidewall spacer structure, at least a portion of the bottom surface portion is etched through the second opening to expose the substrate.

[0015] Illustratively, the bottom surface portion is made of a material different from that of the carbon-containing layer.

[0016] Illustratively, the bottom surface portion is treated with an inhibitor during the material formation process to inhibit formation of the spacer material.

[0017] Illustratively, the inhibitor includes a short-chain aminosilane that inhibits formation of the spacer material during the material formation process.

[0018] Illustratively, the method further includes forming at least one fin including a semiconductor material using the sidewall spacer structure.

[0019] Illustratively, at least a portion of the sidewall spacer structure formed in the cavity serves as a mask to define a fin of the at least one fin.

[0020] Illustratively, the method further comprises:

[0021] After performing the material forming process, removing at least a portion of the carbon-containing layer laterally adjacent to the sidewall spacer structure;

[0022] forming sidewall spacers of a second sidewall spacer material on the sidewalls of the sidewall spacer structure;

[0023] After forming the sidewall spacers of the second sidewall spacer material, removing the sidewall spacer structure;

[0024] The at least one fin is defined using the sidewall spacers of the second sidewall spacer material as a mask.

[0025] Illustratively, the method further includes implanting a dopant into the substrate through the second opening, wherein the sidewall spacer structure inhibits the dopant from being implanted into the substrate.

[0026] Illustratively, the method further comprises:

[0027] After performing the material forming process, the carbon-containing layer is removed.

[0028] In another embodiment, a method includes: forming a carbon-containing layer over a wafer substrate including a semiconductor material; forming a first layer over the carbon-containing layer; and forming a first opening in the first layer using a photolithography process. The first opening has a first lateral dimension in a first lateral direction. The method includes: removing material of the carbon-containing layer through the first opening to form a cavity in the carbon-containing layer; and forming a sidewall spacer structure using a material forming process, the material forming process forming a sidewall spacer material on a sidewall of the cavity of the carbon-containing layer. The sidewall spacer material is inhibited from forming on a bottom surface portion of the cavity. The sidewall spacer structure defines a second opening that exposes the bottom surface portion, the second opening having a second lateral dimension in the first lateral direction that is less than the first lateral dimension. The method includes singulating the wafer into a plurality of integrated circuits after forming the sidewall spacer structure.

[0029] Illustratively, the method further comprises:

[0030] After performing the material forming process but before the singulation, at least a portion of the carbon-containing layer and the formed sidewall spacer material are removed. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0032] Figure 1-5 A partial cross-sectional side view of a semiconductor wafer during a stage in its fabrication is illustrated in accordance with one embodiment of the present invention.

[0033] Figure 6-8 A partial cross-sectional side view of a semiconductor wafer during a stage in its fabrication is illustrated in accordance with another embodiment of the present invention.

[0034] Figure 9-12 A partial cross-sectional side view of a semiconductor wafer during a stage in its fabrication is illustrated in accordance with another embodiment of the present invention.

[0035] Fig.13 A partial cross-sectional side view of a semiconductor wafer during a stage in its fabrication is illustrated in accordance with another embodiment of the present invention.

[0036] Fig.14 A partial cross-sectional side view of a semiconductor wafer during a stage in its fabrication is illustrated in accordance with another embodiment of the present invention.

[0037] Unless otherwise indicated, the same reference numerals are used in different drawings to indicate the same items. The drawings are not necessarily drawn to scale. DETAILED DESCRIPTION

[0038] The following is a detailed description of at least one mode for carrying out the invention. This description is intended to illustrate the invention and should not be considered limiting.

[0039] As disclosed herein, a method for forming a feature on a wafer includes: forming a first opening in a first layer above a carbon-containing layer; and removing material of the carbon-containing layer through the first opening to form a cavity. The method includes forming a spacer material on a sidewall of the carbon-containing layer in the cavity using a material forming process, wherein the spacer material is inhibited from forming on a bottom surface portion of the cavity during the material forming process. The formed spacer material forms a spacer defining a second opening, the second opening having a smaller lateral dimension in a first lateral direction than the first opening.

[0040] In some embodiments, providing a method of forming a spacer material on the sidewalls of a cavity in a carbon-containing layer but inhibiting formation on a bottom surface portion of the cavity can provide a method of forming an opening that is smaller than a lithographically defined opening used to form the cavity. Thus, in some embodiments, the method can be used to form features that are smaller than a critical dimension of a semiconductor process.

[0041] Figure 1 1 is a partial cross-sectional side view of a wafer 101 during its manufacturing stage according to one embodiment of the present invention. The wafer 101 includes a substrate 103 made of one or more semiconductor materials, such as single crystal silicon, silicon germanium, silicon carbide, gallium nitride, gallium arsenide or other III-V semiconductor materials. In one embodiment, the substrate 103 has a bulk-semiconductor configuration. In other embodiments, the substrate 103 may have an SOI (semiconductor on insulator) configuration. In some embodiments, the substrate 103 is formed by a single portion of a semiconductor material grown integrally. In other embodiments, portions of the substrate 103 may include epitaxially grown semiconductor materials. The substrate 103 may also include a dielectric structure (e.g., a shallow trench isolation structure, a buried oxide layer (not shown)).

[0042] The substrate 103 includes semiconductor regions (eg, transistors, diodes) for a plurality of semiconductor devices (eg, transistors, diodes) of the integrated circuit. Figure 1 In some embodiments, the substrate 103 includes semiconductor regions for transistors (e.g., FETs (field effect transistors), bipolar transistors, JFETs (junction field effect transistors), and FinFETs (not shown), stacked transistors, nanotubes, and multi-sheet transistors), as well as semiconductor regions and protection regions for other types of semiconductor devices (e.g., diodes (not shown)).

[0043] An amorphous carbon layer 105 is formed over substrate 103. In one embodiment, layer 105 has a thickness of 500 angstroms, but in other embodiments layer 105 may have other thicknesses. In some embodiments, layer 105 is used as an anti-reflective coating to suppress UV light reflection during a photolithography process. In other embodiments, other types of layers with carbon may be used, such as microcrystalline carbon or diamond-like carbon. In some embodiments, in addition to amorphous carbon, layer 105 may also contain a large amount of other materials, such as hydrogen, nitrogen, fluorine, oxygen, silicon, chlorine, boron, aluminum, germanium, sulfur.

[0044] A silicon oxide layer 107 is formed over layer 105. In one embodiment, layer 107 is formed by a low temperature TEOS process and has a thickness of 200 angstroms, but may be made by other processes and have other thicknesses in other embodiments. A photoresist layer 108 is formed over layer 107. In some embodiments, silicon dioxide layer 107 is used to properly adhere the photoresist to wafer 101 and for optical coupling to minimize reflections. In other words, the combination of the optical properties of carbon layer 105 and the optical and physical properties of capping oxide layer 107 allows the anti-reflective properties of the stack to be maximized for photoresist exposure.

[0045] Layer 108 is patterned by a photolithography process. In one embodiment of the photolithography process, a selective portion of layer 108 is exposed to UV light through an opening (e.g., opening 111) in mask 109. The UV light changes the properties of the exposed portion (e.g., portion 119) of the photoresist layer 108. The different properties of the exposed portion (e.g., portion 119) and the unexposed portion of layer 108 allow the exposed portion to be selectively removed after UV exposure to form a patterned layer. In other embodiments, other types of photolithography processes may be used. For example, the unexposed portion of the photoresist may be removed, wherein the exposed portion is retained.

[0046] like Figure 1 As shown, opening 111 in mask 109 has a lateral width 113. In some embodiments, lateral width 113 is a critical dimension of a semiconductor process used to process wafer 101.

[0047] Figure 2 is after the portion 119 has been removed from the photoresist layer 108 (see Figure 1) and a partial cross-sectional side view of wafer 101 after anisotropic etching has been used to remove a portion of layer 107 exposed by removing the portion of layer 108. Thereafter, wafer 101 is temporally isotropically etched to form cavity 201 in layer 105. In the embodiment shown, a portion of layer 105 forms a bottom portion of cavity 201. In one embodiment, layer 105 may first be etched using a timed anisotropic etch to define vertical sidewalls that conform to the sidewalls of layer 108 and layer 107. The anisotropic etch is followed by a temporally isotropic etch that widens cavity 201 beyond lateral width 113 to undercut layer 107. In one embodiment, the isotropic etch is performed using plasma etching. In some embodiments, resist layer 108 may be removed after layer 107 has been etched.

[0048] After forming cavity 201, bottom portion 203 of layer 105 is exposed to a directional anisotropic hydrogenation plasma treatment that coats the surface of portion 203 with hydrogen. Because the sidewalls of cavity 201 are recessed due to the isotropic etch, the sidewalls are not exposed to hydrogen from the directional plasma treatment.

[0049] Figure 3 2 is a partial cross-sectional side view of wafer 101 after forming sidewall spacers 301 on the sidewalls of cavity 201. In one embodiment, the spacer material is formed by an atomic layer deposition (ALD) process. In one embodiment, spacer 301 is formed of a spacer material (e.g., TiN, TiO2, HfO2, Ru, Pt, Al2O3) formed on the carbon of layer 105 on the sidewalls of cavity 201. Adhesion of the spacer material to hydrogen treated portion 203 is inhibited during the ALD process. Therefore, the spacer material should not be formed on a portion of portion 203. However, in some embodiments, wafer 101 can be anisotropically etched for a short time using an etch chemistry that is selective with respect to the spacer material to remove any small amount of spacer material that may adhere to region 203 outside of sidewall spacers 301.

[0050] like Figure 3 As shown, spacer 301 defines opening 303. The lateral width of opening 303 is narrower than lateral width 113. The lateral width of opening 303 can be controlled by the number of atomic layers of spacer material deposited when forming spacer 301. One advantage of using an ALD spacer formation process is that the spacer width can be controlled using a relatively precise ALD process.

[0051] Figure 41 is a partial cross-sectional side view of wafer 101 after a portion of portion 203 has been anisotropically etched through opening 203 to expose surface 401 of substrate 103. Region 203 is etched using an etch chemistry that is selective with respect to amorphous carbon and with respect to the spacer material of spacer 301 and the silicon oxide of layer 107. Figure 4 As shown, the exposed surface 401 has the same lateral width as the opening 303 .

[0052] Figure 5 4 is a partial cross-sectional side view of wafer 101 after structure 501 has been formed on surface 401 of substrate 103. In one embodiment, structure 501 is a conductive structure (e.g., doped polysilicon, metal) that acts as a contact or terminal of a transistor (e.g., a gate of a FET). The FET may be a planar FET or a finFET, where Figure 5 The view of is a cross-sectional view transversely along the length of the fin. However, in other embodiments, structure 501 may be made of a dielectric or may be made of a single crystalline semiconductor material epitaxially grown from surface 401 .

[0053] In one embodiment, Figure 4 After the stage of , a layer of structural material (e.g., metal, polysilicon, dielectric) filling the opening 303 is formed on the wafer 101. In other embodiments, the semiconductor material can be epitaxially grown in the opening 303. The wafer 101 is then flattened to the top of the spacer 301. The remaining portions of the layer 105 and the sidewall spacer 301 are removed, leaving the structure 501. In an embodiment where the structure 501 is the gate of a FET, the surface 401 can be oxidized to form a gate dielectric before forming the material layer of the structure 501. Moreover, in other embodiments, dopants can be selectively implanted into areas of the wafer 101 through the opening 303, wherein the layer 107, the layer 105 and the spacer 301 act as an implantation mask to prevent other areas from being implanted with dopants.

[0054] exist Figure 5 After the stage of wafer 101, other structures including other conductive structures, doped regions, and dielectrics may be formed on wafer 101. Thereafter, an interconnect layer is formed over wafer 101, wherein the interconnect layer includes one or more metal interconnect layers having conductive interconnects, conductive vias, and intermediate dielectric materials. External die terminals (e.g., bonding pads, pillars, supports) are then formed on wafer 101. Wafer 101 is then singulated into a plurality of integrated circuits. The integrated circuits are then packaged to form packaged integrated circuits implemented in electronic systems (e.g., TVs, computers, cell phones, appliances, automobiles, manufacturing equipment, or communications equipment).

[0055] Figure 6-8is a partial cross-sectional side view of a wafer during various fabrication stages according to another embodiment. Figure 6 In one embodiment, wafer 601 is similar to wafer 101, wherein substrate 603, amorphous carbon layer 605, silicon dioxide layer 607, and photoresist layer 608 are similar to substrate 103, layer 105, layer 107, and layer 108, respectively. Wafer 601 differs from wafer 101 in that silicon dioxide layer 604 is located between layer 605 and substrate 603, which acts as an etch stop for subsequent etching of amorphous carbon layer 605.

[0056] like Figure 6 As shown, a photolithographically defined opening 611 having a lateral width 613 is formed in layers 608, 607, and 605, the opening 611 exposing silicon dioxide layer 604. In the embodiment shown, amorphous carbon layer 605 is anisotropically etched to form a cavity 614 in layer 605 such that the sidewalls of the cavity are aligned with the sidewalls of layers 607 and 608. In some embodiments, resist layer 608 may be removed after layer 607 is etched.

[0057] After the opening 611 is formed, the exposed portion of the layer 604 is treated with an inhibitor such as a short-chain aminosilane (e.g., bis(N,N-dimethylamino)dimethylsilane (DMADMS) and (N,N-dimethylamino)trimethylsilane (DMATMS)), which is used to inhibit the subsequent formation of a spacer material (e.g., Ru, Pt, Al2O3, HfO2) on the layer 604 by an ALD process. The inhibitor is adsorbed on the SiO2 surface of the layer 604, but not on the amorphous carbon of the layer 605, so that the treated SiO2 surface is selectively inactivated for the subsequent ALD process.

[0058] Figure 7 605. is a partial cross-sectional side view of wafer 601 after forming sidewall spacers 711 on the sidewalls of layer 605. In one embodiment, the spacer material is formed by an atomic layer deposition process. In one embodiment, spacers 711 are formed of a spacer material (e.g., HfO2, Ru, Pt, Al2O3) that is formed on the carbon of the carbon sidewalls of cavity 614 and is not formed on a portion of layer 604 due to previous processing of inhibiting precursors. In some embodiments, wafer 601 may be anisotropically etched for a short time using an etch chemistry that is selective with respect to the spacer material to remove any small amount of spacer material of layer 604 that may adhere to the outside of sidewall spacers 301.

[0059] The spacer material is not located over a portion of layer 604 to define opening 703. Figure 7As shown, the lateral width of opening 703 is narrower than lateral width 613. The lateral width of opening 703 can be controlled by the number of atomic layers of spacer material deposited. One advantage of using an ALD spacer formation process to form features having a lateral width less than a critical dimension is that the ALD process is relatively precise, thereby allowing precise spacer width control.

[0060] Figure 8 Wafer 601 is shown after an opening is formed in layer 604 and a conductive dopant (e.g., phosphorus, arsenic, boron) is implanted through opening 703 to form doped region 805, wherein layers 605, 607, and 608 and spacer 703 are used as implantation masks. Region 805 can be used as an end of a semiconductor device, such as a base region or a diode end of a bipolar transistor. Region 805 can also be used as a protection zone for noise isolation in substrate 603. In other embodiments, areas of region 805 can be etched to form trenches, wherein the trenches will be filled with dielectrics. In other embodiments, region 805 can be etched and filled with a conductive material (e.g., metal) to form embedded vias or metal trenches in the substrate. In other embodiments, silicide can be formed on region 805 after implantation, and a conductive contact can be formed in opening 703. In still other embodiments, as Figure 1-5 As in the embodiment of the present invention, a gate structure may be formed in the opening 703. The wafer 601 will be further processed to form a plurality of integrated circuits as described above.

[0061] Figure 9-12 is a partial cross-sectional side view of wafer 901 during various stages of its fabrication for fabricating semiconductor fins. Wafer 901 is similar to wafer 601, wherein substrate 903, layer 904, layer 905, layer 907, and layer 908 are similar to substrate 603, layer 604, layer 605, layer 607, and layer 608. Fig. 9 Two groove openings 911 and 913 are shown. Figure 7 The spacers 711 are formed on the sidewalls of the amorphous carbon layer 905, wherein the spacer portions 915, 916, 917 and 918 are formed on the sidewalls of the amorphous carbon layer 905. Fig. 9 In one embodiment, the spacers in openings 911 and 913 are formed by Figure 6-8 The process of the embodiment can be used to form the Figure 1-5 The embodiment of the present invention may be formed by other processes.

[0062] exist Fig.10 In the embodiment, layers 905, 907 and 908 are removed, thereby leaving portions 915-918. In one embodiment, the lateral width of portions 915-918 is in the range of 10-40% of the width of the critical dimension, but can be other percentages of the critical dimension in other embodiments.

[0063] Fig.11 Wafer 901 is shown after forming sidewall spacer portions 1101 and 1102 on portion 915, forming sidewall spacer portions 1103 and 1104 on portion 916, forming sidewall spacer portions 1105 and 1106 on portion 917, and forming sidewall spacer portions 1107 and 1108 on portion 918. In one embodiment, portions 1011-1018 are formed by forming an oxide or nitride layer over wafer 901 and anisotropically etching the layer to form spacer portions. Portions 1101-1108 and portions 915-918 are physically separated from each other at the ends of trenches (not shown) by patterned etching.

[0064] Fig.12 Wafer 901 is shown after portions 915-918 are removed and portions 1101-1108 are used as masks to form semiconductor fins (e.g., 1201 and 1203) by anisotropically etching substrate 903 using a timed etch. In one embodiment, the lateral thickness of the fins can be in the range of 2-20% of the critical dimension, depending on the thickness of the layers used to form portions 1101-1108, but in other embodiments, the fins can have other percentages of the critical dimension.

[0065] exist Fig.12 After the stage of , portions 1101-1108 are removed, as well as portions of layer 904 located on top of the fins (e.g., 1201 and 1203). A gate structure (not shown) is formed over the fins (1201 and 1203), and source and drain regions are then formed by implanting dopants in the fins on opposite sides of the gate. Contacts (not shown) are then formed to contact the source and drain regions and the gate structure of the finFET.

[0066] Fig.13 A partial cross-sectional side view of a wafer 901 is shown according to an alternative embodiment. Fig.13 The stages of the example follow Fig.10 The stage where no Fig.11 In practice, portions 915-918 are used as an etching mask to form semiconductor fins (1305) by etching substrate 903. The lateral width of the fins depends on the lateral width of portions 915-918. Fins (1305) are used in FinFETs (not shown) that are subsequently formed.

[0067] Fig.14 FIG. 1 is a partial cross-sectional side view of a wafer 1401 according to another embodiment of the present invention. In the embodiment shown, sidewall portions 1415-1418 are arranged in a manner similar to Fig. 9The side wall portions 915-918 are formed in a similar manner, but the side wall portions can be formed by, for example Figure 1-5 The embodiment of the present invention may be formed by other processes.

[0068] Chip 1401 and Fig. 9 The difference of the wafer 901 is that the portions 1415-1418 are used as masks to pattern the fins (1405) of semiconductor material in the substrate of the multi-layer transistor. The patterned semiconductor material includes alternating silicon germanium layers 1422 and 1424 located between silicon layers 1421, 1423 and 1425. In the embodiment shown, the fins (1405) are located on the oxide layer 1404 of the substrate, which is located on the base layer 1403. However, other embodiments may not include layer 1404.

[0069] exist Fig.14 After the stage, portions 1415-1418 and portions of layer 1407 on the fins are removed. Portions of SiGe layers 1424 and 1422 in each fin (1405) are removed to form openings (not shown) between layers 1421, 1423, and 1425. Gate material is then formed in the openings and around portions of layers 1421, 1423, and 1425 to form transistor gates for multi-layer transistors. In other embodiments, the fins may have alternating stacked layers of silicon and silicon germanium of different numbers. In other embodiments, the fins (1405) may be patterned by sidewall portions similar to portions 1101-1108 formed on the sidewalls of portions 1415-1418.

[0070] As shown and described herein, forming sidewall spacers on the sidewalls of a cavity on a carbon-containing layer and inhibiting the formation of spacer material on a bottom surface portion during a material formation process can provide a method for forming an opening with a reduced lateral width from a photolithographically defined opening with a larger lateral width. Thus, features of a semiconductor device can be made to have a lateral width that is smaller than a critical dimension. Forming the spacers using an ADL process can achieve tighter control over the spacer width.

[0071] As disclosed herein, a first structure is "directly above" a second structure if the first structure is above the second structure on a line having a direction perpendicular to the generally planar major side of the wafer or substrate. Fig.12 , spacer portion 1101 is directly above fin 1201. Spacer portion 1108 is not directly above fin 1201. As disclosed herein, a first structure is “directly below” or “directly under” a second structure if the first structure is below the second structure on a line having a direction perpendicular to the major side of the substantially plane of the wafer or substrate. For example, in Fig.12In FIG. 1 , fin 1201 is directly below spacer portion 1101. Fin 1201 is not directly below spacer portion 1108. A structure is “directly in the middle” of two structures on a line if two other structures are on opposite sides of the line. For example, in Fig.12 In the example, the spacer portion 1105 is Fig.12 1 and 1108 are centered on a line between spacer portion 1108 and spacer portion 1101 in a cross-sectional side view of the wafer or substrate. Substrate 903 is not centered on a line between spacer portions 1101 and 1108. A first structure is “directly transverse” to a second structure if the first structure and the second structure are located on a line having a direction parallel to the major side of the generally planar surface of the wafer or substrate. For example, spacer portions 1101 and 1108 are centered on each other. A structure is “directly centered on a line between” two other structures if the two other structures are located on opposite sides of the structure on a line parallel to the major side of the generally planar surface of the wafer or substrate. For example, Fig.12 , spacer portion 1105 is laterally located centered between spacer portions 1101 and 1108. A surface is at a "higher elevation" than another surface if the surface is closer to the top of the active side of the wafer or integrated circuit on a line having a direction perpendicular to the major sides of the generally planar surface of the wafer or integrated circuit. Figure 4 In the view of FIG. 1 , the active side of the wafer 101 is Figure 4 For example, layer 108 is at a higher elevation than spacer 301.

[0072] While particular embodiments of the present invention have been shown and described, those skilled in the art will recognize that, based on the teachings herein, further changes and modifications may be made without departing from the present invention and its broader aspects, and therefore, the appended claims are intended to cover within their scope all such changes and modifications that are within the true spirit and scope of the present invention.

Claims

1. A method, characterized in that include: forming a carbon-containing layer over a substrate comprising a semiconductor material; forming a first layer over the carbon-containing layer; forming a first opening in the first layer, the first opening having a first lateral dimension in a first lateral direction; removing material of the carbon-containing layer through the first opening to form a cavity in the carbon-containing layer; forming a sidewall spacer structure, wherein the forming the sidewall spacer structure comprises performing a material forming process that forms a sidewall spacer material on the sidewalls of the carbon-containing layer of the cavity, wherein the sidewall spacer material is inhibited from forming on a bottom surface portion of the cavity during the material forming process, wherein the sidewall spacer structure defines a second opening that exposes the bottom surface portion, the second opening having a second lateral dimension in the first lateral direction that is smaller than the first lateral dimension.

2. The method according to claim 1, characterized in that Also includes: After performing the material forming process, a second material is formed in the second opening.

3. The method according to claim 1, characterized in that The bottom surface portion is a portion of the carbon-containing layer that is treated with hydrogen after the forming of the cavity.

4. The method according to claim 3, characterized in that After the forming of the sidewall spacer structure, at least a portion of the bottom surface portion is etched through the second opening to expose the substrate.

5. The method according to claim 1, characterized in that The bottom surface portion is made of a material different from that of the carbon-containing layer.

6. The method according to claim 5, characterized in that The bottom surface portion is treated with an inhibitor during the material formation process to inhibit formation of the spacer material.

7. The method according to claim 1, characterized in that Also included is forming at least one fin comprising a semiconductor material using the sidewall spacer structure.

8. The method according to claim 7, characterized in that Also includes: After performing the material forming process, removing at least a portion of the carbon-containing layer laterally adjacent to the sidewall spacer structure; forming sidewall spacers of a second sidewall spacer material on the sidewalls of the sidewall spacer structure; After forming the sidewall spacers of the second sidewall spacer material, removing the sidewall spacer structure; The at least one fin is defined using the sidewall spacers of the second sidewall spacer material as a mask.

9. A method, characterized in that include: forming a carbon-containing layer over a wafer substrate including a semiconductor material; forming a first layer over the carbon-containing layer; forming a first opening in the first layer using a photolithography process, the first opening having a first lateral dimension in a first lateral direction; removing material of the carbon-containing layer through the first opening to form a cavity in the carbon-containing layer; forming a sidewall spacer structure using a material forming process, the material forming process forming a sidewall spacer material on sidewalls of the cavity of the carbon-containing layer, wherein the sidewall spacer material is inhibited from forming on a bottom surface portion of the cavity, wherein the sidewall spacer structure defines a second opening exposing the bottom surface portion, the second opening having a second lateral dimension in the first lateral direction that is less than the first lateral dimension; After said forming the sidewall spacer structures, the wafer is singulated into a plurality of integrated circuits.

10. The method according to claim 9, characterized in that Also includes: After performing the material forming process but before the singulation, at least a portion of the carbon-containing layer and the formed sidewall spacer material are removed.

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