Polycrystalline silicon gate etching method
By introducing the corrective etching step of HBr gas into the polysilicon gate etching process, the problem of line width differences in different structures of the polysilicon gate is solved, and more consistent post-etching size and higher process selectivity are achieved.
Patent Information
- Application Number
- CN202311414207.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-27
- Publication Date
- 2025-04-29
AI Technical Summary
The existing polysilicon gate etching process cannot effectively improve the line width differences of different structures, resulting in inconsistent size after etching.
By adding an etching step using only HBr during the polysilicon gate etching process, the corrected flow rate adjustment of the HBr gas is used to reduce the line width difference of the polysilicon gate structure.
The line width difference of polysilicon gate structure is effectively reduced, the key size after etching is optimized, the selectivity of process integration is improved, and development funds and time is saved.
Smart Images
Figure CN119905395A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to semiconductor manufacturing technology, and in particular to a polysilicon gate etching method. Background Art
[0002] The etching process is one of the most critical processes in the integrated circuit manufacturing process. Its main function is to complete the final transfer and shaping of the pattern in the photolithography process on the silicon wafer. The etching requirements depend on the type of feature pattern to be produced, such as polysilicon gate, shallow trench, metal mask layer or dielectric through hole. The polysilicon gate etching process is the most important in the etching process because its critical dimension (CD) is the smallest among all layers, which is the most critical. Usually, the polysilicon gate etching process can be divided into different processes according to different film structures. Figure 1 The steps shown are: bottom anti-reflection coating (BARC) etching (BARC opening), hard mask layer (HM) etching (HM opening), hard mask layer (HM) trimming (HM trim), photoresist removal (PR strip), polysilicon etching (Poly etch), etc. Among them, polysilicon etching is completed by BT (silicon oxide etching, ME1 (first polysilicon etching) and ME2 (second polysilicon etching), three steps of etching, the purpose is to obtain a better polysilicon gate morphology.
[0003] In the current semiconductor production process, the size (CD) of each layer and structure after etching is determined by the mask and photolithography conditions, and the etching process is basically unable to adjust the size difference between structures with different line widths, such as Figure 2 shown. Summary of the invention
[0004] The technical problem to be solved by the present invention is to provide a polysilicon gate etching method, which can improve the line width difference of different structures in polysilicon etching.
[0005] In order to solve the above technical problems, the present invention provides a polysilicon gate etching method, which comprises the following steps:
[0006] S1. forming a gate oxide layer, a polysilicon layer, a hard mask layer, a bottom anti-reflective coating and a photoresist on a silicon substrate in sequence;
[0007] S2. Photoresist lithography according to the designed line width of the polysilicon gate at various locations on the wafer;
[0008] S3. Injecting etching gas into the etching chamber to etch away the bottom anti-reflection coating outside the polysilicon gate region, and retaining the bottom anti-reflection coating in the polysilicon gate region;
[0009] S4. Injecting only HBr gas as etching gas into the etching chamber at a corrected flow rate to etch the bottom anti-reflective coating (BARC), so that the anti-reflective layer and the photoresist in the polysilicon gate area are further narrowed, and the width difference of the anti-reflective layer on the polysilicon gate at various locations on the wafer is reduced;
[0010] S5. etching the hard mask layer to remove the hard mask layer without the bottom anti-reflective coating, and retaining the hard mask layer covered with the bottom anti-reflective coating;
[0011] S6. Perform subsequent process steps to complete polysilicon gate etching.
[0012] Preferably, step S6 includes the following steps:
[0013] S61. performing correction etching of the hard mask layer to reduce the width of the hard mask layer at each polysilicon gate on the wafer by a corresponding size;
[0014] S62. removing the photoresist and the bottom anti-reflective coating, and retaining the hard mask layer;
[0015] S63. Using the hard mask layer as a protective layer, the polysilicon layer is etched to remove the polysilicon layer not covered by the hard mask layer, and the polysilicon layer covered by the hard mask layer is retained.
[0016] Preferably, the etching gas injected into the etching chamber in step S3 includes HBr gas.
[0017] Preferably, the hard mask layer is composed of at least one silicon oxide layer and / or silicon nitride layer.
[0018] Preferably, the bottom anti-reflective coating comprises a cross-linkable main film-forming resin, a thermal acid generator, a cross-linking agent and an organic solvent.
[0019] Preferably, the bottom anti-reflective coating comprises the following raw materials in percentage by weight: 5-15% of an aromatic glycoluril oligomer solution, 0.5-15% of a main resin, 0.1-5% of a cross-linking agent, 0.1-1% of a thermosensitive acid, and the balance being an organic solvent;
[0020] Wherein, the main resin includes a light-absorbing functional group, a cross-linking functional group and an auxiliary functional group.
[0021] Preferably, in step S4, the correction flow rate is selected and determined according to the designed line width of the polysilicon gate at each location of the wafer and a matrix table of calibrated HBr gas flow rates and line width changes after etching of different structures;
[0022] The matrix table of HBr gas flow and line width changes after etching of different structures is calibrated by a DOE experimental method.
[0023] Preferably, when performing step S4, after selecting and determining the corrected flow rate of HBr, the designed line widths of polysilicon gates of various structures at various locations of the wafer before etching the bottom anti-reflective coating are collected;
[0024] When performing step S5, the width of the hard mask layer at the polysilicon gate of various structures of the wafer after etching the hard mask layer is collected;
[0025] Determine the central design line width of the current process according to the design line widths of the polysilicon gates of various structures at various locations of the wafer before etching the bottom anti-reflective coating collected during step S4 and the hard mask layer widths at the polysilicon gates of various structures of the wafer after etching the hard mask layer collected during step S4;
[0026] The process window of the process is established with the central design line width as the center line.
[0027] The polysilicon gate etching method of the present invention utilizes the characteristic that HBr plasma cloud bombarding photoresist (PR) can cause a qualitative change in the bond energy in the photoresist (for example, 193 nanometer photoresist), and adds a step of line width correction using only HBr in the polysilicon gate etching process. According to the requirements of process integration, the injection flow rate of HBr gas in the line width correction step is adjusted to reduce the line width difference of different polysilicon gate structures, so as to optimize and quantify the key dimensions of polysilicon gate structures of different sizes after etching, and solve the problem that the line width difference of different polysilicon gate structures after polysilicon etching cannot be changed when the current mask and photolithography conditions are fixed. When the mask and photolithography conditions are fixed, according to the requirements of process integration, the post-etching line width size of various polysilicon gate structures can be obtained by adjusting the process conditions of polysilicon gate etching, so that the requirements for the line width after polysilicon gate etching have more selectivity, which can greatly save development funds and development time. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0029] Figure 1 The present invention is a flowchart of the etching process of the existing polysilicon gate;
[0030] Figure 2 It is a schematic diagram of different line width structures after etching in the existing polysilicon gate etching process;
[0031] Figure 3 It is a flow chart of an embodiment of a polysilicon gate etching method of the present invention;
[0032] Figure 4 It is a 193-nanometer photoresist bond;
[0033] Figure 5 It is a 193 nm photoresist bond that has been re-modified by HBr;
[0034] Figure 6 The post-etching dimensions of various structures are obtained by adjusting the process conditions of polysilicon gate etching;
[0035] Figure 7 This is a schematic diagram of the post-etching line width obtained for different lithography line width structures at different HBr dosages. DETAILED DESCRIPTION
[0036] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0037] The words "first", "second" and similar terms used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprises" and similar terms mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "front", "back" and the like are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.
[0038] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.
[0039] Embodiment 1
[0040] A polysilicon gate etching method, such as Figure 3 As shown, the following steps are included:
[0041] S1. A gate oxide layer, a polysilicon layer (POLY), a hard mask layer (HM), a bottom anti-reflection coating (Bottom Anti Reflection Coating, BARC) and a photoresist (PR) are sequentially formed on a silicon substrate (silicon). Figure 1As shown;
[0042] S2. Photoresist (PR) lithography according to the designed line width of the polysilicon gate at various locations on the wafer;
[0043] S3. Injecting etching gas into the etching chamber to etch and remove the bottom anti-reflective coating (BARC) outside the polysilicon gate region, and retaining the bottom anti-reflective coating (BARC) in the polysilicon gate region;
[0044] S4. Inject only HBr (hydrogen bromide) gas as etching gas into the etching chamber at a corrected flow rate, and remove the bottom anti-reflective coating (BARC) outside the polysilicon gate region by etching, and retain the bottom anti-reflective coating (BARC) in the polysilicon gate region; since the etching rate of HBr (hydrogen bromide) gas on the bottom anti-reflective coating (BARC) and the photoresist (PR) is much greater than the etching rate on the hard mask layer (HM), the anti-reflective layer (BARC) and the photoresist (PR) in the polysilicon gate region can be further narrowed. Since different photoresist (PR) widths have different narrowing amounts for the same injection flow rate, that is, the larger the photoresist (PR) width, the greater the narrowing amount for the same injection flow rate, so the width difference of the photoresist (PR) and the anti-reflective layer (BARC) on the polysilicon gate at various locations on the wafer can be reduced, such as Figure 6 As shown;
[0045] S5. etching the hard mask layer (HM), removing the hard mask layer (HM) not covered by the bottom anti-reflective coating (BARC), and retaining the hard mask layer (HM) covered by the bottom anti-reflective coating (BARC);
[0046] S6. Perform subsequent process steps to complete polysilicon gate etching.
[0047] 193 nm photoresist bond Figure 4 As shown, HBr (hydrogen bromide) forms plasma in the etching chamber. When the plasma cloud bombards the photoresist (PR), the bond energy in the photoresist (e.g., 193 nm photoresist) will undergo a qualitative change, such as Figure 5 As shown in the figure, since this reaction is similar to a chemical reaction, the reaction is inconsistent for structures with different line widths.
[0048] The polysilicon gate etching method of the first embodiment utilizes the characteristic that HBr plasma cloud bombarding photoresist (PR) can cause a qualitative change in the bond energy in the photoresist (e.g., 193 nm photoresist), and adds a step of line width correction using only HBr in the polysilicon gate etching process. According to the requirements of process integration, the injection flow rate of HBr gas in the line width correction step is adjusted to reduce the line width difference of different polysilicon gate structures, so as to optimize and quantify the key dimensions of polysilicon gate structures of different sizes after etching, and solve the problem that the line width difference of different polysilicon gate structures after polysilicon etching cannot be changed when the current mask and photolithography conditions are fixed. When the mask and photolithography conditions are fixed, according to the requirements of process integration, the post-etching line width size of various polysilicon gate structures can be obtained by adjusting the process conditions of polysilicon gate etching, so that the requirements for the line width after polysilicon gate etching have more selectivity, which can greatly save development funds and development time.
[0049] Embodiment 2
[0050] Based on the polysilicon gate etching method of the first embodiment, step S6 includes the following steps:
[0051] S61. Performing correction etching of the hard mask layer (HM) to reduce the width of the hard mask layer (HM) at each polysilicon gate on the wafer by a corresponding size;
[0052] S62. removing the photoresist (PR) and the bottom anti-reflective coating (BARC), and retaining the hard mask layer (HM);
[0053] S63. Using the hard mask layer (HM) as a protective layer, the polysilicon layer 12 is etched to remove the polysilicon layer 12 not covered by the hard mask layer (HM), and the polysilicon layer 12 covered by the hard mask layer (HM) is retained.
[0054] Preferably, the etching gas injected into the etching chamber in step S3 includes HBr (hydrogen bromide) gas.
[0055] Preferably, the hard mask layer is composed of at least one silicon oxide layer and / or silicon nitride layer.
[0056] Preferably, the main components of the bottom anti-reflective coating (BARC) include a cross-linkable host film-forming resin, a thermal acid generator, a cross-linking agent, an organic solvent, and the like.
[0057] Preferably, the bottom anti-reflective coating (BARC) comprises the following raw materials in percentage by weight: 5-15% of an aromatic glycoluril oligomer solution, 0.5-15% of a main resin, 0.1-5% of a cross-linking agent, 0.1-1% of a thermal acid, and the remainder being an organic solvent; wherein the main resin comprises a light-absorbing functional group, a cross-linking functional group, and an auxiliary functional group.
[0058] Embodiment 3
[0059] Based on the polysilicon gate etching method of the first embodiment, in step S4, the correction flow rate is selected and determined according to the designed line width of the polysilicon gate at each location of the wafer and the matrix table of the calibrated HBr gas flow rate and the line width change size after etching of different structures, so as to select and use different hydrogen bromide dosages to obtain the line width required by the user, thereby improving the selectivity of process integration;
[0060] The matrix table of HBr gas flow and line width variation after etching of different structures is calibrated by a DOE (design of experiment) experimental method.
[0061] The matrix table of HBr gas flow and line width change after etching of different structures is shown in Table 1 and Figure 7 As shown, at the same HBr gas injection flow rate, the smaller the line width, the greater the line width narrowing; at the same line width, the larger the HBr gas injection flow rate, the smaller the line width narrowing.
[0062] Table 1
[0063]
[0064] Preferably, when performing step S4, after selecting and determining the corrected flow rate of HBr, the designed line widths of polysilicon gates of various structures at various locations of the wafer before etching the bottom anti-reflective coating (BARC) are collected;
[0065] When performing step S5, the width of the hard mask layer (HM) at the polysilicon gate of various structures of the wafer after etching the hard mask layer (HM) is collected;
[0066] Determine the central design line width of the process according to the design line widths of polysilicon gates of various structures at various locations of the wafer before etching the bottom anti-reflective coating (BARC) collected in step S4 and the hard mask layer (HM) widths at polysilicon gates of various structures of the wafer after etching the hard mask layer (HM) collected in step S5;
[0067] With the central design line width as the center line, the process window of the process is established to ensure the stability of subsequent mass production.
[0068] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. A polysilicon gate etching method, characterized in that: The following steps are involved: S1. forming a gate oxide layer, a polysilicon layer, a hard mask layer, a bottom anti-reflective coating and a photoresist on a silicon substrate in sequence; S2. Photoresist lithography according to the designed line width of the polysilicon gate at various locations on the wafer; S3. Injecting etching gas into the etching chamber to etch away the bottom anti-reflection coating outside the polysilicon gate region, and retaining the bottom anti-reflection coating in the polysilicon gate region; S4. Inject only HBr gas as etching gas into the etching chamber at a corrected flow rate to etch the bottom anti-reflection coating, so that the anti-reflection layer and the photoresist in the polysilicon gate area are further narrowed, so that the width difference of the anti-reflection layer on the polysilicon gate at various locations on the wafer is reduced; S5. etching the hard mask layer to remove the hard mask layer without the bottom anti-reflective coating, and retaining the hard mask layer covered with the bottom anti-reflective coating; S6. Perform subsequent process steps to complete polysilicon gate etching.
2. The polysilicon gate etching method according to claim 1, characterized in that: Step S6 includes the following steps: S61. performing correction etching of the hard mask layer to reduce the width of the hard mask layer at each polysilicon gate on the wafer by a corresponding size; S62. removing the photoresist and the bottom anti-reflective coating, and retaining the hard mask layer; S63. Using the hard mask layer as a protective layer, the polysilicon layer is etched to remove the polysilicon layer not covered by the hard mask layer, and the polysilicon layer covered by the hard mask layer is retained.
3. The polysilicon gate etching method according to claim 1, characterized in that: In step S3, the etching gas injected into the etching chamber includes HBr gas.
4. The polysilicon gate etching method according to claim 1, characterized in that: The hard mask layer is composed of at least one silicon oxide layer and / or silicon nitride layer.
5. The polysilicon gate etching method according to claim 1, characterized in that: The bottom anti-reflection coating comprises a cross-linkable main film-forming resin, a thermal acid generator, a cross-linking agent and an organic solvent.
6. The polysilicon gate etching method according to claim 1, characterized in that: The bottom anti-reflection coating comprises the following raw materials in percentage by mass: 5-15% of an aromatic glycoluril oligomer solution, 0.5-15% of a main resin, 0.1-5% of a cross-linking agent, 0.1-1% of a thermosensitive acid, and the balance being an organic solvent; Wherein, the main resin includes a light-absorbing functional group, a cross-linking functional group and an auxiliary functional group.
7. The polysilicon gate etching method according to claim 1, characterized in that: In step S4, the correction flow rate is selected and determined according to the designed line width of the polysilicon gate at each location of the wafer and a matrix table of calibrated HBr gas flow rates and line width changes after etching of different structures; The matrix table of HBr gas flow and line width changes after etching of different structures is calibrated by a DOE experimental method.
8. The polysilicon gate etching method according to claim 1, characterized in that: When performing step S4, after selecting and determining the corrected flow rate of HBr, the designed line widths of polysilicon gates of various structures at various locations of the wafer before etching the bottom anti-reflective coating are collected; When performing step S5, the width of the hard mask layer at the polysilicon gate of various structures of the wafer after etching the hard mask layer is collected; Determine the central design line width of the current process according to the design line widths of the polysilicon gates of various structures at various locations of the wafer before etching the bottom anti-reflective coating collected during step S4 and the hard mask layer widths at the polysilicon gates of various structures of the wafer after etching the hard mask layer collected during step S4; The process window of the process is established with the central design line width as the center line.