Chip mounting method and chip packaging method

Abstract

The invention provides a chip mounting method and a chip packaging method, relates to the technical field of semiconductors, and aims to control the chip mounting cost while ensuring the chip quality. The chip mounting method comprises the following steps: providing a carrier film provided with a plurality of bare chips, wherein the plurality of bare chips are divided into a plurality of grades; moving a plurality of bare chips of a target grade onto the substrate, wherein the target grade is the grade with the largest number of bare chips in the plurality of grades; the positions of the remaining bare chips on the bearing film are adjusted, so that the distance between any two adjacent bare chips in the remaining bare chips is larger than or equal to the preset distance; and moving the bare chips belonging to different grades in the remaining bare chips to different substrates in sequence. The chip mounting method is applied to the chip packaging method so as to improve the yield of chip packaging.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a chip mounting method and a chip packaging method. Background Art

[0002] Die attach (DA) is a very important process in the chip packaging process. Before die attach, the wafer needs to be cut into multiple chips. Multiple chips can be divided into multiple levels according to performance (for example, storage capacity, processing speed, etc.). During the die attach process, chips of different levels need to be sorted onto different substrates.

[0003] How to control the cost of chip mounting while ensuring the quality of the chip has become an urgent problem to be solved in this field. Summary of the invention

[0004] The embodiments of the present disclosure provide a chip mounting method and a chip packaging method, so as to control the chip mounting cost while ensuring the chip quality.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] In one aspect, a chip mounting method is provided. The chip mounting method includes: providing a carrier film provided with a plurality of bare chips, wherein the plurality of bare chips are divided into a plurality of grades. Moving a plurality of bare chips of a target grade onto a substrate, wherein the target grade is a grade with the largest number of bare chips among the plurality of grades. Adjusting the positions of the remaining bare chips on the carrier film so that the distance between any two adjacent bare chips among the remaining bare chips is greater than or equal to a preset distance. Moving the bare chips of different grades among the remaining bare chips sequentially onto different substrates.

[0007] In the chip mounting method provided by the embodiment of the present disclosure, a carrier film provided with a plurality of bare chips is first provided, and the plurality of bare chips are divided into a plurality of levels, and then a plurality of bare chips in a level (i.e., a target level) with the largest number of bare chips among the plurality of levels are moved to a substrate, and the positions of the remaining bare chips on the carrier film are adjusted so that the distance between any two adjacent bare chips among the remaining bare chips is greater than or equal to a preset distance, and finally the bare chips belonging to different levels among the remaining bare chips are moved to different substrates in sequence. In this way, after the bare chips of the target level on the carrier film are moved, by adjusting the positions of the remaining bare chips on the carrier film, the spacing between the remaining bare chips can be made larger, so that the remaining bare chips on the carrier film are not easy to collide with each other when the carrier film is loose and drooping, thereby effectively ensuring the yield of the remaining bare chips, avoiding the problem of the remaining bare chips being damaged or broken due to mutual collision, and improving the reliability of the chip mounting process and the yield of the packaged chip.

[0008] Compared with the solution in the related art of moving the remaining dies belonging to different levels to a new carrier film, the embodiment of the present application adjusts (or integrates) the positions of the remaining dies on the same carrier film, without adding a new carrier film or adding a process of moving the remaining dies to different carrier films, thereby reducing costs, making the chip mounting process simpler, and increasing chip mounting efficiency.

[0009] At the same time, compared with the solution of the related art in which a wafer expansion ring is formed on the side of the carrier film away from the bare chip, the embodiment of the present application does not require a new wafer expansion ring, nor does it require an increase in the installation process of the wafer expansion ring, thereby reducing costs, making the chip mounting process simpler, and increasing chip mounting efficiency.

[0010] In some embodiments, adjusting the positions of the remaining dies on the carrier film includes arranging the remaining dies into at least one row. This simplifies the adjustment process of the remaining dies by the chip mounting machine, and facilitates the subsequent chip mounting machine to pick up the remaining dies after adjustment, thereby improving chip mounting efficiency.

[0011] In some embodiments, the remaining die include multiple levels; the arranging the remaining die into at least one row includes: after the die of the same level are arranged, the die of another level are arranged. In this way, the distance between the multiple die of the same level of the remaining die after adjustment is closer, and when the chip mounting machine sorts the multiple die of the same level, the picking efficiency of the chip mounting machine can be higher, which is conducive to improving the efficiency of chip mounting.

[0012] In some embodiments, adjusting the positions of the remaining die on the carrier film includes: dividing the remaining die into at least one die group. The spacing between any two adjacent die in the die group is less than the preset distance. Adjusting the position of at least one die in the die group so that the spacing between any two adjacent die in the die group is greater than or equal to the preset distance.

[0013] In this way, the embodiment of the present disclosure can adjust the positions of some of the remaining dies whose spacing is less than the preset distance, so that the number of dies that need to be adjusted can be reduced, which is beneficial to improving the speed and efficiency of adjusting the remaining dies, and further beneficial to improving the speed of chip mounting.

[0014] In some embodiments, adjusting the position of at least one die in the die group includes: dividing the plurality of die in the die group into a first die and a second die; and keeping the position of the first die unchanged and adjusting the position of the second die.

[0015] In the process of adjusting the positions of the remaining die on the carrier film, the embodiment of the present disclosure first divides the remaining die into at least one die group, then divides the plurality of die in the die group into a first die and a second die, and finally adjusts the position of the second die, keeping the position of the first die unchanged. In this way, in the process of adjusting the positions of the remaining die on the carrier film, the number of the remaining die that needs to be adjusted can be small, which is conducive to further improving the speed and efficiency of adjusting the remaining die, and further conducive to improving the speed of chip mounting.

[0016] In some embodiments, the plurality of dies are arranged into a plurality of rows along a first direction parallel to the carrier film, and the plurality of dies are arranged into a plurality of columns along a second direction parallel to the carrier film, and the first direction intersects with the second direction; after the plurality of dies of a target grade are moved onto the substrate, a plurality of vacancies are formed on the carrier film; and adjusting the positions of the remaining dies on the carrier film comprises: peeling at least a portion of the remaining dies from the carrier film; and placing the peeled dies on the vacancies.

[0017] When a chip mounting machine is used to operate multiple bare chips on a carrier film, it is necessary to establish a coordinate system based on the image of the carrier film, so as to determine the positions of the multiple bare chips on the carrier film and determine the path that the picking tool in the chip mounting machine needs to move when picking up the bare chips. When adjusting the positions of the remaining bare chips on the carrier film, the disclosed embodiment peels at least a portion of the bare chips from the carrier film, and then places the bare chips in an empty position, so that when a new image of the carrier film is subsequently formed and a new coordinate system is established based on the new carrier film, the new coordinate system can overlap with the original coordinate system, so that when the adjusted remaining bare chips are picked up based on the new image of the carrier film and the new coordinate system, there is no need to recalculate and plan the required path of the picking tool. This setting can effectively simplify the subsequent picking process of the remaining bare chips on the carrier film using the chip mounting machine, ensure the accuracy of the picking process, and improve the efficiency of chip mounting.

[0018] In some embodiments, after adjusting the positions of the remaining die on the carrier film, in the first direction, the spacing between two adjacent die is greater than or equal to the size of the die in the first direction; after adjusting the positions of the remaining die on the carrier film, in the second direction, the spacing between two adjacent die is greater than or equal to the size of the die in the second direction.

[0019] In this way, in the first direction, the distance between two adjacent bare chips can be larger, and in the second direction, the distance between two adjacent bare chips can also be larger. Even if the carrier film is subsequently taken out of the chip mounting machine and the carrier film is loose and drooping, it is not easy for the two adjacent bare chips to collide with each other, thereby effectively protecting the bare chips.

[0020] In some embodiments, the preset distance is the minimum size of the die. In this way, the spacing between the remaining die on the carrier film after adjustment can be larger, and even if the carrier film is subsequently removed from the chip mounting machine and the carrier film sags, it is not easy for two adjacent die to collide, which helps to avoid the problem of die damage or cracking.

[0021] In some embodiments, the number of remaining dies is less than the number of dies of the target grade. Thus, after the dies of the target grade are moved from the carrier film to the substrate, there is more space on the carrier film for adjusting the positions of the remaining dies, so that the distance between any two adjacent dies among the remaining dies is greater than or equal to the preset distance.

[0022] In some embodiments, adjusting the positions of the remaining die on the carrier film includes: adjusting the positions of the remaining die on the carrier film when the carrier film is in a taut state.

[0023] In this way, on the one hand, it is convenient for the chip mounting machine to pick up and place the remaining bare chips on the carrier film, thereby improving the efficiency of adjusting the positions of the remaining bare chips on the carrier film. On the other hand, it can also avoid the problem that the carrier film is loose and drooping, causing the bare chips that have not been adjusted on the carrier film to collide with each other, thereby ensuring the yield of the remaining bare chips in the process of adjusting the positions of the remaining bare chips on the carrier film.

[0024] In some embodiments, after adjusting the positions of the remaining bare chips on the carrier film, the chip mounting method further includes: generating a first image of the carrier film including the remaining bare chips; moving the bare chips of different levels among the remaining bare chips to different substrates in sequence, including: moving the bare chips of the same level to one substrate according to the first image; generating a second image of the carrier film including the remaining bare chips, and moving the bare chips of another level to another substrate according to the second image, until all the remaining bare chips on the carrier film are moved.

[0025] After the die on the carrier film is moved, the embodiment of the present application will regenerate an image (for example, the first image and the second image), so that the remaining die can be picked up according to the latest image, effectively ensuring the accuracy of the operation when picking up the remaining die, which is conducive to improving the efficiency of chip mounting.

[0026] On the other hand, a chip packaging method is provided, which includes the chip mounting method provided by any of the above embodiments.

[0027] It can be understood that the beneficial effects that can be achieved by the chip packaging method provided by the above embodiments of the present disclosure can refer to the beneficial effects of the chip mounting method mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0029] Figure 1 is a schematic diagram of a die collision on a carrier film according to some embodiments;

[0030] Figure 2 is a flow chart of a chip mounting method according to some embodiments;

[0031] Figure 3 for Figure 2 A schematic structural diagram of the carrier film and the bare chip corresponding to step S100 in the flowchart shown;

[0032] Figure 4 and Figure 5 for Figure 2 A schematic structural diagram of the carrier film and the bare chip corresponding to step S200 in the flowchart shown;

[0033] Figure 6 for Figure 2 A schematic structural diagram of the carrier film and the bare chip corresponding to step S300 in the flowchart shown;

[0034] Figure 7 is another flow chart of a chip mounting method according to some embodiments;

[0035] Figure 8 is a schematic structural diagram of a carrier film and a bare chip corresponding to step S331 according to some embodiments;

[0036] Fig. 9 is a schematic structural diagram of a carrier film and a bare chip corresponding to step S351 according to some embodiments;

[0037] Fig.10 is a schematic structural diagram of a carrier film and a bare chip corresponding to step S352 according to some embodiments;

[0038] Fig.11 is another flow chart of a chip mounting method according to some embodiments;

[0039] Figure 12 to Figure 14 for Figure 2 The schematic diagram of the structure of the carrier film and the bare chip corresponding to step S400 in the flowchart shown. DETAILED DESCRIPTION

[0040] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0041] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0042] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0043] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0044] When describing some embodiments, the term "connected" and its derivative expressions may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0045] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0046] In the context of this disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “on” or “over” something, but also includes the meaning of “on” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0047] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0048] Chip packaging mainly includes wafer pretreatment, chip mounting, chip binding and testing processes. Among them, wafer pretreatment may include, for example, wafer thinning and wafer cutting. During wafer thinning, mechanical grinding or chemical mechanical grinding can be used to grind the back of the wafer to thin the wafer to a suitable packaging level. During wafer cutting, the wafer can be cut by a dicing machine to form multiple bare chips (ie, chips). Before cutting the wafer, a dicing film can be bonded to the back of the wafer. The dicing film can reduce the fragmentation generated during the dicing process. The dicing film can also fix the wafer to be diced to maintain the integrity of the wafer during the dicing process and prevent the bare chip from falling.

[0049] Although multiple dies are cut from the same wafer, the multiple dies can also be divided into different levels according to their different performances. The performance mentioned here can be, for example, the storage capacity (storage volume) of the die or the processing rate of the die.

[0050] Chip attach is a very important process in the chip packaging process. Through chip attach, the multiple dies that have been separated can be moved from the dicing film to the substrate. At this time, the dicing film can be used as a carrier film for the multiple dies. Of course, after the wafer is cut, a separate carrier film can be formed on the back of the multiple dies before chip attach. The multiple dies separated from the same wafer can be divided into multiple levels. During the chip attach process, the dies of different levels can be moved to different substrates respectively.

[0051] Chip bonding is also a key process in the packaging process. It mainly uses gold wire, copper wire or aluminum wire to connect the pads on the chip with the gold fingers on the substrate by welding. Testing is a key process to ensure that the electrical connection of the packaged chip meets the requirements. By testing the packaged chip with test equipment, good products can be distinguished from bad ones.

[0052] In the chip mounting process, in order to move different grades of dies to different substrates for packaging, the chip mounting machine needs to pick up and transfer multiple dies multiple times. Before the chip mounting machine picks up the wafer, the carrier film needs to be expanded to overcome the gravity of multiple dies and the carrier film, so that different parts of the carrier film are located on the same plane, which makes it easier for the chip mounting machine to sort the dies.

[0053] However, if Figure 1 As shown, after multiple dies on the same carrier film are picked up and transferred multiple times, the carrier film will be expanded multiple times. After the carrier film is removed from the chip mounting machine, the carrier film will sag, causing the distance between two adjacent dies on the carrier film to decrease. The two adjacent dies are prone to collision, resulting in damage (chipping) or cracking of the die.

[0054] To solve the above problem, in the related art, after picking up multiple bare chips belonging to one level on multiple carrier films, multiple bare chips belonging to another level on multiple carrier films are collectively picked up onto a new carrier film, and the operation is repeated until the remaining multiple bare chips on the multiple carrier films are all moved to the new carrier film.

[0055] Although the related art places the remaining bare chips on new carrier films respectively, after picking up multiple bare chips belonging to one level on multiple carrier films and before picking up multiple bare chips belonging to another level on multiple carrier films and putting them on new carrier films together, the original carrier film may still be loose when removed from the chip mounting machine, and the remaining bare chips on the original carrier film may still collide, thereby causing damage or breakage of the bare chips.

[0056] In addition, the above process adds a process of collectively picking up multiple bare chips belonging to another level on multiple carrier films and placing them on a new carrier film, making the chip mounting process more complicated. At the same time, more carrier films are used in the above process, making the cost of chip mounting higher.

[0057] Another solution is proposed in the related art, that is, before placing the carrier film with multiple dies in the chip mounting machine, a wafer expansion ring is installed on the back of the carrier film (or wafer), and the wafer expansion ring is used to support the dies and the carrier film. In this way, after the dies of different grades on the carrier film are transferred to the substrate, the carrier film will not be loose, thereby avoiding the problem of collision between the dies of multiple grades remaining on the carrier film due to the loosening of the carrier film.

[0058] However, adopting this method will increase the process of ring attachment during chip attachment, making the chip attachment process more complicated. At the same time, adopting the above method will also increase the use of wafer expansion rings, making the cost of chip attachment process higher.

[0059] Based on the above content, the embodiment of the present application provides a chip mounting method. Figure 2 As shown, the chip mounting method includes steps S100 to S400.

[0060] S100, such as Figure 3 As shown, a carrier film 20 provided with a plurality of dies 10 is provided, and the plurality of dies 10 are divided into a plurality of levels C.

[0061] For some examples, see Figure 3 The plurality of bare chips 10 may be arranged in a plurality of rows along a first direction X parallel to the carrier film 20, and the plurality of bare chips 10 may be arranged in a plurality of columns along a second direction Y parallel to the carrier film 20. The first direction X and the second direction Y intersect. Figure 3 In the figure, the first direction X and the second direction Y are perpendicular to each other as an example.

[0062] The number of the dies 10 in different rows may be the same or different, and the number of the dies 10 in different columns may be the same or different.

[0063] Of course, the arrangement of the plurality of bare chips 10 on the carrier film 20 in the embodiment of the present disclosure is not limited thereto.

[0064] In the embodiment of the present disclosure, there is no restriction on the shape and size of the projection of the die 10 on the carrier film 20, and the shape and size can be designed according to actual needs. Figure 3 As shown, the projection of the die 10 on the carrier film 20 may be rectangular.

[0065] In some examples, such as Figure 3 As shown, the projection sizes of the plurality of dies 10 on the carrier film 20 may be the same.

[0066] In other examples, the projections of the plurality of dies 10 on the carrier film 20 may be different in size. In this case, the projections of the plurality of dies 10 on the carrier film 20 may be different in size, or the projections of some of the plurality of dies 10 on the carrier film 20 may be the same in size, and the projections of another portion of the plurality of dies 10 on the carrier film 20 may be different in size.

[0067] In the embodiment of the present disclosure, there is no limitation on the number of the bare chips 10 on the carrier film 20. It is understandable that Figure 3 It is only a schematic diagram of multiple bare chips 10 on the carrier film 20. Figure 3 The number of dies 10 shown does not limit the number of dies 10 on the carrier film 20 in the embodiments of the present disclosure.

[0068] In the embodiment of the present disclosure, there is no limitation on the number of levels C into which the multiple dies 10 on the same carrier film 20 are divided. For example, the multiple dies 10 on the same carrier film 20 can be divided into 2 levels, 3 levels, 4 levels or more levels. When different wafers are divided to form multiple dies 10, the number of levels C into which the multiple dies 10 belonging to different wafers are divided can be the same or different.

[0069] Figure 3 In the example, a plurality of bare chips 10 are divided into three levels C. Figure 3 As shown, the three levels C are respectively a first level C1, a second level C2 and a third level C3.

[0070] It is understandable that the embodiment of the present disclosure does not limit the number of bare dies 10 in different levels C. The number of bare dies 10 in different levels C may be the same or different. Figure 3 In the example, the number of the dies 10 in the first level C1 is different from the number of the dies 10 in the second level C2, and the number of the dies 10 in the first level C1 is different from the number of the dies 10 in the third level C3.

[0071] In the disclosed embodiment, there is no limitation on the material, thickness, shape and size of the carrier film 20 , and they can be designed according to actual needs.

[0072] S200, such as Figure 4 As shown, a plurality of dies 10 of a target level C0 are moved onto the substrate 30 , and the target level C0 is the level with the largest number of dies 10 among the multiple levels C. Figure 3In the example, the third level C3 is taken as the level with the largest number of dies 10 among the multiple levels C. Figure 3 The third level C3 is the target level C0.

[0073] In some examples, the ratio of the number of dies 10 with target grade C0 to the number of all dies 10 on the carrier film 20 may be greater than or equal to 70%. For example, the number of dies 10 with target grade C0 may account for 70%, 80%, 90%, 95%, etc. of the number of all dies 10 on the carrier film 20.

[0074] In some examples, a die attach machine may be used to move the plurality of dies 10 onto the substrate 30. Exemplarily, the die attach machine may include an ejection tool and a pick-up tool, and during step S200, the ejection tool is located on a side of the carrier film 20 away from the die 10. The pick-up tool is located on a side of the die 10 away from the carrier film 20.

[0075] In the process of using a chip placement machine to move multiple dies 10 of target level C0 onto the substrate 30, the ejection tool can move toward the carrier film 20, penetrate the carrier film 20 and contact the die 10, and apply force to the die 10, so that the die 10 overcomes the adhesive force between the die 10 and the carrier film 20, so that a gap appears between the die 10 and the carrier film 20, and the die 10 can be easily detached from the carrier film 20. The pick-up tool contacts the die 10, drives the die 10 to move to the side away from the carrier film 20, and moves the die 10 to the substrate 30. Exemplarily, the substrate 30 is coated with adhesive, and the die 10 is connected to the substrate 30 through the adhesive.

[0076] In some examples, during the process of moving the plurality of dies 10 of the target level C0 onto the substrate 30 , the plurality of dies 10 in the target level C0 may all be connected to the substrate 30 .

[0077] In other examples, during the process of moving the plurality of dies 10 of the target level C0 onto the substrate 30, a portion of the dies 10 of the target level C0 may be in contact with the substrate 30, and another portion of the dies 10 may be in contact with the dies 10. Figure 4 As shown, some of the dies 10 on the substrate 30 may be stacked and electrically connected.

[0078] When the bare die 10 is a memory chip, some of the bare die 10 are stacked and electrically connected to increase the storage capacity per unit area of ​​the system.

[0079] When some of the bare dies 10 are stacked, the embodiment of the present application does not limit the number of the stacked bare dies 10 and can be designed according to actual needs. Figure 4 A stacking arrangement of four bare chips is used as an example.

[0080] In the embodiment of the present application, there is no restriction on the layout of the plurality of bare chips 10 in the target level C0 after being moved to the substrate 30. Figure 4 As shown, the plurality of dies 10 may be arranged in at least one row or at least one column on the substrate 30 .

[0081] It is to be understood that in the embodiment of the present disclosure, “moving multiple dies 10 of target level C0 onto substrate 30” is not limited to moving multiple dies 10 of target level C0 onto one substrate 30. When one substrate 30 can no longer carry any more dies 10, the dies that have not been moved in target level C0 can be moved onto another substrate 30. However, in order to avoid mixing dies of different levels on the same substrate, the substrate carrying the dies 10 of target level C0 is different from the substrate carrying the remaining dies 10 in step S400 described below.

[0082] like Figure 5 As shown, after step S200, a plurality of vacancies 21 may be formed on the carrier film 20. Figure 3 The plurality of vacancies 21 correspond one-to-one to the positions of the plurality of dies 10 in the target level C0.

[0083] S300, such as Figure 6 As shown, the positions of the remaining dies 10 on the carrier film 20 are adjusted so that the distance between any two adjacent dies 10 among the remaining dies 10 is greater than or equal to the preset distance D.

[0084] Here, “the distance between any two adjacent bare chips 10 ” refers to the distance between the mutually adjacent boundaries of any two adjacent bare chips 10 .

[0085] like Figure 6 As shown, “the distance between any two adjacent bare chips 10” refers to the distance L1 between two adjacent bare chips 10 in the first direction X parallel to the carrier film 20, and also refers to the distance L2 between two adjacent bare chips 10 in the second direction Y parallel to the carrier film 20. Of course, it also refers to the distance between two adjacent bare chips 10 in other directions parallel to the carrier film 20.

[0086] In some examples, the number of remaining dies 10 is less than the number of dies 10 of target level C0. Thus, after the dies 10 of target level C0 are moved from the carrier film 20 to the substrate 30, there is more space on the carrier film 20 for adjusting the positions of the remaining dies 10, so that the distance between any two adjacent dies 10 among the remaining dies 10 is greater than or equal to the preset distance.

[0087] In the embodiment of the present application, there is no limitation on the value of the preset distance D, which can be designed according to actual conditions. For example, the preset distance can be designed according to the size of the die 10 and the degree of relaxation and sagging of the carrier film 20 , as well as the size of the carrier film 20 .

[0088] In some examples, such as Figure 6 As shown, the predetermined distance D may be the minimum size of the die 10 .

[0089] It is understood that the “minimum size of the die 10” refers to the minimum size of the die 10 in a direction parallel to the carrier film 20. Figure 6 As shown, the projection of the die 10 on the carrier film 20 is a rectangle. At this time, the minimum size of the die 10 is the width of the die 10 , that is, the size of the die 10 in the first direction X.

[0090] When the preset distance is the minimum size of the die 10, the spacing between the remaining die 10 on the carrier film 20 after adjustment is greater than or equal to the minimum size of a die 10. In this way, even if the carrier film 20 is subsequently taken out of the chip mounting machine and the carrier film 20 sags, it is not easy for two adjacent die 10 to collide, which helps to avoid the problem of die damage or cracking.

[0091] In some examples, such as Figure 7 As shown, step S300 may include step S310 and step S320.

[0092] S310 , peeling at least a portion of the remaining dies 10 from the carrier film 20 .

[0093] At this time, the remaining bare chips 10 may be peeled off from the carrier film 20 , or a portion of the remaining bare chips 10 may be peeled off from the carrier film 20 , while the other portion of the bare chips 10 remain unchanged.

[0094] S320, see Figure 6 , the peeled die 10 is placed on the empty position 21 .

[0095] It is understandable that step S310 and step S320 are described with the remaining multiple dies 10 as a whole. In the actual operation of the above steps S310 and S320, the remaining dies 10 can be peeled off one by one and then placed on the empty space 21. After the remaining dies 10 are peeled off from the carrier film 20, the empty space 21 can also be formed at the position of the carrier film 20 corresponding to the die 10. After the other dies 10 are subsequently peeled off, the other dies 10 peeled off can also be placed on the empty space 21.

[0096] It is understandable that when the chip mounting machine is used to operate the multiple dies 10 on the carrier film 20, a coordinate system can be established according to the image of the carrier film 20, so as to determine the positions of the multiple dies 10 on the carrier film 20 and determine the path that the pick-up tool in the chip mounting machine needs to move when picking up the dies 10. In the embodiment of the present disclosure, when adjusting the positions of the remaining dies 10 on the carrier film 20, at least a portion of the dies 10 are peeled off from the carrier film 20, and then the dies 10 are placed on the empty space 21, so that when a new image of the carrier film 20 is subsequently formed and a new coordinate system is established based on the new carrier film 20, the new coordinate system can overlap with the original coordinate system, so that when the adjusted remaining dies 10 are picked up according to the new image of the carrier film and the new coordinate system, there is no need to recalculate and plan the required path of the pick-up tool. Such a setting can effectively simplify the subsequent picking process of the remaining dies 10 on the carrier film 20 by the chip mounting machine, ensure the accuracy of the picking process, and improve the efficiency of chip mounting.

[0097] Continue reading Figure 6 In the case where the positions of the remaining die 10 on the carrier film 20 are adjusted by the methods provided in the above steps S310 and S320, after the positions of the remaining die 10 on the carrier film 20 are adjusted, in the first direction X parallel to the carrier film 20, the distance L1 between two adjacent die 10 may be greater than or equal to the size of the die 10 in the first direction X. After the positions of the remaining die 10 on the carrier film are adjusted, in the second direction Y parallel to the carrier film 20, the distance L2 between two adjacent die 10 may be greater than or equal to the size of the die 10 in the second direction Y.

[0098] In this way, in the first direction X, the spacing between two adjacent bare chips 10 can be larger, and in the second direction Y, the spacing between two adjacent bare chips 10 can also be larger. Even if the carrier film 20 is subsequently taken out of the chip mounting machine and the carrier film 20 is loose and drooping, it is not easy for the two adjacent bare chips 10 to collide with each other, thereby effectively protecting the bare chips 10.

[0099] In some embodiments, the remaining plurality of dies 10 after adjustment may be randomly distributed on a plurality of vacancies of the carrier film 20. At this time, two adjacent dies 10 may belong to the same level or different levels. The distance between a pair of adjacent dies 10 may be equal to or different from the distance between another pair of adjacent dies 10. The remaining plurality of dies 10 may be concentrated in one area of ​​the carrier film 20, or may be respectively concentrated in different areas of the carrier film 20, or may be evenly dispersed on the carrier film 20.

[0100] Figure 6It shows the situation that two adjacent dies 10 belong to the same level C, while two adjacent dies 10 belong to different levels C. Figure 6 It also shows that in the first direction X parallel to the carrier film 20 , the distance L1 between a pair of adjacent die 10 is equal to the distance L1 between another pair of adjacent die 10 . Figure 6 It also shows that the remaining plurality of dies 10 are concentrated and distributed in one area of ​​the carrier film 20 .

[0101] In other embodiments, Figure 8 As shown, in order to simplify the adjustment process of the chip mounting machine on the remaining bare die 10 and facilitate the subsequent chip mounting machine to pick up the remaining bare die 10 after adjustment, step S300 may include S330.

[0102] S330 , arranging the remaining bare chips 10 into at least one row. Figure 8 In the figure, the remaining bare chips 10 are arranged in two rows as an example.

[0103] It is understandable that the “at least one row” mentioned here is not limited to at least one row along the first direction X parallel to the carrier film 20 in the above embodiment, but may also be at least one row along other directions parallel to the carrier film 20 (such as the above second direction).

[0104] At this time, arranging the remaining bare chips into at least one row may be achieved through step S310 and step S320 or may not be achieved through step S310 and step S320.

[0105] In some examples, the number of dies 10 in each row of dies 10 may be the same. In other examples, such as Figure 8 As shown, the number of dies 10 in each row of dies 10 may vary.

[0106] For some examples, see Figure 8 , step S330 may include step S331.

[0107] S331 , after the dies 10 belonging to the same level C are arranged, the dies 10 belonging to another level C are arranged.

[0108] In this way, the distance between the multiple bare chips 10 belonging to the same level C in the remaining bare chips 10 after adjustment is closer. When the chip mounting machine sorts the multiple bare chips 10 belonging to the same level C, the picking efficiency of the chip mounting machine can be higher, which is beneficial to improving the efficiency of chip mounting.

[0109] In some other embodiments, Fig. 9 and Fig.10As shown, the above step S300 may include step S340 and step S350.

[0110] S340, such as Fig. 9 As shown, the remaining dies 10 are divided into at least one die group 101. The distance between any two adjacent dies 10 in the die group 101 is less than a preset distance.

[0111] In the embodiment of the present application, there is no limitation on the number of die groups 101 into which the remaining die 10 is divided, and the remaining die 10 can be divided according to actual needs. Fig. 9 In the example, the remaining die 10 is divided into five die groups 101. It is understandable that, in addition to the die 10 in the die group 101, the remaining die 10 on the carrier film 20 may also include other die 10. The distance between the other die mentioned here is greater than or equal to the preset distance, and the spacing between the other die and the die 10 in the die group 101 is also greater than or equal to the preset distance.

[0112] In some examples, the number of dies 10 in a die group 101 may be the same. In other examples, the number of dies 10 in a die group 101 may be different. In still other examples, Fig. 9 As shown, the number of dies 10 in some die groups 101 may be the same, and the number of dies 10 in another part of the die groups 101 may be different. Fig. 9 The numbers of dies 10 in the five die groups 101 shown may be 4, 4, 3, 3, and 2, respectively.

[0113] In some examples, such as Fig. 9 As shown, the multiple dies 10 in one die group 101 may all belong to the same level C. In other examples, the multiple dies 10 in one die group 101 may also belong to different levels C.

[0114] S350, such as Fig. 9 As shown, the position of at least one die 10 in the die group 101 is adjusted so that the distance between any two adjacent die 10 in the die group 101 is greater than or equal to a preset distance.

[0115] Here, “adjusting the position of at least one die 10 in the die group 101 ” may mean adjusting the position of one die 10 in the die group 101 , or may mean adjusting the positions of multiple die 10 in the die group 101 .

[0116] The embodiment of the present disclosure first divides the plurality of dies 10 on the carrier film 20 into a plurality of die groups 101, and then adjusts the position of at least one die 10 in the die group 101, so that the spacing between any two adjacent dies 10 in the die group 101 is greater than or equal to the preset distance. In this way, the embodiment of the present disclosure can only adjust the positions of some of the remaining dies 10 whose spacing is less than the preset distance, so that the number of dies 10 that need to be adjusted can be small, which is conducive to improving the speed and efficiency of adjusting the remaining dies 10, and further conducive to improving the speed of chip mounting.

[0117] In order to further simplify the process of adjusting the positions of the remaining dies 10 , some dies 10 may be selected from the die group 101 , and their positions may be kept unchanged, while the positions of the remaining dies 10 in the die group 101 are adjusted.

[0118] On this basis, for some examples, see Fig. 9 and Fig.10 , the above step S350 may include step S351 and step S352.

[0119] S351, such as Fig. 9 As shown, the plurality of dies 10 in the die group 101 are divided into a first die 10 a and a second die 10 b .

[0120] The first die 10a is the die 10 that is not expected to be adjusted in position. The second die 10b is the die 10 that is expected to be adjusted in position. For example, Fig. 9 As shown, the first die 10 a may be any die 10 in the die group 101 , and the second die 10 b may be another die 10 in the die group 101 .

[0121] In the embodiment of the present application, there is no restriction on the number of the first die 10a and the number of the second die 10b, and the design can be made according to actual needs. The selection of the first die 10a and the selection of the second die 10b can be determined according to the positions of the plurality of die 10 in the die group 101, and the present disclosure does not restrict this. Of course, the fewer the number of the second die 10b in the die group 101, the simpler the adjustment process.

[0122] S352, such as Fig.10 As shown, the position of the first die 10a is kept unchanged, and the position of the second die 10b is adjusted.

[0123] For example, the second die 10b can be moved along the first direction X or the second direction Y parallel to the carrier film 20. In this way, the adjustment process of the second die 10b can be relatively simple, thereby facilitating further improving the adjustment efficiency of the positions of the die 10 in the die group 101.

[0124] Of course, when there is no space on the carrier film 20 to arrange the second die 10 b in the first direction X and the second direction Y parallel to the carrier film 20 , the position of the second die 10 b may not be adjusted along the first direction X and the second direction Y.

[0125] Exemplarily, when adjusting the position of the second die 10 b , the above steps S310 and S320 may also be used for adjustment, that is, the second die 10 b is peeled off from the carrier film 20 , and then the peeled second die 10 b is placed on the empty position 21 .

[0126] In the process of adjusting the positions of the remaining die 10 on the carrier film 20, the embodiment of the present disclosure first divides the remaining die 10 into at least one die group 101, then divides the multiple die 10 in the die group 101 into the first die 10a and the second die 10b, and finally adjusts the position of the second die 10b, while keeping the position of the first die 10a unchanged. In this way, in the process of adjusting the positions of the remaining die 10 on the carrier film 20, the number of the remaining die 10 that needs to be adjusted can be small, which is conducive to further improving the speed and efficiency of adjusting the remaining die 10, and further conducive to improving the speed of chip mounting.

[0127] In some embodiments, step S300 may include: adjusting the positions of the remaining dies 10 on the carrier film 20 when the carrier film 20 is in a taut state.

[0128] In this way, on the one hand, it is convenient for the chip mounting machine to pick up and place the remaining bare dies 10 on the carrier film 20, thereby facilitating the efficiency of adjusting the positions of the remaining bare dies 10 on the carrier film 20. On the other hand, it can also prevent the carrier film 20 from sagging and causing the bare dies 10 that have not been adjusted on the carrier film 20 to collide with each other, thereby ensuring the yield of the remaining bare dies 10 in the process of adjusting the positions of the remaining bare dies 10 on the carrier film 20.

[0129] In some embodiments, Fig.11 As shown, after step S300, the chip mounting method further includes step S401.

[0130] S401, generating a first image M1 of the carrier film 20 including the remaining die 10. The first image M1 may be as follows: Figure 6 As shown, it can also be Figure 8 As shown, you can also Fig.10 In this way, after adjusting the positions of the remaining die 10 on the carrier film 20 , the chip mounting machine can determine the positions of the remaining die 10 according to the first image M1 , thereby planning the order of picking up the remaining die 10 .

[0131] S400, such as Figure 12 to Figure 14 As shown, the remaining dies 10 belonging to different levels C are moved to different substrates 30 (eg, a first substrate 31 and a second substrate 32 ) in sequence.

[0132] Figure 12 to Figure 14 In the example, the bare chips 10 of the first level C1 are first moved onto the first substrate 31 , and then the bare chips 10 of the second level C2 are moved onto the second substrate 32 , wherein the first substrate 31 and the second substrate 32 are different from the above-mentioned substrate 30 .

[0133] It is understandable that when the space provided by the substrate 30 is insufficient to accommodate the die 10, a new substrate 30 may be used to carry the die 10. However, the grade of the die 10 carried on the substrate 30 should be the same.

[0134] In some examples, based on Figure 8 The first image M1 shown, Fig.11 As shown, step S400 includes step S410 and step S420.

[0135] S410, see Fig.12 , the dies 10 belonging to the same level C are moved to one substrate 30 according to the first image M1 . Fig.12 In the example, moving the die 10 belonging to the first level C1 onto the first substrate 31 according to the first image M1 is taken as an example.

[0136] S420, see Fig.13 and Fig.14 , generating a second image M2 of the carrier film 20 including the remaining die 10, and assigning another level C (eg, Fig.13 The die 10 of the second level C2 shown is moved to another substrate (eg Fig.14 The second image M2 may be as shown in FIG. 1 , and the remaining bare chips 10 on the carrier film 20 may be moved to the second substrate 32 until all the remaining bare chips 10 on the carrier film 20 are moved. Fig.13 shown.

[0137] Figure 6 , Figure 8 and Fig.10 The remaining dies 10 include dies 10 of two levels C (first level C1 and second level C2) as an example. Therefore, after the dies 10 of another level (second level C2) are moved to another substrate 30 (i.e., second substrate 32) according to the second image M2, the remaining dies 10 on the carrier film 20 can be completely moved.

[0138] After the bare die 10 on the carrier film 20 is moved, the embodiment of the present application will regenerate an image (for example, the first image M1 and the second image M2), so that the remaining bare die 10 can be picked up according to the latest image, which effectively ensures the accuracy of the operation when picking up the remaining bare die 10, which is conducive to improving the efficiency of chip mounting.

[0139] In the chip mounting method provided in the embodiment of the present disclosure, a carrier film 20 provided with a plurality of bare chips 10 is first provided, and the plurality of bare chips 10 are divided into a plurality of grades C. Subsequently, a plurality of bare chips 10 in grade C (i.e., target grade C0) having the largest number of bare chips 10 among the plurality of grades C are moved onto a substrate 30, and the positions of the remaining bare chips 10 on the carrier film 20 are adjusted so that, among the remaining bare chips 10, the distance between any two adjacent bare chips 10 is greater than or equal to a preset distance, and finally, the bare chips 10 belonging to different grades among the remaining bare chips 10 are moved to different substrates 30 in sequence. In this way, after the bare die 10 of the target grade C0 on the carrier film 20 is moved, the positions of the remaining bare die 10 on the carrier film 20 can be adjusted to make the spacing between the remaining bare die 10 larger, so that the remaining bare die 10 on the carrier film 20 are not easy to collide with each other when the carrier film 20 is relaxed and drooped, thereby effectively ensuring the yield of the remaining bare die 10, avoiding the problem of the remaining bare die 10 being damaged or broken due to mutual collision, and improving the reliability of the chip mounting process and the yield of the packaged chip.

[0140] Compared with the solution in the related art of moving the remaining dies belonging to different levels to a new carrier film, the embodiment of the present application adjusts (or integrates) the positions of the remaining dies 10 on the same carrier film 20, without adding a new carrier film 20, and without adding a process of moving the remaining dies 10 to different carrier films 20, thereby reducing costs, making the chip mounting process simpler, and increasing chip mounting efficiency.

[0141] At the same time, compared with the solution of the related art in which a wafer expansion ring is formed on the side of the carrier film away from the bare chip, the embodiment of the present application does not require a new wafer expansion ring, nor does it require an increase in the installation process of the wafer expansion ring, thereby reducing costs, making the chip mounting process simpler, and increasing chip mounting efficiency.

[0142] An embodiment of the present application also provides a chip packaging method, which may include the chip mounting method provided by any of the above embodiments.

[0143] In addition to the above-mentioned chip mounting method, the chip packaging method provided in the embodiment of the present disclosure may also include steps such as wafer preprocessing, chip binding and testing.

[0144] It can be understood that the beneficial effects that can be achieved by the chip packaging method provided in the embodiment of the present application are the same as the beneficial effects that can be achieved by the chip mounting method provided in any of the above embodiments, and will not be repeated here.

[0145] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A chip mounting method, characterized in that: include: providing a carrier film provided with a plurality of dies, the plurality of dies being divided into a plurality of levels; moving a plurality of dies of a target level onto a substrate, wherein the target level is a level having the largest number of dies among the plurality of levels; Adjusting the positions of the remaining bare chips on the carrier film so that the distance between any two adjacent bare chips among the remaining bare chips is greater than or equal to a preset distance; The remaining dies belonging to different levels are moved to different substrates in sequence.

2. The chip mounting method according to claim 1, characterized in that: The adjusting the positions of the remaining bare chips on the carrier film comprises: Arrange the remaining dies into at least one row.

3. The chip mounting method according to claim 2, characterized in that: The remaining dies include a plurality of levels; and arranging the remaining dies into at least one row includes: After the die belonging to the same level are arranged, the die belonging to another level are arranged.

4. The chip mounting method according to claim 1, characterized in that: The adjusting the positions of the remaining bare chips on the carrier film comprises: Divide the remaining die into at least one die group; the distance between any two adjacent die in the die group is less than the preset distance; The position of at least one die in the die group is adjusted so that a distance between any two adjacent die in the die group is greater than or equal to the preset distance.

5. The chip mounting method according to claim 4, characterized in that: Adjusting the position of at least one die in the die group includes: dividing a plurality of dies in the die group into a first die and a second die; The position of the first die is kept unchanged, and the position of the second die is adjusted.

6. The chip mounting method according to claim 1, characterized in that: The plurality of bare chips are arranged into a plurality of rows along a first direction parallel to the carrier film, and the plurality of bare chips are arranged into a plurality of columns along a second direction parallel to the carrier film, and the first direction intersects with the second direction; After a plurality of dies of a target grade are moved onto the substrate, a plurality of vacancies are formed on the carrier film; The adjusting the positions of the remaining bare chips on the carrier film comprises: peeling at least a portion of the remaining dies from the carrier film; The peeled die is placed on the vacant position.

7. The chip mounting method according to claim 6, characterized in that: After adjusting the positions of the remaining dies on the carrier film, in the first direction, the spacing between two adjacent dies is greater than or equal to the size of the dies in the first direction; After the positions of the remaining dies on the carrier film are adjusted, in the second direction, the spacing between two adjacent dies is greater than or equal to the size of the dies in the second direction.

8. The chip mounting method according to any one of claims 1 to 7, characterized in that: The preset distance is the minimum size of the die.

9. The chip mounting method according to any one of claims 1 to 7, characterized in that: The number of remaining dies is less than the number of dies of the target grade.

10. The chip mounting method according to any one of claims 1 to 7, characterized in that: The adjusting the positions of the remaining bare chips on the carrier film comprises: When the carrier film is in a tensioned state, positions of the remaining bare chips on the carrier film are adjusted.

11. The chip mounting method according to any one of claims 1 to 7, characterized in that: After adjusting the position of the remaining die on the carrier film, the chip mounting method further includes: generating a first image of the carrier film including the remaining die; The method of moving the remaining bare chips belonging to different levels to different substrates in sequence includes: moving the bare chips belonging to the same level to one substrate according to the first image; generating a second image of a carrier film including the remaining bare chips, and moving the bare chips of another level to another substrate according to the second image until all the remaining bare chips on the carrier film are moved.

12. A chip packaging method, characterized in that: include: A chip mounting method as claimed in any one of claims 1 to 11.

Images