Semiconductor structure and forming method thereof
By forming a high density padding layer on the side walls and bottom surfaces of the isolation trench during semiconductor manufacturing and filling the isolation layer thereon, the problem of forming a depression area at the top corner of the STI is solved, and the manufacturing efficiency and yield of the semiconductor structure are significantly improved.
Patent Information
- Application Number
- CN202510065797.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-15
- Publication Date
- 2025-04-29
AI Technical Summary
During semiconductor manufacturing, a recessed area is easily formed at the corners of the STI, resulting in the formation of parasitic transistors, increasing the risk of current leakage and threshold voltage reduction, and increasing the risk of gate material residue. The existing solutions are complex and inefficient.
By forming a high density pad layer on the side walls and bottom surfaces of the isolation trench and filling it with an isolation layer, the density of the pad layer is greater than the density of the isolation layer to form an isolation structure and reduce the formation of the depression area.
The depression depth at the top corner of the isolation structure is significantly reduced, the leakage current of the semiconductor structure is reduced, the manufacturing yield is improved, the manufacturing process is simplified, and the efficiency is improved.
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Figure CN119905453A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art
[0002] STI (Shallow Trench Isolation) is a process technology for realizing device isolation in integrated circuits. It is formed by etching shallow trenches on a silicon substrate and filling the shallow trenches with insulating materials. In the etching process and other processing processes after the formation of STI, a recessed area, i.e., a divot, is easily formed at the corner of the top of the STI. In the process of forming a gate structure above the silicon substrate, the polysilicon material used to form the gate electrode can be filled into the recessed area, thereby forming an unexpected parasitic transistor in the silicon substrate. The presence of the parasitic transistor will cause the semiconductor structure to generate additional current leakage and a reduction in threshold voltage during operation. In addition, the presence of the recessed area will also increase the risk of residual gate material in the process of forming the gate structure.
[0003] In order to reduce the negative impact of the recessed area at the top corner of the STI on the performance of the semiconductor structure, the industry has adopted a variety of methods, such as precisely controlling the chemical mechanical polishing process of the insulating material to ensure uniform STI thickness and adjusting the wet etching conditions to reduce over-etching; for example, after forming the shallow trench, the silicon nitride covering the surface of the silicon substrate is etched back to leave a margin for etching the insulating material at the corner of the STI, thereby reducing the probability of the recessed area. However, the above method requires precise control and adjustment, which not only increases the difficulty of the semiconductor structure manufacturing process and reduces the manufacturing efficiency of the semiconductor structure, but also has an insignificant effect in reducing the generation of the recessed area.
[0004] Therefore, how to effectively reduce the probability of a recessed area at the top corner of the STI while simplifying the manufacturing process of the semiconductor structure and improving the manufacturing efficiency and manufacturing yield of the semiconductor structure is a technical problem that needs to be solved urgently. Summary of the invention
[0005] The present invention provides a semiconductor structure and a method for forming the same, which are used to simplify the manufacturing process of the semiconductor structure and improve the manufacturing efficiency and manufacturing yield of the semiconductor structure while effectively reducing the probability of a recessed area being generated at a corner of a top of a STI.
[0006] According to some embodiments, the present invention provides a method for forming a semiconductor structure, comprising the following steps:
[0007] Providing a substrate having an isolation trench;
[0008] forming a liner layer covering at least the sidewall surface and the bottom surface of the isolation trench;
[0009] An isolation layer is formed to fill the isolation trench and cover the liner layer, wherein the density of the liner layer is greater than the density of the isolation layer, so as to form an isolation structure including the isolation trench, the liner layer and the isolation layer.
[0010] In some embodiments, the substrate is a silicon substrate; the specific steps of forming a liner layer covering at least the top sidewall of the isolation trench include:
[0011] The sidewall surface and the bottom surface of the isolation trench are oxidized by a thermal oxidation process to form the liner layer which continuously covers the sidewall surface and the bottom surface of the isolation trench.
[0012] In some embodiments, the specific steps of oxidizing the sidewall surface and the bottom surface of the isolation trench by using a thermal oxidation process include:
[0013] The sidewall surface and the bottom surface of the isolation trench are oxidized by an in-situ water vapor generation process.
[0014] In some embodiments, the thickness of the liner layer is
[0015] In some embodiments, the specific steps of forming an isolation layer filling the isolation trench and covering the liner layer include:
[0016] An oxide material is deposited in the isolation trench by using a chemical vapor deposition process to form the isolation layer which fills the isolation trench and covers the liner layer.
[0017] In some embodiments, after forming an isolation layer filling the isolation trench and covering the liner layer, the method further includes the following steps:
[0018] A wet etching process is used to etch part of the isolation layer to reduce the height of the isolation layer. The wet etchant used in the wet etching process has a lower etching rate for the liner layer than for the isolation layer.
[0019] In some embodiments, the wet etchant is hydrofluoric acid.
[0020] In some embodiments, the top corner of the isolation layer remaining after the wet etching process has a recess, and the depth of the recess is less than
[0021] According to some other embodiments, the present invention further provides a semiconductor structure, including:
[0022] substrate;
[0023] The isolation structure comprises an isolation trench in the substrate, a liner layer at least covering the sidewall surface and the bottom surface of the isolation trench, and an isolation layer filling the isolation trench and covering the liner layer, wherein the density of the liner layer is greater than the density of the isolation layer.
[0024] In some embodiments, the liner layer is a thermal oxide layer, and the isolation layer is a deposited oxide layer.
[0025] In some embodiments, the thickness of the thermal oxide layer is
[0026] In some embodiments, the top corner of the isolation layer has a recess, and the depth of the recess is less than
[0027] The semiconductor structure and the method for forming the same provided by the present invention form a liner layer that at least covers the sidewall surface and the bottom surface of the isolation trench and an isolation layer that fills the isolation trench and covers the liner layer, and the density of the liner layer is greater than the density of the isolation layer, so that the liner layer has a higher corrosion resistance than the isolation layer, and the etching rate of the liner layer at the top corner of the isolation trench can be made lower than the etching rate of the isolation layer in the subsequent etching process, so that the recess depth at the top corner of the isolation structure can be significantly reduced, and the negative effects such as the leakage current of the semiconductor structure can be reduced, thereby helping to improve the manufacturing yield of the semiconductor structure. At the same time, by forming the liner layer with a higher density in the isolation trench, it is also helpful to further enhance the isolation effect of the isolation structure including the liner layer and the isolation layer. In addition, the present invention is simple to operate, does not require precise control and adjustment of the chemical mechanical polishing process, and does not require back etching of the silicon nitride layer to leave a margin for etching the liner layer and / or the isolation layer at the corner, thereby helping to simplify the manufacturing process of the semiconductor structure and improve the manufacturing efficiency of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present invention;
[0029] Figure 2 is a schematic diagram of the structure after a liner layer is formed in an isolation trench in a specific embodiment of the present invention;
[0030] Figure 3 is a schematic diagram of a structure after an isolation layer is formed in an isolation trench in a specific embodiment of the present invention;
[0031] Figure 4 is a structural schematic diagram of the initial moment of etching the isolation layer using a wet etching process in a specific embodiment of the present invention;
[0032] Figure 5 is a structural schematic diagram of etching the isolation layer and the liner layer using a wet etching process in a specific embodiment of the present invention;
[0033] Figure 6 is a schematic structural diagram of a specific embodiment of the present invention after the isolation layer and the liner layer are etched for a period of time using a wet etching process;
[0034] Figure 7 It is a TEM comparison diagram of an isolation structure with liner layers of different thicknesses formed in a specific embodiment of the present invention.
[0035] Description of Reference Numerals
[0036] 20 Substrate
[0037] 21 Isolation trench
[0038] 22 cushion layer
[0039] 23 Silicon nitride mask layer
[0040] 30 Isolation Layer DETAILED DESCRIPTION
[0041] The specific implementation manner of the semiconductor structure and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.
[0042] This specific embodiment provides a method for forming a semiconductor structure. Figure 1 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present invention. Figure 1 As shown, the method for forming the semiconductor structure comprises the following steps:
[0043] Step S11, providing a substrate having an isolation trench;
[0044] Step S12, forming a liner layer that at least covers the sidewall surface and the bottom surface of the isolation trench;
[0045] Step S13, forming an isolation layer filling the isolation trench and covering the liner layer, wherein the density of the liner layer is greater than the density of the isolation layer, so as to form an isolation structure including the isolation trench, the liner layer and the isolation layer.
[0046] Figure 2 is a schematic diagram of a structure after a liner layer is formed in an isolation trench in a specific embodiment of the present invention. Figure 2 As shown, the substrate 20 is a silicon substrate; the specific steps of forming the liner layer 22 covering at least the sidewall surface and the bottom surface of the isolation trench 21 include:
[0047] The sidewall surface and the bottom surface of the isolation trench 21 are oxidized by a thermal oxidation process to form the liner layer 22 that continuously covers the sidewall surface and the bottom surface of the isolation trench 21 .
[0048] Specifically, the substrate 20 is a silicon substrate, and the substrate 20 includes a top surface and a bottom surface relatively distributed along a first direction D1. In one example, before etching the substrate 20, a dielectric layer (not shown in the figure) covering the top surface of the substrate 20 can also be formed by a thermal oxidation process to protect the top surface of the portion of the substrate 20 that does not need to be etched during the process of etching the substrate 20 to form the isolation trench 21. In the process of forming the isolation trench 21, a silicon nitride mask layer 23 can be formed above the substrate 20 first, and the silicon nitride mask layer 23 can be patterned to form an etching window. The substrate 20 is etched downward along the etching window to form the isolation trench 21 extending from the top surface of the substrate 20 along the first direction D1 to the inside of the substrate 20. In one example, the substrate 20 includes a plurality of isolation trenches 21 arranged at intervals along a second direction D2, and the area between adjacent isolation trenches 21 is used as an active area. Wherein, the second direction D2 is parallel to the top surface of the substrate 20.
[0049] There are two main reasons for the depression at the top corner of the isolation structure: on the one hand, when the insulating dielectric material is directly filled in the isolation trench 21, the filled insulating dielectric material will form a stress concentration area at the top corner of the isolation trench 21, and the insulating dielectric material located in the stress concentration area is more likely to be over-corroded in the subsequent etching process, thereby generating a depression; on the other hand, the density of the filling layer formed by depositing the insulating dielectric material in the isolation trench 21 by the CVD (Chemical Vapor Deposition) process is poor, and it is more likely to be corroded by the etchant used in the subsequent etching processes, thereby generating a depression. In this specific embodiment, before forming an isolation layer filled in the isolation trench and covering the liner layer, a thermal oxidation process is first used to oxidize the side wall surface and bottom surface of the isolation trench 21 to form a thermal oxidation layer that continuously covers the side wall surface and bottom surface of the isolation trench 21, and the thermal oxidation layer is used as the liner layer 22. Since the density of the liner layer 22 formed by the thermal oxidation process is greater than the density of the isolation layer formed by the deposition process, on the one hand, the liner layer 22 with greater density can reduce the etching rate at the corner of the top of the isolation groove 21 during the subsequent wet etching process, thereby significantly reducing the recess depth at the top corner of the isolation structure; on the other hand, by first forming the liner layer 22 with higher density covering the side wall and bottom surface of the isolation groove 21, and then depositing the isolation layer, the stress concentration effect at the top corner of the isolation groove 21 can be reduced, thereby further reducing the recess depth at the top corner of the isolation structure.
[0050] In order to further improve the quality of the liner layer 22, in some embodiments, the specific steps of oxidizing the sidewall surface and the bottom surface of the isolation trench 21 by a thermal oxidation process include:
[0051] The sidewall surface and the bottom surface of the isolation trench 21 are oxidized by an in-situ steam generation (ISSG) process.
[0052] In some embodiments, the thickness of the thermal oxide layer is
[0053] Specifically, by increasing the thickness of the thermal oxide layer so that the thickness of the thermal oxide layer is Thus, the thermal oxide layer can fully cover the top corner of the isolation trench 21, avoiding the partial corner of the top of the isolation trench 21 being covered by the subsequently deposited isolation layer due to the thickness of the thermal oxide layer being too thin, so as to further reduce the recess depth at the top corner of the isolation structure. At the same time, the thickness of the thermal oxide layer is set to Avoid affecting the subsequent filling of the isolation layer due to the excessive thickness of the thermal oxide layer.
[0054] In some embodiments, the top corner of the isolation layer 30 remaining after the wet etching process has a recess, and the depth of the recess is less than
[0055] Figure 7 TEM comparison diagram of an isolation structure with different thicknesses of liner layers formed in a specific embodiment of the present invention. In one example, the thickness of the liner layer 22 is When the depth of the depression is Figure 7 As shown in (a), the depth of the depression is about 6.3 nm; the thickness of the liner layer 22 is When the depth of the depression is Figure 7 As shown in (b), the depth of the depression is about 0.8 nm. Figure 7 It can be seen that by increasing the thickness of the liner layer 22, not only the depth of the depression can be significantly reduced, but also the depression can be made smoother in the width direction (for example, the second direction D2). It can also make the top corner of the isolation structure more rounded, thereby further reducing the leakage current of the semiconductor structure and improving the performance of static random access memory (SRAM).
[0056] Figure 3 is a schematic diagram of a structure after an isolation layer is formed in an isolation trench in a specific embodiment of the present invention. Figure 3 As shown, the specific steps of forming the isolation layer 30 filling the isolation trench 21 and covering the liner layer 22 include:
[0057] An oxide material is deposited in the isolation trench 21 by a chemical vapor deposition process to form the isolation layer 30 that fills the isolation trench 21 and covers the liner layer 22 .
[0058] In order to reduce the height of the isolation structure to facilitate the implementation of subsequent processes, in some embodiments, after forming the isolation layer 30 filling the isolation trench 21 and covering the liner layer 22, the following steps are further included:
[0059] A wet etching process is used to etch part of the isolation layer 30 to reduce the height of the isolation layer 30 . The wet etchant used in the wet etching process has a lower etching rate for the liner layer 22 than for the isolation layer 30 .
[0060] In some embodiments, the wet etchant is hydrofluoric acid.
[0061] Figure 4 is a structural schematic diagram of the initial moment of etching the isolation layer using a wet etching process in a specific embodiment of the present invention, Figure 5 is a structural schematic diagram of etching the isolation layer and the liner layer using a wet etching process in a specific embodiment of the present invention, Figure 6 It is a schematic diagram of the structure after the isolation layer and the liner layer are etched for a period of time by a wet etching process in a specific embodiment of the present invention. Figure 4 , Figure 5 and Figure 6 The solid arrow in the figure indicates the direction in which the wet etchant etches the isolation structure, and the length of the solid arrow indicates the etching rate of the wet etchant. The following description is made by taking the case that the material of the liner layer 22 and the material of the isolation layer 30 are both silicon dioxide, and the density of the liner layer 22 is greater than the density of the isolation layer 30. For example, when forming Figure 2 After the liner layer 22 is formed, the silicon nitride mask layer 23 and part of the liner layer 22 are removed by chemical mechanical polishing. Next, the isolation layer 30 is deposited in the isolation trench 21 by chemical vapor deposition, so that the isolation layer 30 fills the isolation trench 21 and covers part of the top surface of the substrate 20, so that the isolation layer 30 protrudes from the top surface of the substrate 20, and the isolation layer 30 completely covers the liner layer 22. When the isolation structure is etched by a wet etchant such as hydrofluoric acid, the wet etchant first contacts only the exposed isolation layer 30, and the wet etchant has the same etching rate for the isolation structure in all directions, such as Figure 4 After the wet etchant etches away a portion of the isolation layer 30, the liner layer 22 is exposed. Since the density of the liner layer 22 is greater than the density of the isolation layer 30, the etching rate of the wet etchant on the liner layer 22 is less than the etching rate of the wet etchant on the isolation layer 30, as shown in FIG. Figure 5 After etching continues for a period of time (for example, after the etching endpoint is reached), the liner layer 22 is not etched or is only slightly etched, so that only the sidewall of the isolation layer 30 forms a shallow depression, as shown in FIG. Figure 6 shown.
[0062] This specific embodiment also provides a semiconductor structure. The semiconductor structure can be used as follows Figure 1-Figure 7 The semiconductor structure is formed by the method of forming the semiconductor structure shown in FIG. Figure 6 .like Figure 1-Figure 7 As shown, the semiconductor structure comprises:
[0063] Substrate 20;
[0064] The isolation structure includes an isolation trench 21 located in the substrate 20, a liner layer 22 covering at least the side wall surface and the bottom surface of the isolation trench 21, and an isolation layer 30 filling the isolation trench 21 and covering the liner layer 22, wherein the density of the liner layer 22 is greater than the density of the isolation layer 30.
[0065] In this specific embodiment, the liner layer 22 is arranged between the isolation layer 30 and the inner wall of the isolation groove 21, and the density of the liner layer 22 is greater than the density of the isolation layer 30. On the one hand, the liner layer 22 with greater density can reduce the etching rate at the corner of the top of the isolation groove 21 during the subsequent wet etching process, thereby significantly reducing the recess depth at the top corner of the isolation structure; on the other hand, by first forming the liner layer 22 with higher density covering the side wall surface and bottom surface of the isolation groove 21, and then depositing the isolation layer 30, the stress concentration effect at the top corner of the isolation groove 21 can be reduced, thereby further reducing the recess depth at the top corner of the isolation structure.
[0066] In some embodiments, the liner layer 22 is a thermal oxide layer, and the isolation layer 30 is a deposited oxide layer.
[0067] In order to further reduce the recess depth at the top corner of the isolation structure and avoid affecting the filling effect of the isolation layer 30, in some embodiments, the thickness of the thermal oxide layer is
[0068] In some embodiments, the top corner of the isolation layer 30 has a depression, and the depth of the depression is less than
[0069] The semiconductor structure and the method for forming the same provided in this specific embodiment, by forming a liner layer covering at least the sidewall surface and the bottom surface of the isolation trench and an isolation layer filled in the isolation trench and covering the liner layer, and the density of the liner layer is greater than the density of the isolation layer, so that the liner layer has a higher corrosion resistance than the isolation layer, and the etching rate of the liner layer at the top corner of the isolation trench can be made smaller than the etching rate of the isolation layer in the subsequent etching process, so that the recess depth at the top corner of the isolation structure can be significantly reduced, and the negative effects such as the leakage current of the semiconductor structure can be reduced, thereby helping to improve the manufacturing yield of the semiconductor structure. At the same time, by forming the liner layer with a higher density in the isolation trench, it is also helpful to further enhance the isolation effect of the isolation structure including the liner layer and the isolation layer. In addition, the specific embodiment is simple to operate, does not require precise control and adjustment of the chemical mechanical polishing process, and does not require back etching of the silicon nitride layer to leave a margin for etching the liner layer and / or the isolation layer at the corner, thereby helping to simplify the manufacturing process of the semiconductor structure and improve the manufacturing efficiency of the semiconductor structure.
[0070] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A method for forming a semiconductor structure, characterized in that: The steps include: Providing a substrate having an isolation trench; forming a liner layer covering at least the sidewall surface and the bottom surface of the isolation trench; An isolation layer is formed to fill the isolation trench and cover the liner layer, wherein the density of the liner layer is greater than the density of the isolation layer, so as to form an isolation structure including the isolation trench, the liner layer and the isolation layer.
2. The method for forming a semiconductor structure according to claim 1, wherein: The substrate is a silicon substrate; The specific steps of forming a liner layer covering at least the sidewall surface and the bottom surface of the isolation trench include: The sidewall surface and the bottom surface of the isolation trench are oxidized by a thermal oxidation process to form the liner layer which continuously covers the sidewall surface and the bottom surface of the isolation trench.
3. The method for forming a semiconductor structure according to claim 2, wherein: The specific steps of oxidizing the sidewall surface and the bottom surface of the isolation trench by using a thermal oxidation process include: The sidewall surface and the bottom surface of the isolation trench are oxidized by an in-situ water vapor generation process.
4. The method for forming a semiconductor structure according to claim 2, wherein: The thickness of the lining layer is 5. The method for forming a semiconductor structure according to claim 1, wherein: The specific steps of forming an isolation layer filled in the isolation trench and covering the liner layer include: An oxide material is deposited in the isolation trench by using a chemical vapor deposition process to form the isolation layer which fills the isolation trench and covers the liner layer.
6. The method for forming a semiconductor structure according to claim 5, characterized in that: After forming an isolation layer filling the isolation trench and covering the liner layer, the method further includes the following steps: A wet etching process is used to etch part of the isolation layer to reduce the height of the isolation layer. The wet etchant used in the wet etching process has a lower etching rate for the liner layer than for the isolation layer.
7. The method for forming a semiconductor structure according to claim 6, wherein: The wet etchant is hydrofluoric acid.
8. The method for forming a semiconductor structure according to claim 6, wherein: The top corner of the isolation layer remaining after the wet etching process has a depression, and the depth of the depression is less than 9. A semiconductor structure, characterized in that: include: substrate; The isolation structure comprises an isolation trench in the substrate, a liner layer at least covering the sidewall surface and the bottom surface of the isolation trench, and an isolation layer filling the isolation trench and covering the liner layer, wherein the density of the liner layer is greater than the density of the isolation layer.
10. The semiconductor structure according to claim 9, characterized in that: The liner layer is a thermal oxide layer, and the isolation layer is a deposited oxide layer.
11. The semiconductor structure according to claim 10, characterized in that: The thickness of the thermal oxide layer is 12. The semiconductor structure according to claim 11, characterized in that: The top corner of the isolation layer has a depression, and the depth of the depression is less than