Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, the semiconductor structure comprises a semiconductor substrate, the first surface of the semiconductor substrate comprises a first epitaxial layer, a second epitaxial layer, an x direction, a y direction, a plurality of first areas and a plurality of second areas, the x direction and the y direction are perpendicular to each other, and the first areas and the second areas are alternately distributed along the x direction; the plurality of first grooves are positioned in the second epitaxial layer of the plurality of second regions; the second groove and the third groove are located in part of the first groove and extend into the first epitaxial layer, part of the second groove is communicated in the first epitaxial layer, and part of the third groove is communicated in the first epitaxial layer; the metal connecting structures are positioned in the first groove, the second groove and the third groove; and a first through-silicon-via connection structure and a second through-silicon-via connection structure which are located on the second surface of the semiconductor substrate, penetrate through the semiconductor substrate and are electrically connected with the bottom surfaces of the metal connection structures located in the second groove and the third groove respectively.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Metal wiring is an important part of semiconductor technology. In advanced technology nodes, the size of the wiring on the front side of the wafer is severely limited due to the increase in metal wiring density. The back-side power delivery network (BSPDN) process arranges signal lines on the front side of the wafer and power lines on the back side of the wafer to save wiring space and reduce the resistance of the power lines and the coupling noise of the signal lines.

[0003] However, in the current BSPDN process, there is a problem that the metal connection structure and the through-silicon via connection structure are easily misaligned, which affects the contact resistance and even causes the electrical connection between the metal connection structure and the through-silicon via connection structure to be disconnected.

[0004] Therefore, it is necessary to provide a more effective and reliable technical solution to enable the metal connection structure and the through-silicon via connection structure to be precisely connected to improve device reliability. Summary of the invention

[0005] The present application provides a semiconductor structure and a method for forming the same, which can enable a metal connection structure and a through-silicon via connection structure to be precisely connected, thereby improving device reliability.

[0006] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein a first epitaxial layer and a second epitaxial layer are formed on a first surface of the semiconductor substrate, the first surface of the semiconductor substrate includes an x ​​direction and a y direction perpendicular to each other, and the semiconductor substrate includes a plurality of first regions and a second region alternately distributed along the x direction; forming a plurality of first grooves extending along the y direction in the second epitaxial layer of the plurality of second regions; etching a portion of the first groove so that the portion of the first groove extends to the first epitaxial layer to form a second groove and a third groove respectively, wherein the second groove and the third groove are respectively located at different positions along the y direction in different first grooves; etching the first epitaxial layer along the second groove so that a portion of the second groove is connected, and etching the first epitaxial layer along the third groove so that a portion of the third groove is connected; forming a metal connection structure in the first groove, the second groove, and the third groove; forming a first through-silicon via connection structure and a second through-silicon via connection structure on the second surface of the semiconductor substrate, which penetrate the semiconductor substrate and are electrically connected to the bottom surfaces of the metal connection structures located in the second groove and the third groove respectively.

[0007] In some embodiments of the present application, the material of the first epitaxial layer is silicon germanium, and the material of the second epitaxial layer is silicon.

[0008] In some embodiments of the present application, the first through silicon via connection structure is connected to a power source, and the second through silicon via connection structure is grounded.

[0009] In some embodiments of the present application, every two adjacent second grooves are connected and every two adjacent third grooves are connected.

[0010] In some embodiments of the present application, the method for forming the semiconductor structure further includes: forming a transistor structure in the second epitaxial layer of the first region.

[0011] Another aspect of the present application also provides a semiconductor structure, including: a semiconductor substrate, a first surface of the semiconductor substrate is formed with a first epitaxial layer and a second epitaxial layer, the first surface of the semiconductor substrate includes an x ​​direction and a y direction perpendicular to each other, and the semiconductor substrate includes a plurality of first regions and a second region alternately distributed along the x direction; a plurality of first grooves extending along the y direction in the second epitaxial layer located in the plurality of second regions; a second groove and a third groove located in part of the first grooves and extending into the first epitaxial layer, wherein the second groove and the third groove are respectively located at different positions along the y direction in different first grooves, part of the second grooves are connected in the first epitaxial layer, and part of the third grooves are connected in the first epitaxial layer; a metal connection structure located in the first groove, the second groove and the third groove; a first through-silicon via connection structure and a second through-silicon via connection structure located on the second surface of the semiconductor substrate, penetrating the semiconductor substrate and electrically connected to the bottom surface of the metal connection structure located in the second groove and the third groove, respectively.

[0012] In some embodiments of the present application, the material of the first epitaxial layer is silicon germanium, and the material of the second epitaxial layer is silicon.

[0013] In some embodiments of the present application, the first through silicon via connection structure is connected to a power source, and the second through silicon via connection structure is grounded.

[0014] In some embodiments of the present application, every two adjacent second grooves are connected and every two adjacent third grooves are connected.

[0015] In some embodiments of the present application, the semiconductor structure further includes: a transistor structure located in the second epitaxial layer in the first region.

[0016] The present application provides a semiconductor structure and a method for forming the same, which connects some adjacent metal connection structures, so that the metal connection structure and the through-silicon via connection structure can be precisely connected, thereby improving device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The following drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0018] Figure 1 to Figure 2 It is a structural schematic diagram of each step in a method for forming a semiconductor structure;

[0019] Figures 3 to 26 It is a structural schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0021] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.

[0022] Figure 1 to Figure 2 It is a structural schematic diagram of each step in a method for forming a semiconductor structure.

[0023] refer to Figure 1 As shown, a semiconductor substrate 100 is provided, and the semiconductor substrate 100 includes a plurality of alternately distributed first regions 110 and second regions 120, a transistor structure (not shown in the figure) is formed on the first surface of the semiconductor substrate 100 in the first region 110, a metal connection structure 140 is formed in the second region 120, and a first interlayer dielectric layer 130 and a second interlayer dielectric layer 150 are also sequentially formed on the first surface of the semiconductor substrate 100.

[0024] The transistor structure formed in the first region 110 may be any transistor structure, such as MOSFET, etc. Figure 1As shown, since the transistor structure formed in the first region 110 can be any transistor structure, the present application omits the transistor structure for the purpose of simplicity. However, those skilled in the art should be able to know the shape and distribution of the corresponding transistor structure on the first region 110 in combination with common knowledge after determining the type of the transistor structure. For example, if the transistor structure is a MOSFET, the semiconductor substrate 100 of the corresponding first region 110 may include structures such as a gate, a source, and a drain.

[0025] Signal routes electrically connected to the metal connection structure 140 may also be formed in the second interlayer dielectric layer 150 .

[0026] refer to Figure 2 As shown, a through silicon via connection structure 160 is formed on the second surface of the semiconductor substrate 100 in the second region 120 , penetrating the semiconductor substrate 100 and electrically connecting the bottom surface of the metal connection structure 140 .

[0027] In terms of process design, the through-silicon via connection structure 160 should be located exactly in the second region 120 and electrically connected to the bottom surface of the metal connection structure 140. However, in the actual process, since the grooves formed by the current etching process generally show the characteristic of decreasing size along the etching direction, the bottom surface of the metal connection structure 140 and the bottom surface of the through-silicon via connection structure 160 are small in size due to the high aspect ratio, and are difficult to align. The through-silicon via connection structure 160 has a small diameter and a large depth. It is necessary to etch a semiconductor substrate 100 that is more than 300nm thick. The redundancy of the lithography alignment is very small. A deviation of 10 to 20nm will cause the connection to be misaligned, affecting the contact resistance, and in severe cases, will cause the power connection to be disconnected. Especially when the etching process itself also has errors, when the through-silicon via connection structure 160 deviates from the second region 120, the bottom surface of the metal connection structure 140 and the bottom surface of the through-silicon via connection structure 160 are prone to docking offset (refer to Figure 2 The dashed box 161) even fails to connect (refer to Figure 2 In addition, the size of the through silicon via connection structure 160 cannot be further reduced, and cannot adapt to the reduction of the front-end process size in advanced processes.

[0028] Based on the above problems, the present application provides a semiconductor structure and a method for forming the same, which connects some adjacent metal connection structures, so that the metal connection structure and the through-silicon via connection structure can be precisely docked, thereby improving device reliability, and the size of the through-silicon via connection structure can be reduced as the size of the front-end process is reduced.

[0029] Figures 3 to 26The following is a schematic diagram of the structure of each step in the method for forming a semiconductor structure according to an embodiment of the present application. The method for forming a semiconductor structure according to an embodiment of the present application is described in detail in conjunction with the accompanying drawings.

[0030] refer to Figure 3 and Figure 4 As shown, Figure 3 is a top view (specifically, a top view of the first surface of the semiconductor substrate 200), Figure 4 For along Figure 3 A semiconductor substrate 200 is provided, wherein a first epitaxial layer 210 and a second epitaxial layer 220 are formed on a first surface of the semiconductor substrate 200, wherein the first surface of the semiconductor substrate 200 includes an x ​​direction and a y direction perpendicular to each other, and the semiconductor substrate 200 includes a plurality of first regions 201 and second regions 202 alternately distributed along the x direction.

[0031] In some embodiments of the present application, the material of the semiconductor substrate 200 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.

[0032] In some embodiments of the present application, the material of the first epitaxial layer 210 is silicon germanium (the ratio of germanium atoms in silicon germanium to the total atomic number is 5% to 100%). The material of the second epitaxial layer 220 is silicon. The method of forming the first epitaxial layer 210 and the second epitaxial layer 220 is, for example, an epitaxial growth process.

[0033] In some embodiments of the present application, the first region 201 is used to form a transistor structure, and the second region 202 is used to fabricate a shallow trench isolation (STI) structure on the front side of the wafer and / or a metal connection on the back side.

[0034] In some embodiments of the present application, the number of the first areas 201 and the second areas 202 is arbitrary, and the embodiments of the present application only take five first areas 201 and four second areas 202 as examples.

[0035] refer to Figure 5 and Figure 6 As shown, Figure 5 is a top view, Figure 6 For along Figure 5In some embodiments of the present application, the method for forming the semiconductor structure further includes: forming a transistor structure (not shown) in the second epitaxial layer 220 in the first region 201 ; and forming a first interlayer dielectric layer 230 on the surface of the second epitaxial layer 220 .

[0036] The transistor structure formed in the first region 201 may be any transistor structure known to those skilled in the art, such as a planar or three-dimensional MOSFET. Figure 6 As shown, since the transistor structure formed in the first region 201 can be any transistor structure known to those skilled in the art, the present application omits the transistor structure for the purpose of simplicity. However, those skilled in the art should be able to know the shape and distribution of the corresponding transistor structure on the first region 201 in combination with common knowledge after determining the type of the transistor structure. For example, if the transistor structure is a MOSFET, a gate, a source, a drain and other structures can be formed on the second epitaxial layer 220 of the corresponding first region 201.

[0037] refer to Figure 7 and Figure 8 As shown, Figure 7 is a top view, Figure 8 For along Figure 7 A plurality of first trenches 241 extending along the y direction are formed in the second epitaxial layer 220 of the plurality of second regions 202. Specifically, the first trenches 241 penetrate the first interlayer dielectric layer 230 and extend into the second epitaxial layer 220. It should be noted that in the top view, the first trenches 241 expose the second epitaxial layer 220. Figure 7 The first trench 241 is shown in a shape exposing the second epitaxial layer 220 .

[0038] In some embodiments of the present application, the width of the first groove 241 is less than or equal to the width of the second region 202. In the embodiment of the present application, the width of the first groove 241 is equal to the width of the second region 202 as an example.

[0039] refer to Fig. 9 and Fig.10 and Fig.11 As shown, Fig. 9 is a top view, Fig.10 For along Fig. 9 The longitudinal section at the dotted line XX, Fig.11 For along Fig. 9A longitudinal cross-sectional view at the dotted line YY in the middle. Part of the first trench 241 is etched so that the part of the first trench 241 extends to the first epitaxial layer 210 to form a second trench 242 and a third trench 243, respectively, wherein the second trench 242 and the third trench 243 are respectively located at different positions along the y direction in different first trenches 241. It should be noted that in the top view, the second trench 242 and the third trench 243 expose the first epitaxial layer 210, so Fig. 9 The second trench 242 and the third trench 243 are shown in a shape exposing the first epitaxial layer 210 .

[0040] In some embodiments of the present application, preferably, the second groove 242 and the third groove 243 are respectively located in adjacent first grooves 241 .

[0041] refer to Fig.12 and Fig.13 and Fig.14 As shown, Fig.12 is a top view, Fig.13 For along Fig.12 The longitudinal section at the dotted line XX, Fig.14 For along Fig.12 The first epitaxial layer 210 is etched along the second trench 242 to connect part of the second trench 242 and the first epitaxial layer 210 is etched along the third trench 243 to connect part of the third trench 243 . Fig.12 In the figure, the adjacent second grooves 242 and the adjacent third grooves 243 are connected by dotted lines.

[0042] In some embodiments of the present application, the method of etching the first epitaxial layer 210 includes an isotropic etching process.

[0043] It should be noted that the present application only uses two adjacent second grooves 242 and two adjacent third grooves 243 being connected as an example. In fact, the number of the second regions 202 may be greater, and the number of the second grooves 242 and the third grooves 243 may also be greater. Accordingly, a greater number of adjacent second grooves 242 and third grooves 243 may be connected. For example, three or four adjacent second grooves 242 are connected, and three or four adjacent third grooves 243 are connected.

[0044] refer to Fig.15 and Fig.16 and Fig.17 As shown, Fig.15 is a top view, Fig.16 For along Fig.15 The longitudinal section at the dotted line XX, Fig.16 For along Fig.15A metal connection structure 240 is formed in the first trench 241 , the second trench 242 and the third trench 243 .

[0045] In some embodiments of the present application, an insulating layer (not shown in the figure) is formed between the metal connection structure 240 and the first epitaxial layer 210 and the second epitaxial layer 220 for electrically isolating the metal connection structure 240 and the first epitaxial layer 210 and the second epitaxial layer 220 .

[0046] In some embodiments of the present application, the top surface of the metal connection structure 240 is lower than the top surface of the first interlayer dielectric layer 230 and higher than the bottom surface of the first interlayer dielectric layer 230. The top surface refers to a side away from the first surface of the semiconductor substrate 200, and the bottom surface refers to a side close to the first surface of the semiconductor substrate 200.

[0047] In some embodiments of the present application, the material of the metal connection structure 240 is, for example, copper or tungsten.

[0048] refer to Fig.18 and Fig.19 and Fig. 20 As shown, Fig.18 is a top view, Fig.19 For along Fig.18 The longitudinal section at the dotted line XX, Fig. 20 For along Fig.18 A filling layer 250 is formed in the first trench 241, the second trench 242 and the third trench 243 to fill the first trench 241, the second trench 242 and the third trench 243. The material of the filling layer 250 is the same as that of the first interlayer dielectric layer 230, for example, silicon oxide.

[0049] In the technical solution of the present application, some of the metal connection structures 240 are interconnected (for example, the metal connection structures 240 in the adjacent second grooves 242 and the adjacent third grooves 243). Therefore, the bottom width of this part of the metal connection structure 240 is large enough. When the through-silicon via connection structure is subsequently formed, the through-silicon via connection structure is not easy to deviate from the bottom surface of the metal connection structure 240, so that the metal connection structure and the through-silicon via connection structure can be accurately docked, thereby improving the reliability of the device. In addition, since there is no need to consider the bottom surface deviation problem between the through-silicon via connection structure and the metal connection structure 240, the size of the through-silicon via connection structure can be made smaller.

[0050] refer to Fig.21 and Fig. 22 and Fig.23 As shown, Fig.21 is a top view, Fig. 22 For along Fig.21 The longitudinal section at the dotted line XX, Fig.23 For along Fig.21 A second interlayer dielectric layer 260 is formed on the surfaces of the first interlayer dielectric layer 230 and the filling layer 250 .

[0051] In some embodiments of the present application, the material of the second interlayer dielectric layer 260 is, for example, silicon oxide.

[0052] In some embodiments of the present application, signal routes electrically connected to the metal connection structure 240 may also be formed in the second interlayer dielectric layer 260 .

[0053] refer to Fig.24 and Fig.25 and Fig.26 As shown, Fig.24 is a top view, Fig.25 For along Fig.24 The longitudinal section at the dotted line XX, Fig.26 For along Fig.24 A first through silicon via connection structure 271 and a second through silicon via connection structure 272 are formed on the second surface of the semiconductor substrate 200 to penetrate the semiconductor substrate 200 and electrically connect the bottom surfaces of the metal connection structures 240 located in the second trench 242 and the third trench 243 respectively.

[0054] The first TSV connection structure 271 and the second TSV connection structure 272 are in full contact with the bottom surface of the metal connection structure 240. The full contact means that the first TSV connection structure 271 and the second TSV connection structure 272 are in full contact with the bottom surface of the metal connection structure 240 without being offset and contacting the first epitaxial layer 210.

[0055] In some embodiments of the present application, the material of the first TSV connection structure 271 and the second TSV connection structure 272 is, for example, copper or tungsten. The depth of the first TSV connection structure 271 and the second TSV connection structure 272 is 250 to 350 nanometers.

[0056] In some embodiments of the present application, an insulating layer (not shown in the figure) for electrically isolating the first through-silicon via connection structure 271 and the second through-silicon via connection structure 272 from the semiconductor substrate 200 is also formed between the first through-silicon via connection structure 271 and the second through-silicon via connection structure 272 and the semiconductor substrate 200.

[0057] In some embodiments of the present application, the first through silicon via connection structure 271 is connected to a power source (VDD), and the second through silicon via connection structure 272 is connected to a ground (GND).

[0058] In some embodiments of the present application, before forming a first through-silicon via connection structure 271 and a second through-silicon via connection structure 272 on the second surface of the semiconductor substrate 200 that penetrate the semiconductor substrate 200 and electrically connect the bottom surfaces of the metal connection structures 240 located in the second trench 242 and the third trench 243, respectively, the second surface of the semiconductor substrate 200 is also included: thinning the second surface of the semiconductor substrate 200.

[0059] In some embodiments of the present application, the method for forming the semiconductor structure further includes: forming a back-side power delivery network (BSPDN) on the second surface of the semiconductor substrate 200 .

[0060] In the technical solution of the present application, the metal connection structure 240 in part of the adjacent second trench 242 and third trench 243 is connected, so the bottom surface area of ​​this part of the metal connection structure 240 is large, and the through silicon via connection structure (the first through silicon via connection structure 271 and the second through silicon via connection structure 272 can be referred to as through silicon via connection structure) can easily and completely contact the bottom surface of the metal connection structure 240 without deviating and contacting the first epitaxial layer 210. The device reliability is improved.

[0061] In the technical solution of the present application, the metal connection structures 240 in some adjacent second grooves 242 and third grooves 243 are connected. Therefore, this part of the metal connection structure 240 only needs one through-silicon via connection structure to be electrically connected, which can reduce the number of through-silicon via connection structures, save materials, and reduce device weight.

[0062] The present application provides a method for forming a semiconductor structure, which connects some adjacent metal connection structures, so that the metal connection structure and the through-silicon via connection structure can be accurately connected, thereby improving the reliability of the device.

[0063] The embodiment of the present application also provides a semiconductor structure, referring to Fig.24 , 25 and Fig.26, comprising: a semiconductor substrate 200, wherein a first epitaxial layer 210 and a second epitaxial layer 220 are formed on a first surface of the semiconductor substrate 200, wherein the first surface of the semiconductor substrate 200 includes an x ​​direction and a y direction perpendicular to each other, wherein the semiconductor substrate 200 includes a plurality of first regions 201 and a second region 202 alternately distributed along the x direction; a plurality of first trenches 241 located in the second epitaxial layer 220 of the plurality of second regions 202; a second trench 242 and a third trench 243 located in a portion of the first trench 241 and extending to the first epitaxial layer 210, wherein the second trench 242 and the third trench 243 are 243 are respectively located at different positions of the adjacent first trenches 241 along the y direction, part of the second trench 242 is connected in the first epitaxial layer 210, and part of the third trench 243 is connected in the first epitaxial layer 210; the metal connection structure 240 is located in the first trench 241, the second trench 242 and the third trench 243; the first through-silicon via connection structure 271 and the second through-silicon via connection structure 272 are located on the second surface of the semiconductor substrate 200, penetrate the semiconductor substrate 200 and are electrically connected to the bottom surface of the metal connection structure 240 located in the second trench 242 and the third trench 243, respectively.

[0064] In some embodiments of the present application, the material of the semiconductor substrate 200 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.

[0065] In some embodiments of the present application, the material of the first epitaxial layer 210 is silicon germanium. The material of the second epitaxial layer 220 is silicon.

[0066] In some embodiments of the present application, the first region 201 is used to form a transistor structure, and the second region 202 is used to fabricate a shallow trench isolation (STI) structure on the front side of the wafer and / or a metal connection on the back side.

[0067] In some embodiments of the present application, the number of the first areas 201 and the second areas 202 is arbitrary, and the embodiments of the present application only take five first areas 201 and four second areas 202 as examples.

[0068] In some embodiments of the present application, the semiconductor structure further includes: a transistor structure located in the second epitaxial layer 220 in the first region 201 .

[0069] The transistor structure formed in the first region 201 may be any transistor structure known to those skilled in the art, such as a planar or three-dimensional MOSFET. Fig.25 As shown, since the transistor structure formed in the first region 201 can be any transistor structure known to those skilled in the art, the present application omits the transistor structure for the purpose of simplicity. However, those skilled in the art should be able to know the shape and distribution of the corresponding transistor structure on the first region 201 in combination with common knowledge after determining the type of the transistor structure. For example, if the transistor structure is a MOSFET, a gate, a source, a drain and other structures can be formed on the second epitaxial layer 220 of the corresponding first region 201.

[0070] In some embodiments of the present application, the semiconductor structure further includes: a first interlayer dielectric layer 230 located on the surface of the second epitaxial layer 220 .

[0071] refer to Figure 7 and Figure 8 As shown, a plurality of first trenches 241 extending along the y direction are formed in the second epitaxial layer 220 of the plurality of second regions 202 . Specifically, the first trenches 241 penetrate the first interlayer dielectric layer 230 and extend into the second epitaxial layer 220 .

[0072] In some embodiments of the present application, the width of the first groove 241 is less than or equal to the width of the second region 202. In the embodiment of the present application, the width of the first groove 241 is equal to the width of the second region 202 as an example.

[0073] refer to Fig. 9 and Fig.10 and Fig.11 As shown, the semiconductor structure also includes: a second trench 242 and a third trench 243 located in part of the first trench 241 and extending into the first epitaxial layer 210, wherein the second trench 242 and the third trench 243 are respectively located at different positions along the y direction in different first trenches 241, a part of the second trench 242 is connected in the first epitaxial layer 210, and a part of the third trench 243 is connected in the first epitaxial layer 210.

[0074] In some embodiments of the present application, preferably, the second groove 242 and the third groove 243 are respectively located in adjacent first grooves 241 .

[0075] It should be noted that the present application only uses two adjacent second grooves 242 and two adjacent third grooves 243 being connected as an example. In fact, the number of the second regions 202 may be greater, and the number of the second grooves 242 and the third grooves 243 may also be greater. Accordingly, a greater number of adjacent second grooves 242 and third grooves 243 may be connected. For example, three or four adjacent second grooves 242 are connected, and three or four adjacent third grooves 243 are connected.

[0076] refer to Fig.15 and Fig.16 and Fig.17 As shown, a metal connection structure 240 is formed in the first trench 241 , the second trench 242 and the third trench 243 .

[0077] In some embodiments of the present application, the top surface of the metal connection structure 240 is lower than the top surface of the first interlayer dielectric layer 230 and higher than the bottom surface of the first interlayer dielectric layer 230. The top surface refers to a side away from the first surface of the semiconductor substrate 200, and the bottom surface refers to a side close to the first surface of the semiconductor substrate 200.

[0078] In some embodiments of the present application, the material of the metal connection structure 240 is, for example, copper or tungsten.

[0079] refer to Fig.18 and Fig.19 and Fig. 20 As shown, a filling layer 250 is formed in the first trench 241, the second trench 242 and the third trench 243 to fill the first trench 241, the second trench 242 and the third trench 243. The material of the filling layer 250 is the same as that of the first interlayer dielectric layer 230, for example, silicon oxide.

[0080] In the technical solution of the present application, some of the metal connection structures 240 are interconnected (for example, the metal connection structures 240 in the adjacent second grooves 242 and the adjacent third grooves 243). Therefore, the bottom width of this part of the metal connection structure 240 is large enough. When the through-silicon via connection structure is subsequently formed, the through-silicon via connection structure is not easy to deviate from the bottom surface of the metal connection structure 240, so that the metal connection structure and the through-silicon via connection structure can be accurately docked, thereby improving the reliability of the device. In addition, since there is no need to consider the bottom surface deviation problem between the through-silicon via connection structure and the metal connection structure 240, the size of the through-silicon via connection structure can be made smaller.

[0081] refer to Fig.24 and Fig.25 and Fig.26 As shown, a second interlayer dielectric layer 260 is formed on the surfaces of the first interlayer dielectric layer 230 and the filling layer 250 .

[0082] In some embodiments of the present application, the material of the second interlayer dielectric layer 260 is, for example, silicon oxide.

[0083] In some embodiments of the present application, signal routes electrically connected to the metal connection structure 240 may also be formed in the second interlayer dielectric layer 260 .

[0084] refer to Fig.24 and Fig.25 and Fig.26 As shown, a first through-silicon via connection structure 271 and a second through-silicon via connection structure 272 are formed on the second surface of the semiconductor substrate 200 , penetrating the semiconductor substrate 200 and electrically connecting the bottom surfaces of the metal connection structures 240 located in the second trench 242 and the third trench 243 , respectively.

[0085] The first TSV connection structure 271 and the second TSV connection structure 272 are in full contact with the bottom surface of the metal connection structure 240. The full contact means that the first TSV connection structure 271 and the second TSV connection structure 272 are in full contact with the bottom surface of the metal connection structure 240 without being offset and contacting the first epitaxial layer 210.

[0086] In some embodiments of the present application, the material of the first TSV connection structure 271 and the second TSV connection structure 272 is, for example, copper or tungsten. The depth of the first TSV connection structure 271 and the second TSV connection structure 272 is 250 to 350 nanometers.

[0087] In some embodiments of the present application, the first through silicon via connection structure 271 is connected to a power source (VDD), and the second through silicon via connection structure 272 is connected to a ground (GND).

[0088] In some embodiments of the present application, the semiconductor structure further includes: a back-side power delivery network (BSPDN) located on the second surface of the semiconductor substrate 200 .

[0089] In the technical solution of the present application, the metal connection structure 240 in part of the adjacent second trench 242 and third trench 243 is connected, so the bottom surface area of ​​this part of the metal connection structure 240 is large, and the through silicon via connection structure (the first through silicon via connection structure 271 and the second through silicon via connection structure 272 can be referred to as through silicon via connection structure) can easily and completely contact the bottom surface of the metal connection structure 240 without deviating and contacting the first epitaxial layer 210. The device reliability is improved.

[0090] In the technical solution of the present application, the metal connection structures 240 in some adjacent second grooves 242 and third grooves 243 are connected. Therefore, this part of the metal connection structure 240 only needs one through-silicon via connection structure to be electrically connected, which can reduce the number of through-silicon via connection structures, save materials, and reduce device weight.

[0091] The present application provides a semiconductor structure and a method for forming the same, which increases the size of the bottom of the metal connection structure, enables the metal connection structure and the through-silicon via connection structure to be precisely docked, and improves device reliability.

[0092] In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0093] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can also be intermediate elements.

[0094] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or there can be intervening elements. In contrast, the term "directly" means that there are no intervening elements. It should also be understood that the terms "comprising," "containing," "including," or "comprising," when used in this application document, indicate the presence of the recited features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0095] It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present application, the first element in some embodiments can be referred to as the second element in other embodiments. The same reference numerals or the same reference signs represent the same elements throughout the specification.

[0096] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a semiconductor substrate, wherein a first epitaxial layer and a second epitaxial layer are formed on a first surface of the semiconductor substrate, the first surface of the semiconductor substrate includes an x ​​direction and a y direction perpendicular to each other, and the semiconductor substrate includes a plurality of first regions and second regions alternately distributed along the x direction; forming a plurality of first trenches extending along the y direction in the second epitaxial layers of the plurality of second regions; Etching a portion of the first trench so that the portion of the first trench extends to the first epitaxial layer to form a second trench and a third trench respectively, wherein the second trench and the third trench are respectively located at different positions along the y direction in different first trenches; Etching the first epitaxial layer along the second trench to make part of the second trench connected, and etching the first epitaxial layer along the third trench to make part of the third trench connected; forming a metal connection structure in the first trench, the second trench and the third trench; A first through silicon via connection structure and a second through silicon via connection structure are formed on the second surface of the semiconductor substrate, penetrating the semiconductor substrate and electrically connecting the bottom surfaces of the metal connection structures located in the second trench and the third trench respectively.

2. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first epitaxial layer is silicon germanium, and the material of the second epitaxial layer is silicon.

3. The method for forming a semiconductor structure according to claim 1, wherein: The first through silicon via connection structure is connected to a power source, and the second through silicon via connection structure is grounded.

4. The method for forming a semiconductor structure according to claim 1, wherein: Every two adjacent second grooves are connected and every two adjacent third grooves are connected.

5. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: A transistor structure is formed in the second epitaxial layer in the first region.

6. A semiconductor structure, characterized in that: include: A semiconductor substrate, wherein a first epitaxial layer and a second epitaxial layer are formed on a first surface of the semiconductor substrate, the first surface of the semiconductor substrate includes an x ​​direction and a y direction perpendicular to each other, and the semiconductor substrate includes a plurality of first regions and second regions alternately distributed along the x direction; a plurality of first trenches extending along the y direction in the second epitaxial layer located in the plurality of second regions; A second trench and a third trench located in part of the first trench and extending into the first epitaxial layer, wherein the second trench and the third trench are respectively located at different positions along the y direction in different first trenches, a part of the second trench is connected in the first epitaxial layer, and a part of the third trench is connected in the first epitaxial layer; a metal connection structure located in the first trench, the second trench and the third trench; A first through silicon via connection structure and a second through silicon via connection structure located on the second surface of the semiconductor substrate penetrate through the semiconductor substrate and are electrically connected to the bottom surfaces of the metal connection structures located in the second trench and the third trench respectively.

7. The semiconductor structure according to claim 6, wherein: The material of the first epitaxial layer is silicon germanium, and the material of the second epitaxial layer is silicon.

8. The semiconductor structure according to claim 6, wherein: The first through silicon via connection structure is connected to a power source, and the second through silicon via connection structure is grounded.

9. The semiconductor structure according to claim 6, wherein: Every two adjacent second grooves are connected and every two adjacent third grooves are connected.

10. The semiconductor structure according to claim 6, wherein: Also includes: A transistor structure is located in the second epitaxial layer in the first region.

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