Preparation method of metal interconnection structure
By adopting a preparation method of metal interconnect structure in semiconductor integrated circuits, the problems of dielectric material damage, metal layer upside down and hole formation are solved, and higher chip performance and stability are achieved.
Patent Information
- Application Number
- CN202311409079.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-27
- Publication Date
- 2025-04-29
AI Technical Summary
In the prior art, dielectric materials are easily damaged in the process process, and the metal barrier layer and metal seed layer are inverted during the deposition process, resulting in the smaller size of the deposition groove opening, and metal copper has holes in the electroplating process.
A method for preparing a metal interconnect structure is provided, including forming a first dielectric layer and a first metal layer on the substrate, depositing a seed layer, and forming an electroplating window through photolithography etching, controlling the size and morphology of the electroplating metal layer using the sacrificial layer, and forming a metal interconnect layer with two-dimensional unidirectional growth of the electroplating metal, and then forming a second dielectric layer to realize metal interconnection.
It greatly reduces the step height before deposition and electroplating, greatly reduces the difficulty of process integration and the process difficulty of etching, deposition and electroplating, avoids problems such as dielectric material damage, metal layer upside down and hole formation, and improves chip performance and stability.
Smart Images
Figure CN119905455A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of semiconductor integrated circuit design and manufacture, and in particular relates to a method for preparing a metal interconnection structure. Background Art
[0002] With the advancement of semiconductor integrated circuit technology, semiconductor devices are shrinking to the deep submicron range, and the resistance (R) and capacitance (C) of their interconnections are prone to parasitic effects, resulting in metal wire transmission delay (RC time delay). In order to reduce parasitic effects, low-resistance materials (such as copper) or low dielectric constant (1ow-k) dielectric materials are increasingly used in the interconnection integration process of integrated circuits to reduce the RC delay caused by parasitic resistance and parasitic capacitance.
[0003] At present, the advanced process metal interconnection adopts the process of first etching the dielectric material layer to form a Damascus structure and then embedding copper to overcome the difficulty of dry etching of copper. Specifically, the current mainstream single / double Damascus process is to first etch the dielectric layer to form a high aspect ratio structure, then deposit metal and electroplate on the high aspect ratio structure, and then achieve metal interconnection through chemical mechanical polishing (CMP). However, the above process also brings some disadvantages, such as the dielectric material is easily damaged during the process (such as dry etching or wet etching), the metal barrier layer and the metal seed layer are inverted during the deposition process, resulting in a smaller deposition tank opening size, and the metal copper forms copper voids during the electroplating (ECP) process.
[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention
[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for preparing a metal interconnect structure, which is used to solve the problems in the prior art that the dielectric material is easily damaged in the process technology, the metal barrier layer and the metal seed layer are inverted during the deposition process, resulting in a smaller opening size of the deposition tank, and the metal copper forms holes during the electroplating process.
[0006] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for preparing a metal interconnection structure, the preparation method comprising: providing a substrate, the substrate having a first dielectric layer and a first metal layer exposed on the surface of the first dielectric layer; forming a seed layer on the first metal layer and the surface of the substrate; forming a sacrificial layer on the substrate, patterning the sacrificial layer to form a plating window, the plating window at least exposing a portion of the seed layer; electroplating a second metal layer on the seed layer in the plating window, controlling the pattern of the second metal layer by means of the plating window to form a metal interconnection layer; removing the sacrificial layer and the seed layer under the sacrificial layer; forming a second dielectric layer in the area where the sacrificial layer is removed, and planarizing the second dielectric layer to form a metal interconnection structure comprising a second dielectric layer and a metal interconnection layer.
[0007] Optionally, a sacrificial layer is formed on the substrate, and patterning the sacrificial layer includes: forming a photolithography sacrificial layer on the substrate; exposing and developing the photolithography sacrificial layer to form an electroplating window in the photolithography sacrificial layer.
[0008] Optionally, a sacrificial layer is formed on the substrate, and patterning the sacrificial layer includes: forming a carbon-containing material layer on the substrate; forming a hard mask layer on the carbon-containing material layer; forming a photoresist layer on the hard mask layer; exposing and developing the photoresist layer to form a photolithography window in the photoresist layer; patterning the hard mask layer and the carbon-containing material layer based on the photolithography window to form an electroplating window in the hard mask layer and the carbon-containing material layer; and removing the photoresist layer and the hard mask layer.
[0009] Optionally, the carbon-containing material layer includes an amorphous carbon layer, and the hard mask layer includes a dielectric anti-reflection layer; or the carbon-containing material layer includes a spin-on carbon layer, and the hard mask layer includes a silicon anti-reflection layer.
[0010] Optionally, the cross-sectional shape of the plating window includes one of a rectangle and an inverted trapezoid. When the cross-sectional shape of the plating window is an inverted trapezoid, an air gap is formed between the second dielectric layer formed in the area where the sacrificial layer is removed and the metal interconnection layer.
[0011] Optionally, after forming the electroplating window, a pre-cleaning process is further included for the electroplating window to remove residual particles in the electroplating window.
[0012] Optionally, when the second metal layer is electroplated on the seed layer in the electroplating window, the second metal layer grows two-dimensionally upward from the seed layer.
[0013] Optionally, the second metal layer is grown to a thickness smaller than that of the sacrificial layer.
[0014] Optionally, the method further includes forming a metal barrier layer between the first metal layer and the seed layer.
[0015] Optionally, the second dielectric layer is formed in the region where the sacrificial layer is removed by a spin coating process or a chemical vapor deposition process.
[0016] As described above, the method for preparing the metal interconnect structure of the present invention has the following beneficial effects:
[0017] The present invention first deposits a seed layer, then photolithography and etching are performed to define a plating window, a sacrificial layer is used to control the size and morphology of the electroplated metal layer, the electroplated metal grows two-dimensionally to form a metal layer, and a dielectric layer is formed after the sacrificial layer is removed to achieve metal interconnection. The present invention can greatly reduce the step height before deposition and electroplating, greatly reduce the difficulty of process integration and reduce the process difficulty of etching, deposition and electroplating in the process, avoid the problems in the current mainstream copper Damascus process of metal interconnection that the dielectric material is easily damaged in the process, the metal barrier layer and the metal seed layer are inverted during the deposition process, resulting in a smaller opening size of the deposition slot, and the metal copper forms holes during the electroplating process, thereby improving chip performance and stability.
[0018] The present invention can control the morphology of the sacrificial layer through a photolithography or photolithography-etching process, in conjunction with a pre-clean process (pre-clean) and a plasma cleaning process (descum), thereby achieving metal morphology control (such as an inverted trapezoidal metal morphology), which helps to achieve an air gap in the subsequent dielectric layer filling process, reduce the overall K value of the dielectric layer and reduce RC delay.
[0019] The present invention does not need to fill deep holes through physical vapor deposition (PVD) process, the step height is greatly reduced and the process difficulty is greatly reduced, avoiding the risk of the metal barrier layer and the metal seed layer being inverted during the deposition process, causing the opening size of the deposition groove to become smaller.
[0020] When the present invention performs metal electroplating filling on a structure with a high aspect ratio, because the seed layer is only at the bottom, the metal plating grows from the bottom to the top, and the electroplated metal grows in a nearly unidirectional direction, thereby preventing the formation of void defects in the structure with a high aspect ratio, thereby reducing the difficulty of the metal electroplating process.
[0021] The present invention does not need to etch thick films or deep holes, and the difficulty of the etching process is greatly reduced, thereby greatly reducing the demand for etching equipment.
[0022] The present invention avoids possible photolithography quality problems and controls the morphology before electroplating through a pre-cleaning process (pre-clean) and a plasma cleaning process (descum), and can effectively control the final metal morphology.
[0023] The line width and thickness of the metal interconnection of the present invention are relatively uniform, which can avoid the influence of the loading effect during etching and grinding processes, and achieve the stability and improvement of chip parameters. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.
[0025] Figure 1 to Figure 17 It is a schematic structural diagram showing the steps of the method for preparing the metal interconnect structure according to an embodiment of the present invention.
[0026] Component number description
[0027] 10 Base
[0028] 100 substrate layer
[0029] 101 Electrode Structure
[0030] 102 Silicon carbide nitride layer (SiCN)
[0031] 103 Ultra Low K Dielectric Layer (ULK)
[0032] 104 Tetraethyl Silicate Layer (TEOS)
[0033] 105 Silicon Nitride Layer (SiN)
[0034] 106 Silicon dioxide layer (SiO2)
[0035] 107 Photolithography
[0036] 108 Electrode slot
[0037] 109 seed layer
[0038] 110 First metal layer
[0039] 111 Silicon carbide nitride layer (SiCN)
[0040] 112 Image Transfer Layer
[0041] 113 Photolithography
[0042] 202 Metal barrier layer
[0043] 203 Seed Layer
[0044] 204 Carbonaceous material layer
[0045] 205 Hard mask layer
[0046] 206 photoresist layer
[0047] 207 Electroplating Window
[0048] 208 Metal Interconnect Layer
[0049] 209 Second dielectric layer
[0050] 210 Air gap
[0051] 301 Photolithography sacrificial layer DETAILED DESCRIPTION
[0052] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0053] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.
[0054] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.
[0055] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.
[0056] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
[0057] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0058] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0059] In the existing preparation process of metal interconnection structure, there are problems such as dielectric materials being easily damaged during the process, metal barrier layer and metal seed layer being inverted during deposition, resulting in a smaller deposition slot opening size, and metal copper forming holes during electroplating.
[0060] In order to solve the above problems, Figures 1 to 16 As shown, this embodiment provides a method for preparing a metal interconnect structure, and the preparation method comprises the following steps:
[0061] like Figures 1 to 9 As shown, firstly, step 1) is performed to provide a substrate having a first dielectric layer and a first metal layer exposed on the surface of the first dielectric layer.
[0062] In one embodiment, step 1) comprises:
[0063] like Figure 1 As shown, firstly, step 1-1) is performed to provide a substrate structure, wherein the substrate structure includes a substrate layer 100, an electrode structure 101 located on the substrate layer 100, a silicon carbide nitride layer (SiCN) 102 located on the electrode structure 101, an ultra-low-k dielectric layer (ULK) 103 located on the silicon carbide nitride layer (SiCN) 102, an ethyl silicate layer (TEOS) 104 located on the ultra-low-k dielectric layer 103, a silicon nitride layer (SiN) 105 located on the ethyl silicate layer (TEOS) 104, and a silicon dioxide layer (SiO2) 106 located on the silicon nitride layer (SiN) 105, wherein the silicon carbide nitride layer (SiCN) 102 and the ultra-low-k dielectric layer (ULK) 103 together constitute a first dielectric layer, and the ethyl silicate layer (TEOS) 104, the silicon nitride layer (SiN) 105, and the silicon dioxide layer (SiO2) 106 together constitute a hard mask layer. Of course, the first dielectric layer can also be composed of other dielectric materials or dielectric stacks, the above-mentioned ultra-low-k dielectric layer 103 can also be replaced by a low-K dielectric layer (LK) or other dielectric materials, the hard mask layer can also be replaced by other hard mask materials or stacks of hard mask materials, and can also be replaced by photoresist, etc., and is not limited to the examples listed here.
[0064] like Figure 2 As shown, then step 1-2) is performed to form a photolithography pattern 107 on the substrate structure;
[0065] like Figure 3As shown, then step 1-3) is performed to transfer the photolithography pattern 107 to the hard mask layer to form an etching pattern;
[0066] like Figure 4 As shown, step 1-4) is then performed to etch the ultra low k dielectric layer (ULK) 103 through the etching pattern of the hard mask layer to form an electrode groove 108;
[0067] like Figure 5 As shown, then step 1-5) is performed to deposit a metal barrier layer and a seed layer 109 in the electrode groove 108;
[0068] like Figure 6 As shown, then step 1-6) is performed to electroplate a first metal layer 110, such as copper, in the electrode tank through an electroplating process;
[0069] like Figure 7 As shown, step 1-7) is then performed to expose the first metal layer 110 through a chemical mechanical polishing process. In order to ensure that the exposed thickness meets the design requirements, the polishing is usually stopped in the first dielectric layer.
[0070] like Figure 8 As shown, then proceed to step 1-8), deposit a barrier layer (for example, a composite film layer such as a silicon carbide nitride layer (SiCN) 111) on the ultra-low-k dielectric layer (ULK) 103 and the first metal layer 110. For example, in order to increase the image transmission effect and improve the resolution, the composite film layer in the barrier layer may also have Figure 8 The image transfer layer 112 is formed by forming a photolithography pattern 113, and a photolithography pattern 113 is formed to expose the first metal layer 110, and finally the photolithography pattern 113 and the barrier layer are removed to form the substrate 10.
[0071] like Figure 10a to Figure 11b As shown, then step 2) is performed to form a seed layer 203 on the surface of the first metal layer and the substrate; a sacrificial layer is formed on the substrate, and the sacrificial layer is patterned to form an electroplating window 207, and the electroplating window 207 at least partially exposes the seed layer 203. This method of making the seed layer 203 before the sacrificial layer is deposited reduces the complexity of the process. Because if the sacrificial layer is made first, and then the electroplating window 207 is made, and then the barrier layer and the seed layer are deposited in the electroplating window 207, after the metal is electroplated, there is also a seed layer and electroplated metal on the sacrificial layer. If the sacrificial layer is removed, it must be CMP-milled and the sacrificial layer must be exposed. In the present invention, the seed layer is deposited before the sacrificial layer, and then the electroplating window 207 is made. Because there is no seed layer on the top of the sacrificial layer, no metal is deposited on the sacrificial layer during electroplating, and the subsequent process flow for removing the sacrificial layer is simple, which can effectively reduce costs.
[0072] In one embodiment, the step of forming a metal barrier layer 202 between the first metal layer and the seed layer 203 is also included. The metal barrier layer 202 is used to prevent the subsequent metal interconnection layer 208 from diffusing into the dielectric layer on the one hand, and to enhance the bonding strength between the seed layer 203 and the metal interconnection layer 208 and the dielectric layer on the other hand, to prevent the metal interconnection layer 208 from falling off.
[0073] In one embodiment, Fig.10a and Fig.11a As shown, a sacrificial layer is formed on a substrate, and patterning the sacrificial layer includes:
[0074] like Fig.10a As shown, a carbon-containing material layer 204 is formed on a substrate, and the process of forming the carbon-containing material layer may be a spin coating process, a physical vapor deposition process, a chemical vapor deposition process, or the like; in order to further improve the resolution, a hard mask layer 205 may be formed on the carbon-containing material layer 204; a photoresist layer 206 is formed on the hard mask layer 205; and the photoresist layer 206 is exposed and developed to form a photolithography window in the photoresist layer 206.
[0075] like Fig.10a As shown, the hard mask layer 205 and the carbon-containing material layer 204 are patterned based on the photolithography window to form a plating window 207 in the carbon-containing material layer 204; and the photoresist layer 206 and the hard mask layer 205 are removed.
[0076] In one embodiment, the carbon-containing material layer 204 may be an amorphous carbon layer, and the hard mask layer 205 may be a dielectric anti-reflection layer; or the carbon-containing material layer 204 may be a spin-on carbon layer, and the hard mask layer 205 may be a silicon anti-reflection layer.
[0077] In this example, the carbon-containing material layer 204 is used to make the electroplating window 207, which can obtain a relatively smooth side wall, thereby effectively improving the quality of subsequent electroplated metal. At the same time, the carbon-containing material layer can be completely removed by subsequent ashing and cleaning. The removal process is relatively simple, which can help reduce costs.
[0078] In another embodiment, when the resolution requirement is not high, such as Fig.10b and Fig.11b As shown, a sacrificial layer is formed on a substrate, and patterning the sacrificial layer includes:
[0079] like Fig.10b As shown, a photolithography sacrificial layer 301 is formed on the substrate;
[0080] like Fig.11b As shown, the photolithography sacrificial layer 301 is exposed and developed to form a plating window 207 in the photolithography sacrificial layer 301 .
[0081] In this example, photoresist is directly used as a sacrificial layer, and the electroplating window 207 can be formed by only one photolithography-development process. Meanwhile, the photoresist can be completely removed only by ashing and cleaning in the subsequent process. The removal process is relatively simple, which can help reduce costs.
[0082] In one embodiment, after the electroplating window 207 is formed, a pre-cleaning process is further performed on the electroplating window 207, and the pre-cleaning process includes plasma cleaning (especially for small sizes) or mixed acid wet cleaning (mainly for large sizes) to remove residual particles in the electroplating window 207. The pre-cleaning process and the plasma cleaning process can also achieve morphology control of the electroplating window 207. In one embodiment, the cross-sectional shape of the electroplating window 207 includes one of a rectangle and an inverted trapezoid. In this embodiment, the cross-sectional shape of the electroplating window 207 is an inverted trapezoid.
[0083] The present invention can control the morphology of the sacrificial layer through photolithography or photolithography-etching process, in conjunction with a pre-clean process (pre-clean) and a plasma cleaning process (descum), thereby achieving metal morphology control (such as an inverted trapezoidal metal morphology), which helps to achieve an air gap 210 in the subsequent dielectric layer filling process, reduce the overall K value of the dielectric layer and reduce RC delay.
[0084] like Figure 12-13 As shown, step 3) is then performed to electroplate a second metal layer on the seed layer 203 in the electroplating window 207 , and the pattern of the second metal layer is controlled by the electroplating window 207 to form a metal interconnection layer 208 .
[0085] In one embodiment, when the second metal layer is electroplated on the seed layer 203 in the electroplating window 207, the second metal layer grows two-dimensionally upward from the seed layer 203 (because in the present invention, the sacrificial layer is formed before the seed layer, so the seed layer is only exposed at the bottom of the electroplating window, and when the metal layer is formed by electroplating, it only grows unidirectionally from the bottom to the top. This method avoids holes (viods) when electroplating metal in the traditional way). The second metal layer of this example grows two-dimensionally upward from the seed layer 203, which can greatly improve the thickness uniformity of the second metal layer in different electroplating windows 207. Because there is no flattening treatment (such as CMP, etc.) on the top of the metal, the influence of the loading effect of the grinding process is avoided, and the chip parameters are stabilized and improved.
[0086] In one embodiment, the growth thickness of the second metal layer can be set to be less than the thickness of the sacrificial layer to avoid adhesion of the second metal layer in different electroplating windows 207, while saving the subsequent planarization process on the top of the sacrificial layer, because there is no seed layer on the top of the sacrificial layer, and thus no metal layer covering it.
[0087] When the present invention performs metal electroplating filling on a structure with a high aspect ratio, because the seed layer is only at the bottom, the metal plating grows from the bottom to the top, and the electroplated metal grows in a nearly unidirectional direction, thereby preventing the formation of void defects in the structure with a high aspect ratio, thereby reducing the difficulty of the metal electroplating process.
[0088] like Fig.14 As shown, step 4) is then performed to remove the sacrificial layer and the seed layer 203 under the sacrificial layer.
[0089] In one embodiment, the photolithography sacrificial layer 301 is removed by an ashing process and a cleaning process; or the carbon-containing material layer 204 is removed by an ashing process and a cleaning process. For carbon-containing material layers, such as spin-on carbon layers and amorphous carbon layers, this example only requires ashing and cleaning to completely remove them, and the removal process is relatively simple, which can help reduce costs.
[0090] like Fig.15 and Fig.16 As shown, step 5) is finally performed to form a second dielectric layer 209 in the area where the sacrificial layer is removed, and the second dielectric layer 209 is planarized to form a metal interconnection structure including the second dielectric layer 209 and the metal interconnection layer 208.
[0091] In one embodiment, the second dielectric layer 209 is formed in the region where the sacrificial layer is removed by a spin coating process or a chemical vapor deposition process.
[0092] In one embodiment, Fig.16 As shown, when the cross-sectional shape of the electroplating window 207 is an inverted trapezoid, an air gap 210 is formed between the second dielectric layer 209 formed in the area where the sacrificial layer is removed and the metal interconnection layer 208, so as to reduce the overall K value of the dielectric layer and reduce the RC delay. Compared with the prior art, the present invention forms the metal interconnection layer 208 first and then forms the second dielectric layer 209, which is more conducive to forming the second dielectric layer 209 with an air gap, because the damage to the dielectric layer can be avoided. At the same time, the second dielectric layer 209 formed by the above process has better uniformity.
[0093] Of course, if Fig.17 As shown, in other embodiments, the cross-sectional shape of the electroplating window 207 may also be a rectangle, and is not limited to the examples listed above.
[0094] As described above, the method for preparing the metal interconnect structure of the present invention has the following beneficial effects:
[0095] The present invention first deposits a seed layer, then photolithography and etching are performed to define a plating window, a sacrificial layer is used to control the size and morphology of the electroplated metal layer, the electroplated metal grows two-dimensionally to form a metal layer, and a dielectric layer is formed after the sacrificial layer is removed to achieve metal interconnection. The present invention can greatly reduce the step height before deposition and electroplating, greatly reduce the difficulty of process integration and reduce the process difficulty of etching, deposition and electroplating in the process, avoid the problems in the current mainstream copper Damascus process of metal interconnection that the dielectric material is easily damaged in the process, the metal barrier layer and the metal seed layer are inverted during the deposition process, resulting in a smaller opening size of the deposition slot, and the metal copper forms holes during the electroplating process, thereby improving chip performance and stability.
[0096] The present invention can control the morphology of the sacrificial layer through a photolithography or photolithography-etching process, in conjunction with a pre-clean process (pre-clean) and a plasma cleaning process (descum), thereby achieving metal morphology control (such as an inverted trapezoidal metal morphology), which helps to achieve an air gap in the subsequent dielectric layer filling process, reduce the overall K value of the dielectric layer and reduce RC delay.
[0097] The present invention does not need to fill deep holes through physical vapor deposition (PVD) process, the step height is greatly reduced and the process difficulty is greatly reduced, avoiding the risk of the metal barrier layer and the metal seed layer being inverted during the deposition process, causing the opening size of the deposition groove to become smaller.
[0098] When the present invention performs metal electroplating filling on a structure with a high aspect ratio, because the seed layer is only at the bottom, the metal plating grows from the bottom to the top, and the electroplated metal grows in a nearly unidirectional direction, thereby preventing the formation of void defects in the structure with a high aspect ratio, thereby reducing the difficulty of the metal electroplating process.
[0099] The present invention does not need to etch thick films or deep holes, and the difficulty of the etching process is greatly reduced, thereby greatly reducing the demand for etching equipment.
[0100] The present invention avoids possible photolithography quality problems and controls the morphology before electroplating through a pre-cleaning process (pre-clean) and a plasma cleaning process (descum), and can effectively control the final metal morphology.
[0101] The line width and thickness of the metal interconnection of the present invention are relatively uniform, which can avoid the influence of the loading effect during etching and grinding processes, and achieve the stability and improvement of chip parameters.
[0102] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
[0103] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for preparing a metal interconnect structure, characterized in that: The preparation method comprises: Providing a substrate, wherein the substrate has a first dielectric layer and a first metal layer exposed on a surface of the first dielectric layer; forming a seed layer on the first metal layer and the surface of the substrate; Forming a sacrificial layer on the substrate, and patterning the sacrificial layer to form an electroplating window, wherein the electroplating window at least exposes a portion of the seed layer; Electroplating a second metal layer on the seed layer in the electroplating window, and controlling the pattern of the second metal layer through the electroplating window to form a metal interconnection layer; removing the sacrificial layer and the seed layer below the sacrificial layer; A second dielectric layer is formed in the region where the sacrificial layer is removed, and the second dielectric layer is planarized to form a metal interconnection structure including the second dielectric layer and the metal interconnection layer.
2. The method for preparing a metal interconnect structure according to claim 1, characterized in that: Forming a sacrificial layer on the substrate, and patterning the sacrificial layer comprises: forming a photolithography sacrificial layer on the substrate; The photolithography sacrificial layer is exposed and developed to form an electroplating window in the photolithography sacrificial layer.
3. The method for preparing a metal interconnect structure according to claim 1, characterized in that: Forming a sacrificial layer on the substrate, and patterning the sacrificial layer comprises: forming a carbonaceous material layer on the substrate; forming a hard mask layer on the carbon-containing material; forming a photoresist layer on the hard mask layer; Expose and develop the photoresist layer to form a photolithography window in the photoresist layer; The hard mask layer and the carbon-containing material layer are patterned based on the photolithography window to form electroplating windows in the hard mask layer and the carbon-containing material layer to remove the photoresist layer and the hard mask layer.
4. The method for preparing a metal interconnect structure according to claim 3, characterized in that: The carbon-containing material layer includes an amorphous carbon layer, and the hard mask layer includes a dielectric anti-reflection layer; or the carbon-containing material layer includes a spin-on carbon layer, and the hard mask layer includes a silicon anti-reflection layer.
5. The method for preparing a metal interconnect structure according to claim 1, characterized in that: The cross-sectional shape of the electroplating window includes one of a rectangle and an inverted trapezoid. When the cross-sectional shape of the electroplating window is an inverted trapezoid, an air gap is formed between the second dielectric layer formed in the area where the sacrificial layer is removed and the metal interconnection layer.
6. The method for preparing a metal interconnect structure according to claim 1, characterized in that: After forming the electroplating window, the method further includes performing a pre-cleaning process on the electroplating window to remove residual particles in the electroplating window.
7. The method for preparing a metal interconnect structure according to claim 1, characterized in that: When the second metal layer is electroplated on the seed layer in the electroplating window, the second metal layer grows two-dimensionally upward from the seed layer.
8. The method for preparing a metal interconnect structure according to claim 1, characterized in that: The second metal layer is grown to a thickness smaller than that of the sacrificial layer.
9. The method for preparing a metal interconnect structure according to claim 1, characterized in that: The method further includes forming a metal barrier layer between the first metal layer and the seed layer.
10. The method for preparing a metal interconnect structure according to claim 1, characterized in that: A second dielectric layer is formed in the region where the sacrificial layer is removed by a spin coating process or a chemical vapor deposition process.