Semiconductor structure and forming method thereof

Abstract

Semiconductor structures and methods of forming the same are provided. An exemplary method includes forming a metal layer over a substrate; patterning the metal layer to form a first metal line and a second metal line with a trench therebetween; depositing a sacrificial layer in a lower portion of the trench; forming a first dielectric layer on the sacrificial layer; after forming the first dielectric layer, selectively removing the sacrificial layer to form an air gap between the first metal line and the second metal line; and depositing a second dielectric layer over the first dielectric layer and in the upper portion of the trench.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices that can simultaneously support more increasingly complex and sophisticated functions. Therefore, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance and low-power integrated circuits (ICs). To date, these goals have been achieved to a large extent by reducing the size of semiconductor ICs (e.g., minimum component size) and thereby improving production efficiency and reducing related costs. However, such scaling also introduces increased complexity into semiconductor manufacturing processes. Therefore, the continued advancement of semiconductor ICs and devices requires similar advancements in semiconductor manufacturing processes and technology.

[0003] As device dimensions continue to shrink, the performance of back-end-of-line (BEOL) interconnect structures is subject to higher demands. For example, high parasitic capacitance may result in lower device speeds (e.g., RC delays) as the distance between two adjacent conductive features decreases to meet design requirements for smaller technology nodes. Low dielectric constant (low-k) materials have been incorporated into interconnect structures to reduce parasitic capacitance. While low-k materials are used for their purpose of reducing parasitic capacitance, their inadequate thermal conductivity presents challenges in dissipating heat from front-end-of-line (FEOL) devices. Summary of the invention

[0004] Some embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a metal layer above a substrate; patterning the metal layer to form a first metal line and a second metal line with a groove therebetween; depositing a sacrificial layer in a lower portion of the groove; forming a first dielectric layer on the sacrificial layer; after forming the first dielectric layer, selectively removing the sacrificial layer to form an air gap between the first metal line and the second metal line; and depositing a second dielectric layer above the first dielectric layer and in an upper portion of the groove.

[0005] Other embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a metal layer over a substrate; patterning the metal layer to form a groove separating the metal layer into at least a first portion and a second portion; forming a covering layer extending along the top surface and sidewall surfaces of the first portion and the second portion of the metal layer; depositing a maintenance layer between the first portion and the second portion of the metal layer to seal the groove to form an air gap; depositing a thermally conductive layer over the maintenance layer and over the first portion and the second portion of the metal layer, wherein the thermally conductive layer has a thermal conductivity of not less than about 10 W / m·K; and performing a planarization process to partially remove the thermally conductive layer and expose the first portion and the second portion of the metal layer.

[0006] Still other embodiments of the present application provide a semiconductor structure comprising: a conductive via extending through a first dielectric layer; a first metal line located above the conductive via and in electrical contact with the conductive via; and a second metal line located above the first dielectric layer and separated from the first metal line by a dielectric structure, wherein a top surface of the dielectric structure is coplanar with top surfaces of the first metal line and the second metal line, and wherein the dielectric structure comprises: a top pad extending between the first metal line and the second metal line; a thermally conductive layer located above the top pad, wherein the top pad extends along a bottom surface and sidewall surfaces of the thermally conductive layer; and an air gap defined by the top pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 is a partial cross-sectional view of an exemplary semiconductor structure according to one or more aspects of an embodiment of the present disclosure.

[0009] Figure 2 is a flow chart of a method for forming an interconnect layer of a semiconductor structure according to one or more aspects of an embodiment of the present disclosure.

[0010] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 , Fig. 27 , Fig.28 and Fig.29 is a workpiece according to one or more aspects of an embodiment of the present disclosure. Figure 2 Partial cross-sectional views of various manufacturing stages of the method.

[0011] Fig.13 According to one or more aspects of the embodiments of the present disclosure Fig.12 A partial top view of the workpiece shown in . DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0014] In addition, when "about," "approximately," etc. are used to describe a value or a range of values, as understood by one of ordinary skill in the art, the term is intended to encompass values ​​within a reasonable range that takes into account variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the value, a value or range of values ​​encompasses a reasonable range that includes the described value, such as within + / - 10% of the described value. For example, a material layer having a thickness of "about 5 nm" may include a size range from 4.5 nm to 5.5 nm, where the manufacturing tolerance associated with depositing material layers known to one of ordinary skill in the art is + / - 10%.

[0015] As front-end-of-line (FEOL) devices become smaller, back-end-of-line (BEOL) interconnect structures play a greater role in meeting power, performance, and area requirements. BEOL interconnect structures may include low-k dielectric materials to maintain low parasitic capacitance. Typically, low-k dielectric materials exhibit thermal conductivity lower than those of high-k dielectric materials, metals, or semiconductor materials. The low thermal conductivity of low-k dielectric materials hinders their ability to effectively dissipate the heat generated by FEOL devices. In addition, it is becoming increasingly challenging to package all conductive components on one side of the substrate. In order to reduce packaging density, wiring components may be partially moved to the back side of the substrate. Such wiring components may include backside power rails and / or backside contacts. The introduction of backside wiring components further exacerbates heat accumulation due to the increased distance between the device and the heat sink. The industry is scrambling to find solutions for interconnect structures to achieve high thermal conductivity while maintaining low parasitic capacitance.

[0016] The disclosed embodiments provide a method for forming a dielectric structure disposed between adjacent metal lines for heat dissipation and parasitic capacitance reduction. In an exemplary process, a metal layer is patterned to form a metal line with a groove therebetween. A sacrificial layer is then deposited to fill the lower portion of the groove. A maintenance layer is deposited on the sacrificial layer. After forming the maintenance layer, a thermal treatment is performed to selectively remove the sacrificial layer, thereby forming an air gap between the patterned metal lines. After removing the sacrificial layer, a high-κ non-conductive material layer is formed on the maintenance layer to fill the upper portion of the groove. The high-κ non-conductive material layer formed of a material with good thermal conductivity promotes heat dissipation. The air gap between the metal lines helps to maintain low capacitance.

[0017] Various aspects of the disclosed embodiments will now be described in more detail with reference to the accompanying drawings. Figure 1 is a partial cross-sectional view of an exemplary semiconductor structure according to one or more aspects of an embodiment of the present disclosure. Figure 21 is a flow chart illustrating a method 100 for forming an interconnect layer of a semiconductor structure according to one or more aspects of an embodiment of the present disclosure. The method 100 is merely an example and is not intended to limit the disclosed embodiments to what is explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the method 100. For the sake of simplicity, not all steps are described in detail herein. Figures 3 to 29 Describing method 100, Figures 3 to 29 1 is a partial top view or cross-sectional view of a workpiece 200 at different manufacturing stages according to an embodiment of the method 100. Because the workpiece 200 will be manufactured into a semiconductor structure at the end of the manufacturing process, the workpiece 200 may be referred to as a semiconductor structure 200 as the context requires. In addition, throughout the application and across different embodiments, the same reference numerals represent the same components with similar structures and compositions unless otherwise specified. The source / drain region may be referred to as a source or a drain, individually or collectively depending on the context.

[0018] Figure 1 6 is a partial schematic cross-sectional view of various layers (levels) that may be fabricated over a semiconductor substrate (or wafer) 60 to form a portion of a semiconductor structure according to various aspects of an embodiment of the present disclosure. Figure 1 As shown in , each layer includes a device layer DL and a front-side multilayer interconnect structure FMLI disposed above the device layer DL. In various embodiments, the structure may also include a back-side multilayer interconnect structure BMLI disposed below the device layer DL. The back-side multilayer interconnect structure BMLI may be similar to the front-side multilayer interconnect structure FMLI.

[0019] The device layer DL includes devices (eg, transistors, resistors, capacitors, and / or inductors) and / or device components (eg, doped wells, gate structures, and / or source / drain features). Figure 1 In the illustrated embodiment, the device layer DL includes a substrate 60, a doped region 62 (e.g., an n-well and / or a p-well) disposed in the substrate 60, an isolation feature 64, and a transistor T. In the depicted embodiment, the transistor T includes a suspended channel layer 70 disposed between source / drain features 72 and a gate structure 68, wherein the gate structure 68 wraps around and / or surrounds the suspended channel layer 70. Each gate structure 68 has a metal gate stack formed of a gate electrode 74 disposed over a gate dielectric layer 76 and gate spacers 78 disposed along sidewalls of the metal gate stack.

[0020] The multilayer interconnect structures FMLI and BMLI electrically couple the various devices and / or components of the device layer DL so that the various devices and / or components can operate as specified by the design requirements. Each of the multilayer interconnect structures FMLI and BMLI may include one or more interconnect layers. In the described embodiment, the front-side multilayer interconnect structure FMLI includes a contact interconnect layer (CO level), a via zero interconnect layer (V0 level), a metal zero interconnect layer (M0 level), a via one interconnect layer (V1 level), a metal one interconnect layer (M1 level), a via two interconnect layer (V2 level), a metal two interconnect layer (M2 level), a via three interconnect layer (V3 level) and a metal three interconnect layer (M3 level). Each of the CO level, V0 level, M0 level, V1 level, M1 level, V2 level, M2 level, V3 level and M3 level may be referred to as a metal level. The metal line formed at the M0 level may be referred to as an M0 metal line. Similarly, vias or metal lines formed at the V1 level, M1 level, V2 level, M2 level, V3 level, and M3 level may be referred to as V1 vias, M1 metal lines, V2 vias, M2 metal lines, V3 vias, and M3 metal lines, respectively. The disclosed embodiments contemplate a multilayer interconnect structure FMLI having more or fewer interconnect layers and / or levels, for example, a total number of N interconnect layers (levels) of the front-side multilayer interconnect structure FMLI, where N is an integer ranging from 1 to 10. Each level of the front-side multilayer interconnect structure FMLI includes conductive components (e.g., metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (e.g., an interlayer dielectric (ILD) layer and an etch stop layer (ESL)). The dielectric layers of the front-side multilayer interconnect structure FMLI are collectively referred to as dielectric structures 66. In some embodiments, conductive components at the same level (such as the M0 level) of the multilayer interconnect structure FMLI are formed simultaneously. In some embodiments, conductive features at the same level of the multilayer interconnect structure FMLI have top surfaces that are substantially coplanar with each other and / or bottom surfaces that are substantially coplanar with each other.

[0021] exist Figure 1In the illustrated embodiment, the CO level includes a source / drain contact MD disposed in the dielectric structure 66. The source / drain contact MD may be formed on and in contact with a silicide layer disposed directly on the source / drain component 72. The V0 level includes a gate via VG disposed on the gate structure 68 and a source / drain contact via VD disposed on the source / drain contact MD, wherein the gate via VG connects the gate structure 68 to the M0 metal line, and the source / drain via V0 connects the source / drain contact MD to the M0 metal line. In some embodiments, the V0 level may also include a docking contact disposed in the dielectric structure 66. The V1 level includes a V1 via disposed in the dielectric structure 66, wherein the V1 via connects the M0 metal line to the M1 metal line. The M1 level includes an M1 metal line disposed in the dielectric structure 66. The V2 level includes V2 vias disposed in dielectric structure 66, wherein the V2 vias connect the M1 metal line to the M2 metal line. The M2 level includes M2 metal lines disposed in dielectric structure 66. The V3 level includes V3 vias disposed in dielectric structure 66, wherein the V3 vias connect the M2 metal line to the M3 metal line. For clarity, the diagram has been simplified. Figure 1 , to better understand the inventive concepts of the embodiments of the present disclosure.

[0022] refer to Figure 2 and Figure 3 , method 100 includes block 102, where a workpiece 200 is received (or provided). Workpiece 200 includes substrate 202. In some embodiments, substrate 202 includes silicon. Alternatively, according to some embodiments, substrate 202 may include other elemental semiconductors, such as germanium. In some embodiments, substrate 202 additionally or alternatively includes compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. In some embodiments, substrate 202 includes alloy semiconductors, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, and gallium indium phosphide.

[0023] In some embodiments, the substrate 202 includes a semiconductor on insulator (SOI) structure. For example, the substrate may include a buried oxide (BOX) layer formed by a process such as isolation by implanted oxygen (SIMOX). In various embodiments, the substrate 202 includes various p-type doped regions and / or n-type doped regions, such as a p-type well, an n-type well, a p-type source / drain component, and / or an n-type source / drain component, formed by processes such as ion implantation and / or diffusion. The substrate 202 may also include other functional components, such as resistors, capacitors, diodes, transistors (e.g., field effect transistors (FETs)), and source / drain contacts and gate contacts extending to and electrically coupled to the source / drain components and gate structures of the transistors below. The conductive component 203 is disposed in a top portion of the substrate 202. In various embodiments, the conductive component 203 may be one of the gate electrodes 74 or one of the source / drain contacts MD, such as Figure 1 as shown in .

[0024] The workpiece 200 also includes an interlayer dielectric (ILD) layer 204 deposited over the substrate 202. In some embodiments, the ILD layer 204 may include a dielectric material such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. The dielectric material may be formed by plasma enhanced chemical vapor deposition (PECVD), flowable chemical vapor deposition (FCVD), or other suitable methods. In some embodiments, the dielectric material is formed of a low-k (e.g., a dielectric constant value of about 3.9) dielectric material or an extremely low-k (e.g., a dielectric constant value of about 2.5) dielectric material, such as a carbon-containing dielectric material, and may also contain nitrogen, hydrogen, oxygen, and combinations thereof. If an extremely low-k dielectric material is used, a curing process may follow after depositing the extremely low-k dielectric material to increase its porosity, reduce the k value, and improve mechanical strength. The ILD layer 204 includes vias that extend through the ILD layer 204 and provide electrical coupling to conductive features in the substrate 202. In this embodiment, a via 205 is shown. The via 205 extends to and electrically couples to the underlying conductive feature 203. In various embodiments, the via 205 may be one of the gate vias VG or one of the source / drain contact vias VD, such as Figure 1 as shown in .

[0025] refer to Figure 2 and Figure 4, the method 100 includes a block 104 in which a glue layer 206, a metal layer 208, and a hard mask 210 are formed over the ILD layer 204. The glue layer 206 functionally provides adhesion between the ILD layer 204 and the subsequently deposited metal layer 208. The glue layer 206 also serves as an etch stop layer and provides endpoint control during a subsequent etching process. The material composition of the glue layer 206 is selected so that there is an etching selectivity between the glue layer and the metal layer to be formed thereon, so that the etching process that etches through the metal layer stops at the glue layer 206 without causing etching damage to the underlying layers. The glue layer 206 may include tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), or other suitable metal nitrides. The glue layer 206 may be deposited using atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or other suitable methods. In some embodiments, the glue layer 206 has a thickness ranging from about 100 to about 1000 Å. to about Thickness.

[0026] A metal layer 208 is deposited over the glue layer 206. As will be discussed in further detail, the metal layer 208 will be patterned into metal lines, one of which is electrically coupled to the via 205 and the underlying conductive feature 203.

[0027] The conventional process for forming metal lines or vias in the intermetal dielectric (IMD) layer of the interconnect structure is called a "damascene" process. Typically, the damascene process involves forming a groove-shaped opening in the IMD layer. Conventional photolithography and etching techniques are typically used to form the groove-shaped opening. After the groove-shaped opening is formed, a diffusion barrier layer and an adhesive layer are deposited in the groove-shaped opening. Then an electrochemical plating process is used to fill the groove-shaped opening with a metal or metal alloy to form a metal line and possible vias below the metal line. Excess metal material on the surface of the IMD layer is then removed by a CMP process.

[0028] With increasing packaging density in microelectronic devices, copper (Cu) has become a promising material due to its excellent electrical conductivity (5.96×10 7S / m) and outstanding electromigration resistance and used as interconnect metal between other available metal materials. The damascene process using copper (which involves copper electroplating and subsequent copper CMP) is usually used for patterning copper. At the same time, as the size of semiconductor devices continues to shrink, the damascene process using copper has also appeared many potential problems that may affect the quality of the metallization layer. For example, when the critical dimension (CD) of the metal line is below 20 nanometers (nm), the groove-shaped opening may become too narrow and the high aspect ratio, and the stack of diffusion barrier layer and bonding layer will occupy most of the opening, leaving less space for more conductive copper. The remaining smaller amount of copper has a higher resistance and therefore reduces the performance of semiconductor devices. This problem is particularly serious in the high aspect ratio (e.g., >3) groove-shaped openings of small width. In addition, the groove-shaped opening may not be properly filled by the damascene process, so that the top of the opening may be blocked, which may produce a gap below and deteriorate the device performance. In addition, the narrower copper wire may have a shorter life before the subsequent higher current density destroys them through electromigration.

[0029] In comparison, noble metals have become important in technology as conductive components in integrated circuits. The term "noble metal" as used herein means a metal selected from ruthenium (Ru), iridium (Ir), rhodium (Rh), platinum (Pt), palladium (Pd), osmium (Os), silver (Ag) and gold (Au). All other metals are classified as non-noble metals in this article. Different from some non-noble metals (such as copper) that are not suitable for direct patterning, noble metals can be patterned to form metal lines with a CD less than about 20nm due to being suitable for direct patterning in dry etching methods (e.g., reactive ion etching (RIE) processes). In some embodiments, metal layer 208 includes a noble metal, an alloy of two or more noble metals, or an alloy of a noble metal mixed with a non-noble metal, such as copper (Cu), cobalt (Co), molybdenum (Mo), chromium (Cr), tungsten (W), manganese (Mn) and aluminum (Al). In some embodiments, metal layer 208 includes a noble metal selected from the group of Ru, Ir, Rh and Pt, such as Ru in a specific example. In another embodiment, the metal layer 208 includes an alloy of a noble metal and a noble metal or a non-noble metal, such as PtIr, PdPt, or PdNi. In yet another embodiment, the metal used to form the metal layer 208 is not limited to a noble metal as long as the metal is suitable for direct patterning, such as Co, Mo, and W. The metal layer 208 may be deposited by ALD, CVD, PVD, electroplating, or other suitable methods. According to some embodiments, the metal layer 208 may have a thickness ranging from about 100 to about 1000 Å. to about Thickness.

[0030] The hard mask 210 is deposited on the metal layer 208 using ALD, CVD, PVD, or other suitable methods. In the illustrated embodiment, the hard mask 210 is a dual-layer structure and includes a first layer 210a and a second layer 210b formed on the first layer 210a. The first layer 210a and the second layer 210b have different compositions and may be formed of aluminum oxide, silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxynitride, silicon carbon oxynitride, other suitable materials, or combinations thereof.

[0031] refer to Figure 2 and Figure 5 , the method 100 includes block 106, where the hard mask 210 is patterned in a photolithography process and an etching process, and then the metal layer 208 is patterned in a metal etching process to form metal lines. Figure 5 , trench 212 is formed after patterning the metal layer 208 .

[0032] The hard mask 210 is patterned using a suitable process including a double patterning process, a multiple patterning process, photolithography, a self-alignment process, and a mandrel spacer process to define the pattern of lines that will be transferred to the metal layer 208 below. In the illustrated embodiment, a photoresist layer (not shown) is formed on the hard mask 210 using a spin coating process and a soft baking process. Then, the photoresist layer is exposed to radiation. The radiation can be extreme ultraviolet (EUV) radiation using a wavelength of 13.6nm, ultraviolet radiation using a wavelength of 436nm, 405nm, or 365nm, or DUV radiation using a wavelength of 248nm, 193nm, or 157nm, or other available radiation for photolithography, such as an electron beam. Subsequently, the exposed photoresist layer is developed using post-exposure baking (PEB), development, and hard baking to form a patterned photoresist layer above the hard mask 210. The hard mask 210 is etched by etching the opening defined in the patterned photoresist layer to form a patterned hard mask 210. Thereafter, the patterned photoresist layer is removed using a suitable process such as wet stripping or plasma ashing.

[0033] Subsequently, the metal layer 208 is etched in a metal etching process using the patterned hard mask 210 as an etching mask. In the illustrated embodiment, the metal etching process is a dry etching process, such as a plasma etching process. In a furtherance of the embodiment, the metal etching process comprises an RIE process. The RIE process may include process parameters such as a reactor operating pressure ranging from about 10 mTorr to about 300 mTorr, an RF power less than 2700 W (e.g., ranging from about 900 W to about 1600 W), a bias voltage less than about 4500 W, a temperature ranging from about 10° C. to about 80° C., and an RIE etching period ranging from about 200 seconds to about 500 seconds. The RIE source gas may include an ion composition, such as argon (Ar), a fluorine-containing gas (e.g., CF 4 , SF6 , CH 2 F 2 , CHF 3 , C 4 F 8 , C 2 F 6 ) or a combination thereof. The RIE source gas may also include certain chemical etchants, such as chlorine-containing gases (e.g., Cl 2 , CHCl 3 , CCl 4 In some embodiments, the chemical etchant includes boron (B) (e.g., B 2 F 4 , BCl 3 , B 4 Cl 4 , BBr 3 ). In a specific embodiment, the chemical etchant includes a combination of boron and chlorine. In some embodiments, the total etchant flow rate is less than 1800 sccm, such as about 1200 sccm. The chemical etchant may have a flow rate of about 30% to about 50% of the total etchant flow rate, such as about 40%. The resulting metal lines after patterning the metal layer 208 may have a critical dimension (CD) in the sub-20 nm range. As discussed above, the selection of the metal composition (e.g., a noble metal) for the metal layer 208 ensures a bulk metal composition with low resistivity for narrow metal lines. For simplicity, after the operations in box 106, the metal lines patterned by the metal layer 208 are represented as metal lines 208L. Grooves (or openings) 212 are sandwiched between adjacent metal lines 208L, exposing the top surface of the glue layer 206. The glue layer 206 acts as an etch stop layer to protect the ILD layer 204 from the RIE process. Subsequently, the exposed portion of the glue layer 206 is etched in another etching process such as wet etching, dry etching, or a combination thereof. The trench 212 extends down to the top surface of the ILD layer 204. The etching of the hard mask 210, the metal layer 208, and the glue layer 206 may be in-situ.

[0034] refer to Figure 2 and Figure 6 , the method 100 includes block 108, in which a dielectric cap layer 214 is formed over the workpiece 200. In an embodiment, the dielectric cap layer 214 is conformally deposited over the workpiece 200, including in the trench 212, using ALD, CVD, plasma enhanced CVD (PECVD), plasma enhanced ALD (PEALD), or other suitable methods. The term "conformal" may be used herein to facilitate describing a layer having a substantially uniform thickness over various regions. The dielectric cap layer 214 may be deposited to a thickness of about Peace In an embodiment, the dielectric cover layer 214 is formed of a high-κ material. The term "high-κ material" refers to a material having a thermal conductivity of not less than 10 W / m·K (watts / meter·Kelvin). High-κ materials are particularly effective in conducting heat and are also referred to as thermally conductive materials. This means that the dielectric cover layer 214 made of a high-κ material allows heat to pass through it quickly and efficiently. As an example and not limitation, the dielectric cover layer 214 may include a high-κ material such as aluminum nitride (AlN), hexagonal boron nitride (h-BN), graphene oxide, diamond, diamond-like carbon, silicon carbide (SiC), silicon carbonitride (SiCN), transition metal dichalcogenides (TMD) (e.g., MoS 2 、MoSe 2 , WS 2 or WSe 2 ) or any other suitable high-κ material. For aluminum nitride, it exhibits a high thermal conductivity of about 370 W / m·K. For TMD, it typically exhibits a thermal conductivity of more than 10 W / m·K. For h-BN, it is in a layered structure in a crystalline form similar to graphite and exhibits an in-plane thermal conductivity of more than 390 W / m·K at room temperature. In comparison, amorphous BN (a-BN) is in a non-crystalline amorphous form and only exhibits an in-plane thermal conductivity of around 3 W / m·K, which is not considered a high-κ material in the context of the disclosed embodiments.

[0035] refer to Figure 2 and Figures 7 and 8 The method 100 includes a block 110 in which a sacrificial layer 216 is formed over the dielectric cap layer 214 to partially fill the trench 212. In an exemplary process, an organic layer (such as a polymer layer) including C, O, N, and H is deposited over the workpiece 200, such as Figure 7 As shown in . The organic layer can be deposited by using CVD, PECVD, flowable CVD (FCVD), ALD, PEALD, or spin coating. The deposited organic layer can be heated to increase its fluidity to have a smoother top surface. A curing process can then be performed to cure the organic layer. In some examples, the curing process can include a baking process, an annealing process, a drying process, or an ultraviolet (UV) radiation process. Then, the cured organic layer is planarized and selectively etched back to form a sacrificial layer 216 in the lower portion of the trench 212, as shown in FIG. Figure 8 According to some embodiments, the sacrificial layer 216 may have a thickness ranging from about to about As will be discussed in further detail, the etch back of the organic layer is used to define the height of the air gap between the metal lines 208L by removing the sacrificial layer 216 in a subsequent step. Although the sacrificial layer 216 will be removed in a subsequent step, the sacrificial layer 216 is selected so that it can withstand the planarization process and the deposition of the maintenance layer (described below) without being structurally damaged. For those reasons, the sacrificial layer 216 needs to be easy to remove and also remain stable around the deposition temperature of the maintenance layer. Based on these criteria, the sacrificial layer 216 can include polyvinyl alcohol (PVA), polyacrylate, polydimethylsiloxane (PDMS), polycarbonate (PC), or other suitable polymers.

[0036] refer to Figure 2 and Fig. 9 , method 100 includes box 112, in which a maintenance layer 220 is formed over the workpiece 200. In some embodiments, a low-k dielectric material is conformally deposited over the workpiece 200 (including on the sacrificial layer 216 and the dielectric cap layer 214) to form a maintenance layer 220 having a loose structure and covering the sacrificial layer 216. In some embodiments, the maintenance layer 220 has a porous structure. The deposition for forming the maintenance layer 220 can be performed by PVD, CVD, ALD, PECVD, PEALD, or other suitable processes. In some embodiments, the maintenance layer 220 includes silicon oxide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, or other suitable dielectric materials. According to some embodiments, the maintenance layer 220 can have a thickness ranging from about 100 to about 100%. to about Thickness.

[0037] refer to Figure 2 and Fig.10 , method 100 includes block 114, where sacrificial layer 216 is selectively removed to form air gaps 222 between metal lines 208L and below sustaining layer 220. In some embodiments, a thermal treatment (e.g., an annealing process, a baking process) and / or an ultraviolet process may be performed to decompose sacrificial layer 216 into volatile compounds that may diffuse through the porous structure of sustaining layer 220. Removing sacrificial layer 216 forms air gaps 222. Fig.10 As depicted, each of air gaps 222 is defined by dielectric cap layer 214 and sustaining layer 220. Because air has a dielectric constant close to 1, air gaps 222 reduce the effective dielectric constant of the dielectric structure between metal lines 208L.

[0038] refer to Figure 2 and Fig.11, method 100 includes block 116, wherein a high thermal conductivity (high κ) material layer 224 is formed over the sustaining layer 220 using ALD, CVD, plasma enhanced CVD (PECVD), or microwave PECVD. In some embodiments, the high κ material layer 224 may include diamond or diamond-like carbon. In some other embodiments, the high κ material layer 224 includes aluminum nitride (AlN), hexagonal boron nitride (h-BN), graphene oxide, silicon carbide (SiC), silicon carbonitride (SiCN). In an advancement of some embodiments, the high κ material is a low-k (e.g., a dielectric constant value of about 3.9) dielectric material. According to some embodiments, the high κ material layer 224 may have a dielectric constant ranging from about 1.0 to about 1.0. to about The high-κ material in dielectric cover layer 214 and high-κ material layer 224 may be the same or different. For example, high-κ material layer 224 may have a higher thermal conductivity than dielectric cover layer 214. Sustaining layer 220 separates high-κ material layer 224 from dielectric cover layer 214 so that high-κ material layer 224 does not contact dielectric cover layer 214.

[0039] refer to Figure 2 and Fig.12, the method 100 includes a block 118, in which the workpiece 200 is planarized to expose the metal line 208L. After forming the high-κ material layer 224, a planarization process is performed on the workpiece 200. In an embodiment, the planarization process stops after exposing the top surface of the metal line 208L. When the planarization process is completed, the topmost surface of the dielectric cap layer 214, the topmost surface of the maintenance layer 220, and the top surface of the high-κ material layer 224 are coplanar. The maintenance layer 220 extends along the bottom surface and sidewall surface of the high-κ material layer 224 and contacts the dielectric cap layer 214. The dielectric cap layer 214, the maintenance layer 220, the high-κ material layer 224, and the air gap 222 trapped between the dielectric cap layer 214 and the maintenance layer 220 collectively define a dielectric structure disposed between two adjacent metal lines 208L. Because air has a dielectric constant close to 1, the air gap 222 reduces the effective dielectric constant of the dielectric structure between the metal lines 208L. In other words, the air gap 222 between the metal lines helps to maintain low parasitic capacitance between the metal lines 208L. At the same time, the high-κ property caused by applying the high-κ material in the combination of the dielectric cap layer 214, the maintenance layer 220, and the high-κ material layer 224 allows heat to spread horizontally between the metal lines 208L, making it less likely that heat will be trapped in the metal line layer. In some embodiments, the height H2 measured from the top surface of the high-κ material layer 224 to the bottom surface of the maintenance layer 220 is about 20% to about 50% of the height H1 of the metal line 208L. The range from about 20% to about 50% is not trivial or arbitrary. If the ratio of H2 / H1 is less than about 20%, the heat dissipation capability may be impaired due to the relatively thin high-κ material layer 224; if the ratio of H2 / H1 is greater than about 50%, the parasitic capacitance may become too large and thus reduce the circuit speed due to the relatively small volume of the air gap 222.

[0040] Fig.13 Depicted Fig.12 1 is a partial top view of the workpiece at the end of the operation in block 118. More specifically, Figures 3 to 12 along Fig.13 AA cutting in. Fig.13Each metal line 208L extending longitudinally in the Y direction and arranged in the X direction is shown. A metal line 258L formed in a metal line layer directly above the metal line 208L is then depicted in a dotted rectangular frame. A through hole 250 formed to electrically connect the metal line 208L to the metal line 258L is depicted in a dotted circle. Each metal line 258L extends longitudinally in the X direction and is arranged in the Y direction. In an embodiment, the metal line 208L represents an M0 metal line, and the through hole 205 represents one of the V0 through holes, so the metal line 258L to be formed represents an M1 metal line, and the through hole 250 to be formed represents a V1 through hole. In another embodiment, the metal line 208L can represent an M1 metal line, and the through hole 205 represents one of the V1 through holes, so the metal line 258L to be formed represents an M2 metal line, and the through hole 250 to be formed represents a V2 through hole. Figures 14 to 26 The formation of metal line 258L and one of vias 250 is depicted, which is Fig.13 BB cutting in.

[0041] refer to Figure 2 and Fig.14 , the method 100 includes a block 120, wherein a dielectric cap layer 214, a sustaining layer 220, and a high-κ material layer 224 ( Fig.12 ), a first etch stop layer (ESL) 240, a low dielectric constant (or low-k) dielectric layer 242, and a hard mask 244 are formed on the substrate. In some embodiments, the first ESL 240 may include aluminum oxide, aluminum nitride, silicon nitride, silicon oxycarbide, silicon carbonitride, or a combination thereof, and may be deposited using atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or plasma enhanced CVD (PECVD). After forming the first ESL 240, a low-k dielectric layer 242 is formed. The low-k dielectric layer 242 has a dielectric constant less than that of silicon oxide, which is about 3.9. For example, the low-k dielectric layer 242 may include a porous organic silicate film (e.g., SiCOH), tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, silicon oxycarbonitride (SiOCN), boron carbonitride, spin-on silicon-based polymer dielectrics, or combinations thereof. The hard mask 244 is deposited on the low-k dielectric layer 242 using ALD, CVD, PVD, or other suitable methods. In the illustrated embodiment, the hard mask 244 is a single-layer structure or a double-layer structure. The hard mask 244 may be formed of aluminum oxide, silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbon, silicon oxynitride, silicon oxycarbonitride, other suitable materials, or combinations thereof.

[0042] refer to Figure 2 and Fig.15 , the method 100 includes a block 122, wherein a hard mask 244, a low-k dielectric layer 242, and a first ESL 240 are patterned to form a via opening 246. Patterning the hard mask 244, the low-k dielectric layer 242, and the first ESL 240 may include a photolithography process and an etching process, such as depositing a photoresist layer; photolithographically patterning the photoresist layer; etching the hard mask 244 and then etching the low-k dielectric layer 242 and the first ESL 240 using the patterned photoresist layer and the patterned hard mask 244 as an etching mask; and selectively removing the photoresist layer. The photoresist layer may include a hydrocarbon and may be deposited using spin coating. Etching the low-k dielectric layer 242 and the first ESL 240 may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. After forming the via opening 246, the photoresist layer may be removed by ashing or selective etching.

[0043] refer to Figure 2 and Fig.16 , the method 100 includes a block 124, in which a via 250 is formed in the via opening 246. The via 250 extends through the low-k dielectric layer 242 and the first ESL 240 to couple to the metal line 208L. In some embodiments, a layer of metal material is first deposited over the workpiece 200 (including in the via opening 246). In some embodiments, the metal material layer (and the via 250 formed therefrom) includes ruthenium (Ru), tungsten (W), molybdenum (Mo), combinations thereof, or other suitable conductive materials that are not prone to diffusion problems. In some embodiments, the via 250 is made of a different metal than the metal line 208L. In some optional embodiments, the via 250 and the metal line 208L are made of the same metal. The metal material layer can be deposited using ALD, CVD, PEALD, PECVD, electroplating, or chemical plating deposition. After depositing the metal material layer, a planarization process, such as a chemical mechanical polishing (CMP) process, is performed to remove excess metal material layer and hard mask 244 to expose the top surface of low-k dielectric layer 242. After the planarization process, via 250 is formed in via opening 246. To reduce parasitic resistance, via 250 can be formed of metal and does not include a barrier layer. Forming unblocked via 250 advantageously reduces parasitic resistance (e.g., contact resistance) of workpiece 200.

[0044] refer to Figure 2 and Fig.17, method 100 includes box 126, in which a glue layer 256, a metal layer 258, and a hard mask 260 are formed over the low-k dielectric layer 242 and the via 250. The glue layer 256 functionally provides adhesion between the low-k dielectric layer 242 and the subsequently deposited metal layer 258. The glue layer 256 also serves as an etch stop layer and provides endpoint control during subsequent etching processes. The material composition of the glue layer 256 is selected so that there is an etching selectivity between the glue layer and the metal layer to be formed thereon, so that the etching process that etches through the metal layer stops at the glue layer 256 without causing etching damage to the underlying layers. The glue layer 256 may include tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), or other suitable metal nitrides. The glue layer 256 can be deposited using atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or other suitable methods. In some embodiments, the glue layer 256 has a thickness ranging from about 100 to about 1000. to about Thickness.

[0045] Metal layer 258 is deposited on glue layer 256. Similar to metal layer 208, metal layer 258 is formed of a metal suitable for direct patterning. In some embodiments, metal layer 258 includes a noble metal, such as ruthenium (Ru), iridium (Ir), rhodium (Rh), platinum (Pt), palladium (Pd), osmium (Os), silver (Ag) and gold (Au). In some embodiments, metal layer 258 includes an alloy of two or more noble metals or an alloy of a noble metal mixed with a non-noble metal, such as copper (Cu), cobalt (Co), molybdenum (Mo), chromium (Cr), tungsten (W), manganese (Mn) and aluminum (Al). In some embodiments, metal layer 258 includes a noble metal selected from the group of Ru, Ir, Rh and Pt, such as Ru in the specific example. In another embodiment, metal layer 258 includes an alloy of a noble metal with a noble metal or a non-noble metal, such as PtIr, PdPt or PdNi. In yet another embodiment, the metal used to form metal layer 258 is not limited to a noble metal, as long as the metal is suitable for direct patterning, such as Co, Mo, and W. In some embodiments, metal layer 208 and metal layer 258 include different metals, such as two different noble metals. Alternatively, metal layer 208 and metal layer 258 may include the same metal, such as the same noble metal (e.g., Ru). Metal layer 258 may be deposited by ALD, CVD, PVD, electroplating, or other suitable methods. According to some embodiments, metal layer 258 may have a thickness ranging from about 100 nm to about 100 nm. to about Thickness.

[0046] The hard mask 260 is deposited on the metal layer 258 using ALD, CVD, PVD or other suitable methods. In the illustrated embodiment, the hard mask 260 is a single-layer structure or a double-layer structure. The hard mask 260 can be formed of aluminum oxide, silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxynitride, silicon carbon oxynitride, other suitable materials or combinations thereof.

[0047] refer to Figure 2 and Fig.18 The method 100 includes block 128, where the hard mask 260 is patterned in a photolithography process and an etching process, and then the metal layer 258 is patterned in a metal etching process to form metal lines. After the metal layer 258 is patterned, trenches 262 are formed.

[0048] The hard mask 260 is patterned using a suitable process including a double patterning process, a multiple patterning process, photolithography, a self-alignment process, and a mandrel spacer process to define the pattern of the line to be transferred to the metal layer 258 below. In the illustrated embodiment, a photoresist layer (not shown) is formed on the hard mask 260 using a spin coating process and a soft baking process. Then, the photoresist layer is exposed to radiation. The radiation can be extreme ultraviolet (EUV) radiation using a wavelength of 13.6nm, ultraviolet radiation using a wavelength of 436nm, 405nm, or 365nm, or DUV radiation using a wavelength of 248nm, 193nm, or 157nm, or other available radiation for photolithography, such as an electron beam. Subsequently, the exposed photoresist layer is developed using post-exposure baking (PEB), development, and hard baking to form a patterned photoresist layer above the hard mask 260. The hard mask 260 is etched by etching the opening defined in the patterned photoresist layer to form a patterned hard mask 260. Thereafter, the patterned photoresist layer is removed using a suitable process such as wet stripping or plasma ashing.

[0049] Subsequently, the metal layer 258 is etched in a metal etching process using the patterned hard mask 260 as an etching mask. In the illustrated embodiment, the metal etching process is a dry etching process, such as a plasma etching process. In a furtherance of the embodiment, the metal etching process includes a RIE process. The RIE process can be similar to the process applied in etching the metal layer 208. For simplicity, after the operation in box 128, the metal line patterned by the metal layer 258 is represented as metal line 258L. Grooves (or openings) 262 are sandwiched between adjacent metal lines 258L, exposing the top surface of the glue layer 256. The glue layer 256 acts as an etching stop layer to protect the low-k dielectric layer 242 from the RIE process. Subsequently, the exposed portion of the glue layer 256 is etched in another etching process (such as wet etching, dry etching, or a combination thereof). The grooves 262 extend downward to the top surface of the low-k dielectric layer 242. The etching of the hard mask 260, the metal layer 258, and the glue layer 256 can be in situ. As shown in FIG. Fig.18 As depicted in , the top surface of the through-hole 250 may be partially exposed in one or more of the trenches 262 depending on the location of the trenches 262 .

[0050] refer to Figure 2 and Fig.19 The method 100 includes block 130, where a dielectric cap layer 264 is formed over the workpiece 200. In an embodiment, the dielectric cap layer 264 is conformally deposited over the workpiece 200, including in the trench 262, using ALD, CVD, plasma enhanced CVD (PECVD), plasma enhanced ALD (PEALD), or other suitable methods. The dielectric cap layer 264 may be deposited to a thickness of about 100 to about 500 nm. Peace In an embodiment, dielectric cover layer 264 is formed of a high-κ material having a thermal conductivity of not less than 10 W / m·K. This means that dielectric cover layer 264 made of a high-κ material allows heat to pass through it quickly and efficiently. By way of example and not limitation, dielectric cover layer 264 may include a high-κ material such as aluminum nitride (AlN), hexagonal boron nitride (h-BN), graphene oxide, diamond, diamond-like carbon, silicon carbide (SiC), silicon carbonitride (SiCN), transition metal dichalcogenides (TMDs) (e.g., MoS 2 、MoSe 2 , WS 2 or WSe 2 ) or any other suitable high-κ material. In some embodiments, dielectric cap layer 264 and underlying dielectric cap layer 214 may include different high-κ materials. Alternatively, dielectric cap layer 264 and underlying dielectric cap layer 214 may include the same high-κ material. In the illustrated embodiment, dielectric cap layer 264 contacts via 250 if the top surface of via 250 may be partially exposed in one or more of trenches 262.

[0051] refer to Figure 2 and Figure 20 to Figure 21 The method 100 includes block 132, where a sacrificial layer 266 is formed over the dielectric cap layer 264 to partially fill the trench 262. In an exemplary process, an organic layer (such as a polymer layer) including C, O, N, and H is deposited over the workpiece 200, such as Fig. 20As shown in . The organic layer can be deposited by using CVD, PECVD, flowable CVD (FCVD), ALD, PEALD, or spin coating. The deposited organic layer can be heated to increase its fluidity to have a smoother top surface. A curing process can then be performed to cure the organic layer. In some examples, the curing process can include a baking process, an annealing process, a drying process, or an ultraviolet (UV) radiation process. Then, the cured organic layer is planarized and selectively etched back to form a sacrificial layer 266 in the lower portion of the trench 262, as shown in FIG. Fig.21 According to some embodiments, the sacrificial layer 266 may have a thickness ranging from about to about As will be discussed in further detail, the etch back of the organic layer is used to define the height of the air gap between the metal lines 258L by removing the sacrificial layer 266 in a subsequent step. Although the sacrificial layer 266 will be removed in a subsequent step, the sacrificial layer 266 is selected so that it can withstand the planarization process and the deposition of the maintenance layer (described below) without being structurally damaged. For those reasons, the sacrificial layer 266 needs to be easy to remove and also remain stable around the deposition temperature of the maintenance layer. Based on these criteria, the sacrificial layer 266 may include polyvinyl alcohol (PVA), polyacrylate, polydimethylsiloxane (PDMS), polycarbonate (PC) or other suitable polymers. In some embodiments, the sacrificial layer 266 and the underlying sacrificial layer 216 may include different organic materials. Alternatively, the sacrificial layer 266 and the underlying sacrificial layer 216 may include the same organic material.

[0052] refer to Figure 2 and Fig. 22 , method 100 includes box 134, in which a maintenance layer 270 is formed over the workpiece 200. In some embodiments, a low-k dielectric material is conformally deposited over the workpiece 200 (including on the sacrificial layer 266 and the dielectric cap layer 264) to form a maintenance layer 270 having a loose structure and covering the sacrificial layer 266. In some embodiments, the maintenance layer 270 has a porous structure. The deposition for forming the maintenance layer 270 can be implemented by PVD, CVD, ALD, PECVD, PEALD or other suitable processes. In some embodiments, the maintenance layer 270 includes silicon oxide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride or other suitable dielectric materials. In some embodiments, the maintenance layer 270 and the underlying maintenance layer 220 may include different material compositions. Optionally, the maintenance layer 270 and the underlying maintenance layer 220 may include the same material composition. According to some embodiments, the maintenance layer 270 may have a range from about to about Thickness.

[0053] refer to Figure 2 and Fig.23 , method 100 includes block 136, in which sacrificial layer 266 is selectively removed to form air gaps 272 between metal lines 258L and below sustaining layer 270. In some embodiments, a thermal treatment (e.g., an annealing process, a baking process) and / or an ultraviolet process may be performed to decompose sacrificial layer 266 into volatile compounds that can diffuse through the porous structure of sustaining layer 270. Removing sacrificial layer 266 forms air gaps 272. Fig.23 As depicted, each of air gaps 272 is defined by dielectric cap layer 264 and sustaining layer 270. Because air has a dielectric constant close to 1, air gaps 272 reduce the effective dielectric constant of the dielectric structure between metal lines 258L.

[0054] refer to Figure 2 and Fig.24 , method 100 includes box 138, in which a high thermal conductivity (high κ) material layer 274 is formed over the maintenance layer 270 using ALD, CVD, plasma enhanced CVD (PECVD), or microwave PECVD. In some embodiments, the high κ material layer 274 may include diamond, diamond-like carbon. In some other embodiments, the high κ material layer 274 includes aluminum nitride (AlN), hexagonal boron nitride (h-BN), graphene oxide, silicon carbide (SiC), silicon carbonitride (SiCN). In an advancement of some embodiments, the high κ material is a low-k (e.g., a dielectric constant value of about 3.9) dielectric material. According to some embodiments, the high κ material layer 274 may have a dielectric constant ranging from about 1.0 to about 1.0. to about The high-κ material in dielectric cover layer 264 and high-κ material layer 274 may be the same or different. For example, high-κ material layer 274 may have a higher thermal conductivity than dielectric cover layer 264. In addition, in some embodiments, high-κ material layer 274 and underlying high-κ material layer 224 may include different high-κ materials. Alternatively, high-κ material layer 274 and underlying high-κ material layer 224 may include the same high-κ material. Maintenance layer 270 separates high-κ material layer 274 from dielectric cover layer 264 so that high-κ material layer 274 does not contact dielectric cover layer 264.

[0055] refer to Figure 2 and Fig.25, the method 100 includes a block 140, in which the workpiece 200 is planarized to expose the metal line 258L. After forming the high-κ dielectric material layer 274, a planarization process is performed on the workpiece 200. In an embodiment, the planarization process stops after exposing the top surface of the metal line 258L. When the planarization process is completed, the topmost surface of the dielectric cap layer 264, the topmost surface of the maintenance layer 270, and the top surface of the high-κ material layer 274 are coplanar. The maintenance layer 270 extends along the bottom surface and sidewall surface of the high-κ material layer 274 and contacts the dielectric cap layer 264. The dielectric cap layer 264, the maintenance layer 270, the high-κ material layer 274, and the air gap 272 trapped between the dielectric cap layer 264 and the maintenance layer 270 collectively define a dielectric structure disposed between adjacent metal lines 258L. Because air has a dielectric constant close to 1, the air gap 272 reduces the effective dielectric constant of the dielectric structure between the metal lines 258L. In other words, the air gap 272 between the metal lines helps to maintain low parasitic capacitance between the metal lines 258L. At the same time, the high-κ properties caused by the application of high-κ materials in the combination of the dielectric cap layer 264, the maintenance layer 270, and the high-κ material layer 274 allow heat to spread horizontally between the metal lines 258L, making it less likely that heat will be trapped in the metal line layer. In some embodiments, the height H2' measured from the top surface of the high-κ material layer 274 to the bottom surface of the maintenance layer 270 is about 20% to about 50% of the height H1' of the metal line 258L. The range from about 20% to about 50% is not trivial or arbitrary. If the ratio of H2' / H1' is less than about 20%, the heat dissipation capability may be impaired due to the relatively thin high-κ material layer 274; if the ratio of H2' / H1' is greater than about 50%, the parasitic capacitance may become too large and the circuit speed is reduced due to the relatively small volume of the air gap 272. In some embodiments, the height H2' may be greater than the height H2( Fig.12 ). Optionally, height H2' may be the same as height H2. In some embodiments, height H1' may be greater than height H1 ( Fig.12 ). Optionally, the height H1' may be the same as the height H1.

[0056] Still reference Fig.25 , the metal line 258L electrically coupled to the through hole 250 is a functional metal line for conducting signals and / or power. The two adjacent metal lines 258L may also be functional metal lines. Optionally, the two adjacent metal lines 258L may be non-functional (or dummy) metal lines, such as metal fill lines for improving the metal density in the corresponding metal line layer and / or as ground metal lines for shielding interference of the metal lines sandwiched therebetween. In addition, as Fig.25 As depicted in FIG. 2 , the thickness of the dielectric cover layer 264 is less than the thickness of the glue layer 256. Fig.26In the alternative embodiment depicted in FIG. 2 , the thickness of the dielectric cover layer 264 can be greater than the thickness of the glue layer 256, so that the horizontal portion of the dielectric cover layer 264 bridges two adjacent metal lines 258L. The bridging of the two adjacent metal lines 258L with the horizontal portion of the dielectric cover layer 264 provides an additional heat dissipation path in the horizontal direction, so that heat can also directly pass through the horizontal portion of the dielectric cover layer 264. Fig.26 , the horizontal portion of dielectric cap layer 264 is thicker than the vertical portion of dielectric cap layer 264, which may be due to the selective deposition process that allows the high-κ material to be deposited at a higher rate on the dielectric surface of low-k dielectric layer 242 than on the metal surface of metal line 258L. Optionally, the thickness of dielectric cap layer 264 may be conformal, so that the vertical portion of dielectric cap layer 264 is also thicker than glue layer 256.

[0057] After forming metal line 258L, the method proceeds to block 142 to perform further processes to complete the fabrication of the semiconductor device. For example, the operations in blocks 120-140 may be repeated to form an interconnect layer above metal line 258L. Such further processes may include forming a backside multilayer interconnect structure BMLI ( Figure 1 Optionally, a damascene process in addition to the operations in blocks 120-140 may be applied to form an interconnect layer over metal line 258L. Figure 27 to Figure 29 Further shown in .

[0058] refer to Fig. 27, a second etch stop layer (ESL) 280, a low-k dielectric layer 282, and a hard mask 284 are formed over metal line 258L and on dielectric cap layer 264, maintenance layer 270, and high-κ material layer 274. In some embodiments, second ESL 280 may include aluminum oxide, aluminum nitride, silicon nitride, silicon oxycarbide, silicon carbonitride, or a combination thereof. After forming second ESL 280, low-k dielectric layer 282 is formed. Low-k dielectric layer 282 has a dielectric constant less than that of silicon oxide (which is about 3.9). For example, the low-k dielectric layer 282 may include a porous organic silicate film (e.g., SiCOH), tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, silicon oxycarbonitride (SiOCN), boron carbonitride, spin-on silicon-based polymer dielectrics, or a combination thereof. A hard mask 284 is deposited on the low-k dielectric layer 282. The hard mask 284 may be a single-layer structure or a double-layer structure. The hard mask 284 may be formed of aluminum oxide, silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbon, silicon oxynitride, silicon oxycarbonitride, other suitable materials, or a combination thereof.

[0059] refer to Fig.28 , forming the trench opening 286 and the via opening 288 by one or more photolithography processes and etching processes. In some embodiments, forming the opening includes: patterning the hard mask 284 in a first etching process; removing the top portion of the dielectric layer 282 in a second etching process to form the trench opening 286. The second etching process is implemented to partially etch the dielectric layer 282, such as by controlling the etching duration. During the second etching process, only the dielectric layer 282 within the area defined by the trench opening 286 is recessed, but not completely through the dielectric layer 282. The dielectric layer 282 is further etched through the trench opening 286 by a third etching process to form the via opening 288. The third etching process is designed to selectively etch the dielectric layer 282, while the second ESL 280 remains substantially intact. The third etching process extends the via opening 288 downward to the second ESL 280. The formation of the via opening 288 can also be assisted by a photoresist used to define the pattern. The photoresist is then removed in a suitable process (such as resist stripping or plasma ashing). A fourth etching process is then applied to open the second ESL 280. After the fourth etching process, trench openings 286 for metal lines and via openings 288 for vias are both formed in the dielectric layer 282. The trench openings 286 are formed in the upper portion of the dielectric layer 282, and the via openings 288 are formed in the lower portion of the dielectric layer 282.

[0060] refer to Fig.29, metal line 290 is formed in trench opening 286, and via 292 is formed in via opening 288. In some embodiments, metal line 290 and via 292 are formed as a bulk metal layer by filling conductive material in trench opening 286 and via opening 288. The conductive material may be deposited by a suitable technique, such as an electroplating process, PVD or other suitable method. Before depositing the bulk metal layer, a diffusion barrier layer and an adhesion layer (not shown) may be deposited in trench opening 286 and via opening 288. An advantageous feature of having a bulk metal layer formed in a damascene process is that some low resistance conductive materials (e.g., copper) that may not be suitable for a metal etching process may be deposited. In some embodiments, the conductive material is different from the metal used in the relatively narrow metal lines 208L and 258L below. In some embodiments, metal lines 208L and 258L include one or more noble metals as discussed above, while the bulk metal layer for metal line 290 and via 292 includes one or more non-noble metals. For example, the bulk metal layer for metal line 290 and via 292 may include copper (Cu), but other suitable materials may alternatively be utilized, such as tungsten (W), cobalt (Co), nickel (Ni), aluminum (Al), combinations thereof, and the like. In some embodiments, the bulk metal layer also includes a noble metal, but is different from the one or more noble metals used in metal lines 208L and 258L. For example, the bulk metal layer may include Pt, while metal line 208L may include Rh or Au, and metal line 258L may include Ru. In addition, because metal lines 208L and 258L are formed by direct patterning, metal lines 208L and 258L each have a narrower top portion and a wider bottom portion; in comparison, metal line 290, via 292, and via 250 each have a wider top portion and a narrower bottom portion, which is formed by filling trenches in the corresponding dielectric layers rather than direct patterning. Compared to via 250 and via 292 , in some embodiments, via 250 is a barrier-free via as discussed above, while via 292 includes a barrier layer to prevent metal elements (eg, copper) from diffusing into dielectric layer 282 .

[0061] Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to semiconductor structures and their formation. For example, embodiments of the present disclosure provide a dielectric structure disposed between two adjacent metal lines and a method for forming the same. The dielectric structure includes a high-κ dielectric material layer to facilitate heat dissipation. The dielectric structure also includes an air gap, thereby reducing the effective dielectric constant of the dielectric structure and the parasitic capacitance of the semiconductor structure.

[0062] The present disclosure provides many different embodiments. A semiconductor structure and a method for manufacturing the same are disclosed herein. In one exemplary aspect, the present disclosure relates to a method. The method includes: forming a metal layer over a substrate; patterning the metal layer to form a first metal line and a second metal line having a groove therebetween; depositing a sacrificial layer in a lower portion of the groove; forming a first dielectric layer on the sacrificial layer; after forming the first dielectric layer, selectively removing the sacrificial layer to form an air gap between the first metal line and the second metal line; and depositing a second dielectric layer over the first dielectric layer and in an upper portion of the groove. In some embodiments, the metal layer includes a noble metal. In some embodiments, the second dielectric layer has a thermal conductivity of not less than about 10 W / m·K. In some embodiments, the first dielectric layer is a porous dielectric layer, so that during the selective removal of the sacrificial layer, the sacrificial layer decomposes into volatile compounds that diffuse through the porous dielectric layer. In some embodiments, the method further includes: depositing a capping layer before forming the sacrificial layer. The air gap is vertically located between the capping layer and the first dielectric layer. In some embodiments, the capping layer includes a thermally conductive material having a thermal conductivity of not less than about 10 W / m·K. In some embodiments, forming a sacrificial layer includes: depositing a polymer layer in the trench and over the first metal line and the second metal line; planarizing the polymer layer; and etching back the polymer layer. In some embodiments, the method further includes: before forming the metal layer, forming a dielectric layer over the substrate, wherein the via passes through the dielectric layer. The via is located directly below one of the first metal line and the second metal line, and wherein the trench partially exposes the top surface of the via. In some embodiments, the method further includes: after depositing the second dielectric layer, performing a planarization process to expose the first metal line and the second metal line. In some embodiments, after performing the planarization process, the thickness measured from the top surface of the second dielectric layer to the bottom surface of the first dielectric layer is about 20% to about 50% of the thickness of the first metal line and the second metal line.

[0063] In another exemplary aspect, the disclosed embodiments relate to a method. The method includes: forming a metal layer over a substrate; patterning the metal layer to form a groove separating the metal layer into at least a first portion and a second portion; forming a capping layer extending along the top surface and sidewall surface of the first portion and the second portion of the metal layer; depositing a maintenance layer between the first portion and the second portion of the metal layer to seal the groove to form an air gap; depositing a thermally conductive layer over the maintenance layer and over the first portion and the second portion of the metal layer, the thermally conductive layer having a thermal conductivity of not less than about 10 W / m·K; and performing a planarization process to partially remove the thermally conductive layer and expose the first portion and the second portion of the metal layer. In some embodiments, the capping layer has a thermal conductivity of not less than about 10 W / m·K. In some embodiments, the method further includes: depositing a polymer layer over the capping layer and under the maintenance layer to partially fill the groove; and selectively removing the polymer layer after depositing the maintenance layer to form an air gap. In some embodiments, selectively removing the polymer layer includes decomposing the polymer layer into volatile compounds that diffuse through the maintenance layer. In some embodiments, the metal layer includes a noble metal. In some embodiments, the thermally conductive layer is diamond or diamond-like carbon.

[0064] In yet another exemplary aspect, an embodiment of the present disclosure relates to a semiconductor structure. The semiconductor structure includes: a conductive via extending through a first dielectric layer; a first metal line located above the conductive via and in electrical contact with the conductive via; and a second metal line located above the first dielectric layer and separated from the first metal line by a dielectric structure. The top surface of the dielectric structure is coplanar with the top surfaces of the first metal line and the second metal line. The dielectric structure includes: a top pad extending between the first metal line and the second metal line; a thermal conductive layer located above the top pad, the top pad extending along the bottom surface and sidewall surface of the thermal conductive layer; and an air gap defined by the top pad. In some embodiments, the semiconductor structure further includes: a bottom pad extending between the first metal line and the second metal line and in contact with the first dielectric layer, wherein the air gap is vertically located between the bottom pad and the top pad. In some embodiments, the top pad is in contact with the bottom pad. In some embodiments, each of the first metal line and the second metal line has a top width narrower than the bottom width.

[0065] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: forming a metal layer over the substrate; patterning the metal layer to form a first metal line and a second metal line having a trench therebetween; depositing a sacrificial layer in a lower portion of the trench; forming a first dielectric layer on the sacrificial layer; After forming the first dielectric layer, selectively removing the sacrificial layer to form an air gap between the first metal line and the second metal line; as well as A second dielectric layer is deposited over the first dielectric layer and in an upper portion of the trench.

2. The method according to claim 1, wherein: The metal layer includes a noble metal.

3. The method according to claim 1, wherein: The second dielectric layer has a thermal conductivity of not less than about 10 W / m·K.

4. The method according to claim 1, wherein: The first dielectric layer is a porous dielectric layer such that during the selective removal of the sacrificial layer, the sacrificial layer decomposes into volatile compounds that diffuse through the porous dielectric layer.

5. The method according to claim 1, further comprising: Before forming the sacrificial layer, a capping layer is deposited, wherein the air gap is vertically located between the capping layer and the first dielectric layer.

6. The method according to claim 5, wherein: The cover layer includes a thermally conductive material having a thermal conductivity of not less than about 10 W / m·K.

7. The method according to claim 1, wherein: Forming the sacrificial layer comprises: depositing a polymer layer in the trench and over the first metal line and the second metal line; planarizing the polymer layer; and The polymer layer is etched back.

8. The method according to claim 1, further comprising: Before forming the metal layer, a dielectric layer is formed over the substrate, wherein a via passes through the dielectric layer, wherein the via is located directly below one of the first metal line and the second metal line, and wherein the trench partially exposes a top surface of the via.

9. A method of forming a semiconductor structure, comprising: forming a metal layer over the substrate; patterning the metal layer to form a trench separating the metal layer into at least a first portion and a second portion; forming a capping layer extending along top surfaces and sidewall surfaces of the first portion and the second portion of the metal layer; depositing a sustaining layer between the first portion and the second portion of the metal layer to seal the trench to form an air gap; depositing a thermally conductive layer over the sustaining layer and over the first portion and the second portion of the metal layer, wherein the thermally conductive layer has a thermal conductivity of not less than about 10 W / m·K; as well as A planarization process is performed to partially remove the thermal conductive layer and expose the first portion and the second portion of the metal layer.

10. A semiconductor structure comprising: a conductive via extending through the first dielectric layer; a first metal line located above and in electrical contact with the conductive via; as well as a second metal line located above the first dielectric layer and separated from the first metal line by a dielectric structure, wherein a top surface of the dielectric structure is coplanar with top surfaces of the first metal line and the second metal line, and wherein the dielectric structure comprises: a top pad extending between the first metal line and the second metal line; a thermally conductive layer located above the top liner, wherein the top liner extends along a bottom surface and sidewall surfaces of the thermally conductive layer; and An air gap is defined by the top gasket.

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