Interconnection structure and method for forming semiconductor structure

Abstract

A method of forming a semiconductor structure includes forming a conductive feature in a first dielectric layer; forming a second dielectric layer over the conductive feature; forming an opening in the second dielectric layer to expose a top surface of the conductive feature; forming an inhibitor film at a top surface of the conductive member; depositing a thermally conductive layer having a first portion on a sidewall of the opening and a second portion on a top surface of the second dielectric layer; removing the suppression film to expose a top surface of the conductive member; depositing an electrically conductive material in the opening and on the second portion of the thermally conductive layer; removing a portion of the conductive material to expose a second portion of the thermally conductive layer; and forming a third dielectric layer on the second portion of the thermally conductive layer and the second dielectric layer. The embodiment of the invention further discloses an interconnection structure.

Description

Technical Field

[0001] Embodiments of the present application relate to interconnect structures and methods of forming semiconductor structures. Background Art

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each smaller and more complex than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] This reduction has also increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are needed to achieve these advances. The shrinking size and high integration density of semiconductor devices make heat dissipation challenging. For example, as multilayer interconnect (MLI) structures become more compact as IC component sizes continue to shrink, heat generated in the IC device layers may be captured by the dielectric layers of the MLI structure, which typically have poor thermal conductivity and result in sharp localized temperature peaks, sometimes referred to as hot spots. Thermal hot spots caused by device-generated heat can negatively affect the electrical performance of the IC and often lead to electromigration and reliability issues in electronic components in the IC. Therefore, although existing MLI structures are generally adequate for their intended purposes, they are not completely satisfactory in all aspects. Therefore, there is a need to address or mitigate the above-mentioned deficiencies and problems. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a method for forming a semiconductor structure is provided, comprising: forming a conductive component in a first dielectric layer; forming a second dielectric layer above the conductive component; forming an opening in the second dielectric layer to expose a top surface of the conductive component; forming an inhibitor film at the top surface of the conductive component; depositing a thermally conductive layer, the thermally conductive layer having a first portion on a side wall of the opening and a second portion on a top surface of the second dielectric layer; removing the inhibitor film to expose the top surface of the conductive component; depositing a conductive material in the opening and on the second portion of the thermally conductive layer; removing a portion of the conductive material to expose the second portion of the thermally conductive layer; and forming a third dielectric layer on the second portion of the thermally conductive layer and the second dielectric layer.

[0005] According to another aspect of an embodiment of the present application, a method for forming a semiconductor structure is provided, comprising: forming an etch stop layer above a substrate; depositing a dielectric layer above the etch stop layer; etching through the dielectric layer and the etch stop layer to form an opening exposing the top surface of the substrate; depositing an inhibitor film at the bottom of the opening; depositing a two-dimensional material layer on the sidewalls of the opening, wherein the two-dimensional material layer covers the top surface of the dielectric layer; removing the inhibitor film from the bottom of the opening; depositing a liner layer on the two-dimensional material layer and at the bottom of the opening; depositing a conductive material filling the opening; and performing a planarization process to remove the top of the conductive material and the liner layer to expose the two-dimensional material layer, wherein the two-dimensional material layer remains covering the top surface of the dielectric layer.

[0006] According to another aspect of an embodiment of the present application, an interconnect structure is provided, comprising: a first conductive component located in a first dielectric layer; an etch stop layer located above the first conductive component; a second dielectric layer located above the etch stop layer; a second conductive component extending through the second dielectric layer and the etch stop layer and landing on the first conductive component; and a thermally conductive barrier layer inserted between the second conductive component and the second dielectric layer, wherein the thermally conductive barrier layer has a horizontal portion that is in direct contact with a top surface of the second dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A cross-sectional view of layers involved in an interconnect structure of a semiconductor device according to some embodiments of the present disclosure is shown.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 and Fig.14 A cross-sectional view of an interconnect structure at an intermediate stage of forming an interconnect layer including a barrier layer, metal lines, and vias according to some embodiments of the present disclosure is shown.

[0010] Fig.15 A process flow for forming an interconnect structure according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] In addition, for ease of description, spatial relationship terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use or operating processes. The device can be positioned in other ways (rotated 90 degrees or in other orientations), and the device relationship descriptors used in this article can be interpreted accordingly. In addition, when "about", "approximately", etc. are used to describe a number or a range of numbers, unless otherwise stated, the term is intended to cover numbers within + / -10% of the described number. For example, the term "about 5nm" includes a size range of 4.5nm to 5.5nm.

[0013] The integrated circuit manufacturing process flow is generally divided into three categories: front-end process (FEOL), middle process (MEOL) and back-end process (BEOL). FEOL generally includes processes related to the manufacture of IC devices (such as transistors). For example, FEOL processes may include the formation of isolation components, gate structures, and source and drain components (commonly referred to as source / drain components). MEOL generally includes processes related to the manufacture of contacts for conductive components (or conductive regions) of IC devices, such as contacts for gate structures and / or source / drain components. BEOL generally includes processes related to the manufacture of multi-layer interconnect (MLI) structures that interconnect IC components manufactured by FEOL and MEOL (referred to herein as FEOL and MEOL components or structures, respectively), thereby enabling the IC device to operate.

[0014] As integrated circuit technology moves toward smaller technology nodes, BEOL processes are facing significant challenges. For example, advanced IC technology nodes require more efficient heat dissipation paths in MLI structures while significantly reducing the critical dimensions of MLI structure features. Thermal energy in the form of heat may be generated during the operation of a circuit, and some types of circuits may generate more heat than other types of circuits. When heat-generating circuits are packed closely together in an IC, one or more hot spot areas may form. These hot spot areas may refer to areas on the IC that generate more heat per unit area / volume per unit time than other areas of the IC. For example, during IC operation, the temperature of the hot spot area may be higher than that of areas adjacent to the hot spot area. If there are fewer heat dissipation paths available in the IC, thermal hot spots may easily form in the IC. The dielectric layer of the MLI structure generally exhibits poor thermal conductivity, which may not effectively dissipate the heat generated by the underlying device layers.

[0015] The present application discloses an embodiment of an interconnect structure that provides a through-hole and metal line structure (collectively referred to as a contact structure) with enhanced heat dissipation capabilities. The contact structure generally includes a diffusion barrier layer. The diffusion barrier layer has the function of preventing metal elements (such as copper) in the contact structure from diffusing into the dielectric layer surrounding the contact structure. The diffusion barrier layer may also be referred to as a barrier layer for short. Generally, the barrier layer in the MLI structure has poor thermal conductivity. In an embodiment of the present disclosure, the barrier layer is made of a thermally conductive material. In the context of the present disclosure, the terms "conductive" and "electrical conductivity" specifically refer to "electrically conductive" and "electrical conductivity", respectively, to distinguish from the term "thermal conductivity". The thermally conductive material used herein is defined as a material having a thermal conductivity of not less than 10 W / m·K (watts per meter Kelvin). Thermally conductive materials are particularly effective in conducting heat. This means that a barrier layer made of a thermally conductive material allows heat to pass through it quickly and efficiently. In addition, the diffusion barrier layer of the contact structure can extend along the surface of the corresponding dielectric layer of the MLI structure to abut against other barrier layers of adjacent contact structures in the same interconnect layer of the MLI structure, thereby forming a larger heat dissipation plane. Diffusion barriers on different interconnect layers of the MLI structure can also be thermally connected through thermal vias to turn the MLI structure into a three-dimensional (3D) heat dissipation network. In some embodiments, the barrier layer is selectively formed on the sidewalls of the corresponding contact structure, but not directly formed on the underlying interconnect components. By making the barrier layer not directly contact the underlying interconnect components, heat can also be directly dissipated through the metal components in the MLI structure, thereby providing multiple heat dissipation paths.

[0016] Figure 1 Schematic cross-sectional views of the various layers involved in the semiconductor device 100 are shown. It should be noted that Figure 1Schematically shows various levels of interconnect structures and circuit device regions (such as transistors), and may not reflect the actual cross-sectional view of semiconductor device 100. The interconnect structure includes multiple interconnect levels, such as a contact level, an OD (where the term "OD" means "active region") level, a via level, a Via_0 level, a Via_1 level, a Via_2 level, and a Via_3 level, as well as metal layer levels (such as an M1 level, an M2 level, an M3 level, an M4 level, an Mtop level (top metal layer level), etc.). Each of the shown interconnect layers includes one or more low-k dielectric layers and conductive components formed therein. The conductive components at the same interconnect level may have top surfaces that are substantially flush with each other, bottom surfaces that are substantially flush with each other, and may be formed simultaneously. The contact level may include gate contacts (also referred to as contact plugs, labeled as gate_CO) for connecting the gate electrode of a transistor to an overlying level, such as the Via (through hole)_0 level, and source / drain contacts (labeled as "contacts") for connecting the source / drain regions of a transistor to an overlying level. The thicknesses of the metal lines at the metal layer levels M1 level, M2 level, M3 level, M4 level are respectively denoted as T1, T2, T3, T4... Ttop. The Mtop level is respectively denoted as T1, T2, T3, T4... Ttop. It should also be noted that the metal lines at higher levels are generally thicker than those at lower levels (i.e., T1 < T2 < T3 < T4 <... < Ttop). In addition, the metal lines at higher interconnect levels generally have a larger pitch (e.g., the center-to-center distance or edge-to-edge distance between adjacent metal lines) than the metal lines at lower interconnect levels.

[0017] Figures 2 to 14 Shows a cross-sectional view of an intermediate stage of forming a contact structure in semiconductor device 100 according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in, for example, Fig.15 Process flow 200 shown. Additional processes may be provided before, during, and after process flow 200, and for additional embodiments of process flow 200, some of the described processes may be moved, replaced, or eliminated. Additional components may be added to the Figure 2-Figure 14 interconnect structure shown, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the Figure 2-Figure 14 interconnect structure shown.

[0018] Figure 2 Shows a cross-sectional view of semiconductor device 100. The corresponding process is in Fig.15The process flow 200 is shown as process 202. According to some embodiments of the present disclosure, the semiconductor device 100 is a device wafer including active devices (such as transistors and / or diodes) and possible passive devices (such as capacitors, inductors, resistors, etc.). According to alternative embodiments of the present disclosure, the semiconductor device 100 is an interposer wafer, which may or may not include active devices and / or passive devices. According to another alternative embodiment of the present disclosure, the semiconductor device 100 is a packaging substrate, which may include a packaging substrate having a core therein or a coreless packaging substrate. In the subsequent discussion, the device wafer is used as an example of the semiconductor device 100. The teachings of the present disclosure may also be applied to interposer wafers, packaging substrates, packages, etc.

[0019] According to some embodiments of the present disclosure, the semiconductor device 100 includes a semiconductor substrate 102 and a component formed at a top surface of the semiconductor substrate 102. The semiconductor substrate 102 may include crystalline silicon, crystalline germanium, silicon germanium, a III-V compound semiconductor, such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc. The semiconductor substrate 102 may also be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. A shallow trench isolation (STI) region ( Figure 2 Not shown, but Figure 1 100) to isolate active regions within the semiconductor substrate 102. Although not shown, vias may be formed to extend into the semiconductor substrate 102, wherein the vias are used to electrically interconnect features on opposite sides of the semiconductor device 100.

[0020] According to some embodiments of the present disclosure, circuit device 104 is formed on the top surface of semiconductor substrate 102. Examples of circuit device 104 include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of circuit device 104 are not shown here.

[0021] Figure 2The dielectric layer 106 is further shown in FIG. The dielectric layer 106 may be an interlayer dielectric (ILD) layer or an intermetallic dielectric (IMD) layer. According to some embodiments of the present disclosure, the dielectric layer 106 is an ILD layer in which a contact plug is formed. The corresponding dielectric layer 106 may be formed of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), a silicon oxide layer (formed using tetraethyl orthosilicate (TEOS)), etc. The dielectric layer 106 may be formed using spin coating, atomic layer deposition (ALD), flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc. According to some embodiments of the present disclosure, the dielectric layer 106 is an IMD layer in which a metal line and / or a via is formed. The corresponding dielectric layer 106 may be formed of a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. According to some embodiments of the present disclosure, the formation of the dielectric layer 106 includes depositing a dielectric material containing a porogen, and then performing a curing process to drive off the porogen, so that the remaining dielectric layer 106 is porous.

[0022] Conductive component 108 is formed in dielectric layer 106. Conductive component 108 may be a metal line, a conductive via, a contact plug, etc. According to some embodiments, conductive component 108 includes barrier layer 110, liner 112, seed layer 114, and metal filling layer 116 on seed layer 114. Barrier layer 110 may be formed of conductive material (such as Ta, TaN, TaC, Ti, TiN, TiC), dielectric material (such as boron nitride, aluminum nitride, aluminum oxide, silicon carbonitride, silicon carbide) and other suitable materials that can block the diffusion of metal elements, and may be deposited using ALD, CVD, ELD or PVD, and may be formed to a thickness of about 1 nm to about 2 nm. Barrier layer 110 may also be referred to as a diffusion barrier layer. According to some embodiments of the present disclosure, the formation of barrier layer 110 may also adopt the method discussed later, so that barrier layer 110 may be optionally formed of a thermally conductive material (which may be non-conductive in addition), and barrier layer 110 may not be formed below the bottom surface of conductive component 108.

[0023] The liner 112 is deposited on the barrier layer 110. In some embodiments, the liner 112 can be deposited using ALD, CVD, ELD, or PVD, and can be formed to a thickness of about 0.5 nm to 3 nm. The liner 112 can be formed of a suitable metal, metal nitride, or metal carbide, such as Co, CoN, and RuN. In one example, the liner 112 is made of Co. The role of the liner 112 is to increase the adhesion between the seed layer 114 and the barrier layer 110. The liner 112 can also be called an adhesive layer.

[0024] The seed layer 114 is formed on the pad 112. In some embodiments, the seed layer 114 is a metal alloy layer, which contains at least a main metal element, such as copper (Cu), and an added metal element, such as manganese (Mn). In one example, the seed layer 114 is a copper-manganese (CuMn) layer. In other embodiments, Ti, Al, Nb, Cr, V, Y, Tc, Re, etc. can be used as an alternative added metal to form the seed layer 114. In some embodiments, the concentration (atomic percentage) of the added metal element in the copper alloy layer can be in the range of about 0.5% to about 5%. As explained in further detail below, in some embodiments, the concentration of the added metal element in the contact structure at different levels can vary. In one example, the copper alloy layer is a CuMn layer, and the contact structure at a higher level has a higher manganese concentration than the contact structure at a lower level. The seed layer 114 can be deposited using ALD, CVD, ELD, PVD or other suitable deposition techniques.

[0025] The metal filling layer 116 may be formed of copper, copper alloy, aluminum, etc. The barrier layer 110 has the function of preventing the material (such as copper) in the metal filling layer 116 from diffusing into the dielectric layer 106. In some embodiments, the metal filling layer 116 may be deposited using PVD, CVD, ALD, electroplating, ELD or other suitable deposition processes or combinations thereof. After the metal filling layer 116 is deposited, a planarization process such as a chemical mechanical planarization (CMP) process or a mechanical polishing process may be performed to remove excess portions of the conductive material of the metal filling layer 116.

[0026] like Figure 2 As shown, an etch stop layer 118 is formed over the dielectric layer 106 and the conductive component 108. The etch stop layer 118 is formed of a material having a high etch selectivity relative to the overlying dielectric layer 120, so the etch stop layer 118 can be used to stop the etching of the dielectric layer 20. The etch stop layer 118 may include a single layer or a stacked layer. In some embodiments, the etch stop layer 118 is formed of a dielectric material, which may include but is not limited to aluminum oxide, aluminum nitride, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxynitride carbon, methyl silicon, hydrogenated silicon oxide carbon or a combination thereof. For example, the etch stop layer 118 may include a bottom layer of aluminum nitride, a first intermediate layer of silicon oxycarbide disposed on the bottom layer, a second intermediate layer of aluminum oxide disposed on the first intermediate layer, and a top layer of silicon oxycarbide. In various embodiments, the etch stop layer 118 may have a greater thickness than the liner 112.

[0027] A dielectric layer 120 is formed over the etch stop layer 118. Fig.15The corresponding process in the illustrated process flow 200 is illustrated as process 204. According to some embodiments, the dielectric layer 120 is an IMD layer or an ILD layer. The dielectric layer 120 may include a dielectric material, such as an oxide, a nitride, a carbon-containing dielectric material, etc. For example, the dielectric layer 120 may be formed of silicon carbide, silicon oxide, amorphous boron nitride (a-BN), SiCOH, SiCNH, PSG, BSG, BPSG, FSG, TEOS oxide, HSQ, MSQ, etc. The dielectric layer 120 may also be a low-k dielectric layer having a low dielectric constant value of less than about 3.5 or less than about 3.0.

[0028] A patterned hard mask 122 is formed on the dielectric layer 120. The patterned hard mask 122 is formed by patterning the hard mask layer to form openings 128 therein, wherein the openings 128 define a pattern of trenches to be filled to form metal lines. According to some embodiments of the present disclosure, the patterned hard mask 122 is a metal hard mask formed of titanium nitride, aluminum nitride, or the like.

[0029] Figures 3 to 13 2 shows a process for forming metal lines and vias according to some embodiments. Figures 3 to 13 The example shown describes a dual damascene process. According to alternative embodiments, a single damascene process for forming metal lines, vias, contact plugs, etc. may also be considered. Specifically, for simplicity, Figures 2 to 13 A cross-sectional view of an intermediate stage of forming two consecutive metal layer levels and corresponding via levels therebetween (eg, Mx level, Via_x level, and Mx+1 level, x represents an integer) of an interconnect structure of the semiconductor device 100 according to some embodiments.

[0030] like Figure 3 and Figure 4 As shown, a through hole opening 124 and a trench 126 are formed by etching. Fig.15 The corresponding process in the illustrated process flow 200 is shown as process 206. The via opening 124 and the groove 126 can be formed using, for example, photolithography techniques. In an example of a process for forming the via opening 124 and the groove 126, a bottom anti-reflective coating (BARC) 130 is formed on the patterned hard mask 122, and a patterned hard mask 132 is formed on the BARC layer 130. In one example, the BARC layer 130 includes an organic BARC material formed by a spin coating technique. The patterned hard mask 132 is formed by patterning the hard mask layer to form an opening 134 therein, wherein the opening 134 defines a pattern of the via opening 124 to be filled to form a via. Through the opening 134, the BARC layer 130 is etched to form the via opening 124. In the etching process, the via opening 124 extends downward, and then the dielectric layer 120 is etched.

[0031] According to some embodiments of the present disclosure, the dielectric layer 120 is etched using a process gas containing fluorine and carbon, wherein fluorine is used for etching and carbon has the effect of protecting the resulting opening sidewalls. Through the appropriate fluorine and carbon ratio, the through hole opening 124 can have a desired profile. For example, the process gas used for etching includes a fluorine- and carbon-containing gas, such as C4F8, CH2F2 and / or CF4, and a carrier gas, such as N2. In one example of an etching process, the flow rate of C4F8 is in a range between about 0 sccm and about 50 sccm, the flow rate of CF4 is in a range between about 0 sccm and about 300 sccm (at least one of C4F8 and CF4 has a non-zero flow rate), and the flow rate of N2 is in a range between about 0 sccm and about 200 sccm. According to an alternative embodiment, the process gas used for etching includes CH2F2 and a carrier gas such as N2. In an example of an etching process, the flow rate of CH2F2 ranges between about 10 sccm and about 200 sccm, and the flow rate of N2 ranges between about 50 sccm and about 100 sccm.

[0032] During the etching process, the semiconductor device 100 may be maintained at a temperature in the range of about 30° C. to about 60° C. During the etching process, the etching gas may generate plasma. The power of the power radio frequency (RF) used for etching may be lower than about 700 watts, and the pressure of the process gas may be in the range of about 15 mTorr to about 30 mTorr.

[0033] The etching for forming the via opening 124 can be performed using a time mode. As a result of the etching, the via opening 124 is formed to extend to an intermediate level between the top surface and the bottom surface of the dielectric layer 120. Next, the BARC layer 130 and the patterned hard mask 132 are removed, and then the dielectric layer 120 is further etched using the patterned hard mask 122 as an etching mask. In the etching process, which is an anisotropic etching process, the via opening 124 extends downward until the etch stop layer 118 is exposed. While the opening 124 extends downward, a trench 126 is formed to extend into the dielectric layer 120. The etch stop layer 118 is then etched using a suitable etchant, and the metal filling layer 116 is exposed at the bottom of the via opening 124. The resulting structure is as shown in FIG. Figure 4 In the resulting structure, the via opening 124 is located below the trench 126 and connected to the trench 126 .

[0034] According to an alternative embodiment, the via opening 124 and the trench 126 are formed in separate photolithography processes. For example, in a first photolithography process, a via opening 124 extending down to the etch stop layer 118 is formed. In a second photolithography process, the trench 126 is formed. The order of forming the via opening 124 and the trench 126 can also be reversed. After forming the via opening 124 and the trench 126, the patterned hard mask 122 can be removed, for example, in an etching process.

[0035] Next, refer to Figure 5 , forming an inhibitor film 140. The inhibitor film 140 may be selectively deposited on the metal filling layer 116 but not on the dielectric layer 120. Fig.15 The corresponding process in the process flow 200 shown is shown as process 208. In some embodiments, for example, an acid is used for pretreatment, and the acid can be a diluted hydrofluoric acid (HF) solution. The pretreatment can also be performed using a mixed gas of NH3 (ammonia) and NF3 (nitrogen trifluoride). Next, the semiconductor device 100 is further processed in a processing step, and the dangling bonds generated on the surface of the metal filling layer 116 (during the pretreatment) are terminated to produce an inhibitor film 140. According to some embodiments, the attached bond / material may include Si(CH3)3. The process gas may include, for example, bis(trimethylsilyl)amine, hexamethyldisilazane (HMDS), tetramethyldisilazane (TMDS), trimethylchlorosilane (TMCS), dimethyldichlorosilane (DMDCS), methyltrichlorosilane (MTCS), etc. The corresponding process for attaching the bond may include a silylation process. In some embodiments, the inhibitor film 140 may be silane, phosphonic acid, an organic polymer (such as polyimide (PI), polyamide, etc.), etc. In some embodiments, the inhibitor film 140 may be formed of an organic compound having 8 to 20 carbon atoms. Specific examples of materials that can be used for the inhibitor film 140 include dodecylsilane (C 12 H 28 Si), octadecylphosphonic acid (ODPA, C 18 H 39 O3P), pyromellitic anhydride (C 10 H2O6), 1,6-diaminohexane (H2N(CH2)6NH2), ethylenediamine (C2H8N2), adipoyl chloride (C6H8Cl2O2), etc. The resulting inhibitor film 140 can be very thin and can include only some termination bonds. In one example, the inhibitor film 140 can be a monolayer of an inhibitor, such as a monolayer of benzotriazole (BTA). In other examples, the inhibitor film 140 can have a thickness T1 in a range between about 1 nm and about 2 nm, while the thickness T1 can be larger or smaller.

[0036] Reference Figure 6 According to some embodiments of the present disclosure, in order to increase the coverage of the inhibitor film 140, an additional inhibitor film forming process is performed. Fig.15The process flow 200 shown is shown as process 210. In the example of this process, the semiconductor device 100 is taken out of the wet cleaning solution and immersed in the inhibitor forming solution. Since this process is used to further grow the inhibitor film 140, rather than to cause corrosion to the metal filling layer 116, the chemical used for wet cleaning is not included in the inhibitor forming solution. For example, amines and H2O2 may not be included. However, some other chemicals such as ethylene glycol, dimethyl sulfide, etc. may be added to the inhibitor forming solution. An inhibitor (such as HMDS, ODPA or BTA) is added to the inhibitor forming solution, and the inhibitor may be the same or different from the inhibitor used in the wet cleaning solution. The semiconductor device 100 is then immersed in the inhibitor forming solution to further grow and increase the coverage of the inhibitor film 140. According to some embodiments of the present disclosure, the immersion time is in the range of about 30 seconds to about 60 seconds. After immersion, as the thickness increases from T1 to T2 (T2>T1), the inhibitor film 140 can achieve 100% coverage. In some embodiments, T2 is at least 50% greater than T1. When the BTA used in the inhibitor forming solution is different from the BTA used in the wet cleaning solution, the further grown inhibitor film 140 may have a first layer of the first BTA having a thickness of T1 and a second layer of the second BTA having a thickness of T2-T1, with an observable interface between the first layer and the second layer. In various embodiments, the thickened inhibitor film 140 is still thinner than any of the barrier layer 110, the liner 112, and the etch stop layer 118. As described below, the inhibitor film 140 restricts the subsequently formed barrier layer from growing on surfaces not covered by the inhibitor film 140, such as on the top and sidewall surfaces of the dielectric layer 120.

[0037] Next, refer to Figure 7 , a thermally conductive layer 142 is deposited on the top surface of the via opening 124, the trench 126 and the dielectric layer 120. The thermally conductive layer 142 also serves as a diffusion barrier layer, which prevents metal elements (such as copper) in the subsequently formed contact structure from diffusing into the dielectric layer 120. Therefore, the thermally conductive layer 142 is also referred to as a diffusion barrier layer 142 or simply a barrier layer 142. The barrier layer 142 is deposited. The corresponding process is Fig.15The process flow 200 shown is shown as process 212. According to some embodiments of the present disclosure, the material of the barrier layer 142 may include hexagonal boron nitride (h-BN), aluminum nitride (AlN), graphene, transition metal disulfide (TMD) (e.g., MoS2, MoSe2, WS2, or WSe2), etc. For aluminum nitride, it exhibits a high thermal conductivity of about 370 W / m·K. For graphene, it exhibits a high thermal conductivity of more than 3500 W / m·K. For TMD, its thermal conductivity is generally more than 10 W / m·K. For h-BN, it has a layered structure in a crystalline form similar to graphite, and exhibits an in-plane thermal conductivity of more than 390 W / m·K at room temperature. In comparison, amorphous BN (a-BN) is in an amorphous form and exhibits an in-plane thermal conductivity of only about 3 W / m·K, and is not considered a thermally conductive material in the context of the present disclosure. In one example, dielectric layer 120 is formed of a-BN and barrier layer 142 is formed of h-BN. In various embodiments, the thermal conductivity of barrier layer 142 is greater than 10 W / m·K. This threshold is not trivial. If the thermal conductivity is less than about 10 W / m·K, barrier layer 142 may not effectively dissipate heat. When barrier layer 142 is formed of h-BN, aluminum nitride, etc., barrier layer 142 is an electrically insulating and thermally conductive layer.

[0038] In some embodiments, the barrier layer 142 is a two-dimensional (2D) material layer. As is widely accepted in the art, a "2D material" may also be referred to as a "monolayer" material. The 2D material layer 142 may be a 2D material of suitable thickness. In some embodiments, the 2D material includes a monolayer of atoms in each of its monolayer structures, so the thickness of the 2D material refers to multiple monolayers of the 2D material, which may be one monolayer or multiple monolayers. The coupling between two adjacent monolayers of a two-dimensional material includes van der Waals forces, which are weaker than the chemical bonds between atoms within a monolayer. That is, the 2D material layer 142 may be a monolayer or several layers thick, and may exist in the form of a stack of strongly bonded layers with weak interlayer van der Waals forces, allowing the layers to be mechanically or chemically peeled off into thin layers of a single atomic thickness. In some embodiments, the thickness of the 2D material layer 142 may range from about 1 nm to about 2 nm.

[0039] The deposition of the barrier layer 142 may include a plasma enhanced atomic layer deposition (PE-ALD) process or a chemical vapor deposition (CVD) process. In the PE-ALD process, deposition is achieved by using alternating cycles of precursor gas and plasma exposure. An exemplary step of one cycle of the PE-ALD process includes, after loading the semiconductor device 100 into the chamber of a tool performing the PE-ALD process, flowing the precursor gas into the chamber. The precursor gas molecules adsorb onto the surface of the semiconductor device 100 to form a self-limiting monolayer. After the precursor gas exposure, a purge process is performed to purge the precursor gas and any byproducts from the chamber. A plasma treatment process is then performed, which involves flowing a gas with charged ions into the chamber. During the plasma treatment process, an electromagnetic field, radio frequency (RF), or other suitable energy source is applied to direct ions to the semiconductor device 100. The plasma decomposes the precursor molecules and initiates a chemical reaction on the surface of the semiconductor device 100, resulting in thin film growth. The plasma material reacts with the precursor monolayer on the semiconductor device to form a thin film. The ionized gas may be removed from the chamber before performing the next layer deposition cycle. When the barrier layer 142 is formed of h-BN, the precursor may be borazine (B3H6N3), 1,3,5-trimethylborazine (C3H9B3N3), or a combination thereof, and the reaction gas may be N2 plasma, NH3 plasma, or a combination thereof. Using borazine (B3H6N3) and / or 1,3,5-trimethylborazine (C3H9B3N3) as precursors allows the PE-ALD process to be performed at a relatively low temperature, for example, between about 200°C and about 400°C. This is mainly due to the presence of a BN ring structure in borazine and 1,3,5-trimethylborazine. In comparison, if a precursor uses a molecule without a ring, such as borane (BH3), the reaction temperature may have to be increased to above 1000°C. However, BEOL processes typically require a process temperature below about 500°C, otherwise the low-k dielectric layer in the MLI structure may be damaged by excessive temperatures above 500°C. Similarly, the barrier layer 142 may be deposited in a CVD process, wherein a precursor containing cycloborazine (B3H6N3), 1,3,5-trimethylcycloborazine (C3H9B3N3), or a combination thereof may be directly reacted with a reactive gas containing N2 plasma, NH3 plasma, or a combination thereof, followed by a purification process to form the barrier layer 142.

[0040] The inhibitor film 140 blocks or delays the growth of the barrier layer 142 at the bottom of the via opening 124. This is mainly due to the steric hindrance of the inhibitor film 140, and the steric hindrance is at least partially due to its heterocyclic structure. For example, during an ALD cycle, the probability of growing h-BN molecules (assuming that the barrier layer 142 is formed of h-BN) on the inhibitor film 140 is small, while a complete h-BN layer grows on the dielectric layer 120 in each ALD cycle. Therefore, after one ALD cycle, a small portion of the exposed surface of the inhibitor film 140 has h-BN grown on it, which can act as a seed for subsequent growth. After each cycle, a very small additional area of ​​the inhibitor film 140 is covered by the newly grown h-BN. Therefore, most of the inhibitor film 140 does not grow h-BN on it until after multiple ALD cycles. This effect is called growth delay (or incubation delay) on the inhibitor film 140, and since the inhibitor film 140 is not formed on the dielectric layer 120, there is no growth delay on the surface of the dielectric layer 120.

[0041] Due to the growth delay and random seeding of barrier layer 142 on inhibitor film 140, substantially no h-BN will grow on inhibitor film 140 after formation of barrier layer 142 is complete. Alternatively, barrier layer 142 may not extend onto inhibitor film 140. It is possible to grow a small amount of barrier layer 142 on inhibitor film 140, with coverage less than about 20% of the exposed surface of inhibitor film 140. According to some embodiments, barrier layer 142 forms discrete islands 142' on the surface of inhibitor film 140.

[0042] Reference Figure 8 A liner 144 is deposited on the barrier layer 142, for example using ALD, and lines the via opening 124, the trench 126, and the top surface of the dielectric layer 120. Fig.15 In the illustrated process flow 200, the corresponding process is shown as process 214. The liner 144 may be formed of a suitable metal, metal nitride, or metal carbide, such as Co, CoN, and RuN. In yet other embodiments, the liner 144 and the liner 112 have the same material composition. For example, both the liner 144 and the liner 112 may be formed of Co. After forming the liner 144, the thickness T3 of the liner 144 may be about to about within the range.

[0043] The inhibitor film 140 also blocks or delays the growth of the liner 144 at the bottom of the via opening 124. This is due to the steric hindrance of the inhibitor film 140, and the steric hindrance is at least partially due to its heterocyclic structure. For example, during an ALD cycle, there is little chance of growing Co-containing material (assuming the liner 144 includes Co) on the inhibitor film 140, while a complete layer of Co-containing material grows on the barrier layer 142 during each ALD cycle. Therefore, after one ALD cycle, a small portion of the exposed surface of the inhibitor film 140 has Co-containing material grown thereon, which serves as a seed for subsequent growth. Once the Co-containing material grows, the Co-containing material will grow at the same rate as on the barrier layer 142. After each cycle, a small additional area of ​​the inhibitor film 140 is covered by the newly grown Co-containing material. Therefore, most of the inhibitor film 140 does not have Co-containing material grown thereon until after multiple ALD cycles. In comparison, since the inhibitor film 140 is not formed on the barrier layer 142, there is no growth delay on the sidewalls of the barrier layer 142.

[0044] Due to the growth delay and random seeding of the liner 144 on the inhibitor film 140, substantially no Co-containing material may be grown on the inhibitor film 140 after the formation of the liner 144 is complete. Alternatively, the liner 144 may not extend onto the inhibitor film 140. It is possible that a small amount of liner 144 is grown on the inhibitor film 140, with a coverage of less than 20% of the exposed surface of the inhibitor film 140. According to some embodiments, the liner 144 forms discrete islands 144' on the surface of the inhibitor film 140, which have a random and irregular pattern. Also as shown in FIG. Figure 8 As shown, some discrete islands 144 ′ of Co-containing material may overlap discrete islands 142 ′ of h-BN from the barrier layer 142 .

[0045] Reference Fig. 9 , a post-deposition treatment 150 is performed to remove the inhibitor film 140. Fig.15In the process flow 200 shown, the corresponding process is shown as process 216. The post-deposition treatment 150 can be performed by plasma treatment. The process gas may include hydrogen (H2) and a carrier gas (such as argon). During the plasma treatment, the temperature of the semiconductor device 100 may be higher than about 200°C, for example, in the range between about 200°C-300°C. The treatment duration may be in the range of about 30 seconds to about 60 seconds. Plasma treatment is also referred to as plasma deblocking treatment. As a result of the post-deposition treatment, the inhibitor film 140 is removed together with the discrete islands 142' and 144'. In the post-deposition treatment 150, the inhibitor film 140 is decomposed into gas and removed. In the case of removing the inhibitor film 140, a gap 152 is formed between the metal filling layer 116 and the end of the barrier layer 142 and the liner 144. The bottom of the sidewall of the etch stop layer 118 is exposed by the gap 152. The sidewall of the dielectric layer 120 is still covered by the barrier layer 142. An advantageous feature of performing post-deposition processing after depositing the barrier layer 142 is that the high-resistance barrier layer 142 will not be present at the bottom of the via opening 124 .

[0046] Reference Fig.10 A supplemental liner 144 ′ is conformally deposited on the liner 144 , for example using ALD, and lines the via opening 124 , the trench 126 , and the top surface of the dielectric layer 120 . Fig.15 In the illustrated process flow 200, the corresponding process is shown as process 218. The supplementary liner 144' also fills the gap 152. The supplementary liner 144' covers the portion of the top surface of the metal filling layer 116 exposed in the through hole opening 124, and covers the portion of the sidewall of the etch stop layer 118 exposed in the gap 152. The supplementary liner 144' can be formed of a suitable metal, metal nitride or metal carbide, such as Co, CoN and RuN. In some other embodiments, the supplementary liner 144' and the liner 144 have the same material composition. For example, the supplementary liner 144' and the liner 144 can both be formed of Co. The thickness of the supplementary liner 144' can be less than the thickness T3 of the liner 144. In an embodiment where the supplementary liner 144' and the liner 144 are formed of the same conductive material, the supplementary liner 144' is merged with the liner 144, and equivalently, the liner 144 is thickened to a thickness T4 greater than the initial thickness T3. In some embodiments, thickness T4 is about 30% to 80% greater than initial thickness T3. Thickened liner 144 helps reduce contact resistance. In embodiments where supplemental liner 144' and liner 144 are made of different conductive material compositions, an observable interface exists between the two different conductive materials. By filling gap 152, liner 144 separates barrier layer 142 from metal fill layer 116.

[0047] Reference Fig.11 , a seed layer 154 is formed on the liner 144. Fig.15 In the process flow 200 shown, the corresponding process is shown as process 220. In some embodiments, the seed layer 154 is a metal alloy layer, which contains at least a main metal element, such as copper (Cu), and an added metal element, such as manganese (Mn). In one example, the seed layer 154 is a copper-manganese (CuMn) layer. In other embodiments, Ti, Al, Nb, Cr, V, Y, Tc, Re, etc. can be used as an alternative added metal to form the seed layer 154. Adding metal elements helps to improve the electronic migration performance of the device. In some embodiments, the concentration (atomic percentage) of the added metal element in the copper alloy layer can be in the range of about 0.5% to about 5%. The concentration of the added metal element in the contact structure of the lower metal layer level can be less than the concentration of the contact structure on the higher metal layer level. In one example, the copper alloy used for the seed layer 154 and the seed layer 114 is CuMn, and the manganese concentration in the lower seed layer 114 is less than the manganese concentration in the upper seed layer 154, for example, less than 1%. This is because, although a higher concentration of the added metal element further helps to improve the electron migration performance, the contact resistance will also increase due to the relatively high impedance of the added metal element. For conductive components formed in lower metal layers, generally smaller metal line widths and metal line spacings have increased the metal resistance at the lower metal layer levels, so a smaller concentration of the added metal element can alleviate the further increase in metal resistance. For conductive components formed in higher metal layer levels, generally larger metal line widths and metal line spacings can accommodate a larger concentration of the added metal element without worrying about the deterioration of metal resistance. The seed layer 154 can be deposited using ALD, CVD, ELD, PVD or other suitable deposition techniques.

[0048] Reference Fig.12 , depositing conductive material 156 to fill via opening 124 and trench 126. Fig.15 In the process flow 200 shown, the corresponding process is shown as process 222. Fig.11 and Fig.12 The processes shown can be performed in situ in the same vacuum environment without vacuum breaking in between. Figures 7 to 10 Part or all of the deposition process can also be performed in conjunction with Fig.11 and Fig.12 The processes shown are performed in situ in the same vacuum environment without vacuum breaking. According to some embodiments, the deposition of seed layer 154 includes blanket deposition using physical vapor deposition (PVD), and filling the remaining portions of via opening 124 and trench 126 using, for example, electroplating. A planarization process such as a chemical mechanical planarization (CMP) process or a mechanical polishing process may be performed to remove excess portions of conductive material 156, thereby forming vias 164 and metal lines 166, as shown. Fig.13 shown.

[0049] Still refer to Fig.13 , the planarization process can use the barrier layer 142 as a planarization stop layer. In other words, after removing the excess portions of the conductive material 156, the seed layer 154, and the liner 144 from above the top surface of the dielectric layer 120, the barrier layer 142 is exposed. By keeping the horizontal portion of the barrier layer 142 on the top surface of the dielectric layer 120, the barrier layer 142 not only conducts the heat from the conductive feature 108 from one interconnect layer below to the next interconnect layer, but also spreads the heat horizontally along the top surface of the dielectric layer 20. The heat dissipation area is significantly expanded. The thickness of the barrier layer 142 ranges from about 1 nm to about 2 nm. This range is not insignificant. If the thickness of the barrier layer 142 is less than about 1 nm, the barrier layer 142 may be too thin to effectively dissipate heat; if the thickness of the barrier layer 142 is greater than about 2 nm, the thick barrier layer 142 may occupy too much valuable space within the through hole 164, and the overall resistance of the through hole 164 may increase, and the circuit speed may be impaired.

[0050] Due to the selective formation of barrier layer 142, barrier layer 142 includes a portion in contact with dielectric layer 120 to perform a diffusion barrier function, and has no portion interposed between liner 144 (supplemental liner 144') and metal filling layer 116 at the bottom of via 164. Since barrier layer 142 may be non-conductive or have low conductivity, not forming barrier layer 142 at the interface with the underlying contact structure may significantly reduce the contact resistance of via 164.

[0051] After forming vias 164 and metal lines 166, other interconnect layers of the MLI structure may then be deposited over dielectric layer 120 to form an upper portion of the MLI structure. Fig.15 In the illustrated process flow 200 , the corresponding process is shown as process 224 . Fig.14A cross-sectional view of a semiconductor device 100 with multiple interconnection layers of an MLI structure that has been formed is shown. For simplicity, the pad 144 and the seed layer 154 formed in the contact structure are not shown separately. The barrier layer 142 in each corresponding interconnection layer transfers heat upward from the conductive structure of the interconnection layer below, and dissipates heat horizontally within the plane of the corresponding interconnection layer. In addition, if the barrier layer 142 is formed of an electrically insulating material, the horizontal portions of the barrier layer 142 of the vias and metal lines in the same interconnection layer can be adjacent to form a continuous heat dissipation plane. In addition, a thermally conductive via 170 (e.g., a through-substrate via (TSV)) made of a thermally conductive material can be formed to pass through multiple interconnection layers and directly contact the horizontal portions of the barrier layer 142 from different interconnection layers to form a 3D heat dissipation network. The 3D heat dissipation network allows the heat generated in the circuit to be dissipated more effectively. The thermally conductive via 170 can be formed of a thermally conductive material that is the same as or different from the barrier layer 142. For example, both the thermally conductive via 170 and the barrier layer 142 can include h-BN. In another example, the thermally conductive via 170 may include aluminum nitride and the barrier layer 142 may include h-BN.

[0052] Embodiments of the present disclosure have some advantageous features. By forming a thermally conductive barrier layer after forming an inhibitor film, the resulting thermally conductive barrier layer is selectively formed on the sidewalls of the low-k dielectric layer because the growth of the inhibitor film on different materials is selective. This can not only perform a diffusion barrier function, but also promote thermal performance, prevent potential overheating, and help extend the life of the device and maintain the operating efficiency of the device.

[0053] In one exemplary aspect, the present disclosure relates to a method for manufacturing a semiconductor structure. The method includes: forming a conductive component in a first dielectric layer; forming a second dielectric layer above the conductive component; forming an opening in the second dielectric layer to expose the top surface of the conductive component; forming an inhibitor film at the top surface of the conductive component; depositing a thermally conductive layer having a first portion on the sidewall of the opening and a second portion on the top surface of the second dielectric layer; removing the inhibitor film to expose the top surface of the conductive component; depositing a conductive material in the opening and on the second portion of the thermally conductive layer; removing a portion of the conductive material to expose the second portion of the thermally conductive layer; and forming a third dielectric layer on the second portion of the thermally conductive layer and the second dielectric layer. In some embodiments, the deposition of the thermally conductive layer includes a reaction between a precursor and a reactive gas, and wherein the precursor includes a molecule containing a boron nitride ring structure. In some embodiments, the molecule is borazine or 1,3,5-trimethylborazine. In some embodiments, the reaction is performed at a temperature below about 500°C. In some embodiments, the thermally conductive layer includes hexagonal boron nitride. In some embodiments, the method further comprises: depositing a liner on the thermally conductive layer before depositing the conductive material, wherein the liner fills a gap between the thermally conductive layer and the conductive component formed after removing the inhibitor film. In some embodiments, the liner separates the physical contact between the thermally conductive layer and the conductive component. In some embodiments, the formation of the inhibitor film comprises: forming an initial inhibitor layer in a first solution; and thickening the initial inhibitor layer in a second solution different from the first solution to form an inhibitor film. In some embodiments, the thermally conductive layer separates the physical contact between the third dielectric layer and the second dielectric layer. In some embodiments, the thermally conductive layer is configured to prevent metal elements in the conductive material from diffusing into the second dielectric layer.

[0054] In another exemplary aspect, the present disclosure relates to a method for forming a semiconductor structure. The method includes: forming an etch stop layer above a substrate; depositing a dielectric layer above the etch stop layer; etching through the dielectric layer and the etch stop layer to form an opening exposing the top surface of the substrate; depositing an inhibitor film at the bottom of the opening; depositing a two-dimensional material layer on the sidewall of the opening, wherein the two-dimensional material layer covers the top surface of the dielectric layer; removing the inhibitor film from the bottom of the opening; depositing a liner layer on the two-dimensional material layer and at the bottom of the opening; depositing a conductive material filling the opening; and performing a planarization process to remove the top and liner layers of the conductive material to expose the two-dimensional material layer, wherein the two-dimensional material layer remains covering the top surface of the dielectric layer. In some embodiments, the two-dimensional material layer includes hexagonal boron nitride. In some embodiments, removing the inhibitor film creates a gap exposing the etch stop layer. In some embodiments, the etch stop layer is in physical contact with the two-dimensional material layer and the liner layer. In some embodiments, the deposition of the two-dimensional material layer includes a plasma enhanced atomic layer deposition (PE-ALD) process or a chemical vapor deposition (CVD) process. In some embodiments, the two-dimensional material layer has a thermal conductivity greater than 10W / m·K.

[0055] In another exemplary aspect, the present disclosure relates to an interconnect structure. The interconnect structure includes: a first conductive component located in a first dielectric layer; an etch stop layer located above the first conductive component; a second dielectric layer located above the etch stop layer; a second conductive component extending through the second dielectric layer and the etch stop layer and landing on the first conductive component; and a thermally conductive barrier layer inserted between the second conductive component and the second dielectric layer, wherein the thermally conductive barrier layer has a horizontal portion that is in direct contact with a top surface of the second dielectric layer. The second conductive component includes a liner layer that separates the thermally conductive barrier layer from the first conductive component. In some embodiments, the second conductive component includes a liner layer that separates the thermally conductive barrier layer from the first conductive component. In some embodiments, the thermally conductive barrier layer is an electrically insulating layer. In some embodiments, the thermally conductive barrier layer is in physical contact with the etch stop layer.

[0056] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: forming a conductive feature in the first dielectric layer; forming a second dielectric layer over the conductive feature; forming an opening in the second dielectric layer to expose a top surface of the conductive feature; forming an inhibitor film at a top surface of the conductive component; depositing a thermally conductive layer having a first portion on a sidewall of the opening and a second portion on a top surface of the second dielectric layer; removing the inhibiting film to expose the top surface of the conductive member; depositing an electrically conductive material in the opening and on the second portion of the thermally conductive layer; removing a portion of the conductive material to expose a second portion of the thermally conductive layer; as well as A third dielectric layer is formed on the second portion of the thermally conductive layer and the second dielectric layer.

2. The method according to claim 1, wherein: The deposition of the thermally conductive layer includes a reaction between a precursor and a reactive gas, and wherein the precursor includes molecules containing a boron nitride ring structure.

3. The method of claim 2, wherein The molecule is borazine or 1,3,5-trimethylborazine.

4. The method according to claim 2, wherein: The reaction is carried out at a temperature below 500°C.

5. The method according to claim 1, wherein: The heat conducting layer includes hexagonal boron nitride.

6. The method according to claim 1, further comprising: Before depositing the conductive material, a liner is deposited on the thermal conductive layer, wherein the liner fills a gap between the thermal conductive layer and the conductive component formed after removing the inhibitor film.

7. The method according to claim 1, wherein: The formation of the inhibitor film comprises: forming an initial inhibitor layer in the first solution; and The initial inhibitor layer is thickened in a second solution different from the first solution to form the inhibitor film.

8. A method of forming a semiconductor structure, comprising: forming an etch stop layer over the substrate; depositing a dielectric layer over the etch stop layer; etching through the dielectric layer and the etch stop layer to form an opening exposing a top surface of the substrate; depositing an inhibitor film at a bottom of the opening; Depositing a two-dimensional material layer on the sidewalls of the opening, wherein the two-dimensional material layer covers the top surface of the dielectric layer; removing the inhibitor film from the bottom of the opening; depositing a liner layer on the two-dimensional material layer and at the bottom of the opening; depositing a conductive material filling the opening; and A planarization process is performed to remove a top portion of the conductive material and the liner layer to expose the two-dimensional material layer, wherein the two-dimensional material layer remains covering the top surface of the dielectric layer.

9. The method according to claim 8, wherein: The two-dimensional material layer has a thermal conductivity greater than 10 W / m·K.

10. An interconnect structure comprising: A first conductive component disposed in the first dielectric layer; an etch stop layer, located above the first conductive component; a second dielectric layer located above the etch stop layer; a second conductive component extending through the second dielectric layer and the etch stop layer and landing on the first conductive component; as well as A thermally conductive barrier layer is interposed between the second conductive component and the second dielectric layer, wherein the thermally conductive barrier layer has a horizontal portion directly contacting a top surface of the second dielectric layer.

Images