Leaded package for integrated circuit die using routing layers

Abstract

A package for an integrated circuit die (e.g., a chip). A wiring layer is laminated between the chip and the package contact of the package. The chip has a planar surface along which the chip includes a die contact. A wiring layer is tiled along the planar surface of the chip and electrically connects the die contacts of the chip with the package contacts of the package. This allows the chip, wiring layer, and package contact to be stacked together to form a relatively thin, compact package. The routing layer connects the die contacts of the chip with the package contacts of the package such that the die contacts do not have the same layout as the package contacts, allowing packages with the same package contact layout to be used for packaging chips with different die contact layouts. The lead is in conductive contact with the package contact.

Description

Background Art

[0001] An integrated circuit is an electronic circuit whose components are all manufactured on a common semiconductor substrate using semiconductor processing steps. One or more integrated circuits may be incorporated into a package that includes various terminals (e.g., bonding pads, pins, or leads). These terminals may be used, for example, to control the integrated circuit, provide power to the integrated circuit, or allow the integrated circuit to communicate with external components. The package may provide the integrated circuit with additional physical protection, proper heat dissipation, and mechanical compatibility with external components such as a printed circuit board.

[0002] The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is provided merely to illustrate one example technology area in which some embodiments described herein may be practiced. Summary of the invention

[0003] This Summary is provided to introduce in a simplified form selected concepts that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0004] Embodiments described herein relate to a leaded package in which an integrated circuit die (e.g., a chip) is packaged. A wiring layer is stacked between the integrated circuit die and one or more package contacts of the package. Specifically, the integrated circuit die has a planar surface (e.g., a flat top surface), and the integrated circuit die includes a die contact along the planar surface. The wiring layer is laid flat along the planar surface of the integrated circuit die, and electrically connects the conductive contacts of the integrated circuit die to the package contacts of the package. The package contacts are also relatively flat and are laid flat along the flat top surface of the wiring layer. Therefore, each of the conductive contacts, wiring layers, and package contacts of the integrated circuit die is elongated substantially parallel to the planar surface of the integrated circuit die. This allows the integrated circuit die, wiring layers, and package contacts to be stacked together to form a relatively thin, compact package.

[0005] The package uses a wiring layer to connect the die contacts of the integrated circuit die to the package contacts of the package, so that the die contacts of the integrated circuit die do not have to have the same layout as the package contacts of the package. Therefore, a package with the same package contact layout can be used to package various types of integrated circuit dies with different die contact layouts while still allowing the leads of the lead frame to make proper contact with the package contacts. This is because the wiring layer will be customized to properly perform the correct wiring in the case of a given lead position, regardless of the layout of the die contacts of the integrated circuit die. In addition, since the die contacts of the integrated circuit die and the package contacts of the package are in close proximity to each other and connected by the conductive portion of the relatively thin wiring layer, the overall package can be more compact and can operate with high power density, low on-resistance and low parasitic inductance.

[0006] Additional features and advantages will be set forth in the following description, and some features and advantages will be apparent from the description or may be learned by practicing the teachings herein. The features and advantages of the present invention may be realized and obtained by the instruments and combinations particularly pointed out in the appended claims. The features of the present invention will become more fully apparent from the following description and the appended claims or may be learned by practicing the present invention as set forth below. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to describe the manner in which the advantages and features of the circuits, systems, and methods described herein can be obtained, a more particular description of the embodiments briefly described herein will be presented by reference to specific embodiments thereof illustrated in the accompanying drawings. It should be understood that these figures depict only typical embodiments of the circuits, systems, and methods described herein, and therefore should not be considered limiting of the scope thereof. Certain circuits, systems, and methods will be described and explained in greater detail and detail through the use of the accompanying drawings, in which:

[0008] Figure 1 Shown is a telescopic view of a circuit structure that may be included within a package according to the principles described herein.

[0009] Figure 2 Shown is a telescopic view of another circuit structure that may be included within a package according to the principles described herein.

[0010] Figure 3 An example of a portion of a lead frame comprising twenty leads is shown, Figure 2 A circuit structure can be mounted to the lead frame.

[0011] Figure 4 Shown is the installation Figure 3 The lead frame after Figure 2 The packaging of the circuit structure.

[0012] Figure 5 It shows that it can include Figure 2 A package of a circuit structure in which a portion of the leads and the thermal layer protrude or are exposed from the outside of the package.

[0013] Figure 6 A telescopic view of another circuit structure that may be contained within a package and include multiple integrated circuit dies is shown. DETAILED DESCRIPTION

[0014] Embodiments described herein relate to a leaded package in which an integrated circuit die (e.g., a chip) is packaged. A wiring layer is stacked between the integrated circuit die and one or more package contacts of the package. Specifically, the integrated circuit die has a planar surface (e.g., a flat top surface), and the integrated circuit die includes a die contact along the planar surface. The wiring layer is laid flat along the planar surface of the integrated circuit die, and the die contact of the integrated circuit die is electrically connected to the package contact of the package. The package contact is also relatively flat and is laid flat along the flat top surface of the wiring layer. Therefore, each of the die contact, wiring layer, and package contact of the integrated circuit die is elongated substantially parallel to the planar surface of the integrated circuit die. This allows the integrated circuit die, wiring layer, and package contact to be stacked together to form a relatively thin, compact package.

[0015] The package uses a wiring layer to connect the die contacts of the integrated circuit die to the package contacts of the package, so that the die contacts of the integrated circuit die do not have to have the same layout as the package contacts of the package. Therefore, a package with the same package contact layout can be used to package various types of integrated circuit dies with different die contact layouts while still allowing the leads of the lead frame to make proper contact with the package contacts. This is because the wiring layer will be customized to properly perform the correct wiring in the case of a given lead position, regardless of the layout of the die contacts of the integrated circuit die. In addition, since the die contacts of the integrated circuit die and the package contacts of the package are in close proximity to each other and connected by the conductive portion of the relatively thin wiring layer, the overall package can be more compact and can operate with high power density, low on-resistance and low parasitic inductance.

[0016] Figure 1 Shown is a telescopic view of a circuit structure 100 that may be included within a package according to principles described herein. Figure 1Coordinate system 101 is shown. For convenience and clarity of explanation only, the z-axis of coordinate system 101 is referred to as the vertical axis, while the x-axis and y-axis are referred to as the horizontal axes. Therefore, the plane defined by the x-axis and y-axis is horizontal and is referred to as the xy plane in this article. On the x-axis, y-axis, and z-axis, the directions indicated by the arrows will be referred to as the positive x-direction, the positive y-direction, and the positive z-direction, respectively. On the other hand, the directions opposite to the positive x-direction, the positive y-direction, and the positive z-direction will be referred to as the negative x-direction, the negative y-direction, and the negative z-direction, respectively. That is to say, this nomenclature is only for the sake of clarity. Of course, the principles described herein are not limited to how the actual circuit structure or package is oriented in the real world.

[0017] The circuit structure 100 includes an integrated circuit die 110, a wiring layer 120, and a package contact 130 (collectively referred to as a "component"), which are stacked on top of each other in the positive z-direction. That is, the wiring layer 120 is stacked on top of the integrated circuit die 110, and the package contact 130 is stacked on top of the wiring layer 120. Although the circuit structure 100 is shown as including a single integrated circuit die 110, the principles described herein also apply to packages containing multiple integrated circuit dies 110. In addition, for clarity, the circuit structure 100 is shown in a telescopic view, using vertical dashed lines to approximately represent the locations where the components make contact with each other. The telescopic view is presented because it allows the components to be more easily distinguished and better represents the horizontal alignment of the components.

[0018] The integrated circuit die 110 includes a planar surface 111 extending parallel to the xy plane. The integrated circuit die 110 also includes a die contact 112, which also extends parallel to the planar surface 111 of the integrated circuit die 110. The die contact 112 is exposed at the planar surface 111 so that the wiring layer 120 can make contact with the die contact 112. As an example, the die contact 112 can have a top surface that is coplanar with the planar surface 111 of the integrated circuit die 110. As another non-limiting alternative, the die contact 112 can be stacked on top of the planar surface 111 of the integrated circuit die 110.

[0019] Although the integrated circuit die 110 is shown as including a single die contact 112, the principles described herein can also be used to connect multiple die contacts to appropriate package contacts. In addition, although the circuit structure 100 is shown as including a single package contact 130, the principles described herein can also be used to connect multiple package contacts to appropriate die contacts. However, for now, in order to keep the example simple, the circuit structure 100 is shown as connecting a single die contact 112 to a single package contact 130.

[0020] The die contact 112 can, for example, be electrically contacted with an integrated circuit contained within the integrated circuit die 110. As a specific example, assume that the integrated circuit die 110 includes a field effect transistor (e.g., a gallium nitride transistor). In this case, the die contact 112 can be a gate contact electrically connected to the gate terminal of the field effect transistor, a drain contact electrically connected to its drain terminal, or a source contact electrically connected to its source terminal. In fact, if the integrated circuit is a field effect transistor, the integrated circuit die 110 can have a plurality of die contacts, each die contact being used to connect to a corresponding terminal (source, gate, drain, and body (if applicable)) of the field effect transistor. Similarly, the wiring layer can provide electrical connections between the corresponding die contacts (for the source, gate, drain, and body (if applicable)) to the corresponding package contacts. Therefore, an appropriate voltage can be applied to the field effect transistor via the corresponding package contacts.

[0021] The wiring layer 120 is relatively thin in the z-direction, extends parallel to the xy plane, and contacts the integrated circuit die 110. More specifically, the wiring layer 120 is laid flat along the planar surface 111 of the integrated circuit die 110, and electrically connects the die contacts 112 of the integrated circuit die 110 with the package contacts 130. As an example, the wiring layer 120 can be epitaxially grown on the planar surface 111 of the integrated circuit die 110. As an alternative example, the wiring layer 120 can be an interposer placed on the planar surface 111 of the integrated circuit die 110 between the integrated circuit die 110 and the package contacts 130. The package contacts 130 are also relatively thin in the z-direction, and extend parallel to the xy plane but contact the wiring layer 120. Because the wiring layer 120 and the package contacts 130 are thin in the z-direction, and because the components are stacked together in the z-direction, the circuit structure 100 is also relatively thin and compact.

[0022] The circuit structure 100 uses a wiring layer 120 to connect the die contacts 112 of the integrated circuit die 110 to the package contacts 130. This is despite the fact that the layout of the die contacts 112 in the xy plane is different from the layout of the package contacts 130 in the xy plane. In other words, the package contacts 130 do not take the same shape as the die contacts 112 or substantially overlap with them. Despite their different layouts, the wiring layer 120 still enables the electrical connection of the die contacts 112 to the package contacts 130. Therefore, the layout of the die contacts 112 can be independent of the layout of the package contacts 130. This allows the layout of the package contacts to be specifically designed to make contact with one or more appropriate leads of the lead frame, as will be described later.

[0023] Therefore, even if the die contacts 112 and the package contacts 130 do not overlap or overlap very little in the xy plane, the wiring layer 120 facilitates electrical connection between them. For example, in one embodiment, each of the package contacts 130 and the die contacts 112 may overlap each other by no more than fifty percent in the xy plane. In another embodiment, each of the package contacts 130 and the die contacts 112 may overlap each other by no more than twenty percent in the xy plane. In yet another embodiment, the package contacts 130 and the die contacts 112 do not overlap each other at all in the xy plane.

[0024] For context, a package including the circuit structure 100 may use external leads to allow external devices to interact with the integrated circuit die 110 within the circuit structure 100. The leads may be attached to the package contacts 130 of the circuit structure 100 such that a portion of the leads protrudes from the package. Thus, the external device may communicate with the integrated circuit die 110 via an electrical path including the leads, the package contacts 130, the wiring layers 120, and the die contacts 112 of the integrated circuit die 110.

[0025] Therefore, there is flexibility between how the package contacts of the package are laid out and how the die contacts of the integrated circuit die are laid out. Therefore, regardless of how the package contacts of the package are laid out, the die contacts of the integrated circuit die can be laid out in a manner that is optimal for achieving the functionality of the integrated circuit die. As a corollary, packages with the same package contact layout can be used to package various types of integrated circuit dies with different die contact layouts. Since such package contact layouts are laid out to accommodate the leads of the lead frame, this means that the same type of lead frame can be used to accommodate a variety of different packages with different integrated circuit dies.

[0026] Figure 1 The circuit structure 100 of FIG. 1 shows an example embodiment in which the wiring layer 120 can be customized to perform proper wiring between the die contacts 112 of the integrated circuit die 110 and the package contacts 130 of the circuit structure 100. However, the principles described herein are not limited to Figure 1 The layout of the die contacts 112 of the integrated circuit die 110 , the customization of the wiring layer 120 , and the layout of the package contacts 130 are shown.

[0027] The wiring layer 120 includes a conductive portion 121. An insulating layer 123 covers the bottom of the conductive portion 121. However, one or more conductive vias 122 extend from the conductive portion 121 through the insulating layer 123 to the die contact 112 of the integrated circuit die 110. The conductive portion 121 of the wiring layer 120 is electrically connected to the package contact 130. Therefore, the die contact 112 of the integrated circuit die 110 is electrically connected to the package contact 130 via the electrical path provided by the wiring layer 120. Specifically, the electrical path includes the conductive via 122 and the conductive portion 121 of the wiring layer 120.

[0028] like Figure 1 As shown, the wiring layer 120 includes two main parts, including a first part 124A and a second part 124B. The first part 124A is used to make safe electrical contact with the package contact 130. Therefore, the first part 124A has the same shape as the package contact 130 (in the xy plane). This will maximize the cross-section through which current can flow between the package contact 130 and the first part 124A of the wiring layer 120, thereby reducing parasitic inductance. However, even if the shape of the first part 124A is not exactly the same as the package contact 130, such benefits can be achieved.

[0029] On the other hand, the second portion 124B is used to make electrical contact with the die contact 112. Therefore, the second portion 124B has the same shape (in the xy plane) as the die contact 112. This will maximize the cross-section of the conductive via 122 that can be placed between the die contact 112 and the second portion 124B of the wiring layer, thereby also reducing parasitic inductance. However, even if the shape of the second portion 124B is not exactly the same as the die contact 112, such benefits can be achieved.

[0030] In this manner, regardless of the layout of the die contacts 112 of the integrated circuit die 110, the wiring layer 120 can be customized to electrically connect the die contacts 112 of the integrated circuit die 110 with the package contacts 130. In addition, as previously described, because the die contacts 112 of the integrated circuit die 110 and the package contacts 130 are in close proximity to each other, connected by the relatively thin conductive portions 121 and conductive vias 122 of the wiring layer 120, the overall package containing the circuit structure 100 can be more compact and can operate with high power density, low on-resistance, and low parasitic inductance.

[0031] Although Figure 1The integrated circuit die 110 is shown to include only one die contact 112, and the circuit structure 100 includes only one package contact 130, but as previously mentioned, the principles described herein are not limited to the number of die contacts 112 that the integrated circuit die 110 has, and are not limited to the number of package contacts 130 that the circuit structure 100 has. For example, Figure 2 An example embodiment is shown in which the circuit structure 200 includes a plurality of package contacts, and the integrated circuit die has a plurality of die contacts.

[0032] Specifically, Figure 2 Shown is a telescopic view of a circuit structure 200 , which is another example of a circuit structure that may be included in a package according to the principles described herein. Figure 2 Coordinate system 101 is also shown. Circuit structure 200 includes integrated circuit die 210, wiring layer 220, and a plurality of package contacts 230A to 230D (collectively referred to as package contacts 230), which are stacked on top of each other in the positive z-direction. That is, wiring layer 220 is stacked on top of integrated circuit die 210, and package contacts 230 are stacked on top of wiring layer 220.

[0033] Similar to Figure 1 The integrated circuit die 110 includes a planar surface 211 (eg, a top surface) extending parallel to the xy plane. Figure 1 Unlike the integrated circuit die 110 of the integrated circuit die 210, the integrated circuit die 210 includes a plurality of die contacts 212A to 212I (collectively referred to as die contacts 212) extending parallel to the planar surface 211 of the integrated circuit die 210. These die contacts 212 are exposed at the planar surface 211 so that the wiring layer 220 can make contact with the die contacts 212. As an example, the die contacts 212 can have a top surface that is coplanar with the planar surface 211 of the integrated circuit die 210. As another alternative example, the die contacts 212 can be stacked on top of the planar surface 211 of the integrated circuit die 210. As an example, the integrated circuit die 210 can be primarily silicon, as a mechanical basis for epitaxially growing other layers thereon.

[0034] In addition, the integrated circuit die 210 includes a second planar surface 213 (e.g., a bottom surface) on a side of the integrated circuit die 210 opposite the first planar surface 211. The second planar surface 213 also extends parallel to the xy plane. The circuit structure 200 includes a thermal layer 250 that is connected to the second planar surface 213 of the integrated circuit die 210. As an example, the thermal layer 250 can be epitaxially grown on the second planar surface 213 of the integrated circuit die 210. As an example, if the integrated circuit die 210 is composed of silicon, the bottom surface 213 can be a silicon surface on which the thermal layer 250 is epitaxially grown. The thermal layer 250 can cover a majority (e.g., more than 70%) of the second planar surface 213 of the integrated circuit die 210.

[0035] When the circuit structure 200 is packaged in a packaging component ( Figure 2 When the circuit structure is packaged in a package (not shown in the figure), a portion of the thermal layer 250 may still be exposed from the outside of the encapsulation element and connected to the heat sink. Therefore, heat can be transferred from the integrated circuit die 210 to the heat sink via the thermal layer 250. Figure 2 When packaging the circuit structure 200, the integrated circuit die 210 can be maintained within specific temperature operating limits, thereby allowing for improved operating efficiency and reduced power losses.

[0036] Returning to the die contact 212, the die contact 212 can, for example, make electrical contact with an integrated circuit contained within the integrated circuit die 210. As a specific example, assume that the integrated circuit die 210 includes a power transistor and a sensing transistor, each of which is a field effect transistor. Furthermore, assume that the gate terminals of the power transistor and the sensing transistor are connected together, the drain terminals of the power transistor and the sensing transistor are connected together, and the source terminals of the power transistor and the sensing transistor are not connected together.

[0037] In this case, die contacts 212A to 212D may be drain contacts electrically connected to the connected drain terminals of the power transistor and the sensing transistor. In addition, die contacts 212E and 212F may be source contacts electrically connected to the source terminals of the power transistor. In addition, die contact 212G may be a source contact electrically connected to the source terminal of the sensing transistor. Finally, die contacts 212H and 212I may be gate contacts electrically connected to the gate terminals of the power transistor and the sensing transistor. Thus, appropriate voltages may be applied to the power transistor and the sensing transistor via these die contacts 212.

[0038] Similar to Figure 1 The wiring layer 120, Figure 2The wiring layer 220 is relatively thin in the z direction, extends parallel to the xy plane, and contacts the integrated circuit die 210. More specifically, the wiring layer 220 is laid flat along the planar surface 211 of the integrated circuit die 210 and electrically connects the die contacts 212 of the integrated circuit die 210 with the package contacts 230. Figure 1 The wiring layer 220 may be epitaxially grown on the planar surface 211 of the integrated circuit die 210, for example. Alternatively, the wiring layer 220 may be an interposer placed on the planar surface 211 of the integrated circuit die 210. The package contacts 230 are also relatively thin in the z-direction, extend together in the same plane parallel to the xy plane, and lay flat on top of the wiring layer 220 in the z-direction. Thus, similar to Figure 1 As for the circuit structure 100 , since the wiring layer 220 and the package contact 230 are thin in the z-direction, and since the components are stacked together in the z-direction, the circuit structure 200 is also relatively thin and compact.

[0039] Similar to Figure 1 The circuit structure 200 uses a wiring layer 220 to electrically connect the die contacts 212 with the package contacts 230, although there is little to no overlap in the xy plane between the layout of the die contacts 212 and the layout of the package contacts 230. To achieve this, the wiring layer 220 includes a portion for making electrical contact with the die contacts 212 and a different portion for making electrical contact with the package contacts 230.

[0040] That is, the wiring layer 220 includes individual portions 240A to 240D (collectively referred to as "portions 240") that are in electrical contact with the corresponding package contacts 230A to 230D. Specifically, as indicated by the vertical dashed lines, portion 240A is in electrical contact with package contact 230A, portion 240B is in electrical contact with package contact 230B, portion 240C is in electrical contact with package contact 230C, and portion 240D is in electrical contact with package contact 230D. Therefore, portions 240A, 240B, 240C, and 240D may have substantially the same shape as corresponding package contacts 230A, 230B, 230C, and 230D. This will maximize the cross-section through which current can flow between package contact 230 and wiring layer portion 240, thereby reducing parasitic inductance.

[0041] On the other hand, the wiring layer 220 includes various portions 224A to 224H (collectively referred to as "portions 224") that make electrical contact with the die contacts 212 via conductive vias 222. In particular, the wiring layer 220 includes an insulating layer 223 that covers the bottom of the portion 240 and the bottom of the portion 224. In addition, the conductive vias 222 extend from the conductive portion 224 through the insulating layer 223 to the die contacts 212. In this way, the die contacts 212 of the integrated circuit die 210 are electrically connected to the portions 224 of the wiring layer 220 via these conductive vias 222.

[0042] Thus, portions 224A to 224D are in electrical contact with respective die contacts 212A to 212D, thereby electrically connecting wiring layer 220 to the drain terminals of the power transistor and the sensing transistor. In addition, portions 224E and 224F are in electrical contact with respective die contacts 212E and 212F, thereby electrically connecting wiring layer 220 to the source terminal of the power transistor. Continuing, portion 224G is in electrical contact with die contact 212G, thereby electrically connecting wiring layer 220 to the source terminal of the sensing transistor. Finally, portion 224H is in electrical contact with die contact 212H, thereby electrically connecting wiring layer 220 to the gate terminals of the power transistor and the sensing transistor. For completeness, die contacts 212H and 212I may be electrically connected inside integrated circuit die 210. Thus, the portions 224 may have substantially the same shape as their corresponding die contacts 212 , thereby maximizing the cross-sectional area in which the conductive vias 222 may be placed between the die contacts 212 and the corresponding portions 224 of the wiring layer 220 , thereby also reducing parasitic inductance.

[0043] As an example, recall the aforementioned case where the integrated circuit die 210 includes a power transistor and a sensing transistor, the drain terminals of the power transistor and the sensing transistor are connected, the gate terminals are connected, but the source terminals are not connected. In this case, the package contact 230A can be a drain package contact connected to the connected drain terminals of the power transistor and the sensing transistor via a first electrical path. Specifically, the first electrical path includes the package contact 230A, the conductive portion 240A, the portions 224A to 224D, some of the conductive vias 222, and the die contacts 212A to 212D.

[0044] In addition, package contact 230B can be a power transistor source package contact connected to the source terminal of only the power transistor via a second electrical path. Specifically, the second electrical path includes package contact 230B, conductive portion 240B, portions 224E and 224F, some of conductive vias 222, and die contacts 212E and 212F.

[0045] Furthermore, package contact 230C may be a sense transistor source package contact connected to the source terminal of the sense-only transistor via a third electrical path, specifically, the third electrical path including package contact 230C, conductive portion 240C, portion 224G, some of conductive vias 222, and die contact 212G.

[0046] Finally, package contact 230D may be a gate package contact connected to the connected gate terminals of the power transistor and the sense transistor via a fourth electrical path. Specifically, the fourth electrical path includes package contact 230D, conductive portion 240D, portion 224H, some of conductive vias 222, and die contact 212H.

[0047] Thus, the wiring layer 220 is tailored to electrically connect the die contacts 212A to 212I of the integrated circuit die 210 with their corresponding package contacts 230A to 230D, while allowing the package contacts to have an appropriate layout for subsequent connection to the leads of the lead frame. Thus, in the case where the die contacts 212 are connected to the terminals of the field effect transistors contained within the integrated circuit 210, appropriate voltages can be applied to the gate terminals, drain terminals, and source terminals of these field effect transistors via an electrical path that includes the package contacts 230, the conductive portions 240 and 224 of the wiring layer 220, the conductive vias 222 of the wiring layer 220, and the die contacts 212. In addition, because the die contacts 212 and the package contacts 230 are in close proximity to each other, connected by the relatively thin conductive portions 240 and 224 of the wiring layer 220 and the conductive vias 222, the overall package containing the circuit structure 200 can be more compact and can operate with high power density, low on-resistance, and low parasitic inductance.

[0048] As previously expressed, circuit structure 200 may be incorporated into a package that includes leads that enable external devices to interact with integrated circuit die 210 within the package. Figure 3 An example of a portion 300 of a lead frame is shown, which includes twenty leads 301A to 301T (collectively referred to as "leads 301"). The circuit structure 200 is mounted to the leads 301 by turning the circuit structure 200 over. Thus, Figure 3 Coordinate system 101 is also shown, but where the positive z-direction is now facing downward, and where the positive y-direction is now aligned with Figure 2 The direction is opposite.

[0049] Ten leads 301A to 301J (collectively labeled 310A) are drain leads that will make conductive contact with the drain package contact 230A of lead 310A and will make contact with the source package contact 230A of circuit structure 200. Eight leads 301K to 301R (collectively labeled 310B) are power transistor source leads that will make conductive contact with the power transistor source package contact 230B of circuit structure 200. One lead 301S (also labeled 310C) is a sense transistor source lead that will make conductive contact with the sense transistor source package contact 230C of the circuit structure. The last lead 301T (also labeled 310D) is a gate lead that will make conductive contact with the gate package contact 230D of circuit structure 200.

[0050] Figure 4 The package 400 is shown, which includes a package that is turned upside down and mounted on the lead 301. Figure 2 Circuit structure 200. Note that Figure 4 In the negative z direction, the thermal layer faces upward. Figure 1 Although not visible, the package contact 230A of the circuit structure 200 contacts the lead 310A, the package contact 230B of the circuit structure 200 contacts the lead 310B, the package contact 230C of the circuit structure 200 contacts the lead 310C, and the package contact 230D of the circuit structure 200 contacts the lead 310D.

[0051] Specifically, Figure 5 A package 500 is shown, which represents Figure 4 The subsequent manufacturing stage of the package 400. Here, the protective mechanical encapsulation 510 surrounds Figure 4 4, except for the window 510 exposing the thermal layer 250 and the leads 301 extending to the outside of the mechanical encapsulation 501. As an example, the mechanical encapsulation may be an injection molded plastic, or may be a preformed assembly that is latched together.

[0052] review Figure 2 , where package contact 230A is a drain package contact connected to the drain terminals of the power transistor and the sense transistor included in the integrated circuit die 210. In this case, lead 310A may be a drain lead attached to drain package contact 230A of circuit structure 200. Thus, an external device may apply a drain voltage to the connected drain terminals of the power transistor and the sense transistor via lead 310A.

[0053] Furthermore, recall the example in which package contact 230B is a power transistor source package contact connected to only the source terminal of the power transistor. In this case, lead 310B may be a power transistor source lead attached to power transistor source package contact 230B of circuit structure 200. Thus, an external device may apply a power transistor source voltage to the source terminal of the power transistor via lead 310B.

[0054] Furthermore, recalling the example in which package contact 230C is a sense transistor source package contact connected to the source terminal of only the sense transistor, in this case, lead 310C may be a sense transistor source lead attached to sense transistor source package contact 230C of circuit structure 200. Thus, an external device may apply a sense transistor source voltage to the source terminal of the sense transistor via lead 310C.

[0055] Finally, recall the example in which package contact 230D is a gate package contact connected to the gate terminals of the power transistor and the sense transistor. In this case, lead 310D can be a gate lead attached to gate package contact 230D of circuit structure 200. Thus, an external device can apply a gate voltage to the connected gate terminals of the power transistor and the sense transistor via lead 310D.

[0056] As previously expressed, a portion of the thermal layer 250 of the circuit structure 200 may remain exposed from the outside of the encapsulation element 320 of the package 500. Therefore, the portion of the thermal layer 250 that remains exposed can be connected to a heat sink. Therefore, when the package 500 is being used, the heat generated by the integrated circuit die 210 can be transferred to the heat sink via the thermal layer 250. Therefore, the package 500 allows the integrated circuit die 210 to be maintained within specific temperature operating limits, thereby allowing for improved operating efficiency and reduced power losses.

[0057] Although Figure 5 The package 500 has been described as specifically comprising Figure 2 Although the circuit structure 200 of FIG. 1 is shown, the principles described herein are not limited to a package 500 containing any particular circuit structure. In fact, the package 500 may instead contain a different circuit structure, which includes multiple integrated circuit dies, such as Figure 6 The same situation in .

[0058] Specifically, Figure 6 Shown is a circuit structure 600 which is another example of a circuit structure that may be included within a package according to the principles described herein. Figure 6 It also shows that Figure 1 and Figure 2The circuit structure 600 includes a plurality of integrated circuit dies 610A-610D (collectively “integrated circuit dies” 610 ), a wiring layer 620 , a plurality of package contacts 630A-630D (collectively “package contacts 630 ”), and a thermal layer 650 .

[0059] In one embodiment, Figure 6 Each of the integrated circuit dies 610 is Figure 2 In this case, each integrated circuit die 610 may include various die contacts, such as drain contacts, source contacts, and gate contacts, as described with respect to FIG. Figure 2 Each of the integrated circuit dies 610 may have a top planar surface that is substantially coplanar with one another, and each of the die contacts of the integrated circuit dies 610 may also be substantially coplanar with one another. As an example, each of the integrated circuit dies 610 may be a replica of one another. Although each of the integrated circuit dies 610 may be Figure 2 2. Although this is an example of an integrated circuit die 210, in some embodiments, one or more of the integrated circuit dies 610 may contain different circuits.

[0060] Likewise, package contacts 630A to 630D are Figure 2 Thus, as an example, package contacts 630A, 630B, 630C, and 630D may be drain package contact 630A, power transistor source package contact 630B, sense transistor source package contact 630C, and gate package contact 630D, respectively, as described with respect to FIG. Figure 2 Descriptive.

[0061] Similarly, thermal layer 650 is Figure 2 The example of thermal layer 250 is similar to that of FIG. 6 , but may be larger in a planar direction parallel to the xy plane so as to cover a larger surface area of ​​the bottom planar surface of the integrated circuit die 610. Alternatively, the thermal layer 650 may have a similar surface area to that of FIG. Figure 2 The thermal layer 250 is substantially the same size, but each of the integrated circuit dies 610 may instead be Figure 2 A miniaturized version of the integrated circuit die 210 .

[0062] For the sake of explanation and simplicity, the wiring layer 620 is shown as a dashed box. However, in reality, the wiring layer 620 may include various parts that make electrical contact with the package contacts 630 and may have substantially the same shape as the package contacts 630. Similarly, the wiring layer 620 may include various parts that make electrical contact with the die contacts of the integrated circuit die 610 (via conductive vias) and may have substantially the same shape as the die contacts.

[0063] Thus, the wiring layer 620 can electrically connect each of the drain die contacts of the integrated circuit die 610 to the drain package contact 630A. In addition, the wiring layer 620 can electrically connect each of the power transistor source die contacts of the integrated circuit die 610 to the power transistor source package contact 630B. In addition, the wiring layer 620 can electrically connect each of the sense transistor source die contacts of the integrated circuit die 610 to the sense transistor source package contact 630C. Finally, the wiring layer 620 can electrically connect each of the gate die contacts of the integrated circuit die 610 to the gate package contact 630D. Thus, the wiring layer 620 can be customized even with significant complexity to electrically connect the die contacts of multiple integrated circuit dies 610 to their corresponding package contacts 630.

[0064] Thus, what has been described is a package and associated method of manufacture in which the package contact layout is arranged to accommodate the leads of a lead frame. Using this technique, the same lead frame type can be used to accommodate a variety of different packages having different integrated circuit dies.

[0065] Literal support part

[0066] Item 1. A package comprising: an integrated circuit die having a planar surface and having a die contact elongated parallel to the planar surface of the integrated circuit die, the die contact making electrical contact with an integrated circuit of the integrated circuit die; a package contact also elongated parallel to the planar surface of the integrated circuit die; a wiring layer comprising a conductive portion also extending parallel to the planar surface of the integrated circuit die and electrically connecting the package contact with the die contact, wherein the package contact and the die contact have different profiles along the planar surface of the integrated circuit die; and a plurality of leads of a lead frame, at least one of the plurality of leads making electrical contact with the package contact.

[0067] Clause 2. The package of Clause 1, wherein each of the package contacts and the die contacts overlaps the other by no more than 50% in a plane parallel to the planar surface of the integrated circuit die.

[0068] Clause 3. The package of Clause 1, wherein each of the package contacts and the die contacts overlaps the other by no more than 20% in a plane parallel to the planar surface of the integrated circuit die.

[0069] Clause 4. The package of clause 1, wherein the planar surface is a first planar surface, the package further comprising: a thermal layer mounted to a second planar surface of the integrated circuit die, the second planar surface of the integrated circuit die being parallel to the first planar surface of the integrated circuit die but on an opposite side of the integrated circuit die.

[0070] Clause 5. The package of Clause 4, further comprising: an encapsulation element at least partially encapsulating the integrated circuit die, at least one lead making die contact with the package contact extending outside the encapsulation element.

[0071] Item 6. A package according to Item 5, wherein the die contact is a first die contact, the package contact is a first package contact, the conductive portion is a first conductive portion, at least one of the plurality of leads is a first lead of a lead frame, and the package further comprises: a second package contact elongated parallel to a planar surface of the integrated circuit die; and a second lead of the lead frame, the second lead being in conductive contact with the package contact, wherein the integrated circuit die further comprises a second die contact elongated parallel to the planar surface of the integrated circuit die, and the wiring layer further comprises a second conductive portion extending parallel to the planar surface of the integrated circuit die and electrically connecting the second package contact with the second die contact, the second package contact and the second die contact having different profiles along the planar surface of the integrated circuit die.

[0072] Clause 7. The package of Clause 6, the second die contact making electrical contact with an integrated circuit of the integrated circuit die.

[0073] Clause 8. The package of Clause 1, wherein the integrated circuit comprises a gallium nitride transistor.

[0074] Clause 9. The package of Clause 1, wherein the integrated circuit comprises a transistor, and the die contact is a gate contact electrically connected to a gate terminal of the transistor.

[0075] Clause 10. The package of Clause 1, wherein the integrated circuit comprises a transistor, and the die contact is a drain contact electrically connected to a drain terminal of the transistor.

[0076] Clause 11. The package of Clause 1, wherein the integrated circuit comprises a transistor, and the die contact is a source contact electrically connected to a source terminal of the transistor.

[0077] Clause 12. A package as described in clause 1, wherein the integrated circuit die is a first integrated circuit die, the planar surface is a first planar surface, the die contact is a first die contact, the package contact is a first package contact, and at least one lead of the lead frame is a first lead of the lead frame, and the package further includes: a second integrated circuit die, the second integrated circuit die having a second planar surface substantially parallel to the first planar surface of the first integrated circuit die, the second integrated circuit die having a second die contact elongated parallel to the second planar surface of the second integrated circuit die, the second die contact making electrical contact with the integrated circuit of the second integrated circuit die; a second package contact elongated parallel to the second planar surface of the second integrated circuit die, the second lead of the lead frame making conductive contact with the second package contact.

[0078] Clause 13. The package of clause 12, wherein the conductive portion of the wiring layer is a first conductive portion, wherein the wiring layer further comprises a second conductive portion extending parallel to a second planar surface of the integrated circuit die, wherein the second conductive portion of the wiring layer electrically connects the second package contact with the second die contact.

[0079] Clause 14. The package of Clause 13, wherein the first conductive portion of the wiring layer electrically connects the first package contact with the second die contact.

[0080] Clause 15. The package of Clause 12, wherein the second planar surface is coplanar with the first planar surface.

[0081] Clause 16. The package of Clause 15, each of the second package contact and the second die contact overlapping the other by no more than 20% along the second planar surface of the second integrated circuit die.

[0082] Item 17. According to the package described in Item 12, the first integrated circuit die also includes a third die contact elongated parallel to the first planar surface of the first integrated circuit die, wherein the conductive portion of the wiring layer is a first conductive portion, and the wiring layer also includes a second conductive portion extending parallel to the first planar surface and electrically connecting the second package contact with the third die contact, and the second package contact and the third die contact have different profiles along the planar surface of the integrated circuit die.

[0083] Clause 18. The package of Clause 1, wherein the wiring layer is epitaxially grown on a planar surface of the integrated circuit die.

[0084] Clause 19. The package of Clause 1, the wiring layer being part of an interposer between the integrated circuit die and package contacts of the package.

[0085] Although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the described features or acts described above, or the order of acts described above. Rather, the described features and acts are disclosed as example forms of implementing embodiments.

[0086] Without departing from its essential characteristics, the present disclosure may be embodied in other specific forms. The described embodiments are to be considered in all respects as illustrative rather than restrictive. All changes within the equivalent meaning and scope of the claims are to be included within their scope.

[0087] When introducing elements in the appended claims, the articles "a," "an," "the," and "said" mean that there are one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements.

Claims

1. A package comprising: an integrated circuit die having a planar surface and having die contacts elongated parallel to the planar surface of the integrated circuit die, the die contacts making electrical contact with an integrated circuit of the integrated circuit die; package contacts also elongated parallel to the planar surface of the integrated circuit die; a wiring layer including conductive portions also extending parallel to the planar surface of the integrated circuit die and electrically connecting the package contacts with the die contacts, wherein the package contacts and the die contacts have different profiles along the planar surface of the integrated circuit die; as well as A plurality of leads of the lead frame, at least one lead of the plurality of leads being in conductive contact with the package contact.

2. The package of claim 1, each of the package contacts and the die contacts overlapping the other by no more than 50% in a plane parallel to the planar surface of the integrated circuit die.

3. The package of claim 1, each of the package contacts and the die contacts overlapping the other by no more than 20% in a plane parallel to the planar surface of the integrated circuit die.

4. The package of claim 1 , wherein the planar surface is a first planar surface, the package further comprising: A thermal layer is mounted to a second planar surface of the integrated circuit die, the second planar surface of the integrated circuit die being parallel to the first planar surface of the integrated circuit die but on an opposite side of the integrated circuit die.

5. The package according to claim 4, further comprising: An encapsulation element at least partially encapsulates the integrated circuit die, the at least one lead making die contact with the package contact extending outside the encapsulation element.

6. The package according to claim 5, wherein: The die contact is a first die contact, the package contact is a first package contact, the conductive portion is a first conductive portion, the at least one lead of the plurality of leads is a first lead of the lead frame, and the package further comprises: a second package contact elongated parallel to the planar surface of the integrated circuit die; and A second lead of the lead frame, the second lead is in conductive contact with the package contact, wherein The integrated circuit die also includes a second die contact elongated parallel to the planar surface of the integrated circuit die, and The wiring layer also includes a second conductive portion extending parallel to the planar surface of the integrated circuit die and electrically connecting the second package contact with the second die contact, the second package contact and the second die contact having different profiles along the planar surface of the integrated circuit die.

7. The package of claim 6, the second die contact making electrical contact with the integrated circuit of the integrated circuit die.

8. The package according to claim 1, wherein: The integrated circuit includes a gallium nitride transistor.

9. The package according to claim 1, wherein: The integrated circuit includes a transistor, and the die contact is a gate contact electrically connected to a gate terminal of the transistor.

10. The package of claim 1, wherein: The integrated circuit includes a transistor, and the die contact is a drain contact electrically connected to a drain terminal of the transistor.

11. The package according to claim 1, wherein: The integrated circuit includes a transistor, and the die contact is a source contact electrically connected to a source terminal of the transistor.

12. The package of claim 1, wherein: The integrated circuit die is a first integrated circuit die, the planar surface is a first planar surface, the die contact is a first die contact, the package contact is a first package contact, and the at least one lead of the lead frame is a first lead of the lead frame, the package further comprising: a second integrated circuit die having a second planar surface substantially parallel to the first planar surface of the first integrated circuit die, the second integrated circuit die having a second die contact elongated parallel to the second planar surface of the second integrated circuit die, the second die contact making electrical contact with an integrated circuit of the second integrated circuit die; A second package contact is elongated parallel to the second planar surface of the second integrated circuit die, and a second lead of the lead frame is in conductive contact with the second package contact.

13. The package according to claim 12, the conductive portion of the wiring layer is a first conductive portion, wherein The wiring layer also includes a second conductive line portion extending parallel to the second planar surface of the integrated circuit die, wherein the second conductive portion of the wiring layer electrically connects the second package contact with the second die contact.

14. The package of claim 13, wherein: The first conductive portion of the wiring layer electrically connects the first package contact with the second die contact.

15. The package of claim 12, wherein: The second planar surface is coplanar with the first planar surface.

16. The package of claim 15, each of the second package contact and the second die contact overlapped by no more than 20% along the second planar surface of the second integrated circuit die.

17. The package of claim 12, the first integrated circuit die further comprising a third die contact elongated parallel to the first planar surface of the first integrated circuit die, wherein: The conductive portion of the wiring layer is a first conductive portion, and the wiring layer also includes a second conductive portion extending parallel to the first planar surface and electrically connecting the second package contact with the third die contact, the second package contact and the third die contact having different profiles along the planar surface of the integrated circuit die.

18. The package of claim 1, said wiring layer being epitaxially grown on said planar surface of said integrated circuit die.

19. The package of claim 1, the routing layer being part of an interposer between the integrated circuit die and the package contacts of the package.

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