Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a semiconductor layer; the first connecting structure penetrates through the semiconductor layer; the first contact structure is located at the first end of the first connection structure in the thickness direction; the first contact structure comprises a plurality of salient points arranged at intervals, and the salient points are coupled with the first end of the first connection structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] A three-dimensional integrated circuit can be formed by stacking semiconductor chips, and the semiconductor chip has an electronic circuit system formed therein or thereon. These stacked semiconductor chips can be interconnected vertically. The stacked semiconductor chips can be interconnected using through silicon vias (TSV) to form a circuit structure with electrical functions. For example, multiple memory chips, logic chips, or communication chips can be stacked, and multiple memory chips can be interconnected using through silicon vias to obtain high-bandwidth and high-computing power integrated circuits or electronic systems, shortening the length of interconnections between chips to improve performance. With the improvement of the integration of semiconductor chips, the integration of through silicon vias is also getting higher and higher, and there is still a lot of room for improvement in the chip stacking process. Summary of the invention

[0003] According to some aspects of the embodiments of the present disclosure, a semiconductor structure is provided, including: a semiconductor layer; a first connecting structure, which passes through the semiconductor layer; a first contact structure, which is located at the first end of the first connecting structure in the thickness direction; the first contact structure includes a plurality of spaced-apart bumps, which are coupled to the first end of the first connecting structure.

[0004] In some embodiments, the semiconductor structure further includes: a first insulating film having a plurality of first openings; some of the first openings correspond to the first ends of the first connection structures in the thickness direction; and the bumps are disposed in the first openings corresponding to the first connection structures.

[0005] In some embodiments, the semiconductor structure also includes: a first dielectric layer, covering the plurality of the bumps; the first contact structure also includes: a second connection structure, located at one end of the bump away from the first connection structure, the second connection structure passing through the first dielectric layer; the second connection structure includes at least a first sub-connection structure and a second sub-connection structure extending along the thickness direction, and there is a gap between the first sub-connection structure and the second sub-connection structure; the plurality of spaced-apart bumps include at least a first bump and a second bump; the first sub-connection structure contacts the first bump, and the second sub-connection structure contacts the second bump.

[0006] In some embodiments, the first sub-connection structure is in partial contact with the second sub-connection structure.

[0007] In some embodiments, the semiconductor structure further includes: a first barrier layer located between the second connection structure and the first dielectric layer; and the first barrier layer surrounds a sidewall of the second connection structure extending along the thickness direction.

[0008] In some embodiments, the semiconductor structure further includes: a connection layer located between the first connection structure and the semiconductor layer; the connection layer surrounds a side wall of the first connection structure extending along the thickness direction.

[0009] In some embodiments, the semiconductor structure further includes: a first contact located on a side of the second connection structure away from the first connection structure; and the first contact is coupled to the second connection structure.

[0010] In some embodiments, the semiconductor structure also includes: a second contact structure located at the second end of the first connection structure away from the first contact structure in the thickness direction; the second contact structure is coupled to the second end of the first connection structure; a second contact point located on a side of the second contact structure away from the first connection structure; and the second contact point is coupled to the second contact structure.

[0011] According to some aspects of the embodiments of the present disclosure, a method for manufacturing a semiconductor structure is provided, including: providing a semiconductor layer; forming a first connection structure that penetrates at least part of the thickness of the semiconductor layer; attaching a first insulating film having a plurality of first openings on the first connection structure, and part of the first openings expose the first end of the first connection structure in the thickness direction; forming a first dielectric layer on the first insulating film, and forming second openings that penetrate the first dielectric layer; the second openings expose a plurality of the first openings, and the second openings expose the first connection structure through the plurality of the first openings; filling the first openings and the second openings with a conductive material to form a first contact structure; and the first contact structure is coupled to the first end of the first connection structure.

[0012] In some embodiments, the method for forming the first contact structure includes: forming a plurality of bumps in the plurality of first openings of the first insulating film, and forming a second connection structure in the second opening; the second connection structure includes at least a first sub-connection structure and a second sub-connection structure extending along the thickness direction, and there is a gap between the first sub-connection structure and the second sub-connection structure; the plurality of spaced bumps include at least a first bump and a second bump; the first sub-connection structure contacts the first bump, and the second sub-connection structure contacts the second bump.

[0013] In some embodiments, the method for forming the first connection structure includes: etching the semiconductor layer to form a third opening that penetrates at least part of the thickness of the semiconductor layer; filling the third opening with photoresist and removing part of the photoresist in the third opening to form a connection layer on the side wall of the third opening; and forming the first connection structure in the third opening having the connection layer.

[0014] In some embodiments, the manufacturing method further includes: forming a first barrier layer on the sidewall of the second opening, wherein the first barrier layer surrounds the sidewall of the second connection structure extending along the thickness direction.

[0015] In some embodiments, the manufacturing method further includes: forming a first contact on a side of the second connection structure away from the first connection structure; and coupling the first contact to the second connection structure.

[0016] In some embodiments, the first connecting structure penetrates a portion of the thickness of the semiconductor layer, and the manufacturing method further includes: thinning a side of the semiconductor layer away from the first contact to expose the second end of the first connecting structure in the thickness direction so that the first connecting structure penetrates the semiconductor layer; forming a second contact structure on the second end of the first connecting structure, and the second contact structure is coupled to the second end of the first connecting structure; forming a second contact on the second contact structure, and the second contact is coupled to the second contact structure.

[0017] An embodiment of the present disclosure provides a semiconductor structure, including: a semiconductor layer and a first connection structure that penetrates the semiconductor layer along the thickness direction, located at the first end of the first connection structure in the thickness direction, the first contact structure includes a plurality of spaced-apart bumps, and the bumps of the first contact structure are used to couple with the first end of the first connection structure; compared with a solid, integral contact structure, the spaced-apart bumps in the embodiment of the present disclosure are conducive to dispersing stress, reducing stress concentration caused by thermal strain, and reducing deformation of the bumps or structural rupture caused by differences in thermal expansion coefficients between the bumps and other materials. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figures 1 to 4 is a schematic diagram showing the manufacture of a semiconductor structure according to an exemplary embodiment;

[0019] Figure 5 and Figure 6 is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0020] Figure 7 is a schematic diagram of a semiconductor structure manufacturing process according to an embodiment of the present disclosure;

[0021] Figures 8 to 17It is a schematic diagram of manufacturing a semiconductor structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0023] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0024] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0025] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0026] It should be understood that the "some embodiments" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, "in some embodiments" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the sequence number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.

[0027] In some embodiments, for some connection structures, including but not limited to TSV, conductive plugs, and conductive channels, they can extend along the thickness direction of the wafer or device, such as the z direction in the attached figure; they can be used to conduct electrical or signal interconnection for semiconductor structures, devices, and chips. The z direction can be a third direction, and the x direction and the y direction are directions that intersect and are perpendicular to the z direction. The x direction and the y direction can be recorded as the first direction and the second direction respectively; the x and y directions intersect or are perpendicular, and the plane formed by the x and y directions intersects and is perpendicular to the z direction.

[0028] In some embodiments, some methods for making the connection structure 104 are described by way of example; Figure 1 As shown, the semiconductor layer 100 or the dielectric layer is etched to form an opening 101 that penetrates a portion of the thickness of the semiconductor layer 100 or completely penetrates the semiconductor layer 100, and the opening 101 may extend along the z direction. The semiconductor layer 100 may be a semiconductor substrate or a film layer epitaxially grown on a semiconductor substrate; after the opening 101 only penetrates a portion of the thickness of the semiconductor layer 100, the semiconductor layer 100 may be back-thinned to expose the bottom of the opening 101 or the bottom of the connection structure in the opening 101, so that the opening 101 or the connection structure in the opening 101 penetrates the semiconductor layer 100. The etching process may include, but is not limited to, dry etching, wet etching, and combinations thereof.

[0029] Reference Figure 2As shown, a barrier layer 102 is deposited on the sidewall and / or bottom of the opening 101. The material of the barrier layer 102 may include but is not limited to metal nitrides, including but not limited to titanium nitride, tantalum nitride, chromium nitride, aluminum nitride, tungsten nitride or a combination thereof. The deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

[0030] exist Figure 2 The opening 101 with the barrier layer 102 is filled with a conductive material to form a connection structure 104. A deposition process may be performed to form the connection structure 104. The materials of the connection structure 104 may include but are not limited to: copper, aluminum, tungsten, gold, silver, platinum, chromium, nickel, cobalt, titanium and other conductive materials. Figure 3 As shown, a seed layer 103 may be deposited in the opening 101 having the barrier layer 102, and the seed layer 103 may include but is not limited to copper; Figure 4 As shown, a connection structure 104 is formed in the opening 101 with the seed layer 103 by deposition or electroplating process, and the connection structure 104 includes copper. A portion of the conductive material covering the semiconductor layer can be removed by chemical mechanical polishing, and the connection structure 104 in the opening 101 is retained.

[0031] In some embodiments, a dielectric layer may be formed between the barrier layer 102 and the semiconductor layer 100, such as silicon oxide formed by atomic layer deposition or chemical deposition, such as thermal silicon oxide (high-temperature silicon oxide) formed by thermal oxidation; the thermal expansion coefficients of the conductive material in the connection structure 104, the barrier layer 102, and the dielectric layer are different. For example, the connection structure 104-barrier layer 102-dielectric layer is copper-tantalum nitride-silicon oxide. When subjected to high temperature, the expansion degree of copper is greater than that of tantalum nitride and silicon oxide. The copper expands to a greater length in the z direction, which makes the length of the copper layer in the z direction greater than that of tantalum nitride and silicon oxide, resulting in peeling between the copper layer and the tantalum nitride and silicon oxide, and delamination and cracking of the connection structure 104 and the barrier layer 102; in the x direction or other horizontal directions, because copper has a larger thermal expansion coefficient, the copper layer expands laterally, causing an increase in horizontal stress, resulting in bending and cracking of the product. In some embodiments, the front-end, middle-end and back-end processes in the semiconductor manufacturing process may have a larger process temperature range. For example, the front-end process may mainly involve the manufacture of transistors and device structures, and the temperature treatment may include a high temperature of 1000°C. The middle-end and back-end processes may include the manufacture of metal contacts, metal connections and metal wiring, and the temperature treatment may include 400-500°C to prevent the metal from melting or deforming. In some embodiments, in order to facilitate process integration and reduce manufacturing costs, connection structures such as TSV can be manufactured at various process stages, with a larger temperature range. Reducing the thermal strain deformation of the connection structure is conducive to improving the manufacturing yield and device stability.

[0032] According to some aspects of the embodiments of the present disclosure, Figure 5 A semiconductor structure 20 is provided, comprising: a semiconductor layer 200; a first connection structure 210, which penetrates the semiconductor layer 200; a first contact structure 220, which is located at the first end of the first connection structure 210 in the thickness direction (z direction); the first contact structure 220 includes a plurality of spaced-apart bumps 241, and the bumps 241 are coupled to the first end of the first connection structure 210.

[0033] Figure 5 The upper surface of the semiconductor layer 200 may be the front side of the wafer or substrate, or the back side of the wafer or substrate. The semiconductor layer 200 may be a thinned film layer. The first connection structure 210 may penetrate at least a portion of the thickness of the semiconductor layer 200, or completely penetrate the semiconductor layer 200. The first contact structure 220 is located on the first end of the first connection structure 210. Figure 5The top of the first connection structure 210 in the z direction. The first contact structure 220 can be directly contacted and coupled with the first connection structure 210, or connected through other conductive structures, including but not limited to a connection layer, a transition layer, including but not limited to metal silicide, metal nitride, or a low-resistance material with a resistance lower than that of the first connection structure 210, to increase the adhesion between the first contact structure 220 and the first connection structure 210 to reduce the contact resistance. Figure 5 Also shown is an enlarged schematic diagram of a partial cross section of the first contact structure 220 penetrating the first insulating film 261 or at the xoy plane at the first insulating film 261; the cross-sectional outer contour shape of the first contact structure 220 in the xoy plane may include but is not limited to a circle, an ellipse or other regular or irregular arcs; may include a rectangle, a triangle or other regular or irregular polygons; may also include other figures composed of arcs and straight lines; the cross-sectional figure of the first connection structure 210 in the xoy plane may refer to the first contact structure 220 and will not be repeated.

[0034] The first contact structure 220 may include a plurality of spaced substructures, such as conductive bumps 241. The bumps 241 may be columnar and extend in the z direction. There is no restriction on the cross-sectional shape of the bumps 241 in the xoy plane, and there is no restriction on the arrangement and number of the bumps 241. The bumps 241 may include but are not limited to: Figure 5 The bumps 241 are arranged in a circle around the center of the first contact structure 220 (or the predetermined position of the first contact structure 220). At least a portion of the bumps 241 is coupled to the first connection structure 210. Figure 5 All the bumps 241 shown land on the top of the first connection structure 210 and are in contact and coupled with the first connection structure 210. Compared with a solid, overall cylindrical contact structure, the bumps 241 arranged at intervals are conducive to dispersing stress and reducing the difference in thermal expansion coefficients between the bumps 241 and other materials that causes deformation of the bumps 241 or cracking of the structure.

[0035] It can be understood that the multiple bumps 241 arranged at intervals are beneficial to reducing the filling amount of conductive materials such as copper, and reducing the stress concentration caused by the thermal strain of copper and the resulting structural deformation and damage; for example, when thermally strained and deformed in the x direction, there is a buffer and deformation space between the bumps 241 arranged at intervals, so as not to affect the deformation of the overall contact structure; in the thermal strain deformation in the z direction, the bumps 241 do not affect each other, thereby reducing the stress concentration in the z direction to reduce the delamination and rupture of the film layer.

[0036] In some embodiments, a dielectric material may be formed on the first connection structure 210, and the dielectric material may be etched to form a plurality of through holes penetrating the dielectric material, wherein the through holes expose the top of the first connection structure 210; a conductive material may be filled in the through holes to form a bump 241, and the bump 241 is coupled to the first connection structure 210; no through holes may be formed in the area where the dielectric material is not aligned with or does not correspond to the first connection structure 210; when the arrangement density of the through holes is increasing and the size of the through holes is decreasing to improve the conductive performance of the first contact structure 220, the difficulty of etching the openings is increasing. In some other embodiments, an insulating film having a plurality of through holes may be attached to the first connection structure 210, and the through holes of the insulating film may be nanometer-scale. The insulating film serves as a template for the formation of the bump 241, and may shield the area where the insulating film does not correspond to the first connection structure 210. The conductive material may be filled in the through holes that expose the first connection structure 210 to form the bump 241, which may reduce the etching pressure and expand the manufacturing process window.

[0037] In some embodiments, the semiconductor structure 20 further includes: a first insulating film 261 having a plurality of through holes, as described below. Fig.12 The first opening 21 shown in the example; part of the first opening 21 corresponds to the first end of the first connection structure 210 in the thickness direction; the bump 241 is arranged in the first opening 21 corresponding to the first connection structure 210. The first insulating film 261 can be arranged on the first connection structure 210 by hot pressing or adhesive, or on the semiconductor layer 200 provided with the first connection structure 210, the first insulating film 261 covers the semiconductor layer 200 and the first connection structure 210, and the first insulating film 261 has a plurality of first openings 21; the first insulating film 261 area corresponding to or not corresponding to the first connection structure 210 has the first openings 21 arranged at intervals. The first insulating film 261 may include a polymer material, such as polycarbonate or polyurethane, with a pore size of 0 to 10 nanometers.

[0038] A first dielectric layer 262 is disposed on the first insulating film 261, and the first dielectric layer 262 is etched to form a Fig.14The second opening 22 in the example is aligned with or corresponds to the first connection structure 210 in the z direction, the size or diameter of the second opening 22 in the x direction is larger than the size of the top of the first connection structure 210 in the x direction to fully expose the top of the first connection structure 210, and the first dielectric layer 262 removes part of the second opening 22 to block or fill the first opening 21 of the first insulating film 261 that does not correspond to the first connection structure 210. The second opening 22 exposes a plurality of first openings 21 corresponding to the first connection structure 210, the second opening 22 is connected to the plurality of first openings 21 exposed by the second opening 22, and the second opening 22 exposes the top of the first connection structure 210 through the first opening 21. A plurality of bumps 241 are formed by filling the first opening 21 with conductive material through the second opening 22. The plurality of bumps 241 can form a bump 241 array. The plurality of bumps 241 are in contact and coupled with the first connection structure 210, that is, one first connection structure 210 is coupled with a plurality of bumps 241 arranged at intervals. The first opening 21 that does not correspond to the first connection structure 210 does not form a bump 241 because it is blocked by the first dielectric layer 262, thereby reducing leakage and interference. In some embodiments, part of the material of the first dielectric layer 262 is filled into the first opening 21, and when the second opening 22 is formed, the dielectric material in the first opening 21 can be removed to release the first opening 21.

[0039] In some embodiments, the semiconductor structure 20 further includes: a first dielectric layer 262, covering a plurality of bumps 241; the first contact structure 220 further includes: a second connection structure 230, located at one end of the bump 241 away from the first connection structure 210, and the second connection structure 230 penetrates the first dielectric layer 262; the second connection structure 230 at least includes a first sub-connection structure 231a and a second sub-connection structure 231b extending in the thickness direction, and a gap 232 is provided between the first sub-connection structure 231a and the second sub-connection structure 231b; the plurality of spaced bumps 241 at least include a first bump 241a and a second bump 241b; the first sub-connection structure 231a contacts the first bump 241a, and the second sub-connection structure 231b contacts the second bump 241b. The size of the bump 241 and the sub-connection structure in the x or y direction is nanometer-level, such as 0-10 nanometers. The first sub-connection structure 231a is adjacent to or not adjacent to the second sub-connection structure 231b.

[0040] For example, the bump 241 can be used as a seed layer for electroplating to form a second connection structure 230; the second connection structure 230 is located on the bump 241 and is formed in the second opening 22 of the first dielectric layer 262 that exposes the bump 241. The electroplating process parameters are adjusted, including the concentration of the plating solution, the electroplating time, and the electroplating voltage / current, to guide the second connection structure 230 to form a gap 232 in the second opening 22. The second connection structure 230 has a linear or columnar structure extending along the z direction, such as a nanowire nanocolumn structure. For example, the first sub-connection structure 231a and the second sub-connection structure 231b are used as examples. There is a gap 232 between the first sub-connection structure 231a and the second sub-connection structure 231b. The first sub-connection structure 231a and the second sub-connection structure 231b may not be in contact or may be in contact in some areas to form the gap 232. The first sub-connection structure 231a can be formed by electroplating growth or electroplating deposition of the first bump 241a as a seed layer, and the first sub-connection structure 231a is coupled to the first bump 241a; the second sub-connection structure 231b can be formed by electroplating growth or electroplating deposition of the second bump 241b as a seed layer, and the second sub-connection structure 231b is coupled to the second bump 241b. The disclosed embodiment does not limit the number of sub-connection structures, the number of bumps 241, or the specific shape of the gap 232; the sub-connection structure and the bump 241 are made of the same material and can be formed in the same electroplating process, or the bump 241 is formed by physical deposition or chemical deposition, and the sub-connection structure is formed by an electroplating process; there is no obvious physical boundary between the sub-connection structure and the bump 241, and they can be recorded as components of the first contact structure 220.

[0041] In some embodiments, the first sub-connection structure 231 a is partially in contact with the second sub-connection structure 231 b . Figure 5 The schematic diagram of the sub-connection structure in the figure is an ideal schematic diagram. In the specific embodiment, some sub-connection structures of the second connection structure 230 may be in contact in some areas to form gaps 232 of various shapes. The formation position of the gaps 232 may not be restricted; some linear or columnar sub-connection structures are in contact without boundaries, but not all sub-connection structures are in contact, and some areas are gaps 232. In some embodiments, the second connection structure 230 is a conductive column extending in the z direction as a whole, and there is a gap 232 inside the conductive column. The gap 232 may be an irregular linear gap extending in the z direction or in a direction having an angle with the z direction. In some embodiments, the cross-section of the second connection structure 230 in the xoz plane is schematically shown as a multi-layer structure in the x direction, with gaps 232 between layers, and the layers may be partially in contact with each other, and the contact position may be close to the bump 241 in the z direction.

[0042] In some embodiments, taking the first sub-connection structure 231a as an example, when formed using an electroplating process, the first sub-connection structure 231a may include a plurality of linear structures extending or diverging away from the first connection structure 210 with the first bump 241a as a base point, and the plurality of linear structures extend away from the first connection structure 210 with the first bump 241a as a starting point and fan-shape diverge in the x-direction to form a gap 232, and the plurality of linear structures may be partially in contact.

[0043] The gap 232 in the second connection structure 230 can provide a buffer space when heated to reduce deformation and film peeling; when stress in the x-direction or z-direction is generated due to heat, the second connection structure 230 deforms inward along the x-direction to disperse the stress, reducing film rupture caused by stress concentration.

[0044] In some embodiments, reference Figure 5 As shown, the semiconductor structure 20 further includes: a first barrier layer 263, located between the second connection structure 230 and the first dielectric layer 262; the first barrier layer 263 surrounds the sidewalls of the second connection structure 230 extending in the thickness direction. The constituent materials of the first barrier layer 263 may include but are not limited to metal nitrides, may include but are not limited to: titanium nitride, tantalum nitride, chromium nitride, aluminum nitride, tungsten nitride or a combination thereof, and may also include silicon nitride, etc.; the first barrier layer 263 may be a single-layer film layer or a multi-layer film layer, such as a composite film layer of tantalum nitride and silicon nitride, or tantalum nitride and silicon oxide. The first barrier layer 263 can be used to block the diffusion of metal elements in the second connection structure 230 into the dielectric layer, thereby reducing leakage and pollution.

[0045] In some embodiments, reference Figure 5As shown, the semiconductor structure 20 further includes: a connection layer 264, located between the first connection structure 210 and the semiconductor layer 200; the connection layer 264 surrounds the sidewalls of the first connection structure 210 extending in the thickness direction. The connection layer 264 can be an insulating material or a conductive material. The connection layer 264 can only surround the sidewalls of the first connection structure 210 extending in the z direction, or also surround the bottom of the first connection structure 210; a dielectric layer isolation such as silicon oxide or silicon nitride can be set between the connection layer 264 and the semiconductor layer 200 to reduce leakage. The connection layer 264 can include but is not limited to: titanium nitride, tantalum nitride, chromium nitride, aluminum nitride, tungsten nitride or a combination thereof. The connection layer 264 is used to increase the bonding force between the first connection structure 210 and the semiconductor layer 200, reduce film cracking, and also reduce leakage from the first connection structure 210 to the semiconductor layer 200. In some embodiments, the connection layer 264 may include photoresist, specifically cured photoresist; the photoresist may have a certain elasticity, and while improving the bonding force between the first connection structure 210 and the semiconductor layer 200 and reducing leakage, it may also provide a certain deformation buffer, and absorb the stress generated by thermal strain to reduce deformation and cracking. The photoresist may also facilitate the use of photolithography to remove the non-retained portion, and retain the portion as the connection layer 264, so as to facilitate the control of the thickness of the connection layer 264 and the expansion of the manufacturing process window. For example, the connection layer 264 may be a multi-layer structure to optimize electrical isolation and reduce stress concentration performance, such as a multi-layer structure of tantalum nitride and photoresist.

[0046] In some embodiments, reference Figure 5 As shown, the semiconductor structure 20 further includes: a first contact 251 located on a side of the second connection structure 230 away from the first connection structure 210 ; the first contact 251 is coupled to the second connection structure 230 .

[0047] The semiconductor structure 20 also includes other device structures not shown, which may include but are not limited to logic control circuits composed of various transistors, volatile or non-volatile storage structures, including but not limited to NAND flash memory, dynamic random access memory unit DRAM, including but not limited to radio frequency circuits, etc., including but not limited to various wiring layers, conductive plugs, etc. For example, there may be a dielectric material between the semiconductor layer 200 and the first insulating film 261, or there may be a device structure in the dielectric material; or there may be a device structure on the side of the semiconductor layer 200 away from the first contact structure 220, and part of the device structure may be arranged in the semiconductor layer 200, such as including the source, drain and channel of the transistor. The first connection structure 210 can be coupled with each interconnection layer of the semiconductor structure 20 to lead out electrical signals; the first contact 251 can be used as a contact pad, a contact bump, or a bonding pad, which is used to connect with an external integrated circuit for power supply, control signal interaction or data transmission. Exemplarily, the first contact 251 can be used as an IO pad; or as a bonding pad for bonding with other semiconductor structures for electrical signal interconnection, or as a contact point to adapt leads or conductive bumps (such as solder balls, conductive balls, etc.) to other semiconductor structures for electrical signal interconnection, or to couple with a packaging substrate or a silicon interposer.

[0048] In some embodiments, reference Figure 6 As shown, the semiconductor structure 20 also includes: a second contact structure 270, located at the second end of the first connection structure 210 away from the first contact structure 220 in the thickness direction; the second contact structure 270 is coupled to the second end of the first connection structure 210; a second contact 252, located on a side of the second contact structure 270 away from the first connection structure 210; the second contact 252 is coupled to the second contact structure 270. Figure 6 The first connection structure 210 shown penetrates the semiconductor layer 200 along the z direction, and a first contact structure 220 and a first contact 251 are arranged at the upper end (first end) of the first connection structure 210 in the z direction, and a second contact structure 270 and a second contact 252 are arranged at the lower end (second end) of the second connection structure 230; the specific structure of the second contact structure 270 can refer to the first contact structure 220, and the second contact structure 270 may include a plurality of bumps 241 contact-coupled with the first connection structure 210, and a sub-connection structure coupled with the bumps 241, the bumps 241 of the second contact structure 270 may be arranged in the openings of the second insulating film 265, and the sub-connection structure of the second contact structure 270 is arranged in the second dielectric layer 266 and penetrates the second dielectric layer 266. The first contact 251, the first contact structure 220, the first connection structure 210, the second contact structure 270 and the second contact 252 can form a conductive channel 201 in the z direction, which can lead the electrical signal of the semiconductor structure 20 to the upper and lower surfaces; Figure 6When multiple semiconductor structures 20 are stacked, the contacts are used for electrical signal interconnection between the semiconductor structures 20; when multiple semiconductor structures 20 are stacked, the contacts can be used for direct bonding, or a conductive bump can be set between two contacts for coupling. In some embodiments, a device structure may be provided between the first insulating film 261 and the semiconductor layer 200, or a device structure may be provided between the second insulating film 265 and the semiconductor layer 200, a portion of the device structure may be provided in the semiconductor layer 200, and the conductive channel 201 leads the electrical signal of the device structure to realize electrical signal interconnection of multiple semiconductor structures 20 in the z direction.

[0049] In some embodiments, Figure 6 The semiconductor layer 200 may be a packaging substrate, or an interposer, which may include but is not limited to a silicon interposer; some semiconductor structures or semiconductor chips may be located on one side of the first contact 251 and coupled to the first contact 251, or may be located on one side of the second contact 252 and coupled to the second contact 252, and the device structures on both sides of the semiconductor layer 200 are interconnected by electrical signals through the conductive channel 201.

[0050] According to some aspects of the embodiments of the present disclosure, Figure 7 A method for manufacturing a semiconductor structure 20 is provided, comprising: providing a semiconductor layer; forming a first connection structure that penetrates at least part of the thickness of the semiconductor layer; attaching a first insulating film having a plurality of first openings on the first connection structure, wherein part of the first openings expose the first end of the first connection structure in the thickness direction; forming a first dielectric layer on the first insulating film, and forming second openings that penetrate the first dielectric layer; the second openings expose a plurality of the first openings, wherein the second openings expose the first connection structure through the plurality of the first openings; filling the first openings and the second openings with a conductive material to form a first contact structure; and coupling the first contact structure to the first end of the first connection structure.

[0051] Reference Figure 8As shown, a semiconductor layer 200 is provided, or a semiconductor structure 20 having a semiconductor layer 200 is provided. The semiconductor structure 20 also has a device structure not shown. The semiconductor structure 20 may be an intermediate product after executing some manufacturing processes rather than a final product, and may be an intermediate state in a certain manufacturing step; the semiconductor layer 200 is etched to form an opening extending in the semiconductor layer 200. The opening may penetrate a portion of the thickness of the semiconductor layer 200. The back side may be thinned later to allow the opening to penetrate the entire semiconductor layer 200, or the opening may penetrate the entire semiconductor layer 200; the opening is filled with a conductive material to form a first connection structure 210. Alternatively, a connection layer 264 may be formed on the sidewall of the opening, and a first connection structure 210 may be formed in the opening having the connection layer 264. The connection layer 264 is located between the semiconductor layer 200 and the first connection structure 210. The connection layer 264 may increase the adhesion between the semiconductor layer 200 and the first connection structure 210 to reduce the gap between the film layers. The opening may be Figure 8 The third opening 23 shown, the first opening 21, the second opening 22 and the third opening 23 in the embodiment of the present disclosure are only used to distinguish the openings formed in different steps, and do not limit the shape, number and formation order of the openings.

[0052] In some embodiments, the method of forming the first connection structure 210 includes: referring to Figure 8 As shown, the semiconductor layer 200 is etched to form a third opening 23 that penetrates at least a portion of the thickness of the semiconductor layer 200; Fig. 9 As shown, the third opening 23 is filled with photoresist; Fig.10 As shown, part of the photoresist in the third opening 23 is removed to form a connecting layer 264 on the sidewall of the third opening 23; Fig.11 As shown, the first connection structure 210 is formed in the third opening 23 having the connection layer 264 , and the formation process of the first connection structure 210 may include a deposition process or an electroplating process.

[0053] Fig. 9 In the process, a photoresist is spin-coated on the wafer including the semiconductor layer 200 and cured, and the photoresist is filled into the third opening 23; Fig.10 In the process, the third opening 23 is aligned with the photolithography and development, and a part of the photoresist is removed by cleaning, and the photoresist on the side wall of the third opening 23 is retained to form a connection layer 264. Fig.10 In the embodiment, the photoresist at the bottom of the third opening 23 can be removed after development, or when the other side of the semiconductor layer 200 is thinned. Compared with depositing the connection layer 264 in the third opening 23, the barrier layer including the photoresist is formed in combination with the photolithography process, and the thickness of the barrier layer in the x direction can be controlled by the photolithography process, which is beneficial to improve the morphology uniformity of the first connection structure 210 and improve the manufacturing yield.

[0054] In some other embodiments, a barrier layer may be deposited (e.g., atomic layer deposition) on the sidewalls and / or bottom of the third opening 23, and may include but is not limited to titanium nitride, tantalum nitride, chromium nitride, aluminum nitride, tungsten nitride, or a combination thereof, and may include a conductive material or an insulating material.

[0055] In some embodiments, due to the loading effect of etching, Figure 8 The dimension of the opening end of the third opening 23 in the x direction may be larger than the dimension of the bottom; Fig.11 The size of the top of the first connection structure 210 formed in the x or y direction may be larger than the size of the bottom in the x or y direction, that is, the size of the first end of the first connection structure 210 in the x or y direction may be larger than the size of the second end in the x or y direction.

[0056] In some embodiments, reference Fig.12 As shown, a first insulating film 261 having a plurality of first openings 21 is attached to a semiconductor layer 200 having a first connecting structure 210, and the attaching process may include but is not limited to hot pressing or gluing; the first insulating film 261 has a plurality of first openings 21, which may be arranged in an array; some of the first openings 21 of the first insulating film 261 expose the top (first end) of the first connecting structure 210 in the z direction, and another part of the first openings 21 may expose the semiconductor layer 200.

[0057] In some embodiments, reference Fig.13 As shown, a first dielectric layer 262 is deposited on the first insulating film 261, which may include but is not limited to silicon oxide, silicon nitride, silicon oxynitride, or an attached insulating film such as a polymer material film; the first dielectric layer 262 may fill the first opening 21 of the first insulating film 261 or not fill the first opening 21. Fig.14 As shown, the position of the first dielectric layer 262 corresponding to the first connection structure 210 is etched to form a second opening 22 penetrating the first dielectric layer 262, and the second opening 22 reveals a plurality of first openings 21. The second opening 22 corresponds to the first connection structure 210 and the second opening 22 reveals the first connection structure 210 through the plurality of first openings 21, that is, one second opening 22 corresponds to a plurality of first openings 21, and one first connection structure 210 is correspondingly revealed; the first opening 21 not corresponding to the first connection structure 210 is blocked or filled by the first dielectric layer 262. In some embodiments, part of the material of the first dielectric layer 262 is filled into the first opening 21, and when the second opening 22 is formed, the dielectric material in the first opening 21 can be removed to release the first opening 21.

[0058] Reference Fig.15As shown, the first opening 21 and the second opening 22 are filled with a conductive material to form a first contact structure 220, and the first contact structure 220 is coupled to the top of the first connection structure 210. The first contact structure 220 may include a plurality of bumps 241 located in the plurality of first openings 21, and a second connection structure 230 located in the second opening 22. The bumps 241 and the second connection structure 230 may be formed in the same process, such as an electroplating process, or the bumps 241 may be formed using a deposition process, and the second connection structure 230 is formed by electroplating using the bumps 241 as a seed layer.

[0059] In some embodiments, reference Fig.15 As shown, the method for forming the first contact structure 220 includes: forming a plurality of bumps 241 in a plurality of first openings 21 of a first insulating film 261, and forming a second connection structure 230 in a second opening 22; the second connection structure 230 includes at least a first sub-connection structure 231a and a second sub-connection structure 231b extending in a thickness direction, and a gap 232 is provided between the first sub-connection structure 231a and the second sub-connection structure 231b; the plurality of spaced bumps 241 include at least a first bump 241a and a second bump 241b; the first sub-connection structure 231a contacts the first bump 241a, and the second sub-connection structure 231b contacts the second bump 241b.

[0060] For example, the bump 241 can be used as a seed layer for electroplating to form the second connection structure 230; the second connection structure 230 is located on the bump 241 and is formed in the second opening 22 of the first dielectric layer 262 where the bump 241 is exposed. The electroplating process parameters, including the concentration of the electroplating solution, the electroplating time, and the electroplating voltage / current, are adjusted to guide the second connection structure 230 to form a gap 232 in the second opening 22. The second connection structure 230 has a linear or columnar structure extending along the z direction, such as a nanowire nanocolumnar structure. For example, taking the first sub-connection structure 231a and the second sub-connection structure 231b as an example, there is a gap 232 between the first sub-connection structure 231a and the second sub-connection structure 231b, and the first sub-connection structure 231a and the second sub-connection structure 231b may not be in contact or may be in contact in some areas to form the gap 232. The first sub-connection structure 231a can be formed by electroplating growth or electroplating deposition of the first bump 241a as a seed layer, and the first sub-connection structure 231a is coupled to the first bump 241a; the second sub-connection structure 231b can be formed by electroplating growth or electroplating deposition of the second bump 241b as a seed layer, and the second sub-connection structure 231b is coupled to the second bump 241b. The disclosed embodiment does not limit the number of sub-connection structures, the number of bumps 241, or the specific shape of the gap 232; the sub-connection structure and the bump 241 are made of the same material and can be formed in the same electroplating process, or the bump 241 is formed by physical deposition or chemical deposition, and the sub-connection structure is formed by an electroplating process; there is no obvious physical boundary between the sub-connection structure and the bump 241, and they can be recorded as components of the first contact structure 220.

[0061] Fig.15 The illustration of the sub-connection structure is an ideal illustration. In the specific embodiment, some sub-connection structures of the second connection structure 230 may be in contact with each other in some areas to form gaps 232 of various shapes, and the formation positions of the gaps 232 may not be restricted; some linear or columnar sub-connection structures are in contact without boundaries, but not all sub-connection structures are in contact with each other, and some areas are gaps 232.

[0062] In some embodiments, the manufacturing method further comprises: referring to Fig.15As shown, a first barrier layer 263 is formed on the sidewall of the second opening 22, and the first barrier layer 263 surrounds the sidewall of the second connection structure 230 extending in the thickness direction. The first barrier layer 263 is located between the second connection structure 230 and the first dielectric layer 262; the first barrier layer 263 surrounds the sidewall of the second connection structure 230 extending in the z direction. The first barrier layer 263 can be a single-layer film layer or a multi-layer film layer, such as a composite film layer of tantalum nitride and silicon nitride, or tantalum nitride and silicon oxide. The first barrier layer 263 is used to prevent the metal elements in the second connection structure 230 from diffusing into the dielectric layer to reduce leakage.

[0063] In some embodiments, the manufacturing method further comprises: referring to Fig.16 As shown, a first contact 251 is formed on a side of the second connection structure 230 away from the first connection structure 210; the first contact 251 is coupled to the second connection structure 230. Fig.15 A dielectric material is formed on the second connection structure 230 of the first contact structure 220, or on the first dielectric layer 262 having the second connection structure 230, the dielectric material is etched to form a groove that penetrates the dielectric material and exposes the second connection structure 230, and the groove is filled with a conductive material to form a first contact 251. The first contact 251 may include, but is not limited to, conductive materials such as copper, aluminum, tungsten, gold, silver, platinum, chromium, nickel, cobalt, and titanium; for example, copper and aluminum may be included to reduce manufacturing costs. The first contact 251 may be used as a contact pad, a contact bump, or a bonding pad, and is used to connect to an external integrated circuit for power supply, control signal interaction, or data transmission.

[0064] In some embodiments, Fig.16 The first connection structure 210 penetrates a portion of the thickness of the semiconductor layer 200, and the manufacturing method further includes: referring to Fig.17 As shown, the side of the semiconductor layer 200 away from the first contact 251 is thinned to expose the second end of the first connection structure 210 in the thickness direction, so that the first connection structure 210 penetrates the semiconductor layer 200; Fig.16 The semiconductor structure 20 in the embodiment is flipped to expose the surface of the semiconductor layer 200 away from the first contact 251, which is recorded as the back side; the back side of the semiconductor layer 200 is thinned to expose the second end ( Fig.16 The bottom of the first connection structure 210), the barrier layer or the connection layer 264 at the end of the first connection structure 210 may be removed during thinning, and the thinning process may include but is not limited to etching, or chemical mechanical grinding or a combination thereof; Figure 6As shown, a second contact structure 270 is formed on the second end of the first connection structure 210, and the second contact structure 270 is coupled to the second end of the first connection structure 210; a second contact point 252 is formed on the second contact structure 270, and the second contact point 252 is coupled to the second contact structure 270. The formation process and structure of the second contact structure 270 can refer to the first contact structure 220, and the formation process and structure of the second contact point 252 can refer to the first contact point 251, which will not be repeated.

[0065] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: Semiconductor layer; A first connecting structure, penetrating the semiconductor layer; The first contact structure is located at the first end of the first connection structure in the thickness direction; the first contact structure includes a plurality of protrusions arranged at intervals, and the protrusions are coupled to the first end of the first connection structure.

2. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: The first insulating film has a plurality of first openings; some of the first openings correspond to the first ends of the first connecting structures in the thickness direction; and the bumps are arranged in the first openings corresponding to the first connecting structures.

3. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: A first dielectric layer covers the plurality of bumps; the first contact structure further comprises: A second connection structure is located at an end of the bump away from the first connection structure, and the second connection structure penetrates the first dielectric layer; the second connection structure at least includes a first sub-connection structure and a second sub-connection structure extending in the thickness direction, and there is a gap between the first sub-connection structure and the second sub-connection structure; The plurality of spaced-apart bumps include at least a first bump and a second bump; the first sub-connection structure contacts the first bump, and the second sub-connection structure contacts the second bump.

4. The semiconductor structure according to claim 3, characterized in that: The first sub-connection structure is in partial contact with the second sub-connection structure.

5. The semiconductor structure according to claim 3, characterized in that: The semiconductor structure further comprises: The first barrier layer is located between the second connection structure and the first dielectric layer; the first barrier layer surrounds the side wall of the second connection structure extending along the thickness direction.

6. The semiconductor structure according to claim 1, characterized in that The semiconductor structure further comprises: The connection layer is located between the first connection structure and the semiconductor layer; the connection layer surrounds the side wall of the first connection structure extending along the thickness direction.

7. The semiconductor structure according to claim 3, characterized in that: The semiconductor structure further comprises: The first contact point is located at a side of the second connection structure away from the first connection structure; the first contact point is coupled to the second connection structure.

8. The semiconductor structure according to claim 7, characterized in that: The semiconductor structure further comprises: A second contact structure is located at a second end of the first connection structure away from the first contact structure in a thickness direction; the second contact structure is coupled to the second end of the first connection structure; The second contact point is located at a side of the second contact structure away from the first connection structure; the second contact point is coupled to the second contact structure.

9. A method for manufacturing a semiconductor structure, characterized in that: include: providing a semiconductor layer; forming a first connection structure penetrating at least a portion of the thickness of the semiconductor layer; A first insulating film having a plurality of first openings is attached to the first connecting structure, wherein a portion of the first openings exposes a first end of the first connecting structure in a thickness direction; forming a first dielectric layer on the first insulating film, and forming a second opening penetrating the first dielectric layer; the second opening exposes a plurality of the first openings, and the second opening exposes the first connection structure through the plurality of the first openings; The first opening and the second opening are filled with a conductive material to form a first contact structure; the first contact structure is coupled to the first end of the first connection structure.

10. The manufacturing method according to claim 9, characterized in that: The method of forming the first contact structure includes: A plurality of bumps are formed in the plurality of first openings of the first insulating film, and a second connection structure is formed in the second opening; the second connection structure includes at least a first sub-connection structure and a second sub-connection structure extending in the thickness direction, and a gap is provided between the first sub-connection structure and the second sub-connection structure; the plurality of spaced bumps include at least a first bump and a second bump; the first sub-connection structure contacts the first bump, and the second sub-connection structure contacts the second bump.

11. The manufacturing method according to claim 10, characterized in that: The method of forming the first connection structure includes: Etching the semiconductor layer to form a third opening penetrating at least a portion of the thickness of the semiconductor layer; Filling the third opening with photoresist, and removing part of the photoresist in the third opening to form a connecting layer on the sidewall of the third opening; The first connection structure is formed in the third opening having the connection layer.

12. The manufacturing method according to claim 10, characterized in that: The production method further comprises: A first barrier layer is formed on the sidewall of the second opening, and the first barrier layer surrounds the sidewall of the second connection structure extending along the thickness direction.

13. The manufacturing method according to claim 10, characterized in that: The production method further comprises: A first contact is formed on a side of the second connection structure away from the first connection structure; the first contact is coupled to the second connection structure.

14. The manufacturing method according to claim 13, characterized in that: The first connection structure penetrates a portion of the thickness of the semiconductor layer, and the manufacturing method further includes: Thinning a side of the semiconductor layer away from the first contact to expose a second end of the first connection structure in a thickness direction, so that the first connection structure penetrates the semiconductor layer; forming a second contact structure on the second end of the first connecting structure, wherein the second contact structure is coupled to the second end of the first connecting structure; A second contact is formed on the second contact structure, and the second contact is coupled to the second contact structure.

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