Restraining circuit for starting peak of synchronous rectification MOS in Flyback power supply

Abstract

The invention provides a synchronous rectification MOS starting peak suppression circuit in a Flyback flyback power supply, which relates to the technical field of suppression circuits and comprises an input terminal, an auxiliary switch tube Q4, resistors R6 and R9, a high-frequency transformer T2, a load resistor R7, a capacitor C5, a live wire input end L2 and a zero line input end N2. The input end of the rectifier bridge BD2 is connected with the live wire input end L2 and the null line input end N2, and the rectifier bridge BD2 is used for converting input alternating current into direct current; according to the circuit, a PNP triode, a diode and a resistor are additionally arranged on a Gate of a synchronous rectification MOS (Metal Oxide Semiconductor) in the circuit with synchronous rectification at the secondary side of a power supply, a peak coupled to the Gate of the synchronous rectification MOS at the starting moment can be often seen, the MOS is mistakenly started due to the peak, and the synchronous rectification MOS is burnt, so that the synchronous rectification MOS is burnt out due to the fact that the PNP triode, the diode and the resistor are additionally arranged on the Gate of the synchronous rectification in the circuit. When the power supply works normally, the Gate peak suppression circuit is used for suppressing the Gate peak at the start-up moment, but the Gate is not clamped when the power supply works normally, so that the aim of suppressing the start-up moment peak is fulfilled.

Description

Technical Field

[0001] The present invention belongs to the technical field of suppression circuits, and more specifically, particularly relates to a suppression circuit for a startup spike of a synchronous rectification MOS in a flyback flyback power supply. Background Art

[0002] In the circuit with synchronous rectification on the secondary side of the power supply, it is often seen that at the moment of power-on, there is a spike coupled to the Gate of the synchronous rectification MOS. This spike will cause the MOS to start incorrectly, thereby burning the power supply and causing significant property losses. Based on practice and experiments, this article designs a circuit or method to suppress the startup spike. Summary of the invention

[0003] In order to solve the above technical problems, the present invention provides a circuit for suppressing a startup spike of a synchronous rectifier MOS in a Flyback flyback power supply to solve the above problems.

[0004] A circuit for suppressing a startup spike of a synchronous rectifier MOS in a flyback flyback power supply comprises an input terminal, an auxiliary switch tube Q4, resistors R6, R9, a high-frequency transformer T2, a load resistor R7 and a capacitor C5, including a live input terminal L2 and a neutral input terminal N2; a rectifier bridge BD2, whose input end is connected to the live input terminal L2 and the neutral input terminal N2, and is used to convert input alternating current into direct current; a first filter capacitor C6, connected to the output end of the rectifier bridge BD2, and is used to filter the rectified direct current; a power switch tube Q5, one end of which is connected to a filtered direct current power supply, and the power switch tube Q5 is controlled by a PWM driver; an output rectifier diode, comprising D3 and D4; and a second filter capacitor, comprising C7 and C8.

[0005] Preferably, the primary winding of the high-frequency transformer T2 is connected to the other end of the power switch tube Q5, the output rectifier diode is connected to the secondary winding of the high-frequency transformer T2, and is used to convert the alternating current output by the secondary winding of the transformer into direct current, and the second filter capacitor is connected to the output rectifier diode, and is used to filter the output direct current.

[0006] Preferably, the load resistor R7 is connected to the second filter capacitor for stabilizing the output voltage. The circuit has an output terminal Vout for providing a regulated and filtered DC voltage. The auxiliary switch tube Q4 is connected to the secondary winding of the high-frequency transformer T2. The auxiliary switch tube Q4 is controlled by a synchronous rectification driver SRDriver for synchronous rectification operation.

[0007] Preferably, the auxiliary switch tube Q4 has an input capacitor Ciss and a reverse transfer capacitor Crss, which are used to control the switching speed and reduce electromagnetic interference. The resistor R6 is connected between the power switch tube Q5 and the PWM driver. The resistor R9 is connected between the output rectifier diode D4 and the ground GND for current limiting or voltage detection. The capacitor C5 is connected to the secondary winding of the high-frequency transformer T2 for filtering or auxiliary functions.

[0008] Compared with the prior art, the present invention has the following beneficial effects:

[0009] In the present invention, the voltage spike of the gate coupling of the secondary synchronous rectification MOS at the moment of power-on is effectively suppressed and eliminated, thereby avoiding the risk of machine explosion or power supply damage at the moment of power-on.

[0010] In the present invention, the startup stability and reliability of the Flyback flyback power supply are significantly improved, the risk of a sharp increase in current and device damage caused by mis-conduction of the secondary MOS at the startup moment is effectively avoided, and the normal startup of the power supply is ensured.

[0011] In the present invention, by eliminating the voltage spike of the secondary synchronous rectification MOS at the moment of startup, the probability of power supply being damaged due to startup failure is reduced, the cost of repairing and replacing components is reduced, and the service life and economic benefit of the power supply are improved.

[0012] In the present invention, the stability and safety of the flyback power supply under various working conditions are ensured, the adaptability of the power supply to different loads and environments is enhanced, and a continuous, stable and reliable power supply is provided for related equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a traditional schematic diagram without circuits;

[0014] Figure 2 It is a complete circuit diagram of the present invention. DETAILED DESCRIPTION

[0015] The following embodiments of the present invention are described in further detail in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0016] See also Figure 1-Figure 2The present invention provides a circuit for suppressing a startup spike of a synchronous rectifier MOS in a Flyback flyback power supply, comprising an input terminal, an auxiliary switch tube Q4, resistors R6, R9, a high-frequency transformer T2, a load resistor R7 and a capacitor C5, including a live input terminal L2 and a neutral input terminal N2; a rectifier bridge BD2, whose input end is connected to the live input terminal L2 and the neutral input terminal N2, and is used to convert the input alternating current into direct current; a first filter capacitor C6, connected to the output end of the rectifier bridge BD2, and is used to filter the rectified direct current; a power switch tube Q5, one end of which is connected to a filtered direct current power supply, and the power switch tube Q5 is controlled by a PWM driver; an output rectifier diode, including D3 and D4; and a second filter capacitor, including C7 and C8.

[0017] The high-frequency transformer T2 has its primary winding connected to the other end of the power switch tube Q5, and the output rectifier diode is connected to the secondary winding of the high-frequency transformer T2, which is used to convert the AC power output by the secondary winding of the transformer into DC power. The second filter capacitor is connected to the output rectifier diode, which is used to filter the output DC power.

[0018] The load resistor R7 is connected to the second filter capacitor for stabilizing the output voltage. The circuit has an output terminal Vout for providing a regulated and filtered DC voltage. The auxiliary switch tube Q4 is connected to the secondary winding of the high-frequency transformer T2. The auxiliary switch tube Q4 is controlled by the synchronous rectification driver SRDriver for synchronous rectification operation.

[0019] The auxiliary switch tube Q4 has an input capacitor Ciss and a reverse transfer capacitor Crss, which are used to control the switching speed and reduce electromagnetic interference. The resistor R6 is connected between the power switch tube Q5 and the PWM driver. The resistor R9 is connected between the output rectifier diode D4 and the ground GND for current limiting or voltage detection. The capacitor C5 is connected to the secondary winding of the high-frequency transformer T2 for filtering or auxiliary functions.

[0020] Working principle:

[0021] In the first step, the AC power supply is input through L2 and N2, and becomes DC after being rectified by the rectifier bridge BD2. The rectified DC voltage is filtered by the filter capacitor C6 to reduce voltage fluctuations. The PWM driver controls the switching operation of the power switch tube Q5. When Q5 is turned on, the current passes through the primary winding of the transformer T2 to store energy. When Q5 is turned off, the current of the primary winding of the transformer T2 is interrupted, and the magnetic field energy is transferred to the secondary winding. It is rectified by the output rectifier diodes D3 and D4. The rectified output voltage is filtered by the filter capacitors C7 and C8 to obtain a stable DC output voltage. The PWM driver controls the output voltage by adjusting the switching frequency and duty cycle of Q5. The auxiliary switch tube Q4 performs synchronous rectification under the control of the SR driver to improve efficiency. Resistors R6, R9 and capacitor C5 are used for auxiliary functions such as current limiting, voltage detection and filtering.

[0022] In the second step, in the circuit with synchronous rectification on the secondary side of the power supply, it is often seen that at the moment of power-on, there is a spike coupled to the Gate of the synchronous rectification MOS. This spike will cause the MOS to start incorrectly, thereby burning the synchronous rectification MOS. The circuit adds a PNP transistor to the Gate of the synchronous rectification, plus a diode and a resistor, to suppress the Gate spike at the moment of power-on, but does not clamp the Gate when the power supply is working normally, thereby achieving the purpose of suppressing the spike at the moment of power-on.

[0023] The third step is that at the moment when the Flyback flyback power supply is turned on, because the primary PWM drive is turned on, the primary is turned on, and the secondary is turned off, there will be an instantaneous voltage on the DS of the secondary MOS. This instantaneous voltage is VIN / n+VOUT+switching instantaneous spike. Here n is the transformer turns ratio. Depending on the transformer turns ratio, output voltage and power, the actual measurement of this DS voltage may reach between 60V and 150V. At this time, because of the existence of Crss and Ciss of MOS, this DS instantaneous voltage will be coupled to the Gate through Crss and Ciss, resulting in the Gate voltage of 2-3V. The turn-on voltage of MOS is usually 1-3V, so it may cause MOS to turn on. In the flyback power supply, when the primary MOS is turned on, the secondary MOS is also turned on. At this moment, the primary current of the flyback power supply will increase sharply, which may burn the MOS. At this time, if the primary MOS is turned off, this excessive current will be added to the Coss capacitor of the primary MOS, which may also cause the DS of the primary MOS to be damaged by overvoltage. Almost all Flyback flyback circuits with synchronous rectification MOSFETs will have this risk;

[0024] In this circuit, a PNP transistor Q6, a diode D4 and a resistor R9 are added to the Gate of the synchronous rectifier chip. At the moment of power-on, when a spike is coupled to the Gate of the synchronous rectifier MOS Q4, because the synchronous rectifier chip is not powered on, the SRDriver terminal is grounded, and current flows through the base of the transistor Q6. Q6 works normally and will pull the Gate voltage of Q4 to the ground. At this time, the Gate voltage of Q4 is clamped to 0V, and Q4 will not be misled by the voltage coupled at power-on.

[0025] After the power-on is completed, when the power supply is working normally, the synchronous rectification chip is powered on and starts to work normally. The SR Driver end drive is high level. At this time, Q4 is normally driven to conduct through diode D4. Because the base voltage of Q6 is higher than the collector, Q6 does not work, and SR is normally turned on. When the SR Driver end drive is low level, current flows through the base of transistor Q6, and Q6 works normally, which will pull the Gate voltage of Q4 to the ground. At this time, the Gate voltage of Q4 is clamped to 0V. In this way, the normal operation of the SR chip is achieved, Q4 is driven at a normal high level, and Q4 is turned off at a low level, which effectively suppresses and eliminates the voltage spike of the Gate coupling of the secondary synchronous rectification MOS at the moment of power-on, avoiding the risk of machine explosion or power supply damage at the moment of power-on.

[0026] The effect of this circuit was tested with a DELL 65W notebook power supply. The synchronous rectification MOS was made of domestic SL006R100. Without this circuit, the Gate voltage spike of the secondary synchronous rectification was about 2.5V at the moment of power on. The synchronous rectification MOS was slightly mis-conducted, and the primary MOS stress was 656V, which is very dangerous. After adding this circuit, the measured Gate voltage was reduced to 0.3V, which is far lower than the MOS turn-on voltage and is almost completely clamped. The primary MOS stress is 580V. The experiment proves that this circuit has obvious effect.

[0027] The following are the test data of different types of synchronous rectification MOS:

[0028]

[0029]

[0030] Combined with the above data, 6 MOSFETs from different manufacturers are selected. The internal resistance and withstand voltage are exactly the same, but the difference is the ratio of Ciss and Coss. Different MOS junction capacitances are different, and they will be coupled to voltage spikes on the MOS Gate to varying degrees. No matter which MOS is selected, the coupling voltage at the moment of power on exists, but the coupling voltage is different. The VTH turn-on voltage of MOS is about 1.6V. If it is lower than the VTH turn-on voltage of MOS, there is no risk. If it is higher than the VTH turn-on voltage of MOS, there is a high risk. After adding the patented circuit in this article, the Gate coupling voltage is clamped to 0.3V by the circuit, which is much lower than the turn-on voltage VTH of MOS. The VTH turn-on voltage is about 1.6V. The actual measured data of this circuit in the experiment is consistent with the theoretical design, achieving the effect of eliminating spikes.

[0031] The embodiments of the present invention are given for the purpose of illustration and description, and are not intended to be exhaustive or to limit the invention to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments are selected and described in order to better illustrate the principles and practical applications of the present invention and to enable those of ordinary skill in the art to understand the present invention and thereby design various embodiments with various modifications suitable for specific uses.

Claims

1. A circuit for suppressing the startup spike of a synchronous rectifier MOS in a flyback power supply, characterized in that: It includes input terminals, auxiliary switch tube Q4, resistors R6, R9, high-frequency transformer T2, load resistor R7 and capacitor C5, including live input terminal L2 and neutral input terminal N2; A rectifier bridge BD2, whose input end is connected to the live line input end L2 and the neutral line input end N2, and is used to convert the input alternating current into direct current; A first filter capacitor C6 is connected to the output end of the rectifier bridge BD2 and is used to filter the rectified direct current; A power switch tube Q5, one end of which is connected to a filtered DC power supply, and the power switch tube Q5 is controlled by a PWM driver; Output rectifier diodes, including D3 and D4; The second filter capacitor includes C7 and C8.

2. A circuit for suppressing the startup spike of a synchronous rectifier MOS in a flyback power supply as claimed in claim 1, characterized in that: The primary winding of the high-frequency transformer T2 is connected to the other end of the power switch tube Q5.

3. The circuit for suppressing the startup spike of the synchronous rectifier MOS in the Flyback flyback power supply according to claim 1, characterized in that: The output rectifier diode is connected to the secondary winding of the high-frequency transformer T2 and is used to convert the alternating current output by the secondary winding of the transformer into direct current.

4. The circuit for suppressing the startup spike of the synchronous rectifier MOS in the flyback power supply according to claim 1, characterized in that: The second filter capacitor is connected to the output rectifier diode and is used for filtering the output direct current.

5. The circuit for suppressing the startup spike of the synchronous rectifier MOS in the flyback power supply according to claim 1, characterized in that: The load resistor R7 is connected to the second filter capacitor and is used to stabilize the output voltage.

6. A circuit for suppressing a startup spike of a synchronous rectifier MOS in a flyback power supply as claimed in claim 1, characterized in that: The circuit has an output terminal Vout for providing a regulated and filtered DC voltage.

7. A circuit for suppressing the startup spike of a synchronous rectifier MOS in a flyback power supply as claimed in claim 1, characterized in that: The auxiliary switch tube Q4 is connected to the secondary winding of the high-frequency transformer T2 , and the auxiliary switch tube Q4 is controlled by a synchronous rectification driver SRDriver for synchronous rectification operation.

8. A circuit for suppressing the startup spike of a synchronous rectifier MOS in a flyback power supply as claimed in claim 7, characterized in that: The auxiliary switch tube Q4 has an input capacitor Ciss and a reverse transfer capacitor Crss, which are used to control the switching speed and reduce electromagnetic interference.

9. The circuit for suppressing the startup spike of the synchronous rectifier MOS in the flyback power supply according to claim 1, characterized in that: The resistor R6 is connected between the power switch tube Q5 and the PWM driver, and the resistor R9 is connected between the output rectifier diode D4 and the ground GND, for current limiting or voltage detection.

10. The circuit for suppressing the startup spike of the synchronous rectifier MOS in the flyback power supply according to claim 1, characterized in that: The capacitor C5 is connected to the secondary winding of the high-frequency transformer T2 for filtering or auxiliary functions.

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