Discontinuous current type variable duty ratio output resonant gate drive circuit

Abstract

The invention discloses a discontinuous current type variable duty ratio output resonant gate drive circuit, and belongs to the field of power electronics. The resonant gate drive circuit comprises a PMOS (P-channel Metal Oxide Semiconductor) tube, two NMOS (N-channel Metal Oxide Semiconductor) tubes, an inductor L and a voltage stabilizing capacitor, the on-off states of the PMOS tube and the NMOS tubes are controlled by controlling the time sequence of gate drive signals of the PMOS tube and the NMOS tubes, and inductive current flowing through the inductor is in a discontinuous state. The resonant state of the inductor and the gate capacitor of the driven circuit and the duty ratio of the driving output voltage are further controlled. The inductive current of the circuit is discontinuous, the conduction loss of the circuit is greatly reduced, the grid driving energy recovery ratio is improved, and the duty ratio conversion of the driving signal can be realized by controlling the duty ratio of the driving signal. Therefore, the technical problems that the energy recovery rate is low, the number of control signals is large, signal matching is difficult, the occupied area is large, miniaturization is not facilitated, and the duty ratio cannot be adjusted in the driving technology are solved.

Description

Technical Field

[0001] The invention relates to the technical field of power electronics, and in particular to a resonant gate drive circuit with discontinuous current type variable duty ratio output. Background Art

[0002] Due to its excellent soft switching characteristics, the resonant converter circuit (LLC) can achieve ZVS of the primary MOSFET and ZVS and ZCS of the secondary synchronous rectifier in the full load range, making it suitable for working at high frequencies and having very high power density. It is widely used in high power density applications. The driving loss of MOSFETs is proportional to the switching frequency. At MHz operating frequency, the driving loss of MOSFETs has gradually become a key factor limiting its efficiency and power density. Especially in low-voltage and high-current output applications, due to the large output current, the LLC secondary side often needs to connect multiple MOSFETs in parallel to reduce the conduction loss of the synchronous rectifier, which will lead to an increase in the system driving loss. In order to reduce the driving loss of the converter at high frequencies and improve the conversion efficiency and power density of the system, many resonant gate drivers have been proposed in recent years. However, for LLC low-voltage and high-current application drivers, there are problems such as large footprint, low gate drive energy recovery ratio, small driving current, and unadjustable driving signal duty cycle. Summary of the invention

[0003] The present invention provides a discontinuous current type resonant gate drive circuit with variable duty cycle output, which solves the technical problems of the above-mentioned drive technology, such as low energy recovery rate, large number of control signals, difficult signal matching, large occupied area, unfavorable for miniaturization, and unadjustable duty cycle.

[0004] The embodiment of the present invention provides a discontinuous current type variable duty cycle output resonant gate drive circuit, comprising: a PMOS tube Q1, an NMOS tube Q2 and an NMOS tube Q3, an inductor L and a voltage stabilizing capacitor C R ;

[0005] The gate of the PMOS tube Q1 is connected to the first driving signal, the source is connected to the external power supply, the drain is connected to one end of the inductor L, the drain of the NMOS tube Q2 and the driving signal output end of the resonant gate driving circuit, and the driving signal output end is connected to the signal input end of the driven circuit;

[0006] The gate of the NMOS tube Q2 is connected to the second driving signal, and the source is grounded;

[0007] The gate of the NMOS tube Q3 is connected to the third driving signal, the drain is connected to the other end of the inductor L, and the source is connected to the voltage stabilizing capacitor C R One end of the voltage stabilizing capacitor C RThe other end is grounded;

[0008] By controlling the timing of the first drive signal, the second drive signal and the third drive signal, the switching states of the PMOS tube Q1, the NMOS tube Q2 and the NMOS tube Q3 and the inductor current flowing through the inductor L are controlled to be in a discontinuous state, thereby controlling the resonance state of the inductor L and the gate capacitance of the driven circuit and the duty cycle of the driving output voltage.

[0009] Optionally, in an embodiment of the present invention, controlling the switching states of the PMOS transistor Q1, the NMOS transistor Q2, and the NMOS transistor Q3 by controlling the timing of the first drive signal, the second drive signal, and the third drive signal includes:

[0010] The first driving signal v that controls the PMOS tube Q1 g1 is high level, the PMOS tube Q1 is turned off, and when the first drive signal v g1 is low level, the PMOS tube Q1 is turned on;

[0011] The second driving signal v that controls the NMOS tube Q2 g2 is high level, the NMOS tube Q2 is turned on, and when the second drive signal v g2 is low level, the NMOS tube Q2 is turned off;

[0012] The third driving signal v that controls the NMOS tube Q3 g3 is high level, the NMOS tube Q3 is turned on, and when the third drive signal v g3 is at a low level, the NMOS tube Q3 is turned off.

[0013] Optionally, in one embodiment of the present invention, the driven circuit includes a driven transistor Q and an equivalent gate capacitor C geq ; Among them, the equivalent gate capacitance C geq One end of is connected to the gate of the driven tube and the driving signal output end of the resonant gate driving circuit, the other end is connected to the source of the driven tube and ground, and the drain of the driven tube is connected to the main power circuit; by controlling the timing of the first driving signal, the second driving signal and the third driving signal to control the switching state of the PMOS tube Q1, the NMOS tube Q2 and the NMOS tube Q3 and the inductor current flowing through the inductor L is a discontinuous state, and then the resonant state of the inductor L and the gate capacitance of the driven circuit and the duty cycle of the driving output voltage are controlled. The working mode is:

[0014] During t0-t1: the first drive signal, the second drive signal and the third drive signal are all at high level, and the equivalent gate capacitance C geqThe initial voltage at both ends is 0, the NMOS tube Q2 and the NMOS tube Q3 are turned on, and the voltage stabilizing capacitor C R The inductor L is charged resonantly, and the inductor current i L Starting from 0, the voltage stabilizing capacitor C R The voltage across the terminals drops;

[0015] During t1-t2: the first drive signal and the third drive signal are at a high level, the second drive signal is at a low level, the NMOS transistor Q2 is turned off, and the voltage stabilizing capacitor C R , the inductor L and the equivalent gate capacitance C geq Resonance, inductor current i L It rises first and then falls, driving the output voltage v gsr Keep rising until it is equal to the external power supply Vcc voltage;

[0016] During t2-t3: the first drive signal and the second drive signal are at a low level, the third drive signal is at a high level, the PMOS tube Q1 is turned on, the external power supply Vcc, the inductor L, the voltage stabilizing capacitor C R Resonant charging and discharging, inductor current i L The voltage stabilizing capacitor C R The voltage across the terminals rises;

[0017] During t3-t4: the first drive signal, the second drive signal and the third drive signal are all at low level, the NMOS tube Q3 is turned off, and the drive output voltage v gsr Clamped to high level by external power supply Vcc;

[0018] During t4-t5: the first drive signal and the second drive signal are at a low level, the third drive signal is at a high level, the NMOS tube Q3 is turned on, the external power supply Vcc is supplied to the inductor L, and the voltage stabilizing capacitor C is turned on. R Charging, inductor current i L From 0 to approximately linear increase, the voltage stabilizing capacitor C R The voltage across the terminals rises;

[0019] During t5-t6: the first drive signal and the third drive signal are at a high level, the second drive signal is at a low level, the PMOS tube Q1 is turned off, and the equivalent gate capacitance C geq , the inductor L and the stabilizing capacitor C R Resonance, inductor current i L It rises first and then falls, driving the output voltage v gsr Keep decreasing until it reaches zero;

[0020] During t6-t7: the first drive signal, the second drive signal and the third drive signal are all at high level, the NMOS tube Q2 is turned on, the inductor L and the voltage stabilizing capacitor C R Resonance, inductor current i L The voltage stabilizing capacitor C R The voltage across the two ends rises until the inductor current i L Reduced to 0;

[0021] During t7-t8: the first drive signal and the second drive signal are at a high level, the third drive signal is at a low level, the NMOS tube Q3 is turned off, and the inductor current i L is 0, the driving output voltage v gsr The voltage is clamped to 0 by the NMOS tube Q2.

[0022] The discontinuous current type resonant gate drive circuit with variable duty cycle output according to the embodiment of the present invention has the following beneficial effects:

[0023] 1) The circuit of the present invention has a small inductance value, which saves cost and space and is conducive to miniaturization and integration;

[0024] 2) The inductor current of the circuit of the present invention is discontinuous, which greatly reduces the conduction loss of the circuit and improves the gate drive energy recovery ratio;

[0025] 3) The circuit of the present invention realizes soft switching, reduces the switching loss of the circuit, and can work efficiently at high frequencies;

[0026] 4) The circuit of the present invention can realize the duty cycle conversion of the driving signal by controlling the duty cycle of the driving signal.

[0027] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0029] Figure 1 A resonant gate driving circuit diagram of a discontinuous current type variable duty cycle output according to an embodiment of the present invention;

[0030] Figure 2 is a timing diagram of key waveforms of an embodiment of the present invention;

[0031] Figure 3(a)-Figure 3(h) Schematic diagram of current loops in different modes of a circuit according to an embodiment of the present invention;

[0032] Figure 4 This is a key waveform timing diagram of the change in the output duty cycle of the circuit drive according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0034] Figure 1 A resonant gate drive circuit diagram of a discontinuous current type variable duty cycle output is provided according to an embodiment of the present invention.

[0035] like Figure 1 As shown, the discontinuous current type variable duty cycle output resonant gate drive circuit includes: a PMOS tube Q1, an NMOS tube Q2 and an NMOS tube Q3, an inductor L and a voltage stabilizing capacitor C R .

[0036] The gate of the PMOS tube Q1 is connected to the first driving signal, the source is connected to the external power supply, the drain is connected to one end of the inductor L, the drain of the NMOS tube Q2 and the driving signal output end of the resonant gate driving circuit, and the driving signal output end is connected to the signal input end of the driven circuit;

[0037] The gate of the NMOS tube Q2 is connected to the second driving signal, and the source is grounded;

[0038] The gate of the NMOS tube Q3 is connected to the third driving signal, the drain is connected to the other end of the inductor L, and the source is connected to the voltage stabilizing capacitor C R One end of the voltage stabilizing capacitor C R The other end is grounded;

[0039] By controlling the timing of the first drive signal, the second drive signal and the third drive signal, the switching states of the PMOS tube Q1, the NMOS tube Q2 and the NMOS tube Q3 and the discontinuous state of the inductor current flowing through the inductor L are controlled, thereby controlling the resonance state of the inductor L and the gate capacitance of the driven circuit and the duty cycle of the driving output voltage.

[0040] like Figure 1 As shown, the drive circuit is powered by an external power supply Vcc, and includes a PMOS tube Q1, two NMOS tubes Q2 and Q3, an inductor L and a voltage stabilizing capacitor C R , using the principle of LC lossless resonant charging and discharging, through the external input drive signal v g1 -v g3The timing of the three MOSs is used to control the switching states respectively, realizing the resonant charging and discharging of the inductor and the gate capacitor, thereby achieving a nearly lossless gate drive. By controlling the current flowing through the inductor to be discontinuous, low cycle conduction loss and a smaller inductor design are achieved, thereby realizing a resonant gate drive circuit with a high energy recovery ratio and a small footprint.

[0041] Figure 1 The driven circuit also includes the driven tube Q and the equivalent gate capacitor C geq ; Among them, the equivalent gate capacitance C geq One end is connected to the gate of the driven tube and the driving signal output end of the resonant gate driving circuit, the other end is connected to the source of the driven tube and the ground, and the drain of the driven tube is connected to the main power circuit.

[0042] like Figure 2 As shown, the switching states of the PMOS tube Q1, the NMOS tube Q2 and the NMOS tube Q3 are controlled by controlling the timing of the first driving signal, the second driving signal and the third driving signal, including:

[0043] The first driving signal v that controls the PMOS tube Q1 g1 is high level, PMOS tube Q1 is turned off, and when the first drive signal v g1 It is low level, and the PMOS tube Q1 is turned on;

[0044] The second driving signal v that controls the NMOS tube Q2 g2 is high level, NMOS tube Q2 is turned on, and when the second drive signal v g2 It is low level, and the NMOS tube Q2 is turned off;

[0045] The third driving signal v that controls the NMOS tube Q3 g3 is high level, NMOS tube Q3 is turned on, and when the third drive signal v g3 It is at low level and NMOS tube Q3 is turned off.

[0046] By controlling the three-way driving signal v g1 -v g3 The timing of the drive output signal v gsr control.

[0047] In one embodiment of the present invention, Figure 3(a)-Figure 3(h) As shown, in one working cycle, the proposed discontinuous current type variable duty cycle output resonant gate drive circuit can be in eight states according to different working modes, where the red part is the main current path in this working mode, and the current direction is indicated by an arrow.

[0048] like Figure 4As shown in the figure, the proposed discontinuous current type variable duty cycle output resonant gate drive circuit can be used according to system requirements by controlling the three-way drive signal v g1 -v g3 The timing can realize the driving output signal v gsr Duty cycle changes.

[0049] Combination Figure 2 and Figure 3(a)-Figure 3(h) , the specific circuit working mode under steady state is analyzed as follows:

[0050] As shown in FIG3(a), during t0-t1: the first drive signal, the second drive signal and the third drive signal are all at high level, and the equivalent gate capacitance C geq The initial voltage at both ends is 0, NMOS tube Q2 and NMOS tube Q3 are turned on, and the voltage stabilizing capacitor C R The inductor L is charged resonantly, and the inductor current i L It starts from 0 and rises linearly. R The voltage across the terminals drops;

[0051] As shown in FIG3(b), during t1-t2: the first drive signal and the third drive signal are at a high level, the second drive signal is at a low level, the NMOS tube Q2 is turned off, and the voltage stabilizing capacitor C R , inductor L and equivalent gate capacitance C geq Resonance, inductor current i L It rises first and then falls, driving the output voltage v gsr Keep rising until it is equal to the external power supply Vcc voltage;

[0052] As shown in FIG3(c), during t2-t3: the first drive signal and the second drive signal are at a low level, the third drive signal is at a high level, the PMOS tube Q1 is turned on, the external power supply Vcc, the inductor L, and the voltage stabilizing capacitor C R Resonant charging and discharging, inductor current i L The voltage drops to 0, and the voltage stabilizing capacitor C R The voltage across the terminals rises;

[0053] As shown in FIG3(d), during t3-t4: the first drive signal, the second drive signal and the third drive signal are all at low level, the NMOS tube Q3 is turned off, and the drive output voltage v gsr Clamped to high level by external power supply Vcc;

[0054] As shown in FIG3(e), during t4-t5: the first drive signal and the second drive signal are at a low level, the third drive signal is at a high level, the NMOS tube Q3 is turned on, the external power supply Vcc is supplied to the inductor L, and the voltage stabilizing capacitor C R Charging, inductor current i LFrom 0 to approximately linear rise, the voltage stabilizing capacitor C R The voltage across the terminals rises;

[0055] As shown in FIG3(f), during t5-t6: the first drive signal and the third drive signal are at a high level, the second drive signal is at a low level, the PMOS tube Q1 is turned off, and the equivalent gate capacitance C geq , inductor L and stabilizing capacitor C R Resonance, inductor current i L It rises first and then falls, driving the output voltage v gsr Keep decreasing until it reaches zero;

[0056] As shown in FIG3(g), during t6-t7: the first drive signal, the second drive signal and the third drive signal are all high level, the NMOS tube Q2 is turned on, the inductor L and the stabilizing capacitor C R Resonance, inductor current i L Drop, the voltage stabilizing capacitor C R The voltage across the two ends rises until the inductor current i L Reduced to 0;

[0057] As shown in FIG3(h), during t7-t8: the first drive signal and the second drive signal are at a high level, the third drive signal is at a low level, the NMOS tube Q3 is turned off, and the inductor current i L is 0, the driving output voltage v gsr Clamped to 0 by NMOS tube Q2.

[0058] contrast Figure 2 and Figure 4 The discontinuous current type variable duty cycle resonant gate drive circuit is proposed to achieve the driving voltage v by changing the duration of a working cycle t3-t4. gsr Duty cycle changes.

[0059] According to the resonant gate drive circuit with discontinuous current type variable duty cycle output proposed in the embodiment of the present invention, the switching of the switch tube is controlled by controlling three drive signals, and the inductor and the gate capacitance of the driven tube form resonance, thereby realizing energy recovery and greatly reducing the driving loss. By controlling the current flowing through the inductor to be in a discontinuous state, low cycle conduction loss and a smaller inductor design are achieved, thereby achieving a high energy recovery ratio, a small footprint and a variable duty cycle output.

[0060] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0061] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

Claims

1. A discontinuous current type variable duty cycle output resonant gate drive circuit, characterized in that: include: PMOS tube Q1, NMOS tube Q2 and NMOS tube Q3, inductor L and voltage stabilizing capacitor C R ; The gate of the PMOS tube Q1 is connected to the first driving signal, the source is connected to the external power supply, the drain is connected to one end of the inductor L, the drain of the NMOS tube Q2 and the driving signal output end of the resonant gate driving circuit, and the driving signal output end is connected to the signal input end of the driven circuit; The gate of the NMOS tube Q2 is connected to the second driving signal, and the source is grounded; The gate of the NMOS tube Q3 is connected to the third driving signal, the drain is connected to the other end of the inductor L, and the source is connected to the voltage stabilizing capacitor C R One end of the voltage stabilizing capacitor C R The other end is grounded; By controlling the timing of the first drive signal, the second drive signal and the third drive signal, the switching states of the PMOS tube Q1, the NMOS tube Q2 and the NMOS tube Q3 and the inductor current flowing through the inductor L are controlled to be in a discontinuous state, thereby controlling the resonance state of the inductor L and the gate capacitance of the driven circuit and the duty cycle of the driving output voltage.

2. The discontinuous current type variable duty cycle output resonant gate drive circuit according to claim 1, characterized in that: Controlling the switching states of the PMOS tube Q1, the NMOS tube Q2, and the NMOS tube Q3 by controlling the timing of the first driving signal, the second driving signal, and the third driving signal includes: The first driving signal v that controls the PMOS tube Q1 g1 is high level, the PMOS tube Q1 is turned off, and when the first drive signal v g1 is low level, the PMOS tube Q1 is turned on; The second driving signal v that controls the NMOS tube Q2 g2 is high level, the NMOS tube Q2 is turned on, and when the second drive signal v g2 is low level, the NMOS tube Q2 is turned off; The third driving signal v that controls the NMOS tube Q3 g3 is high level, the NMOS tube Q3 is turned on, and when the third drive signal v g3 is at a low level, the NMOS tube Q3 is turned off.

3. The discontinuous current type variable duty cycle output resonant gate drive circuit according to claim 2, characterized in that: The driven circuit includes a driven tube Q and an equivalent gate capacitor C geq ; Among them, the equivalent gate capacitance C geq One end of is connected to the gate of the driven tube and the driving signal output end of the resonant gate driving circuit, the other end is connected to the source of the driven tube and ground, and the drain of the driven tube is connected to the main power circuit; by controlling the timing of the first driving signal, the second driving signal and the third driving signal to control the switching state of the PMOS tube Q1, the NMOS tube Q2 and the NMOS tube Q3 and the inductor current flowing through the inductor L is a discontinuous state, and then the resonant state of the inductor L and the gate capacitance of the driven circuit and the duty cycle of the driving output voltage are controlled. The working mode is: During t0-t1: the first drive signal, the second drive signal and the third drive signal are all at high level, and the equivalent gate capacitance C geq The initial voltage at both ends is 0, the NMOS tube Q2 and the NMOS tube Q3 are turned on, and the voltage stabilizing capacitor C R The inductor L is charged resonantly, and the inductor current i L Starting from 0, the voltage stabilizing capacitor C R The voltage across the terminals drops; During t1-t2: the first drive signal and the third drive signal are at a high level, the second drive signal is at a low level, the NMOS transistor Q2 is turned off, and the voltage stabilizing capacitor C R , the inductor L and the equivalent gate capacitance C geq Resonance, inductor current i L It rises first and then falls, driving the output voltage v gsr Keep rising until it is equal to the external power supply Vcc voltage; During t2-t3: the first drive signal and the second drive signal are at a low level, the third drive signal is at a high level, the PMOS tube Q1 is turned on, the external power supply Vcc, the inductor L, the voltage stabilizing capacitor C R Resonant charging and discharging, inductor current i L The voltage stabilizing capacitor C R The voltage across the terminals rises; During t3-t4: the first drive signal, the second drive signal and the third drive signal are all at low level, the NMOS tube Q3 is turned off, and the drive output voltage v gsr Clamped to high level by external power supply Vcc; During t4-t5: the first drive signal and the second drive signal are at a low level, the third drive signal is at a high level, the NMOS tube Q3 is turned on, the external power supply Vcc is supplied to the inductor L, and the voltage stabilizing capacitor C is turned on. R Charging, inductor current i L From 0 to approximately linear increase, the voltage stabilizing capacitor C R The voltage across the terminals rises; During t5-t6: the first drive signal and the third drive signal are at a high level, the second drive signal is at a low level, the PMOS tube Q1 is turned off, and the equivalent gate capacitance C geq , the inductor L and the stabilizing capacitor C R Resonance, inductor current i L It rises first and then falls, driving the output voltage v gsr Keep decreasing until it reaches zero; During t6-t7: the first drive signal, the second drive signal and the third drive signal are all at high level, the NMOS tube Q2 is turned on, the inductor L and the voltage stabilizing capacitor C R Resonance, inductor current i L The voltage stabilizing capacitor C R The voltage across the two ends rises until the inductor current i L Reduced to 0; During t7-t8: the first drive signal and the second drive signal are at a high level, the third drive signal is at a low level, the NMOS tube Q3 is turned off, and the inductor current i L is 0, the drive output voltage v gsr The voltage is clamped to 0 by the NMOS tube Q2.

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