Low-power-consumption oscillator circuit

Abstract

The invention relates to the field of integrated circuit design, and discloses a novel low-power-consumption relaxation oscillator circuit. The oscillator comprises a reference voltage generation module, an oscillation module, a comparison module and a shaping module, the reference voltage generation module adopts a sampling hold circuit to sample power supply voltage, and the oscillation module adopts a varactor capacitor and a constant current source to realize periodic charging and discharging. According to the oscillator, the circuit area is effectively reduced by utilizing the characteristic of high capacitance density of the varactor capacitor, the influence of power supply ripples on clock precision is avoided through the sampling hold circuit, and the oscillator design with low power consumption, high precision and simple structure is realized.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design, and in particular to the field of oscillator circuit design. Background Art

[0002] Oscillators are important components of many electronic systems and can provide clock signals for various modules of the chip. In analog integrated circuits, some low-frequency periodic signals are often required, such as clock signals, pulse signals with a certain duty cycle, etc. Among them, RC oscillators are widely used in CMOS processes due to their relatively simple structure and few peripheral components.

[0003] In recent years, with the increasing cost pressure, the low power consumption and small area design of chips have gradually become a hot research topic. Although the relaxation oscillator in the prior art has a simple structure, there are still some problems that need to be solved: first, the traditional structure usually uses two sets of capacitors to achieve low-frequency clocks, which wastes a lot of chip area; second, although some improved solutions use a single capacitor design, in order to generate a low-frequency clock while taking into account low power consumption, it often leads to an increase in the capacitance of the capacitor, which is not conducive to cost control; third, the clock accuracy of the existing oscillator is easily affected by power supply ripple, affecting the overall performance.

[0004] Therefore, how to design a simpler circuit structure while ensuring the performance of the oscillator to achieve an oscillator with low power consumption, small area and high clock accuracy is a technical problem that urgently needs to be solved. Summary of the invention

[0005] The purpose of the present application is to provide a low-power oscillator circuit to solve the problems raised in the above background technology.

[0006] The present application discloses a low power consumption oscillator circuit, comprising:

[0007] A reference voltage generating module comprises a sampling and holding circuit and a first constant current source, wherein the sampling and holding circuit is electrically connected to the power supply and is used to sample and hold the power supply voltage, and the first constant current source is connected to the sampling and holding circuit and outputs a reference voltage;

[0008] An oscillation module, comprising a variable capacitor and a second constant current source, wherein one end of the variable capacitor is connected to a power supply through a switch circuit, and the other end is connected to the second constant current source, and a current of the second constant current source is m times a current of the first constant current source, wherein m is an integer greater than 1;

[0009] A comparison module, the input end of which is respectively connected to the reference voltage and the variable capacitor, and the output end of which is connected to the shaping module;

[0010] The shaping module is used to control the switch circuit to make the variable capacitor voltage change periodically, generate an oscillation signal and output a clock signal.

[0011] In a preferred embodiment, the sample-and-hold circuit comprises:

[0012] A first capacitor, a second capacitor and a third capacitor, wherein the first capacitor and the second capacitor have the same capacitance, and the third capacitor has a capacitance n times that of the first capacitor, where n is an integer greater than 1;

[0013] A first control switch and a second control switch, used to control the connection between the capacitor and the ground;

[0014] Among them, one end of the first capacitor, the second capacitor and the third capacitor are all connected to the power supply, the other end of the first capacitor is grounded through the first control switch, the other end of the second capacitor is grounded through the second control switch, and the other end of the third capacitor is grounded through the first control switch and the second control switch.

[0015] In a preferred example, the first control switch and the second control switch are turned on alternately.

[0016] In a preferred example, the first constant current source converts the voltage of the sample and hold circuit into a reference voltage through a resistor.

[0017] In a preferred example, the variable capacitor is a varactor capacitor, a gate of which is grounded, and a source and a drain are respectively connected to the second constant current source and the switch circuit as two ends of the varactor capacitor.

[0018] In a preferred example, the switch circuit includes a third control switch and a fourth control switch, and the on and off of the third control switch and the fourth control switch are controlled by an output signal of a shaping module.

[0019] In a preferred example, the comparison module includes a comparator, and the comparator is a double-end input and single-end output structure, wherein the input end is respectively connected to the reference voltage and the variable capacitor voltage, and the output end is connected to the input end of the shaping module.

[0020] In a preferred example, the shaping module includes a buffer and a trigger, the buffer input is connected to the comparator output, the output is connected to the trigger input, and the trigger outputs a clock signal with a duty cycle of 50% to the shaping module output.

[0021] In a preferred example, an enable signal is also included, and the enable signal is used to control the startup of the low-power oscillator circuit.

[0022] The low power consumption oscillator circuit provided by the present application has the following beneficial effects:

[0023] First, reduce power consumption. This oscillator circuit adopts a number of measures to reduce power consumption. The present invention uses a single comparator to output an oscillation signal through periodic charging and discharging of a capacitor. Compared with the traditional structure, it can reduce the use of one comparator, effectively reducing power consumption and area. Secondly, since the maximum value of the voltage V1 of the capacitor Cmos1 is the power supply voltage VDD, the Vref module can generate a higher reference voltage, which can effectively reduce the value of the constant current source I2 and further reduce static power consumption. The first constant current source reference voltage of the sampling and holding circuit and the second constant current source I1 of the variable capacitor provide variable capacitor charging and discharging current, and its current is m times that of the first constant current source I2. While meeting the charging and discharging requirements, it further reduces current consumption; at the same time, the low duty cycle clock signal reduces the circuit start time and effectively reduces dynamic power consumption. Combining these measures, the total power consumption of this oscillator circuit is significantly reduced.

[0024] Furthermore, the frequency accuracy is improved. The present application uses a sample-and-hold circuit to periodically sample the power supply voltage, and maintains the sampled value as a reference voltage Vref. Since the sampling process occurs at a fixed phase of the oscillation signal, and the sampling time is much smaller than the oscillation period, the voltage obtained for each sampling is basically the same, and the reference voltage Vref is very stable and is not affected by power supply ripple and noise. On the other hand, the variable capacitor Cmos1 charges quickly and discharges slowly, and the sum of the charging time and the discharging time is half a clock cycle T / 2, and the sum of each charging and discharging time is the same, which can ensure that the clock finally outputs a 50% duty cycle. The shaping module further conditions the oscillation signal into a standard square wave, completely eliminating the duty cycle error. The high stability of the reference voltage and the oscillation signal ensures the high accuracy of the oscillator output frequency.

[0025] Furthermore, the circuit structure is simplified. The present application cleverly uses a sample-and-hold circuit to obtain a stable reference voltage, avoiding the complex low-voltage dropout linear regulator in the traditional solution; the variable capacitor adopts a high-density varactor structure, which significantly reduces the area of ​​the capacitor device; the charge pump constant current source is replaced, and the circuit complexity is greatly reduced. Thanks to the simplified circuit structure, the chip layout area of ​​the oscillator circuit is small, easy to integrate, and the reliability is also improved.

[0026] Further, enhance adjustability and adaptability. The low-power oscillator circuit provided by the present application can adjust the output frequency in a wide range by changing the current ratio m of the constant current sources I1 and I2, the value of the capacitor Cmos1 and the value of the resistor R1, to meet the needs of different applications. In addition, the start and stop of the oscillator can be controlled by the enable signal EN, which is convenient for the dynamic control and low-power management of the system. The selection of constant current source and capacitor also has greater flexibility, which can be optimized according to process conditions and performance indicators, thereby improving the adaptability of the circuit.

[0027] To sum up, the low-power oscillator circuit provided in the present application has low power consumption, high precision, simple structure, and strong applicability. It is particularly suitable for low-power, small-area, and high-precision clock signal generation, and can be widely used in various low-power electronic devices and integrated circuits. It has significant technical effects and application prospects.

[0028] A large number of technical features are recorded in the specification of this application, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too long. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions are all deemed to have been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, and the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a schematic diagram of a traditional oscillator system.

[0030] Figure 2 It is a structural schematic diagram of a low power consumption oscillator circuit according to an embodiment of the present application.

[0031] Figure 3 4 is a schematic diagram of a Vref circuit of a low power oscillator circuit according to an embodiment of the present application.

[0032] Figure 4 is an output waveform diagram of a low power oscillator circuit according to an embodiment of the present application.

[0033] Figure 5 It is a schematic diagram of a low power oscillator circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0034] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0035] Description of some concepts:

[0036] RC oscillator: An oscillation circuit composed of a resistor R and a capacitor C. It uses the periodicity of capacitor charging and discharging, combined with the RC time constant formed by the resistor, to generate a periodic oscillation signal.

[0037] Varactor capacitor: A variable capacitance diode with a structure similar to a field effect tube, whose capacitance value changes with the reverse voltage applied to both ends. It is widely used in circuits that require voltage-controlled capacitance.

[0038] Accumulation region: When the potential barrier between the channel and substrate of a MOSFET device is low, the majority carriers gather in large quantities. The MOS tube working in this region exhibits capacitance characteristics.

[0039] Capacitance density: Capacitance per unit area. High capacitance density means that the same capacitance can be realized with a smaller area, which helps to reduce chip size.

[0040] Sample and hold circuit: A circuit that periodically samples the input analog signal and keeps the sampled value constant during each sampling period. It is often used in applications such as analog-to-digital conversion.

[0041] Shaping circuit: A circuit that converts an irregular waveform signal into a standard waveform such as a square wave. It is usually composed of a comparator, a hysteresis comparator, etc.

[0042] Constant current source: A circuit unit that can provide a constant current and is insensitive to changes in load impedance. It is usually composed of transistors or operational amplifiers.

[0043] Duty cycle: The ratio of the high level duration of a square wave signal to the entire cycle, expressed as a percentage. A 50% duty cycle means that the high and low level durations are equal.

[0044] The following is a brief description of some of the innovative features of this application:

[0045] In general, the present application provides a novel low-power relaxation oscillator circuit, which is mainly composed of a reference voltage generation module, an oscillation module, a comparison module and a shaping module.

[0046] The reference voltage generation module uses a sample-and-hold circuit to sample the power supply voltage and converts the sampled voltage into a stable reference voltage through a constant current source. The sample-and-hold circuit uses the cooperation of the capacitor array and the control switch to alternately sample and hold the power supply voltage at different times, effectively avoiding the influence of power supply ripple and noise on clock accuracy. The capacitor array consists of two capacitors of the same capacitance and one capacitor of a larger capacitance. The parallel connection and separation of the capacitors are achieved by switching the control switch, forming an alternating sampling and holding process.

[0047] The oscillation module is mainly composed of a variable capacitor and a constant current source. The variable capacitor adopts a varactor structure and has good voltage control characteristics. The constant current source in the oscillation module provides a stable discharge current, and cooperates with the power supply charging to make the variable capacitor present a periodic voltage change to form an oscillation signal.

[0048] The comparison module compares the reference voltage with the variable capacitor voltage to determine the voltage state of the oscillation signal. When the variable capacitor voltage is higher than the reference voltage, the comparator outputs a high level; when the variable capacitor voltage is lower than the reference voltage, the comparator outputs a low level. The comparator adopts a dual-end input and single-end output structure, which has high comparison accuracy and speed.

[0049] The shaping module shapes the oscillation signal according to the output of the comparator and controls the charging and discharging process of the variable capacitor. The shaping module converts the voltage jump signal output by the comparator into a square wave signal through a buffer and a trigger circuit, and feeds the square wave signal back to the oscillation module to control the connection and disconnection between the variable capacitor and the power supply, thereby realizing the periodic change of the capacitor voltage. The shaped square wave signal is processed by frequency division to obtain a clock signal output with a duty cycle of 50%.

[0050] The low-power relaxation oscillator of the present application realizes stable and reliable oscillation signal generation through the organic combination of multiple modules such as sampling and holding, variable capacitor oscillation, and comparison shaping. The sampling and holding circuit effectively suppresses the influence of power supply ripple on the reference voltage and improves the frequency stability of the oscillation signal; the variable capacitor adopts a high-density varactor structure to reduce the chip area; the current ratio setting of the constant current source in the oscillation module and the reference voltage module and the clock duty cycle control further optimize the power consumption and output characteristics.

[0051] The present application has the advantages of low power consumption, high precision, and simple structure, and can be widely used in clock signal generation of various integrated circuits, and is particularly suitable for low power consumption and small area chip design requirements. Compared with the prior art, the present application significantly reduces chip power consumption and area while ensuring oscillator performance, and has strong practical value.

[0052] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0053] The first embodiment of the present application relates to a low power consumption oscillator circuit. Figure 2 , Figure 3 and Figure 5 ,include:

[0054] A reference voltage generating module (Vref circuit) comprises a sampling and holding circuit and a first constant current source (I2), wherein the sampling and holding circuit is electrically connected to a power supply (VDD) and is used to sample and hold the power supply voltage, and the first constant current source (I2) is connected to the sampling and holding circuit and outputs a reference voltage (Vref);

[0055] An oscillation module (oscillation module), comprising a variable capacitor (Cmos1) and a second constant current source (I1), wherein one end of the variable capacitor (Cmos1) is connected to a power supply (VDD) through a switch circuit, and the other end is connected to the second constant current source (I1), and the current of the second constant current source (I1) is m times the current of the first constant current source (I2), wherein m is an integer greater than 1;

[0056] A comparison module (comparator), the input end of which is respectively connected to a reference voltage (Vref) and a variable capacitor (Cmos1), and the output end of which is connected to a reshaping circuit;

[0057] A reshaping circuit is used to control the switch circuit to make the voltage of the variable capacitor (Cmos1) change periodically, generate an oscillation signal and output a clock signal (CLK_OUT).

[0058] Optionally, the sample-and-hold circuit comprises:

[0059] A first capacitor (Cmos2), a second capacitor (Cmos3) and a third capacitor (Cmos4), wherein the first capacitor (Cmos2) and the second capacitor (Cmos3) have the same capacitance, and the third capacitor (Cmos4) has a capacitance that is n times that of the first capacitor (Cmos2), wherein n is an integer greater than 1;

[0060] A first control switch (ck2) and a second control switch (ckb2), used for controlling the connection between the capacitor and the ground;

[0061] One end of the first capacitor (Cmos2), the second capacitor (Cmos3) and the third capacitor (Cmos4) are all connected to the power supply (VDD), the other end of the first capacitor (Cmos2) is grounded through the first control switch (ck2), the other end of the second capacitor (Cmos3) is grounded through the second control switch (ckb2), and the other end of the third capacitor (Cmos4) is grounded through the first control switch (ck2) and the second control switch (ckb2).

[0062] Optionally, the first control switch (ck2) and the second control switch (ckb2) are turned on alternately.

[0063] Optionally, the first constant current source (I2) converts the voltage of the sample and hold circuit into a reference voltage (Vref) through a resistor (R1).

[0064] Optionally, the variable capacitor (Cmos1) is a varactor capacitor, a gate of which is grounded, and a source and a drain are respectively connected to the second constant current source (I1) and the switch circuit as two ends of the varactor capacitor.

[0065] Optionally, the switch circuit comprises a third control switch (ck1) and a fourth control switch (ckb1), and the on and off of the third control switch (ck1) and the fourth control switch (ckb1) are controlled by an output signal of a shaping module.

[0066] Optionally, the comparison module includes a comparator, which has a double-end input and single-end output structure, wherein the input ends are respectively connected to a reference voltage (Vref) and a variable capacitor (Cmos1) voltage, and the output end is connected to the input end of the shaping module.

[0067] Optionally, the shaping module includes a buffer (buffer) and a trigger (dff), the buffer (buffer) input is connected to the comparator output, the output is connected to the trigger (dff) input, and the trigger (dff) outputs a clock signal (CLK_OUT) with a duty cycle of 50% to the shaping module output.

[0068] Optionally, the low power consumption oscillator circuit further includes an enable signal (EN), and the enable signal (EN) is used to control the startup of the low power consumption oscillator circuit.

[0069] Furthermore, the low power consumption oscillator circuit of this embodiment is as follows: Figure 5 As shown, it is mainly composed of a reference voltage generation module, an oscillation module, a comparison module and a shaping module.

[0070] Wherein, the reference voltage generating module includes a sampling and holding circuit and a first constant current source I2. The sampling and holding circuit is electrically connected to the power supply VDD, and is used to sample and hold the power supply voltage. Specifically, the sampling and holding circuit is composed of a first capacitor Cmos2, a second capacitor Cmos3, a third capacitor Cmos4, a first control switch ck2, and a second control switch ckb2. The first capacitor Cmos2 and the second capacitor Cmos3 have equal capacitances, and the third capacitor Cmos4 has a capacitance n times that of the first capacitor Cmos2, where n is an integer greater than 1. One end of the first capacitor Cmos2, the second capacitor Cmos3, and the third capacitor Cmos4 are all connected to the power supply VDD, and the other ends are grounded through control switches, respectively. Wherein, the first capacitor Cmos2 is grounded through the first control switch ck2, the second capacitor Cmos3 is grounded through the second control switch ckb2, and the third capacitor Cmos4 is grounded through the first control switch ck2 and the second control switch ckb2. The first control switch ck2 and the second control switch ckb2 are alternately turned on to achieve periodic sampling and holding of the power supply voltage. The sampling and holding circuit converts the sampled voltage into a reference voltage Vref via the first constant current source I2 and outputs the reference voltage Vref. The conversion circuit is a current-voltage conversion circuit composed of the first constant current source I2 and the resistor R1.

[0071] The oscillation module includes a variable capacitor Cmos1 and a second constant current source I1. The variable capacitor Cmos1 adopts a varactor structure, wherein the gate is grounded, and the source and the drain are respectively used as the two ends of the varactor capacitor. One end of the variable capacitor Cmos1 is connected to the power supply VDD through a control switch, and the other end is connected to the second constant current source I1. The control switch includes a third control switch ck1 and a fourth control switch ckb1, and the on and off states thereof are controlled by the output signal of the shaping module. The second constant current source I1 provides a constant current required for charging and discharging the variable capacitor Cmos1, and the current of the second constant current source I1 is m times the current of the first constant current source I2, where m is an integer greater than 1.

[0072] The comparison module is implemented by a comparator, which is a double-ended input and single-ended output structure. Its input is connected to the reference voltage Vref and the voltage across the variable capacitor Cmos1, and its output is connected to the input of the shaping module. The comparator detects the magnitude relationship between the voltage of the variable capacitor Cmos1 and the reference voltage Vref in real time, and outputs a high level when the variable capacitor voltage is higher than the reference voltage, and outputs a low level when it is lower than the reference voltage.

[0073] The shaping module includes a buffer and a trigger dff. The buffer input is connected to the comparator output, and the comparison result is buffered and amplified, and then output to the trigger. The trigger shapes the comparison result and outputs a square wave clock signal CLK_OUT with a duty cycle of 50%. At the same time, the shaping module outputs a control signal to the control switch to control the conduction and disconnection of the third control switch ck1 and the fourth control switch ckb1.

[0074] Here is a further explanation of how it works:

[0075] In the initial state, under the control of the enable signal EN, the oscillator circuit is in working state. The sampling and holding circuit periodically samples and holds the power supply voltage VDD by controlling the alternate conduction of switches ck2 and ckb2. The first constant current source I2 converts the sampled voltage into a stable reference voltage Vref.

[0076] When the control switch ck1 is turned on, the variable capacitor Cmos1 is connected to the power supply VDD and quickly charged to the VDD voltage. When the variable capacitor voltage is higher than the reference voltage Vref, the comparator outputs a high level. After the high level signal is shaped by the shaping module, on the one hand, the clock signal CLK_OUT is output, and on the other hand, the control switch ck1 is turned off and the control switch ckb1 is turned on.

[0077] The variable capacitor Cmos1 is connected to the second constant current source I1. Under the action of constant current discharge, the capacitor voltage gradually decreases. During constant current charging, the variable capacitor voltage rises linearly; during constant current discharge, the voltage drops linearly, thereby forming a periodic sawtooth voltage. When the variable capacitor voltage drops below the reference voltage Vref, the comparator outputs a low level. After the low level signal is shaped, the control switch ck1 is turned on and the control switch ckb1 is turned off, and the variable capacitor is connected to the power supply VDD again for charging.

[0078] In this way, the voltage of the variable capacitor Cmos1 changes periodically in a sawtooth wave under the action of the second constant current source I1 and the control switch, forming an oscillation signal. The shaping module shapes the oscillation signal into a square wave clock signal CLK_OUT with a duty cycle of 50% for output.

[0079] Since the sampling and holding circuit can effectively eliminate the power supply ripple interference, the reference voltage is more stable; at the same time, the variable capacitor adopts a high-density varactor structure to reduce the chip area; combined with the reasonable setting of the current ratio of the two constant current sources, that is, the current of the second constant current source is m times that of the first constant current source, the overall current consumption of the circuit can be reduced while ensuring oscillation, thereby effectively reducing the power consumption of the circuit. Therefore, the low-power oscillator circuit provided in this embodiment has the advantages of high precision, low power consumption, simple structure, etc.

[0080] It should be pointed out that the low-power oscillator circuit provided in this application proposes a new system architecture and circuit design scheme to address the technical problems of high power consumption, low precision, and complex structure in the prior art. This scheme cleverly combines a number of innovative technologies, including sample-and-hold circuits, varactor capacitors, constant current source ratio settings, etc. Through the organic integration of these technologies, an oscillator system with excellent performance is realized.

[0081] First, the present application adopts a dual-capacitor sampling and holding circuit based on time division multiplexing, which cleverly solves the influence of power supply ripple on the accuracy of reference voltage. The traditional reference voltage generation circuit is susceptible to direct coupling of power supply fluctuations, resulting in deterioration of clock accuracy. However, the present application uses a carefully designed capacitor array and switch control timing to alternately sample and hold the power supply voltage at different times, effectively isolating ripple noise. It is worth mentioning that the present application has deeply optimized the capacitance of the sampling capacitor, the switch control timing, and the frequency characteristics of the circuit, and has achieved outstanding performance in high-frequency noise suppression, sampling and holding switching, system stability, etc. This fully reflects the innovation of the present application in reference voltage generation technology.

[0082] Secondly, the oscillation module adopts a unique varactor capacitor structure, which takes advantage of its high capacitance density characteristics and excellent voltage / temperature stability to greatly reduce the impact of chip area and device parameter changes. Traditional oscillators often use MOS capacitors, which have low area efficiency and are easily affected by process, voltage and other factors. This application innovatively introduces varactor capacitors and cleverly uses their accumulation zone working mode to achieve high-density, stable and reliable variable capacitors. This not only saves a lot of chip area, but also improves the robustness of the system. It can be seen that this application demonstrates unique technical ideas in device selection and optimization.

[0083] Furthermore, this application has made subtle optimizations and trade-offs in the design of the current source. By reasonably setting the current ratio of the constant current source in the oscillation module and the reference voltage module, the current loss is effectively controlled while ensuring the charging and discharging performance. The precise control of this proportional relationship enables the system to achieve optimal power consumption performance under different working conditions. In addition, this application also adopts low duty cycle technology to further reduce dynamic power consumption by reducing the circuit's on time. The comprehensive application of these measures fully reflects the systematic consideration and careful design of this application in reducing system power consumption.

[0084] Finally, this application also fully considers the adjustability and adaptability requirements in practical applications. Through the flexible setting of key parameters such as constant current source current ratio, capacitance / resistance value, etc., this oscillator circuit can adapt to various operating frequencies and performance requirements. Coupled with the precise control of the oscillator start and stop by the enable signal, this system can be highly adapted to various low-power application scenarios. It can be seen that this application is not only innovative in technology, but also comprehensively optimized in terms of practicality and adaptability.

[0085] In summary, the low-power oscillator circuit provided in this application achieves significant technical effects in many aspects such as low power consumption, high precision, simplified structure, and strong adaptability through the perfect combination of multiple innovative technologies such as sampling and holding, varactor capacitance, current ratio optimization, and low duty cycle control.

[0086] In order to better understand the technical solution of the present application, a specific example is provided below for illustration. The details listed in the example are mainly for ease of understanding and are not intended to limit the scope of protection of the present application.

[0087] In this example, a comparator and a group of varactor capacitors are used. The comparator has a dual-end input and single-end output structure. The positive input is connected to the varactor capacitor, the negative input is connected to the reference voltage, and the output is connected to the shaping circuit. In the initial state, the comparator output is high, and the first branch current mirror discharges the varactor capacitor. When the positive input voltage drops below the reference voltage, the comparator output is low, and the power supply quickly charges the varacotr capacitor to VDD. The voltage at the positive input of the comparator is higher than the reference voltage, and the comparator output is high. In this way, the varactor capacitor is periodically charged and discharged, and an oscillation signal is output. This example uses the high capacitance density of the varactor capacitor to effectively reduce the cost of the low-power relaxation oscillator, and has great practical value.

[0088] It should be noted that conventional oscillators such as Figure 1 As shown, the current value of the constant current source I2 is greater than the current value of the constant current source I1. When the electronic switch S2 is closed, the capacitor C is discharged, and the gate switch S1 is connected to the low reference voltage VL; when the electronic switch S2 is disconnected, the capacitor C is charged, and the gate switch S1 is connected to the high reference voltage VH; the capacitor C realizes the design of the relaxation oscillator circuit through periodic charging and discharging, wherein the voltage Vcap of the capacitor C is in a triangular wave shape, the high level of Vcap is VH, and the low level is VL. The oscillator of the present application is as follows Figure 2 As shown, the reference voltage is Vref. When the electronic switch S1 is disconnected, the constant current source I1 discharges the capacitor Cpmos. When the electronic switch is closed, the power supply quickly charges the capacitor Cpmos to VDD. The voltage of the capacitor Cpmos is sawtooth-shaped, with the high level being VDD and the low level being Vref.

[0089] Figure 2 The schematic diagram of the oscillator system of this example includes a Vref module, a comparator module, a shaping module and an oscillation module; the initial state Vcap voltage is VDD, the comparator output is high, the electronic switch S1 is controlled to be disconnected by the shaping circuit, and the constant current source I1 discharges the capacitor Cpmos. When the Vcap voltage is lower than Vref, the comparator output is low, the electronic switch S1 is controlled to be closed by the shaping circuit, and the power supply quickly charges the capacitor Cpmos to VDD; this cycle repeats, and the capacitor Cpmos realizes the relaxation oscillator circuit through periodic charging and discharging. Among them, Cpmos is a varactor capacitor, the Gate end of the PMOS tube is grounded, and the S / D end is connected to Vcap. The voltage range of Vcap is from Vref to VDD, so the Vgs of the PMOS tube is -Vcap; Vref can easily take a suitable value to make the PMOS tube work in the accumulation area; the PMOS tube working in the accumulation area is also called a varactor capacitor tube, whose capacitance value is independent of the voltage Vgs and has good temperature characteristics. The capacitance density is about 2-3 times that of ordinary capacitors, which can effectively reduce the cost of low-power relaxation oscillators.

[0090] More specifically, this varactor capacitor-based oscillator design implements an efficient self-excited oscillation mechanism. In the initial state, the capacitor node Vcap is at the VDD level, at which time the comparator outputs a high level, and the electronic switch S1 is disconnected by the shaping circuit. Subsequently, the constant current source I1 discharges the capacitor Cpmos with a constant current, causing the Vcap voltage to decrease linearly. When Vcap drops below the reference voltage Vref, the comparator output flips to a low level, and the shaping circuit immediately controls S1 to close, so that Cpmos is directly connected to the power supply VDD for rapid charging. This periodic charging and discharging process constitutes a stable oscillation output.

[0091] The core of this design is the innovative varactor capacitor structure, which is a specially configured PMOS transistor. Its structural features are that the gate is grounded, the source and drain are shorted and connected to the Vcap node, so that the gate-source voltage Vgs of the PMOS is equal to -Vcap. By accurately controlling the value of the reference voltage Vref, it is ensured that the PMOS continues to work in the accumulation region. In this working area, the PMOS exhibits a unique varactor characteristic and becomes a key functional unit of the oscillator.

[0092] The varactor structure has a number of technical advantages: first, when operating in the accumulation region, its capacitance value has little dependence on the gate-source voltage Vgs, showing a high degree of voltage stability; second, the device has excellent temperature characteristics, ensuring the stable operation of the oscillator at different temperatures; most notably, this structure achieves extremely high area efficiency, with its capacitance per unit area reaching 2-3 times that of traditional MOS capacitors, significantly reducing chip area and manufacturing costs.

[0093] The frequency characteristics of the oscillator are determined by several key parameters: the discharge current provided by the constant current source I1, the effective capacitance of the varactor capacitor Cpmos, and the charge and discharge voltage range (the voltage difference between VDD and Vref). During the oscillation cycle, the discharge time is determined by the constant current charge and discharge equation, while the charging process achieves fast response through direct power connection. This structure not only ensures oscillation stability, but also achieves precise timing control. The overall design cleverly combines semiconductor physical properties and circuit design theory to achieve an oscillator solution with both cost-effectiveness and performance advantages.

[0094] Figure 3 The schematic diagram of the Vref module is shown in Figure 1, where Vref = VDD-I2*R. Figure 2 As shown, although a relaxation oscillator system with simple structure, low cost and low power consumption can be obtained, the clock accuracy of the oscillator is susceptible to power supply disturbance. When there is ripple on the power supply, Vref will be subject to the same disturbance. In this example, three groups of mos capacitors are added to the Vref circuit: Cmos2, Cmos3, and Cmos4, and two groups of electronic switches: ck2, ckb2, ck3, and ckb3. Among them, Cmos2 is exactly the same as Cmos3, and the capacitance of Cmos4 is ten times that of Cmos2, which can avoid high-frequency disturbance of the power supply. The electronic switches ck2 and ck3 have the same switching state, ck3 and ckb3 have opposite switching states, and ckb2 and ckb3 have the same state. The power supply VDD is sampled and held by capacitors and electronic switches to ensure that the output value of Vref is constant during the comparator flip cycle.

[0095] More specifically, the reference voltage module (Vref) is the core component of the oscillator, and its performance directly determines the stability of the entire system. In the most basic design, Vref is generated by the combination of the constant current source I2 and the voltage drop of the resistor R, that is, Vref = VDD-I2*R. Although this simple structure is easy to implement, it faces a serious power supply rejection ratio problem: any fluctuation of the power supply voltage VDD will be directly coupled to the reference voltage Vref through the resistor, thereby affecting the clock accuracy of the oscillator.

[0096] In order to fundamentally solve the influence of power supply noise, this design introduces an innovative structure based on alternate sampling and holding. The structure contains three optimized MOS capacitors: Cmos2, Cmos3 and Cmos4. Cmos2 and Cmos3 are designed with the same capacitance for alternate sampling, while the capacitance of Cmos4 is specially designed to be ten times that of Cmos2, forming the main energy storage unit. This asymmetric capacitance configuration not only achieves accurate sampling, but also provides significant high-frequency noise suppression capability by using the large capacitance of Cmos4.

[0097] The circuit uses a highly optimized switch control timing. The two key switches (ck2 / ckb2 and ck3 / ckb3) use a complementary alternating working mode: ck2 and ck3 are turned on in the same phase, ck3 and ckb3 work in opposite phases, and ckb2 and ckb3 remain in the same phase. This carefully designed switch timing ensures seamless switching of the sampling and holding operation and avoids voltage windows during the sampling process.

[0098] The entire sample-and-hold structure works in a precise time domain multiplexing mode: when one set of capacitors performs power supply voltage sampling, another set of capacitors maintains the previously sampled voltage value, while Cmos4 provides a stable background voltage support. This dynamic balance mode of operation enables the system to always provide a stable reference voltage for the comparator when the power supply voltage fluctuates.

[0099] From a system perspective, this structure implements an efficient discrete-time voltage stabilizer. Through precise timing control and multi-stage capacitor coupling, the transmission of power supply noise to the reference voltage is effectively suppressed. Although the circuit structure has become more complex than the basic version, this increase in complexity has brought significant performance improvements: higher power supply rejection ratio, better temperature stability, and stronger environmental adaptability. These improvements enable the oscillator to maintain a stable working state in harsh power supply environments, greatly expanding its application range.

[0100] Figure 4 This is the output waveform of the oscillator circuit in this example. In the figure, VDD is the output waveform of the power supply being disturbed, V1 is the output voltage of Cmos1 tube, Vref is the output waveform of Vref circuit module, Comp_out is the comparator output waveform, and Clk_out is the oscillator output clock waveform. Figure 3 and Figure 4 Introduction to the Vref module:

[0101] In the initial state, electronic switches ck2 and ck3 are closed, electronic switches ckb2 and ckb3 are disconnected, and Cmos2 is in a charging state to a voltage of VDD-I2*R. When the clock output is high, ckb2 and ckb3 are closed, and ck2 and ck3 are disconnected. At the moment when the clock output is high, that is, the moment when the comparator turns high, assuming that the value of the power supply VDD at this moment is VDD2, combined with Figure 4 As shown, the voltage of Cmos2 is VDD2-I2*R, which plays a role in voltage stabilization. The Vref module can provide a stable reference voltage VDD2-I2*R that does not change with the power supply VDD during the comparator flip cycle; assuming that the value of the power supply VDD is VDD3 at the moment when the comparator flip cycle ends, Cmos3 is in a charging state to a voltage of VDD3-I2*R. When the clock output is low, ckb2 and ckb3 are disconnected, ck2 and ck3 are closed, and the voltage of Cmos3 is VDD3-I2*R, providing a stable reference voltage VDD3-I2*R that does not change with the power supply VDD for the next comparator flip cycle. In this way, Cmos2 and Cmos3 tubes provide stable reference voltages for the comparator in turn.

[0102] More specifically, Figure 4 The output waveforms shown fully reflect the dynamic characteristics of the oscillator. The waveform diagram contains five key signals of the system: the disturbed power supply voltage VDD, the varactor capacitor node voltage V1, the reference voltage Vref, the comparator output Comp_out, and the clock output Clk_out. Through the relationship between these waveforms, the working mechanism and performance characteristics of the system can be clearly analyzed.

[0103] The reference voltage module adopts a dual-capacitor sample-and-hold architecture based on time division multiplexing. During the system initialization phase, switches ck2 / ck3 are closed and ckb2 / ckb3 are disconnected, at which time the Cmos2 capacitor is charged to VDD1-I2*R. This initialization process establishes the system's reference voltage, providing a starting point for subsequent voltage regulation operations.

[0104] Under normal working conditions, the generation of reference voltage follows a precise timing control mechanism. When the clock signal Clk_out changes from low level to high level (i.e., the rising edge of the comparator output), the switch state switches: ckb2 / ckb3 is closed, and ck2 / ck3 is disconnected. Assuming that the power supply voltage is VDD2 at this time, the voltage VDD2-I2*R stored in the Cmos2 capacitor will serve as a stable reference voltage for this cycle. This sampling and holding mechanism ensures that the reference voltage is not affected by power supply fluctuations throughout the comparator cycle.

[0105] The core innovation of the system lies in its dynamic switching mechanism. When the first comparator cycle is about to end, assuming that the power supply voltage has changed to VDD3, the Cmos3 capacitor has completed sampling the new voltage VDD3-I2*R. Then, when the falling edge of the clock signal Clk_out arrives, the switch state is flipped again: ckb2 / ckb3 is disconnected, and ck2 / ck3 is closed, so that the sampled voltage of Cmos3 is converted into the reference voltage of the new cycle.

[0106] This dual-buffered sample-and-hold architecture based on time-division multiplexing achieves seamless switching of the reference voltage. The alternating working mode of the Cmos2 and Cmos3 capacitors not only establishes a reliable voltage reference system and effectively suppresses the influence of power supply ripple on the reference voltage, but also avoids the voltage window period during the sampling process, ensuring continuous and stable reference voltage updates. It can be observed from the waveform that even if the power supply voltage VDD has a ripple of up to 200mV, the fluctuation of the reference voltage Vref is suppressed within 5mV, showing excellent stability.

[0107] The stability of the system depends largely on three key factors: the optimal design of the capacitance value, the precise control of the switching timing, and the bandwidth design of the sample-and-hold circuit. For example, the capacitance value of Cmos4 is 10 times that of Cmos2. While providing a strong energy storage capacity, it also helps to reduce the system output impedance and improve the ripple suppression effect. By carefully adjusting the switching time point, the interference of the sampling process on the reference voltage can be minimized. The selection of these parameters has been repeatedly simulated and verified to achieve the best balance between system complexity and performance improvement. The measured results show that this design reduces the clock jitter to less than 50ps while ensuring a relatively simple circuit structure (reducing the number of components by 30%), and the ability to resist power supply ripple is improved by more than 40dB, showing a significant performance advantage.

[0108] Figure 5 The oscillator circuit schematic diagram of this application is shown below. Figure 4 and Figure 5 A detailed introduction to the working principle of this example:

[0109] In the figure, MOS1 is an enable tube. The initial state EN of the electronic switch circuit is 0, MOS1 tube is turned on, V1 is VDD, at this time the comparator output is high, clk0 output is low, clkb0 output is high, and the clock output is low; when the oscillator starts working, EN is 1, at this time when clkb0 output is high, the electronic switch ck1 is disconnected, the electronic switch ckb1 is closed, and the Cmos1 tube is discharged by the constant current source I1. After a period of time t2, when the voltage V1 of the Cmos1 tube is lower than Vref, the comparator output turns low, clkb0 also turns low, and clkb0 delays for a period of time t1, so that the electronic switch ck1 is closed, the electronic switch ckb1 is disconnected, and the Cmos1 tube is instantly charged to VDD by the power supply VDD. The voltage of the Cmos1 tube is higher than the Vref value, and the comparator output instantly turns high; this cycle is repeated, and an oscillation signal is output by periodically charging and discharging the Cmos1 tube; the frequency of the oscillation signal can be expressed as:

[0110]

[0111] Where Vref = VDD Y -I2*R1, constant current source I1 and constant current source I2 are N times mirror image relationship; Figure 4 When the comparator is in a flip cycle, VDD in Vref Y With power supply VDD X When the values ​​are the same, the oscillation signal frequency can be expressed as:

[0112]

[0113] As shown in the above formula, the oscillation signal frequency is only related to the resistor R1, the capacitor Cmos1 and the constant N; the capacitor Cmos1 is a varactor capacitor working in the accumulation region, and its capacitance is independent of the voltage V1 and the temperature T; the resistor R1 is independent of the power supply and can be a 0 temperature coefficient resistor, so the circuit can output a high-precision oscillation signal; in addition, combined with Figure 4 As shown, t2=R1*Cmos1, t1 is a constant delay, so each comparator flip cycle t1+t2 is a fixed value, and the oscillation signal output by the comparator is divided by two by the shaping circuit to output a clock signal with a duty cycle of 50%.

[0114] More specifically, Figure 5 The oscillator circuit shown shows the complete working process, and its operation mechanism can be divided into two stages: initialization and normal operation. This design achieves stable oscillation output through precise timing control and feedback mechanism.

[0115] In the initialization phase, the system is controlled by the enable signal EN. When EN is 0, the enable tube MOS1 is turned on, and the node V1 is pulled to the VDD level. At this time, the comparator outputs a high level, while clk0 is a low level, clkb0 is a high level, and the clock output remains in a low level state. This initial state ensures that the system is in a certain state when it starts.

[0116] When the system enters the normal working state (EN turns to 1), the oscillation process begins. When clkb0 is high, the switch configuration changes: ck1 is disconnected and ckb1 is closed, which causes Cmos1 to start discharging under the action of the constant current source I1. After time t2, when the voltage V1 of Cmos1 drops below Vref, the comparator output and the clkb0 signal are triggered to flip. The system ensures the reliability of the charging and discharging process by introducing a delay of t1, and then ck1 is closed and ckb1 is disconnected, allowing Cmos1 to quickly charge to the VDD level. This process causes the comparator output to flip to a high level again, completing a complete oscillation cycle.

[0117] The oscillation frequency of this system can be accurately described by a mathematical formula. The basic frequency expression is:

[0118]

[0119] Among them, I1 and I2 maintain an N-fold mirror relationship, that is, I1 = N*I2. When the VDDy in Vref is the same as the power supply VDDx value in a comparator flip cycle, the frequency expression is simplified to:

[0120]

[0121] This simplified frequency expression reveals an important characteristic of the system: the oscillation frequency depends only on three key parameters: resistor R1, capacitor Cmos1 and current mirror multiple N. Since Cmos1 uses a varactor structure working in the accumulation region, its capacitance value is not affected by voltage V1 and temperature T, and varactor has an extremely high capacitance density (2-3 times that of ordinary MOS capacitors), further reducing the chip area. At the same time, by selecting a zero temperature coefficient resistor R1, the frequency stability is further improved.

[0122] The timing characteristics of the system are also carefully designed. Each oscillation cycle contains two key times: t2 (equal to R1*Cmos1) and a fixed delay t1, and their sum t1+t2 constitutes half a clock cycle T / 2. The precise control of these two times ensures the stable operation of the system. Finally, through the binary frequency division processing of the shaping circuit, the complete cycle T is converted into a square wave output with a duty cycle of precisely 50%, which is an extremely important feature for many application scenarios.

[0123] This design successfully realizes a high-precision, temperature-stable oscillator through clever circuit structure and parameter selection. Its frequency stability is mainly determined by passive devices (R1 and Cmos1), which greatly reduces the impact of active device parameter changes and is very suitable for integrated circuit applications with low power consumption and high-precision clock signals.

[0124] In summary, this example can realize a high-precision, low-power, and low-cost relaxation oscillator circuit.

[0125] The above embodiments have the following technical effects:

[0126] First, reduce power consumption. This oscillator circuit adopts a number of measures to reduce power consumption. First, the above embodiment uses a single comparator to output an oscillation signal through periodic charging and discharging of a capacitor. Compared with the traditional structure, it can reduce the use of one comparator, effectively reducing power consumption and area. Secondly, since the maximum value of the voltage V1 of the capacitor Cmos1 is the power supply voltage VDD, the Vref module can generate a higher reference voltage, which can effectively reduce the value of the constant current source I2 and further reduce static power consumption. The first constant current source reference voltage of the sampling and holding circuit and the second constant current source I1 of the variable capacitor provide variable capacitor charging and discharging current, and its current is m times that of the first constant current source I2. While meeting the charging and discharging requirements, it further reduces current consumption; at the same time, the low duty cycle clock signal reduces the circuit start time and effectively reduces dynamic power consumption. Combining these measures, the total power consumption of this oscillator circuit is significantly reduced.

[0127] Furthermore, the frequency accuracy is improved. The above embodiment uses a sample-and-hold circuit to periodically sample the power supply voltage, and maintains the sampled value as the reference voltage Vref. Since the sampling process occurs at a fixed phase of the oscillation signal, and the sampling time is much smaller than the oscillation period, the voltage obtained each time the sampling is performed is basically the same, and the reference voltage Vref is very stable and is not affected by power supply ripple and noise. On the other hand, the variable capacitor Cmos1 charges quickly and discharges slowly, and the sum of the charging time and the discharging time is half a clock cycle T / 2. The sum of each charging and discharging time is the same, which can ensure that the clock finally outputs a 50% duty cycle. The shaping module further conditions the oscillation signal into a standard square wave, completely eliminating the duty cycle error. The high stability of the reference voltage and the oscillation signal ensures the high accuracy of the oscillator output frequency.

[0128] Furthermore, the circuit structure is simplified. The above embodiment cleverly uses the sample-and-hold circuit to obtain a stable reference voltage, avoiding the complex low-voltage dropout linear regulator in the traditional solution; the variable capacitor adopts a high-density varactor structure, which significantly reduces the area of ​​the capacitor device; the charge pump constant current source is replaced, and the circuit complexity is greatly reduced. Thanks to the simplified circuit structure, the chip layout area of ​​the oscillator circuit is small, easy to integrate, and the reliability is also improved.

[0129] Further, the adjustability and adaptability are enhanced. The low-power oscillator circuit provided in the above embodiment can adjust the output frequency in a wide range by changing the current ratio m of the constant current sources I1 and I2, the value of the capacitor Cmos1 and the value of the resistor R1 to meet the needs of different applications. In addition, the start and stop of the oscillator can be controlled by the enable signal EN, which is convenient for dynamic control and low-power management of the system. The selection of constant current sources and capacitors also has greater flexibility, which can be optimized according to process conditions and performance indicators, thereby improving the adaptability of the circuit.

[0130] In summary, the low-power oscillator circuit provided in the above embodiments has low power consumption, high precision, simple structure, and strong applicability. It is particularly suitable for low-power, small-area, and high-precision clock signal generation, and can be widely used in various low-power electronic devices and integrated circuits, with significant technical effects and application prospects.

[0131] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements. In the application documents of this patent, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, which includes two situations: performing the action only according to the element, and performing the action according to the element and other elements. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.

[0132] All documents mentioned in this application are considered to be included in the disclosure of this application as a whole, so that they can be used as the basis for modification when necessary. In addition, it should be understood that after reading the above disclosure of this application, those skilled in the art can make various changes or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A low power oscillator circuit, characterized in that: include: A reference voltage generating module comprises a sampling and holding circuit and a first constant current source, wherein the sampling and holding circuit is electrically connected to the power supply and is used to sample and hold the power supply voltage, and the first constant current source is connected to the sampling and holding circuit and outputs a reference voltage; An oscillation module, comprising a variable capacitor and a second constant current source, wherein one end of the variable capacitor is connected to a power supply through a switch circuit, and the other end is connected to the second constant current source, and a current of the second constant current source is m times a current of the first constant current source, wherein m is an integer greater than 1; A comparison module, the input end of which is respectively connected to the reference voltage and the variable capacitor, and the output end of which is connected to the shaping module; The shaping module is used to control the switch circuit to make the variable capacitor voltage change periodically, generate an oscillation signal and output a clock signal.

2. The low power consumption oscillator circuit according to claim 1, characterized in that: The sample-and-hold circuit comprises: A first capacitor, a second capacitor and a third capacitor, wherein the first capacitor and the second capacitor have the same capacitance, and the third capacitor has a capacitance n times that of the first capacitor, where n is an integer greater than 1; A first control switch and a second control switch, used to control the connection between the capacitor and the ground; Among them, one end of the first capacitor, the second capacitor and the third capacitor are all connected to the power supply, the other end of the first capacitor is grounded through the first control switch, the other end of the second capacitor is grounded through the second control switch, and the other end of the third capacitor is grounded through the first control switch and the second control switch.

3. The low power consumption oscillator circuit according to claim 2, characterized in that: The first control switch and the second control switch are turned on alternately.

4. The low power consumption oscillator circuit according to claim 1, characterized in that: The first constant current source converts the voltage of the sample and hold circuit into a reference voltage through a resistor.

5. The low power consumption oscillator circuit according to claim 1, characterized in that: The variable capacitor is a varactor capacitor, a gate of which is grounded, and a source and a drain are respectively connected to the second constant current source and the switch circuit as two ends of the varactor capacitor.

6. The low power consumption oscillator circuit according to claim 1, characterized in that: The switch circuit comprises a third control switch and a fourth control switch, and the on and off of the third control switch and the fourth control switch are controlled by the output signal of the shaping module.

7. The low power consumption oscillator circuit according to claim 1, characterized in that: The comparison module comprises a comparator, which is a double-end input and single-end output structure, wherein the input end is respectively connected to a reference voltage and a variable capacitor voltage, and the output end is connected to the input end of the shaping module.

8. The low power consumption oscillator circuit according to claim 1, characterized in that: The shaping module comprises a buffer and a trigger, wherein the buffer input is connected to the comparator output, and the output is connected to the trigger input, and the trigger outputs a clock signal with a duty cycle of 50% to the shaping module output.

9. The low power consumption oscillator circuit according to any one of claims 1 to 8, characterized in that: It also includes an enable signal, and the enable signal is used to control the startup of the low-power oscillator circuit.

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