Bias circuit and low noise amplifier circuit including same

Abstract

A bias circuit and a low noise amplifier circuit including the same are provided. The bias circuit may be connected to a first transistor configured to amplify an input radio frequency (RF) signal and may be configured to provide a bias voltage to a second transistor that amplifies an output RF signal of the first transistor. The bias circuit may include a current source configured to receive a supply voltage and generate a reference current; the current-voltage conversion circuit is configured to convert the reference current into the bias voltage and supply the bias voltage to a control terminal of the second transistor.

Description

Technical Field

[0001] The following description relates to a bias circuit and a low noise amplifier circuit including the bias circuit. Background Art

[0002] In a front end module (FEM) of a communication system, a low noise amplifier (LNA) for reception may generally use a power supply voltage of 1.8 V. However, in order to reduce power consumption of the communication system, the power supply voltage is reduced to 1.2 V.

[0003] In current communication systems, the power supply voltage is divided into 1.8V and 1.2V, and in some examples, both power supply voltages of 1.8V and 1.2V are supported.

[0004] Generally, a low noise amplifier may include a common source transistor and a common gate transistor having a common source and common gate structure. A bias circuit of the common gate transistor applies a bias voltage using a power supply voltage, and the bias voltage when a power supply voltage of 1.8 V is used may be different from the bias voltage when a power supply voltage of 1.2 V is used. Therefore, a method for providing a constant bias voltage even if the power supply voltage changes is required.

[0005] The above information is presented as background information only to help understand the present disclosure. The above description should not be interpreted as these contents belonging to the prior art of the present disclosure. Summary of the invention

[0006] This summary is provided to introduce selected concepts in a simplified form, and these concepts are further described in the following detailed description. This summary is neither intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0007] In one general aspect, a bias circuit connected to a first transistor (the first transistor is configured to amplify an input radio frequency (RF) signal) and configured to provide a bias voltage to a second transistor (the second transistor amplifies an output RF signal of the first transistor) includes: a current source configured to receive a power supply voltage and generate a reference current; and a current-to-voltage conversion circuit configured to convert the reference current into the bias voltage and provide the bias voltage to a control terminal of the second transistor.

[0008] The current source may be configured to increase the magnitude of the reference current as temperature increases.

[0009] The current source may include: a third transistor configured to have a first terminal connected to a power supply terminal supplying the power supply voltage and a second terminal connected to the ground through a resistor; and a fourth transistor connected to the third transistor in a current mirror structure and configured to generate the reference current by mirroring the current of the third transistor, wherein the resistance value of the resistor decreases as the temperature increases.

[0010] The current source may also include: an operational amplifier configured to have a first terminal to which a reference voltage is applied, a second terminal connected to the second terminal of the third transistor, and an output terminal connected to a control terminal of the third transistor and a control terminal of the fourth transistor, and the operational amplifier is configured to operate so that the voltage of the second terminal of the operational amplifier is equal to the reference voltage.

[0011] The current source may also include: a fifth transistor, configured to have a first terminal connected to the power supply terminal and connected to the third transistor in a current mirror structure; a sixth transistor, configured to have a first terminal connected to the second terminal of the third transistor, a second terminal connected to the resistor, and a control terminal connected to the second terminal of the fifth transistor; and a seventh transistor, connected between the second terminal of the fifth transistor and the ground, and configured to have a control terminal connected to the second terminal of the sixth transistor.

[0012] The current source may also include: a fifth transistor, configured to have a first terminal connected to the power supply terminal and connected to the third transistor in a current mirror structure; a sixth transistor, connected between the second terminal of the fifth transistor and the ground in a diode manner; and a seventh transistor, configured to have a first terminal connected to the second terminal of the third transistor, a second terminal connected to the resistor, and a control terminal connected to the control terminal of the sixth transistor.

[0013] The current-voltage conversion circuit may include: a plurality of resistors connected in series between the current source and the ground; and a plurality of switches connected between one end of a corresponding resistor among the plurality of resistors and the control terminal of the second transistor. The current-voltage conversion circuit may include: a plurality of resistors connected in parallel between the current source and the ground; and a plurality of switches connected between one end of a corresponding resistor among the plurality of resistors and the current source.

[0014] The current-voltage conversion circuit may include: a plurality of diodes connected in series between the current source and ground; and a plurality of switches connected between one end of a corresponding diode among the plurality of diodes and the control terminal of the second transistor, respectively.

[0015] In one general aspect, a low noise amplifier circuit includes: a common source transistor configured to amplify an input radio frequency (RF) signal and output the amplified RF signal; a common gate transistor connected to the common source transistor in a common source and common gate structure, the common gate transistor configured to operate based on a bias voltage input to a control terminal and configured to amplify the amplified RF signal output from the common source transistor and output a signal obtained by amplifying the amplified RF signal; and a bias circuit configured to generate a reference current through a power supply voltage and configured to generate the bias voltage using the reference current.

[0016] The bias circuit may include: a current source configured to receive the power supply voltage and configured to generate the reference current; and a current-voltage conversion circuit configured to convert the reference current into the bias voltage and configured to provide the bias voltage to the control terminal of the common-gate transistor, wherein the current source is configured to increase the amplitude of the reference current as the temperature increases.

[0017] The current source may include: a third transistor configured to have a first terminal connected to a power supply terminal supplying the power supply voltage and a second terminal connected to the ground through a resistor; and a fourth transistor connected to the third transistor in a current mirror structure and configured to generate the reference current by mirroring the current of the third transistor, wherein the resistance value of the resistor decreases as the temperature increases.

[0018] The current source may also include: an operational amplifier configured to have a first terminal to which a reference voltage is applied, a second terminal connected to the second terminal of the third transistor, and an output terminal connected to a control terminal of the third transistor and a control terminal of the fourth transistor, and the operational amplifier is configured to operate so that the voltage of the second terminal of the operational amplifier is equal to the reference voltage.

[0019] The current source may also include: a fifth transistor, configured to have a first terminal connected to the power supply terminal and connected to the third transistor in a current mirror structure; a sixth transistor, configured to have a first terminal connected to the second terminal of the third transistor, a second terminal connected to the resistor, and a control terminal connected to the second terminal of the fifth transistor; and a seventh transistor, connected between the second terminal of the fifth transistor and the ground, and configured to have a control terminal connected to the second terminal of the sixth transistor.

[0020] The current source may also include: a fifth transistor, configured to have a first terminal connected to the power supply terminal and connected to the third transistor in a current mirror structure; a sixth transistor, connected between the second terminal of the fifth transistor and the ground in a diode manner; and a seventh transistor, configured to have a first terminal connected to the second terminal of the third transistor, a second terminal connected to the resistor, and a control terminal connected to the control terminal of the sixth transistor.

[0021] The current-voltage conversion circuit may include a plurality of resistors connected between the current source and ground and configured to convert the reference current into the bias voltage, and the bias voltage is generated by at least one resistor among the plurality of resistors.

[0022] Other features and aspects will be readily apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a diagram schematically illustrating an example low noise amplifier circuit according to one or more embodiments.

[0024] Figure 2 It is shown Figure 1 A circuit diagram of an example of a current source is shown.

[0025] Figure 3 It is shown Figure 1 A circuit diagram of another example of a current source is shown.

[0026] Figure 4 It is shown Figure 1 A circuit diagram of another example of a current source is shown.

[0027] Figure 5 It is shown Figure 1 A circuit diagram of another example of a current source is shown.

[0028] Figure 6 It is shown Figure 1 Schematic diagram of an example of a current-to-voltage conversion circuit shown.

[0029] Figure 7 It is shown Figure 1 Schematic diagram of another example of a current-to-voltage conversion circuit shown.

[0030] Figure 8 It is shown Figure 1 Schematic diagram of another example of a current-to-voltage conversion circuit shown.

[0031] Fig. 9 is a diagram illustrating an example bias circuit with a voltage source according to one or more embodiments.

[0032] Fig.10 It shows that Fig. 9 The bias circuit shown and Figure 1 A diagram of the gate bias voltage provided by the bias circuit shown.

[0033] Fig.11 It is shown that Fig. 9 The gain characteristics of the LNA circuit shown in the bias circuit and include Figure 1 FIG. 5 is a graph of the gain characteristics of the LNA circuit shown in FIG.

[0034] Fig.12 It shows that the temperature is Fig. 9 The bias circuit shown and Figure 6 A diagram of the gate bias voltage provided by the bias circuit shown.

[0035] Fig.13 It shows the temperature including Fig. 9 The gain characteristics of the LNA circuit shown in the bias circuit and include Figure 1 FIG. 5 is a graph of the gain characteristics of the LNA circuit shown in FIG.

[0036] Throughout the drawings and detailed description, like reference numerals refer to like elements unless otherwise described. The drawings may not be drawn to scale, and the relative size, proportion, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0037] Hereinafter, although examples of the present disclosure will be described in detail with reference to the accompanying drawings, it should be noted that the examples are not limited thereto.

[0038] The following specific embodiments are provided to help the reader gain a comprehensive understanding of the methods, devices, and / or systems described herein. However, various changes, modifications, and equivalents of the methods, devices, and / or systems described herein will be readily understood after understanding the present disclosure. For example, the order of operations described herein is merely an example and is not limited to the order set forth herein, but changes may be made that will be readily understood after understanding the present disclosure, except for operations that must occur in a particular order. In addition, descriptions of features known in the art may be omitted for increased clarity and brevity.

[0039] The features described herein may be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided only to illustrate some of the many possible ways to implement the methods, devices, and / or systems described herein that will be readily understood after understanding the present disclosure.

[0040] Throughout the specification, when an element such as a layer, a region, or a substrate is described as being “on”, “connected to”, or “coupled to” another element, the element may be directly “on”, “connected to”, or “coupled to” another element, or one or more other elements may be present between them. In contrast, when an element is described as being “directly on”, “directly connected to”, or “directly coupled to” another element, there are no other elements present between them.

[0041] As used herein, the term "and / or" includes any one of the associated listed items or any combination of any two or more items; similarly, "at least one of..." includes any one of the associated listed items or any combination of any two or more items.

[0042] Although terms such as "first", "second", and "third" may be used herein to describe various members, components, regions, layers, or portions, these members, components, regions, layers, or portions are not limited by these terms. Rather, these terms are only used to distinguish one member, component, region, layer, or portion from another member, component, region, layer, or portion. Therefore, without departing from the teachings of the examples described herein, the first member, first component, first region, first layer, or first portion referred to may also be referred to as the second member, second component, second region, second layer, or second portion.

[0043] For ease of description, spatially relative terms such as "above", "above", "below", "below", etc. may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. Such spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as being "above" or "above" relative to another element will be "below" or "below" relative to the other element. Therefore, the term "above" includes both "above" and "below" orientations depending on the spatial orientation of the device. The device may also be positioned in other ways (rotated 90 degrees or in other orientations), and the spatially relative terms used herein will be interpreted accordingly.

[0044] The terms used herein are only used to describe various examples and are not used to limit the present disclosure. Unless the context clearly indicates otherwise, singular expressions (e.g., "a", "an", and "the") are also intended to include plural expressions. The terms "include", "comprises", and "have" list the presence of stated features, quantities, operations, components, elements, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, operations, components, elements, and / or combinations thereof.

[0045] Variations in the shapes shown in the drawings may occur due to manufacturing techniques and / or tolerances. Therefore, the examples described herein are not limited to the specific shapes shown in the drawings but include changes in shapes that occur during manufacturing.

[0046] Here, it should be noted that use of the term "may" with respect to examples (e.g., with respect to what an example may include or implement) means that there is at least one example that includes or implements such features, but is not limited to all examples including or implementing such features.

[0047] The features of the examples described herein may be combined in various ways that will be readily understood after understanding the present disclosure. In addition, although the examples described herein have various configurations, other configurations that will be readily understood after understanding the present disclosure are feasible.

[0048] In all one or more examples, the radio frequency (RF) signal may have a format according to random wireless and wired protocols, which are specified by the following by way of example only but not limitation: Wi-Fi (IEEE 802.11 series, etc.), WiMAX (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution Data Optimized (Ev-DO), Enhanced High Speed ​​Packet Access (HSPA+), Enhanced High Speed ​​Downlink Packet Access (HSDPA+), Enhanced High Speed ​​Uplink Packet Access (HSUPA+), Enhanced Data Rates for GSM Evolution (EDGE), Global System for Mobile Communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, third generation mobile communication technology (3G), fourth generation mobile communication technology (4G), fifth generation mobile communication technology (5G), and any other wireless protocols and wired protocols specified after the above protocols.

[0049] One or more examples may provide a bias circuit that provides a constant bias voltage and a low noise amplifier circuit that includes the bias circuit.

[0050] Figure 1 is a diagram schematically illustrating an example low noise amplifier circuit according to one or more embodiments.

[0051] Reference Figure 1 , the low noise amplifier (LNA) circuit 100 may include a transistor M1 and a transistor M2 connected between an input terminal IN and an output terminal OUT. The LNA circuit 100 may also include a coupling capacitor C1, a resistor R1, and an inductor L1.

[0052] In the LNA circuit 100 according to one or more embodiments, the transistor M1 and the transistor M2 may be connected in a cascode structure. In an example, the transistor M1 may be a common-source transistor, and the transistor M2 may be a common-gate transistor.

[0053] A gate of the transistor M1 may be connected to the input terminal IN.

[0054] A coupling capacitor C1 may be connected between a gate of the transistor M1 and the input terminal IN, and a gate bias voltage Vg1 may be applied to the gate of the transistor M1 through a resistor R1 .

[0055] The source of transistor M1 may be connected to ground, and the drain of transistor M1 may be connected to the source of transistor M2.

[0056] The drain of the transistor M2 may be connected to the output terminal OUT, and the gate bias voltage Vg2 may be applied to the gate of the transistor M2. In addition, the inductor L1 may be connected between the drain of the transistor M2 and a power supply voltage source supplying the power supply voltage VDD, and the power supply voltage VDD may be provided to the drain of the transistor M2 through the inductor L1.

[0057] The RF signal may be input to the gate of the transistor M1 through the coupling capacitor C1 , the RF signal may be amplified by the transistor M1 and the transistor M2 , and the amplified RF signal may be output to the output terminal OUT.

[0058] In an example, the bias circuit 110 may be connected to the gate of the transistor M2 , may generate a constant gate bias voltage Vg2 from a power supply voltage VDD, and may provide the gate bias voltage Vg2 to the gate of the transistor M2 .

[0059] The bias circuit 110 may include a current source 112 and a current-to-voltage conversion circuit 114 .

[0060] The current source 112 may supply a constant current through the power supply voltage VDD. In an example, the current source 112 may have a proportional to absolute temperature (PTAT) characteristic that increases the magnitude of the current as the temperature increases.

[0061] The current-voltage conversion circuit 114 may convert the current supplied from the current source 112 into a voltage, and provide the converted voltage to the gate of the transistor M2 as a gate bias voltage Vg2 .

[0062] Therefore, even if the power supply voltage VDD changes, the bias circuit 110 can generate a constant current through the current source 112, and thus can provide a constant gate bias voltage Vg2 to the gate of the transistor M2 even when various power supply voltages VDD are supplied.

[0063] Generally, the gain characteristic of the LNA circuit decreases as the temperature increases, and the gain characteristic increases as the temperature decreases. Therefore, by increasing the magnitude of the current as the temperature increases, the bias circuit 110 according to the embodiment can provide a larger gate bias voltage Vg2 as the temperature increases, thereby compensating for the performance change (e.g., performance loss) of the LNA circuit caused by the temperature increase.

[0064] Figure 2 It is shown Figure 1 A circuit diagram of an example of a current source is shown.

[0065] Reference Figure 2 , the current source 200 may include an operational amplifier 210, a transistor M3, a transistor M4, and a resistor R2.

[0066] exist Figure 2 In the embodiment, transistors M3 and M4 may be implemented as transistors such as, but not limited to, field effect transistors (FETs) and bipolar transistors. Figure 2 , the transistors M3 and M4 are shown as p-type transistors. However, this is only an example, and the transistors M3 and M4 may be n-type transistors.

[0067] In the following description, for convenience, it is assumed that transistors M3 and M4 are FETs. However, this is only an example, and transistors M3 and M4 can be replaced by other transistors. In the example, the gate of the transistor can play the role of a control terminal, so the gate of the transistor can be annotated as a "control terminal". Since the source of the transistor is one terminal of the transistor, the source of the transistor can be annotated as a "first terminal" or a "second terminal". Since the drain of the transistor is another terminal of the transistor, the drain of the transistor can be labeled as a "second terminal" or a "first terminal".

[0068] The operational amplifier 210 may have a non-inverting terminal +, an inverting terminal −, and an output terminal. A reference voltage VREF may be input to the non-inverting terminal + of the operational amplifier 210, and an inverting terminal − of the operational amplifier 210 may be connected to a node N1.

[0069] Due to the operation of the operational amplifier 210, the voltage of the inverting terminal - and the reference voltage VREF input to the non-inverting terminal + can be the same, so the voltage VOUT output from the operational amplifier 210 can be set so that the voltage of the non-inverting terminal + and the voltage of the inverting terminal - can be the same voltage.

[0070] The output terminal of the operational amplifier 210 may be connected to the gate of the transistor M3 and the gate of the transistor M4. That is, the voltage VOUT output from the operational amplifier 210 may be applied to the gate of the transistor M3 and the gate of the transistor M4. The source of the transistor M3 and the source of the transistor M4 may be connected to the power supply voltage VDD. In an example, the power supply voltage VDD may be a battery voltage.

[0071] The drain of the transistor M3 may be connected to the inverting terminal − of the operational amplifier 210 through the node N1 .

[0072] Resistor R2 may be connected between node N1 and ground.

[0073] The drain current IM3 of the transistor M3 may have the relationship of the following Equation 1.

[0074] Formula 1:

[0075]

[0076] Since the gate of transistor M3 and the gate of transistor M4 are connected to each other, and the gate of transistor M3 and the gate of transistor M4 are connected to the output terminal of operational amplifier 210, when transistors M3 and M4 operate in the saturation region, transistors M3 and M4 may have a current mirror structure. Therefore, the current IREF output by transistor M4 may have the relationship of the following formula 2.

[0077] Formula 2:

[0078] IREFK1XIM3

[0079] In Formula 2, K1 may represent a ratio of sizes (eg, but not limited to, line widths) of transistor M3 and transistor M4. In an example, if the size of transistor M4 is 10 times that of transistor M3, K1 may be 10.

[0080] Therefore, even if the power supply voltage VDD changes, the current source 200 can also provide a constant current IREF. In other words, even if the power supply voltage VDD changes, the reference voltage VREF input to the non-inverting terminal + has a fixed value, so even if the power supply voltage VDD changes, the drain current IM3 of the transistor M3 does not change, so the current IREF can also have a constant value.

[0081] In addition, in an example, the resistor R2 may have a temperature coefficient satisfying the PTAT characteristic. Therefore, the performance variation of the LNA circuit 100 with respect to temperature may be compensated. In an example, the current source 200 may increase the current IREF as the temperature increases, and according to this characteristic, the resistance value of the resistor R2 may decrease as the temperature increases.

[0082] Figure 3 It is shown Figure 1 A circuit diagram of another example of a current source is shown.

[0083] Reference Figure 3 , the current source 300 may include a transistor M5, a transistor M6, a transistor M7, a transistor M8, a transistor M9 and a resistor R3.

[0084] Various transistors such as, but not limited to, field effect transistors (FETs) and bipolar transistors may be used as the transistors M5 , M6 , M7 , M8 , and M9 .

[0085] In an example, transistors M5 and M6 may be n-type transistors, and transistors M7, M8, and M9 may be p-type transistors. This is an example, and transistors M5, M6, M7, M8, and M9 may be n-type transistors. Figure 3 Transistors in different types of transistors.

[0086] The power supply voltage VDD may be input to the source of the transistor M8. In addition, the power supply voltage VDD may also be input to the source of the transistor M7 and the source of the transistor M9.

[0087] The gate of transistor M8, the gate of transistor M7 and the gate of transistor M9 are connected together, and the gate of transistor M8 and the drain of transistor M8 are connected to each other. That is, transistor M8 can be connected in the form of a diode. Therefore, transistors M8 and M7 and transistors M8 and M9 can have a current mirror structure, and transistor M8 can supply current I2 from power supply voltage VDD to transistor M7 and transistor M9.

[0088] The drain of transistor M7 may be connected to the drain of transistor M5, and the source of transistor M5 may be connected to ground. The drain of transistor M8 may be connected to the drain of transistor M6, and the source of transistor M6 may be connected to ground. Resistor R3 may be connected between the source of transistor M6 and ground. In addition, the gate of transistor M5 may be connected to the source of transistor M6, and the gate of transistor M6 may be connected to the drain of transistor M5.

[0089] When the voltage between the gate of transistor M5 and the source of transistor M5 is V GS1 When , the current I2 flowing through the transistor M8 may have the relationship of the following formula 3.

[0090] Formula 3:

[0091]

[0092] The voltage V between the gate of transistor M5 and the source of transistor M5 GS1and the current I1 flowing through the transistor M7 may have the relationship shown in the following Formula 4.

[0093] Formula 4:

[0094]

[0095] In the example, W is the gate width of transistor M5, and L is the gate length of transistor M5. ox can represent the gate oxide film capacitance per unit area, and μ n It can represent the electron mobility. V TH1 may represent the threshold voltage of transistor M5.

[0096] Equation 4 can be summarized as the following Equation 5, and the current I2 flowing through the transistor M8 can be expressed as the following Equation 6.

[0097] Formula 5:

[0098]

[0099] Formula 6:

[0100]

[0101] Transistors M8 and M7 have a current mirror structure, and if transistors M8 and M7 are of the same size, the magnitudes of currents I1 and I2 may be the same. In addition, if transistors M8 and M9 are of the same size, the magnitude of current IREF may be equal to the magnitude of current I2. Therefore, current IREF flowing through transistor M9 may be expressed as Equation 7.

[0102] Formula 7:

[0103]

[0104] In an example, β1 may be equal to β in Equation 8.

[0105] Formula 8:

[0106]

[0107] As can be seen from Equation 7, since the current IREF may not be affected by the power supply voltage VDD, the current source 300 may provide a constant current IREF even if the power supply voltage VDD changes.

[0108] In addition, in an example, the resistor R3 may have a temperature coefficient satisfying the PTAT characteristic. Therefore, the performance variation of the LNA circuit 100 with respect to temperature may be compensated.

[0109] Figure 4 It is shown Figure 1 A circuit diagram of another example of a current source is shown.

[0110] Reference Figure 4 , the current source 400 may include a transistor M10 , a transistor M11 , a transistor M12 , a transistor M13 , a transistor M14 and a resistor R4 .

[0111] Various transistors such as, but not limited to, field effect transistors (FETs) and bipolar transistors may be used as the transistor M10 , the transistor M11 , the transistor M12 , the transistor M13 , and the transistor M14 .

[0112] In an example, transistors M10 and M11 may be n-type transistors, and transistors M12, M13, and M14 may be p-type transistors. This is only an example, and transistors M10, M11, M12, M13, and M14 may be Figure 4 Transistors in different types of transistors.

[0113] The power supply voltage VDD may be input to the source of the transistor M13. In addition, the power supply voltage VDD may also be input to the source of the transistor M12 and the source of the transistor M14.

[0114] The gate of transistor M12, the gate of transistor M13 and the gate of transistor M14 are connected together, and the gate of transistor M13 and the drain of transistor M13 are connected to each other. That is, transistor M13 can be connected in the form of a diode. Therefore, transistors M13 and M12 and transistors M13 and M14 can have a current mirror structure, and transistor M13 can supply current I from power supply voltage VDD to transistor M12 and transistor M14.

[0115] The drain of transistor M12 may be connected to the drain of transistor M10, and the source of transistor M10 may be connected to ground. In addition, the drain of transistor M10 may be connected to the gate of transistor M10. That is, transistor M10 may be connected in the form of a diode.

[0116] The drain of transistor M13 may be connected to the drain of transistor M11, and the source of transistor M11 may be connected to ground. Resistor R4 may be connected between the source of transistor M11 and ground. The gate of transistor M10 may be connected to the gate of transistor M11. Therefore, transistor M10 and transistor M11 may have a current mirror structure.

[0117] When the voltage between the gate of transistor M10 and the source of transistor M10 is V GS1 And the voltage between the gate of transistor M11 and the source of transistor M11 is V GS2 When , the current I and the resistance of the resistor R4 may have the relationship of the following formula 9.

[0118] Formula 9:

[0119] VGS1VGs2+IR

[0120] In Formula 9, R may represent the resistance value of the resistor R4.

[0121] Equation 9 can be converted into the following equation 10.

[0122] Formula 10:

[0123]

[0124] In an example, β1 may be a size parameter of the transistor M10, β2 may be a size parameter of the transistor M11, and β1 and β2 may be obtained as in Equation 8. VTH may represent a threshold voltage of the transistor M10. K may represent a size ratio of the transistor M11 to the transistor M10.

[0125] If the transistors M14 and M13 have the same size, the current IREF may be equal to the current I and may be expressed as the following Equation 11.

[0126] Formula 11:

[0127]

[0128] As can be seen from Equation 11, since the current IREF may not be affected by the power supply voltage VDD, the current source 400 may supply a constant current IREF even if the power supply voltage VDD changes.

[0129] In addition, in an example, the resistor R4 may have a temperature coefficient satisfying the PTAT characteristic. Therefore, the performance variation of the LNA circuit 100 with respect to temperature may be compensated.

[0130] In the example, when Figure 2 The current source 200 shown, Figure 3 The current source 300 and Figure 4 The current source 400 shown generates a current IREF with a small amplitude, which can be obtained by connecting a current mirror circuit with Figure 2 The current source 200 shown, Figure 3 The current source 300 and Figure 4 The circuit combination of the current source 400 shown is used to increase the amplitude of the current IREF. Figure 5 This example is shown in .

[0131] Figure 5 It is shown Figure 1 A circuit diagram of another example of a current source is shown.

[0132] Reference Figure 5 , the current source 500 may include a current generating circuit 510 and a current mirror circuit 520 .

[0133] The current generating circuit 510 may be Figure 2 The current source 200 shown, Figure 3 The current source 300 and Figure 4 One of the current sources 400 shown. Figure 5 Shows Figure 4 The current source 400 is shown as the current generating circuit 510 .

[0134] The current mirror circuit 520 may mirror the current IREF1 generated by the current generating circuit 510 to generate a current IREF that is greater than the current IREF1 .

[0135] The current mirror circuit 520 may include a plurality of mirror transistors TRm1 to TRm7 , switch elements SW1 to SW3 , and transistors TRoff1 and TRoff2 .

[0136] The mirror transistors TRm1 to TRm5 may be n-type transistors, and the mirror transistors TRm6 and TRm7 may be p-type transistors. The transistor TRoff1 may be an n-type transistor, and the transistor TRoff2 may be a p-type transistor. This may be an example.

[0137] The drain of the mirror transistor TRm1 may be connected to the drain of the transistor M14 in the current generating circuit 510, the source of the mirror transistor TRm1 may be connected to the ground, and the drain and gate of the mirror transistor TRm1 may be connected to each other. That is, the mirror transistor TRm1 may be connected in the form of a diode.

[0138] The gates of the mirror transistors TRm2 to TRm5 are connected to the gate of the mirror transistor TRm1. The drains of the mirror transistors TRm2 to TRm5 may be connected to the node N2, and the sources of the mirror transistors TRm2 to TRm5 may be connected to the ground. In an example, the switch element SW1 may be connected between the drain of the mirror transistor TRm3 and the node N2, the switch element SW2 may be connected between the drain of the mirror transistor TRm4 and the node N2, and the switch element SW3 may be connected between the drain of the mirror transistor TRm5 and the node N2. The magnitude of the current IREF may be adjusted according to the on operation or off operation of each of the switch elements SW1 to SW3.

[0139] The power supply voltage VDD may be input to the source of the mirror transistor TRm6. In addition, the power supply voltage VDD may also be input to the source of the mirror transistor TRm7.

[0140] The drain of the mirror transistor TRm6 may be connected to the node N2, the gate of the mirror transistor TRm7 may be connected to the gate of the mirror transistor TRm6, and the drain of the mirror transistor TRm6 and the gate of the mirror transistor TRm6 may be connected to each other. The current IREF may be output through the drain of the mirror transistor TRm7.

[0141] Since the mirror transistor TRm6 may be connected in the form of a diode, the mirror transistor TRm6 and the mirror transistor TRm7 may have a current mirror structure, and the mirror transistor TRm6 may supply the current Im6 from the power supply voltage VDD to the mirror transistor TRm7.

[0142] Here, the current Im6 is the sum of the currents Im2 , Im3 , Im4 , and Im5 flowing through the mirror transistors TRm2 to TRm5 , and the magnitude of the current Im6 may be adjusted according to the on operation or off operation of each of the switch elements SW1 to SW3 .

[0143] Currents Im2 to Im5 flowing through the mirror transistors TRm2 to TRm5 may be determined based on the current Im1 flowing through the mirror transistor TRm1 .

[0144] The current Im1 flowing through the mirror transistor TRm1 may be determined according to the current IREF1 output from the current generating circuit 510 .

[0145] In an example, if the mirror transistors TRm1 to TRm7 are the same size and the switch elements SW1 to SW3 are all turned on, the magnitude of the current IREF may be four times the magnitude of the current Im1.

[0146] The transistor TRoff1 may be connected between the gate of the mirror transistor TRm1 and the ground, and the transistor TRoff2 may be connected between the power supply voltage VDD and the gate of the mirror transistor TRm6 .

[0147] The transistors TRoff1 and TRoff2 may block the supply of the current IREF in the shutdown mode of the LNA circuit 100. In the shutdown mode of the LNA circuit 100, the transistors TRoff1 and TRoff2 may be turned on to turn off the bias circuit 110. When the LNA circuit 100 is turned off, the transistors TRoff1 and TRoff2 may be turned on, and thus 0 V may be applied to the gates of the mirror transistors TRm1 to TRm5, and the power supply voltage VDD may be applied to the mirror transistors TRm6 and TRm7, and thus all the mirror transistors TRm1 to TRm7 may be turned off.

[0148] Figure 6 It is shown Figure 1 Schematic diagram of an example of a current-to-voltage conversion circuit shown.

[0149] Reference Figure 6 , the current-voltage conversion circuit 600 may include a plurality of resistors R5 to R8, a plurality of switches SW4 to SW7, a resistor Rf, and a capacitor Cf.

[0150] A plurality of resistors R5 to R8 may be connected in series between an output terminal of the current source 112 and ground.

[0151] The switch SW4 may be connected between the first end of the resistor R5 (ie, the output terminal of the current source 112 ) and the node N3 .

[0152] The switch SW5 may be connected between the second end of the resistor R5 (ie, the first end of the resistor R6 ) and the node N3 .

[0153] The switch SW6 may be connected between the second end of the resistor R6 (ie, the first end of the resistor R7 ) and the node N3 .

[0154] The switch SW7 may be connected between the second end of the resistor R7 (ie, the first end of the resistor R8 ) and the node N3 .

[0155] The resistor Rf may be connected between the node N3 and the node N4, and the capacitor Cf may be connected between the node N4 and the ground. The node N4 may be an output terminal of the current-voltage conversion circuit 600 and may be connected to Figure 1 The gate of transistor M2 is shown.

[0156] The current-voltage conversion circuit 600 can generate a gate bias voltage Vg2 applied to the gate of the transistor M2 through the input current IREF, and can adjust the voltage amplitude of the gate bias voltage Vg2 applied to the gate of the transistor M2 according to the on or off operation of the switches SW4 to SW7.

[0157] In an example, if a constant current IREF from the current source 112 is input to the current-voltage conversion circuit 600 and only the switch SW4 is turned on, the gate bias voltage Vg2 applied to the gate of the transistor M2 may be expressed as the following Equation 12.

[0158] Formula 12:

[0159] Vg2=(R5+R6+R7+R8)×IREF

[0160] As shown in Equation 12, if the current IREF is constant, the gate bias voltage Vg2 applied to the gate of the transistor M2 may have a constant voltage regardless of the power supply voltage VDD.

[0161] Figure 7 It is shown Figure 1 Schematic diagram of another example of a current-to-voltage conversion circuit shown.

[0162] Reference Figure 7 , the current-voltage conversion circuit 700 may include a plurality of resistors R9 , R10 , and R11 , a plurality of switches SW9 , SW10 , and SW11 , a resistor Rf, and a capacitor Cf.

[0163] The resistors R9 , R10 , and R11 may each be connected in series between the output terminal of the current source 112 and the ground, that is, the resistors R9 , R10 , and R11 may be connected in parallel between the output terminal of the current source 112 and the ground.

[0164] Switch SW9 may be connected between node N3 (ie, the output terminal of current source 112 ) and resistor R9 , switch SW10 may be connected between the output terminal of current source 112 and resistor R10 , and switch SW11 may be connected between the output terminal of current source 112 and resistor R11 .

[0165] The resistor Rf may be connected between the output terminal of the current source 112 and the node N4, and the capacitor Cf may be connected between the node N4 and the ground. The node N4 may be the output terminal of the current-voltage conversion circuit 700 and may be connected to the Figure 1 The gate of transistor M2 is shown.

[0166] The current-voltage conversion circuit 700 can generate a gate bias voltage Vg2 applied to the gate of the transistor M2 through the input current IREF, and can adjust the voltage amplitude of the gate bias voltage Vg2 applied to the gate of the transistor M2 according to the on operation or off operation of the switches SW9, SW10 and SW11.

[0167] In an example, if a constant current IREF from the current source 112 is input to the current-voltage conversion circuit 700 and only the switch SW9 is turned on, the gate bias voltage Vg2 applied to the gate of the transistor M2 may be expressed as the following Equation 13.

[0168] Formula 13:

[0169] Vg2=R9×IREF

[0170] In another example, if a constant current IREF from the current source 112 is input to the current-voltage conversion circuit 700 and the switches SW9 and SW10 are turned on, the gate bias voltage Vg2 applied to the gate of the transistor M2 may be expressed as the following Equation 14.

[0171] Formula 14:

[0172]

[0173] As shown in Equation 13 and Equation 14, if the current IREF is constant, the gate bias voltage Vg2 applied to the gate of the transistor M2 may have a constant voltage regardless of the power supply voltage VDD.

[0174] Figure 8 It is shown Figure 1 Schematic diagram of another example of a current-to-voltage conversion circuit shown.

[0175] Reference Figure 8 , the current-to-voltage conversion circuit 800 may include a plurality of diode-connected transistors D1, D2, D3, and D4, instead of Figure 6 A plurality of resistors R5, R6, R7, and R8 are shown. That is, a plurality of diode-connected transistors D1, D2, D3, and D4 may be connected in series between the output terminal of the current source 112 and ground.

[0176] The current-voltage conversion circuit 800 can generate a gate bias voltage Vg2 applied to the gate of the transistor M2 by the input current IREF, and can adjust the voltage amplitude of the gate bias voltage Vg2 applied to the gate of the transistor M2 according to the on operation or off operation of the switches SW4 to SW7. Here, if the current IREF is constant, the gate bias voltage Vg2 applied to the gate of the transistor M2 can have a constant voltage regardless of the power supply voltage VDD.

[0177] Fig. 9 is a diagram illustrating an example of a bias circuit having a voltage source according to one or more embodiments.

[0178] like Fig. 9 As shown, the bias circuit 900 may include a voltage source 910 and a voltage divider circuit 920 .

[0179] The voltage source 910 may supply the voltage Vin from the power supply voltage VDD. In one example, the voltage source 910 may generate the voltage Vin from the power supply voltage VDD using a low dropout (LDO) circuit and provide the voltage Vin to the voltage dividing circuit 920.

[0180] The voltage divider circuit 920 can convert the voltage Vin supplied from the voltage source 910 into a predetermined voltage and provide the converted voltage as the gate bias voltage Vg2 to the gate of the transistor M2. Figure 6 The current-to-voltage conversion circuit 600 shown is the same or similar.

[0181] Unlike the previously described embodiments, Fig. 9 The bias circuit 900 shown may use a voltage source 910 and may provide a gate bias voltage Vg2 via a voltage divider circuit 920 .

[0182] However, when the voltage source 910 is used, the gate bias voltage Vg2 may vary as the power supply voltage VDD changes.

[0183] In the example, when the switch SW5 is turned on and the remaining switches SW4, SW6 and SW7 are turned off, Fig. 9 The gate bias voltage Vg2 provided by the bias circuit 900 shown can be expressed as the following equation 15.

[0184] Formula 15:

[0185]

[0186] As shown in Equation 15, the output of the bias circuit 900 may depend on the voltage Vin supplied from the voltage source 910, and when the power supply voltage VDD changes, the voltage Vin may change, and thus the gate bias voltage Vg2 may also change.

[0187] Typically, the power supply voltage VDD may be 1.2V or 1.8V, and the bias circuit 900 may provide a gate bias voltage Vg2 depending on the power supply voltage VDD. Therefore, it may be difficult to supply a constant voltage to the gate of the transistor M2. In contrast, if a current source may be used as in the embodiment, a constant current IREF may be provided even if the power supply voltage VDD changes, and thus a constant gate bias voltage may be supplied to the gate of the transistor M2.

[0188] Fig.10 It shows that Fig. 9 The bias circuit shown and Figure 1 A diagram of the gate bias voltage provided by the bias circuit shown.

[0189] exist Fig.10 In the figure, the gate bias voltage P1 can represent the gate bias voltage when the power supply voltage VDD is 1.2V. Fig. 9 The gate bias voltage P2 can represent the voltage output by the bias circuit 900 when the power supply voltage VDD is 1.8V. Fig. 9 The gate bias voltage P3 can represent the voltage output by the bias circuit 900 when the power supply voltage VDD is 1.2V. Figure 1 The gate bias voltage P4 can represent the voltage output by the bias circuit 110 when the power supply voltage VDD is 1.8V. Figure 1 Here, the voltage output by the bias circuit 110 is Figure 6 The current-to-voltage conversion circuit 600 shown in FIG. 1 is used as the current-to-voltage conversion circuit 114, and Figure 3 The current source 300 shown is used as the current source 112 .

[0190] like Fig.10 As shown, in Fig. 9In the example of the bias circuit 900 shown, it can be seen that as the power supply voltage VDD changes from 1.2 V to 1.8 V, the gate bias voltage changes from a gate bias voltage P1 of about 1.01 V to a gate bias voltage P3 of about 1.52 V. In contrast, in the bias circuit 110 according to the embodiment, the gate bias voltages P2 and P4 can be considered constant at about 0.98 V regardless of how the power supply voltage VDD changes.

[0191] Fig.11 It is shown that Fig. 9 The gain characteristics of the LNA circuit shown in the bias circuit and include Figure 1 FIG. 5 is a graph of the gain characteristics of the LNA circuit shown in FIG.

[0192] exist Fig.11 In the embodiment, the gain characteristic 20 may be expressed as including Fig. 9 The gain characteristic of the LNA circuit of the bias circuit 900 shown in FIG. 4 at a power supply voltage VDD of 1.2V may be represented by a gain characteristic 40 including: Figure 1 The gain characteristic of the LNA circuit of the bias circuit 110 shown in FIG. 1 is at a power supply voltage VDD of 1.2V. The gain characteristic 10 may include Fig. 9 The gain characteristic of the LNA circuit of the bias circuit 900 shown in FIG. 3 under the power supply voltage VDD of 1.8V, the gain characteristic 30 may be represented by Figure 1 The gain characteristic of the LNA circuit of the bias circuit 110 shown in FIG. 1 is at a power supply voltage VDD of 1.8V. Figure 6 The current-to-voltage conversion circuit 600 shown in FIG. 1 is used as the current-to-voltage conversion circuit 114, and Figure 3 The current source 300 shown is used as the current source 112 .

[0193] like Fig.11 As shown, it can be seen that the LNA circuit including the bias circuit 110 has a smaller gain variation than the LNA circuit including the bias circuit 900 .

[0194] In addition, in the example of the bias circuit 900 that uses the voltage of the voltage source 910 by dividing the voltage of the voltage source 910 by resistance, it is impossible to compensate for the performance variation of the LNA circuit according to temperature variation because the resistance characteristic also changes according to temperature.

[0195] In contrast, as in an embodiment, the bias circuit 110 having the current source 112 may be implemented to operate with a PTAT characteristic to compensate for performance variations with respect to temperature. Thus, variations in the performance of the LNA circuit according to temperature may be reduced.

[0196] In the example, Figure 3 The temperature coefficient of the current IREF of the current source 300 shown can be expressed as the following equation 16.

[0197] Formula 16:

[0198]

[0199] In the example, TCR can be expressed as Figure 3 The temperature coefficient of resistor R3 is shown. T may represent temperature.

[0200] As shown in equation 16, the temperature coefficient TC of the current IREF is I It can be determined by the temperature coefficient of the resistor R3. Therefore, by using the resistor R3 that can provide the desired performance according to the temperature change, the current source 300 operating with the PTAT characteristic can be realized, and thus the performance change of the LNA circuit according to the temperature can be reduced.

[0201] Fig.12 It shows that the temperature is Fig. 9 The bias circuit shown and Figure 6 The bias circuit shown provides a diagram of the gate bias voltage, and Fig.13 It shows the temperature including Fig. 9 The bias circuit shown in the LNA circuit and includes Figure 1 FIG. 5 is a graph of the gain characteristics of the LNA circuit shown in FIG.

[0202] exist Fig.12 and Fig.13 In this example, a power supply voltage VDD of 1.2V is used.

[0203] like Fig.12 As shown, bias circuit 110 can provide a gate bias voltage 60 that increases as the temperature increases, and bias circuit 900 can provide a gate bias voltage 50 that gradually decreases as the temperature increases. Fig.13 As shown, it can be seen that as the temperature increases, including Figure 1 The variation of the gain characteristic 80 of the LNA circuit of the bias circuit 110 shown is less than that of the circuit including Fig. 9 The bias circuit 900 is shown to change the gain characteristic 70 of the LNA circuit.

[0204] In addition, when using Fig. 9 When the voltage source 910 is shown, an LDO circuit that generates a constant voltage or a circuit having an operation similar to that of the LDO circuit must be used to reduce the characteristic deviation depending on the power supply voltage, however, this may reduce the voltage, which may result in performance loss. In addition, because the LDO circuit occupies a large area, it is difficult to miniaturize the integrated circuit (IC).

[0205] In contrast, if the current source 112 is used as in the embodiment, a constant gate voltage can be supplied without an LDO circuit, and it can also be beneficial to reduce the design area of ​​the LNA circuit.

[0206] According to at least one embodiment, even if the power supply voltage changes, a constant bias voltage can be provided by providing a constant reference current. Therefore, even if the power supply voltage changes, the change in the gain characteristic of the low noise amplifier circuit can be reduced.

[0207] In addition, according to at least one embodiment, a bias voltage adjusted according to temperature variation can be provided by adjusting the amplitude of a reference current according to temperature variation. As a result, variation in gain characteristics of a low noise amplifier circuit according to temperature can be reduced.

[0208] Although specific examples have been shown and described above, it will be readily understood after understanding the present disclosure that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein will be understood only as descriptive, and not for limiting purposes. The description of the features or aspects in each example will be considered applicable to similar features or aspects in other examples. If the described techniques are performed in a different order, and / or if the components in the described system, architecture, device, or circuit are combined in a different manner and / or replaced or supplemented by other components or their equivalents, the components in the described system, architecture, device, or circuit may be obtained. Therefore, the scope of the present disclosure is not limited by specific embodiments, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents will be interpreted as being included in the present disclosure.

Claims

1. A bias circuit, the bias circuit being connected to a first transistor and configured to provide a bias voltage to a second transistor, the first transistor being configured to amplify an input radio frequency signal, the second transistor amplifying an output radio frequency signal of the first transistor, the bias circuit comprising: a current source configured to receive a supply voltage and generate a reference current; as well as The current-voltage conversion circuit is configured to convert the reference current into the bias voltage and provide the bias voltage to the control terminal of the second transistor.

2. The bias circuit according to claim 1, wherein: The current source is configured to increase the magnitude of the reference current as temperature increases.

3. The bias circuit according to claim 1, wherein: The current source comprises: a third transistor configured to have a first terminal connected to a power supply terminal supplying the power supply voltage and a second terminal connected to a ground through a resistor; and a fourth transistor connected to the third transistor in a current mirror configuration and configured to generate the reference current by mirroring the current of the third transistor, The resistance value of the resistor decreases as the temperature increases.

4. The bias circuit according to claim 3, wherein: The current source further comprises: An operational amplifier is configured to have a first terminal to which a reference voltage is applied, a second terminal connected to the second terminal of the third transistor, and an output terminal connected to a control terminal of the third transistor and a control terminal of the fourth transistor, and the operational amplifier is configured to operate so that a voltage of the second terminal of the operational amplifier is equal to the reference voltage.

5. The bias circuit of claim 3, wherein: The current source further comprises: a fifth transistor configured to have a first terminal connected to the power supply terminal and connected to the third transistor in a current mirror configuration; a sixth transistor configured to have a first terminal connected to the second terminal of the third transistor, a second terminal connected to the resistor, and a control terminal connected to the second terminal of the fifth transistor; and A seventh transistor is connected between the second terminal of the fifth transistor and the ground and is configured to have a control terminal connected to the second terminal of the sixth transistor.

6. The bias circuit of claim 3, wherein: The current source further comprises: a fifth transistor configured to have a first terminal connected to the power terminal and connected to the third transistor in a current mirror configuration; a sixth transistor connected in a diode manner between the second terminal of the fifth transistor and the ground; and A seventh transistor is configured to have a first terminal connected to the second terminal of the third transistor, a second terminal connected to the resistor, and a control terminal connected to the control terminal of the sixth transistor.

7. The bias circuit of claim 1 , wherein: The current-voltage conversion circuit comprises: a plurality of resistors connected in series between the current source and ground; and A plurality of switches are respectively connected between one end of a corresponding resistor among the plurality of resistors and the control terminal of the second transistor.

8. The bias circuit of claim 1, wherein: The current-voltage conversion circuit comprises: a plurality of resistors connected in parallel between the current source and ground; and A plurality of switches are respectively connected between one end of a corresponding resistor among the plurality of resistors and the current source.

9. The bias circuit of claim 1 , wherein: The current-voltage conversion circuit comprises: a plurality of diodes connected in series between the current source and ground; and A plurality of switches are respectively connected between one end of a corresponding diode among the plurality of diodes and the control terminal of the second transistor.

10. A low noise amplifier circuit comprising: a common-source transistor configured to amplify an input radio frequency signal and output the amplified radio frequency signal; a common-gate transistor connected to the common-source transistor in a common-source common-gate structure, the common-gate transistor being configured to operate based on a bias voltage input to a control terminal and configured to amplify the amplified radio frequency signal output from the common-source transistor and output a signal obtained by amplifying the amplified radio frequency signal; as well as The bias circuit is configured to generate a reference current through a power supply voltage and is configured to generate the bias voltage using the reference current.

11. The low noise amplifier circuit according to claim 10, wherein: The bias circuit comprises: a current source configured to receive the power supply voltage and configured to generate the reference current; and a current-voltage conversion circuit configured to convert the reference current into the bias voltage and configured to provide the bias voltage to a control terminal of the common-gate transistor, The current source is configured to increase the amplitude of the reference current as the temperature increases.

12. The low noise amplifier circuit according to claim 11, wherein: The current source comprises: a third transistor configured to have a first terminal connected to a power supply terminal supplying the power supply voltage and a second terminal connected to a ground through a resistor; and a fourth transistor connected to the third transistor in a current mirror configuration and configured to generate the reference current by mirroring the current of the third transistor, The resistance value of the resistor decreases as the temperature increases.

13. The low noise amplifier circuit according to claim 12, wherein: The current source further comprises: An operational amplifier is configured to have a first terminal to which a reference voltage is applied, a second terminal connected to the second terminal of the third transistor, and an output terminal connected to a control terminal of the third transistor and a control terminal of the fourth transistor, and the operational amplifier is configured to operate so that a voltage of the second terminal of the operational amplifier is equal to the reference voltage.

14. The low noise amplifier circuit according to claim 12, wherein: The current source further comprises: a fifth transistor configured to have a first terminal connected to the power supply terminal and connected to the third transistor in a current mirror configuration; a sixth transistor configured to have a first terminal connected to the second terminal of the third transistor, a second terminal connected to the resistor, and a control terminal connected to the second terminal of the fifth transistor; and A seventh transistor is connected between the second terminal of the fifth transistor and the ground and is configured to have a control terminal connected to the second terminal of the sixth transistor.

15. The low noise amplifier circuit according to claim 12, wherein: The current source further comprises: a fifth transistor configured to have a first terminal connected to the power terminal and connected to the third transistor in a current mirror configuration; a sixth transistor connected in a diode manner between the second terminal of the fifth transistor and the ground; and A seventh transistor is configured to have a first terminal connected to the second terminal of the third transistor, a second terminal connected to the resistor, and a control terminal connected to the control terminal of the sixth transistor.

16. The low noise amplifier circuit according to claim 11, wherein: The current-voltage conversion circuit includes a plurality of resistors connected between the current source and ground and configured to convert the reference current into the bias voltage, and The bias voltage is generated by at least one resistor among the plurality of resistors.

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