Dual-power output circuit for preventing abnormal jump in power-off process and working method
By designing a dual power output circuit including level converter, driving circuit, core logic voltage monitoring circuit and comparator, the problem of abnormal jump in the output signal during power down by the dual power output circuit is solved, the stable maintenance of the output signal is achieved, and the stability and reliability of the power down process is improved.
Patent Information
- Application Number
- CN202411728277.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-28
- Publication Date
- 2025-04-29
AI Technical Summary
In the dual power output circuit, if the core logic voltage is powered off first, and the input and output unit voltage is powered off later, the output voltage may be uncontrollable, causing abnormal jumps in the output signal, affecting the normal operation of external devices.
Design a dual power output circuit including a level converter, a driving circuit, a core logic voltage monitoring circuit and a comparator. By comparing the bandgap reference output reference voltage with the core logic monitoring output voltage, the working mode of the level converter is controlled to ensure that when the core logic voltage is powered off first, the input and output unit voltage is powered off later, and the output signal state remains stable.
It effectively prevents abnormal jumps of the output signal during power-down, ensures normal operation of external devices connected to the output circuit, and improves the stability and reliability of the power-down process.
Smart Images
Figure CN119906410A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductor integrated circuits and relates to a dual power supply output circuit and a working method for preventing abnormal jumps during power-off. Background Art
[0002] The input and output circuit is an indispensable module in the design of monolithic integrated circuits. Its main function is to complete the interaction between the internal signals of the chip and the external signals. Its main functions include enhancing the output signal driving capability, identifying the high and low levels of the input signal, improving the circuit's own ESD resistance, and realizing level conversion and level transmission matching. For very large-scale integrated circuits, in order to improve the performance of the core logic circuit and reduce the static power consumption and dynamic power consumption of the circuit, the factory core logic voltage adopts a lower operating voltage, such as 1.0V and 1.2V; at the same time, in order to increase the output interface circuit driving capability, the input and output unit voltage adopts a higher operating voltage, such as 3.3V and 2.5V. Therefore, the output unit of the very large-scale integrated circuit generally adopts a dual power supply method.
[0003] For output circuit units that use dual power supply, the power supply includes the core logic voltage VDDC and the input and output unit voltage VDDIO, and the output signal state is closely related to the core logic voltage. The power supply design of integrated circuit board-level application systems is usually complex, and the power-off process is different for different application environments and system designs. For dual power output circuits, if the core logic voltage VDDC is powered off first and the input and output unit voltage VDDIO is powered off later during the system power-off process, the output voltage will be uncontrolled, resulting in abnormal jumps in the output signal, so that the external devices connected to the output circuit may perform erroneous operations, such as memory content being rewritten, and the device executing erroneous instructions. At present, some dual power output circuits lack the design of output state control during the power-off process. Although some dual power output circuits include the output state control function during the power-off process, they have problems such as temperature sensitivity and insufficient voltage judgment accuracy. Summary of the invention
[0004] In view of the problems existing in the prior art, the present invention provides a dual power supply output circuit that prevents abnormal jumps during the power-off process. Its purpose is to prevent abnormal jumps in the output signal state of the output circuit when the core logic voltage is powered off first and the input and output unit voltages are powered off later.
[0005] The present invention is achieved through the following technical solutions: A dual power supply output circuit for preventing abnormal jumps during power-off, comprising: Level converter 821, driver circuit 822, core logic voltage monitoring circuit 823 and comparator 824; The input end of the level converter 821 is connected to the power input signal VIN; The input terminal of the comparator 824 is connected to the input reference voltage VREF and the input bias voltage VB; The output signal VC of the core logic voltage monitoring circuit 823 is connected to the input end of the comparator 824, the output signal SEL of the comparator 824 is connected to the input end of the level converter 821, the first signal VA2 and the second signal VB2 output by the level converter 821 are connected to the input end of the driving circuit 822, and the driving circuit 822 outputs the voltage signal VOUT; the level conversion circuit 821 is powered by the core logic voltage VDDC and the input-output unit voltage VDDIO; The driving circuit 822 is powered by the input-output unit voltage VDDIO, the core logic voltage monitoring circuit 823 is powered by the core logic voltage VDDC, and the comparator 824 is powered by the input-output unit voltage VDDIO.
[0006] Preferably, when the core logic voltage VDDC and the input-output unit voltage VDDIO are both powered, the dual power output circuit 811 for preventing abnormal jumps during power-off operates in a normal working mode, and the output voltage signal VOUT changes with the power input signal VIN.
[0007] Preferably, when the input-output unit voltage VDDIO is powered and the core logic voltage VDDC is not powered, the dual power output circuit 811 for preventing abnormal jumps during power-off operates in an output holding mode, and the output voltage signal VOUT is stably maintained in the last state.
[0008] Preferably, when the input-output unit voltage VDDIO is not powered, the dual power supply output circuit 811 for preventing abnormal jumps during the power-off process operates in a non-driving mode, and the output voltage signal VOUT is at a low level.
[0009] Preferably, the level converter 821 includes 5 inverters, 4 selectors, 6 pmos transistors and 6 nmos transistors.
[0010] Preferably, the driving circuit 822 includes 3 pmos transistors and 3 nmos transistors.
[0011] Preferably, the comparator 824 includes 2 pmos transistors and 3 nmos transistors.
[0012] Preferably, the core logic voltage monitoring circuit 823 includes two resistors.
[0013] A working method of a dual power supply output circuit for preventing abnormal jumps during power-off, characterized in that it includes: The working process of the level converter 821 is as follows: When the core logic voltage VDDC and the input-output unit voltage VDDIO are both powered, the SEL signal is at a high level, the level converter 821 is in a normal working mode, and the output first signal VA2 and the second signal VB2 change with the power input signal VIN; When the input-output unit voltage VDDIO is powered and the core logic voltage VDDC is not powered, the SEL signal is at a low level, the level converter 821 is in an output voltage holding mode, and the output first signal VA2 and the second signal VB2 maintain the most recent state without jumping; The working process of the driving circuit 822 is: The driving circuit 822 is powered by the input-output unit voltage VDDC to achieve driving enhancement of the internal signal. When the input first signal VA2 and the second signal VB2 are both high, the output voltage signal VOUT is high; when the input first signal VA2 and the second signal VB2 are both low, the output voltage signal VOUT is low. The working process of the core logic voltage monitoring circuit 823 is as follows: The core logic voltage monitoring circuit 823 is powered by the core logic voltage VDDC, and outputs a voltage VC after monitoring the voltage VDDC and dividing the voltage. The output voltage VC increases as the core logic voltage VDDC increases. The working process of the comparator 824 is as follows: The comparator 824 is powered by the input-output unit voltage VDDIO to compare the input voltages VC and VREF. When the voltage VC is less than the voltage VREF, the comparator output signal SEL is low level; when the voltage VC is greater than the voltage VREF, the comparator 824 output signal SEL is high level.
[0014] 10. An integrated circuit based on a dual power supply output circuit for preventing abnormal jumps during power-off, comprising a dual power supply output circuit 811 for preventing abnormal jumps during power-off, a bandgap reference 812, and a signal input unit 813 of the integrated circuit.
[0015] The output signals VB and VREF of the bandgap reference 812 and the power input signal VIN are connected to the input end of the dual power output circuit 811 for preventing abnormal jumps during the power-off process. The output voltage signal VOUT of the dual power output circuit 811 for preventing abnormal jumps during the power-off process is connected to the input end of the signal input unit 813 of the integrated circuit. The signal input unit 813 of the integrated circuit outputs the signal SIG.
[0016] Compared with the prior art, the present invention has the following beneficial technical effects: The present invention proposes a dual power supply output circuit for preventing abnormal jumps during power-off, and its purpose is to prevent abnormal jumps in the output signal state of the output circuit when the core logic voltage is powered off first and the input-output unit voltage is powered off later. The circuit includes a level converter with a holding function, a driving circuit, a core logic voltage monitoring circuit and a comparator. The level converter with a holding function is used, and the bandgap reference output reference voltage is compared with the core logic monitoring output voltage to control it. When the core logic voltage is powered off first and the input-output unit voltage is powered off later, the comparator outputs a low level, the dual power supply output circuit is in a holding working mode, the output signal state remains stable, and the external device connected to the output circuit is prevented from performing erroneous operations.
[0017] The present invention proposes a working process of a dual power output circuit for preventing abnormal jumps during a power-off process. A level converter with a holding function realizes the conversion of a power input signal VIN from a core logic voltage to an input output voltage, and when SEL is at a high level, the output signal changes with the power input signal VIN, and the converter is in a normal working mode; when SEL is at a low level, the output signal is stably maintained in the final state; the driving circuit realizes the buffering and driving of the input signal, ensuring the matching and adaptability of the output voltage signal VOUT with an outsourced load; the core logic voltage monitoring circuit realizes the monitoring of the voltage VDDC by means of a resistor voltage divider and outputs it to a comparator; the comparator realizes the comparison of the output reference voltage VREF and the core logic voltage monitoring value VC, and when the voltage VREF is greater than the voltage VC, the comparator outputs a low level; when the voltage VREF is less than the voltage VC, the comparator outputs a high level. Aiming at the demand of output circuit state control during power-off process, the present invention proposes a dual-power output circuit which can prevent abnormal jumps during power-off process. By monitoring the core logic voltage VDDC and comparing it with the reference voltage, the working mode of the level converter with a holding function is controlled to ensure that when the input-output unit voltage VDDIO is powered and the core logic voltage VDDC is not powered, the output voltage of the dual-power output circuit is stably maintained at the last state.
[0018] The invention discloses an integrated circuit of a dual power supply output circuit for preventing abnormal jumps during power-off. By comparing a bandgap reference voltage with a core logic monitoring voltage, the working state of a level converter with a holding function is controlled, thereby suppressing abnormal jumps during power-off of the dual power supply output circuit.
[0019] Furthermore, through the level converter with a hold function, the circuit can stably maintain the last state of the output signal when SEL is low, effectively preventing abnormal jumps that may occur during power-off. This stability is critical for situations where it is necessary to ensure that the signal remains unchanged during power switching or power failure.
[0020] Furthermore, the design of the driving circuit ensures good matching and adaptability between the output voltage signal VOUT and the external load. The circuit can adjust the output according to different load characteristics, thereby providing more stable and reliable signal transmission and reducing signal distortion or loss caused by load changes.
[0021] Furthermore, the core logic voltage monitoring circuit monitors the voltage VDDC in real time through a resistor voltage divider, providing the system with real-time voltage status information. This monitoring mechanism helps to detect and respond to voltage anomalies in a timely manner, thereby protecting the circuit from damage caused by overvoltage or undervoltage.
[0022] Furthermore, the comparator accurately controls the switching timing of the power supply by comparing the output reference voltage VREF and the core logic voltage monitoring value VC. When the relationship between the voltage VREF and VC changes, the comparator can respond quickly and output the corresponding level signal to ensure the accuracy and timeliness of the power supply switching. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 It is a typical application diagram of a dual power output circuit 811 to prevent abnormal jumps during power-off; Figure 2 It is a block diagram of a dual power supply output circuit 811 for preventing abnormal jump; Figure 3 It is a waveform diagram of a dual power supply output circuit to prevent abnormal jumps during power-off; Figure 4 It is a structural diagram of a dual power supply output circuit 811 for preventing abnormal jumps during power-off; DETAILED DESCRIPTION The present invention is further described in detail below in conjunction with specific embodiments, which are intended to explain the present invention rather than to limit it.
[0024] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0025] The present invention discloses a dual power supply output circuit for preventing abnormal jumps during power-off. By comparing a bandgap reference voltage with a core logic monitoring voltage, the working state of a level converter with a holding function is controlled to suppress abnormal jumps during power-off of the dual power supply output circuit. The circuit includes a level converter with a holding function 821, a driving circuit 822, a core logic voltage monitoring circuit 823, and a comparator 824. The level conversion circuit with a holding function 821 is powered by a core logic voltage VDDC and an input-output unit voltage VDDIO, the driving circuit 822 is powered by VDDIO, the core logic voltage monitoring circuit is powered by VDDC, and the comparator is powered by VDDIO. The power input signal VIN is connected to the input end of the level converter 821 with a holding function, the input reference voltage VREF and the input bias voltage VB are connected to the input end of the comparator 824, the output signal VC of the core logic voltage monitoring circuit 823 is connected to the input end of the comparator 824, the output signal SEL of the comparator 824 is connected to the input end of the level converter 821 with a holding function, the first signal VA2 and the second signal VB2 output by the level converter 821 with a holding function are connected to the input end of the driving circuit 822, and the driving circuit 822 outputs the voltage signal VOUT. The level converter with a holding function is used, and the bandgap reference output reference voltage is compared with the core logic monitoring output voltage to control it. When the core logic voltage is powered off first and the input and output unit voltage is powered off later, the comparator outputs a low level, the dual power output circuit is in a holding working mode, and the output signal state remains stable, preventing the external device connected to the output circuit from performing an erroneous operation.
[0026] like Figure 1 As shown, an integrated circuit of a dual power supply output circuit for preventing abnormal jumps during power-off includes a dual power supply output circuit 811 for preventing abnormal jumps during power-off, a bandgap reference 812, and a signal input unit 813 of other integrated circuits.
[0027] The bandgap reference 812 output signals VB and VREF, and the power input signal VIN are connected to the input end of the dual power output circuit 811 for preventing abnormal jumps during the power-off process. The dual power output circuit 811 for preventing abnormal jumps during the power-off process outputs a voltage signal VOUT connected to the input end of the signal input unit 813 of other integrated circuits, and the signal input unit 813 of other integrated circuits outputs a signal SIG. By comparing the bandgap reference voltage with the core logic monitoring voltage, the circuit can accurately determine the voltage state during the power-off process and control the operation of the level converter accordingly. This helps prevent abnormal signal jumps caused by voltage fluctuations or instability, thereby improving the stability and reliability of the power-off process.
[0028] like Figure 2As shown, a dual power supply output circuit 811 for preventing abnormal jumps during power-off process of the present invention includes a level converter 821 with a holding function, a driving circuit 822, a core logic voltage monitoring circuit 823 and a comparator 824.
[0029] like Figure 2 As shown, the power input signal VIN and the comparator 824 output signal SEL are connected to the input end of the level converter 821 with a holding function, the bandgap reference 812 outputs the reference voltage VREF and the bias voltage VB, and the output signal of the core logic voltage monitoring circuit 823 are connected to the input end of the comparator 824, the first signal VA2 and the second signal VB2 output by the level converter 821 with a holding function are connected to the input end of the driving circuit 822, and the driving circuit 822 outputs the voltage signal VOUT.
[0030] The level converter 821 with a holding function realizes the conversion of the power input signal VIN from the core logic voltage to the input output voltage, and when SEL is at a high level, the output first signal VA2 and the second signal VB2 change with the power input signal VIN, and the converter is in a normal working mode; when SEL is at a low level, the output first signal VA2 and the second signal VB2 are both stably maintained in the final state; the driving circuit 822 realizes the buffering and driving of the input first signal VA2 and the second signal VB2 to ensure the matching and adaptability of the output voltage signal VOUT with the external load; the core logic voltage monitoring circuit 823 monitors the voltage VDDC through a resistor divider and outputs it to the comparator 824; the comparator 824 compares the output reference voltage VREF with the core logic voltage monitoring value VC, and when the voltage VREF is greater than the voltage VC, the comparator 824 outputs a low level; when the voltage VREF is less than the voltage VC, the comparator 824 outputs a high level.
[0031] like Figure 4As shown, the level converter 821 with a holding function includes 5 inverters, 4 selectors, 6 pmos transistors and 6 nmos transistors; the output signal SEL of the comparator 824 is connected to the s end of the selector sel1, the s end of the selector sel2, the s end of the selector sel3 and the s end of the selector sel4, the power input signal VIN is connected to the input end of the inverter inv1, the output end of the inverter inv1 is connected to the input end of the inverter inv2 and the input end of the inverter inv3, the output end of the inverter inv2 is connected to the input end b of the selector sel1, the output end y of the selector sel1 is connected to the input end of the transistor mp1 The g terminal, the g terminal of the transistor mn1, and the g terminal of the transistor mn3 are connected, the s terminal of the transistor mp1 is connected to the core logic voltage VDDC, the d terminal of the transistor mp1 is connected to the d terminal of the transistor mn1 and the b terminal of the selector sel2, the s terminal of the transistor mn1 is connected to the ground line, the output terminal y of the selector sel2 is connected to the g terminal of the transistor mn2, the s terminal of the transistor mn2 is connected to the ground line, the d terminal of the transistor mn2 is connected to the d terminal of the transistor mp2 and the g terminal of the transistor mp3, the g terminal of the transistor mp2 is connected to the d terminal of the transistor mp3, the d terminal of the transistor mn3, the second signal VA2, the input terminal of the inverter inv4 and the selector s The input terminal a of el2 is connected, the s terminal of transistor mp2 and the s terminal of transistor mp3 are connected to the input-output voltage VDDIO, the s terminal of transistor mn3 is connected to the ground line, the output terminal of inverter inv4 is connected to the input terminal a of selector sel1, the output terminal of inverter inv3 is connected to the input terminal b of selector sel3, the output terminal y of selector sel3 is connected to the g terminal of transistor mp4, the g terminal of transistor mn4, and the g terminal of transistor mn6, the s terminal of transistor mp4 is connected to the core logic voltage VDDC, the d terminal of transistor mp4 is connected to the d terminal of transistor mn4 and the b terminal of selector sel4, and the transistor mn4 is connected to the ground line. The s-end of the selector sel4 is connected to the ground line, the output end y of the selector sel4 is connected to the g-end of the transistor mn5, the s-end of the transistor mn5 is connected to the ground line, the d-end of the transistor mn5 is connected to the d-end of the transistor mp5 and the g-end of the transistor mp6, the g-end of the transistor mp5 is connected to the d-end of the transistor mp6, the d-end of the transistor mn6, the output signal VB2, the input end of the inverter inv5 and the input end a of the selector sel4 are connected, the s-end of the transistor mp5 and the s-end of the transistor mp6 are connected to the input-output voltage VDDIO, the s-end of the transistor mn6 is connected to the ground line, and the output end of the inverter inv5 is connected to the input end a of the selector sel3;The level converter 821 with a holding function realizes the conversion of the power input signal VIN core logic voltage to the input and output unit voltage, and ensures that during the power-off process, if the input and output voltage VDDIO is powered and the core logic voltage VDDC is not powered, the converter works in the holding working mode, and the output first signal VA2 and the second signal VB2 are stably maintained in the last state. ;
[0032] like Figure 4 As shown, the driving circuit 822 includes 3 pmos transistors and 3 nmos transistors; the second signal VA2 of the level converter 821 with a holding function is connected to the g terminal of the transistor mp7 and the g terminal of the transistor mn7, the d terminal of the transistor mp7 is connected to the t terminal of the transistor mn7 and the g terminal of the transistor mp9, the d terminal of the transistor mp9 is connected to the d terminal of the transistor mn9 and the output voltage signal VOUT, the output signal VB2 of the level converter 821 with a holding function is connected to the g terminal of the transistor mp8 and the g terminal of the transistor mn8, the d terminal of the transistor mp8 is connected to the t terminal of the transistor mn8 and the g terminal of the transistor mn9, the s terminal of the transistor mp7, the s terminal of the transistor mp8 and the s terminal of the transistor mp9 are connected to the input-output voltage VDDIO, and the s terminal of the transistor mn7, the s terminal of the transistor mn8 and the s terminal of the transistor mn9 are connected to the ground line; the driving circuit 822 increases the driving capability of the input first signal VA2 and the second signal VB2, so that the output voltage signal VOUT can drive the load connected thereto.
[0033] like Figure 4 As shown, the core logic voltage monitoring circuit 823 includes two resistors; the a-end of the resistor res1 is connected to the core logic voltage VDDC, the b-end of the resistor res1 is connected to the a-end of the resistor res2 and the output signal VC, and the b-end of the resistor res2 is connected to the ground line; the core logic voltage monitoring circuit 823 realizes the detection of the voltage VDDC, and the output voltage VC increases as the core logic voltage VDDC increases.
[0034] like Figure 4As shown, the comparator 824 includes two pmos transistors and three nmos transistors; the core logic voltage monitoring circuit 823 output signal VC is connected to the g end of the transistor mn10, the bandgap reference 812 output signal VB is connected to the g end of the transistor mn12, the bandgap reference 812 output signal VREF is connected to the g end of the transistor mn11, the s end of the transistor mn12 is connected to the ground line, the d end of the transistor mn12 is connected to the s end of the transistor mn10 and the s end of the transistor mn11, and the transistor m The d end of n10 is connected to the g end of transistor mp10 and the g end of transistor mp11, the d end of transistor mp11 is connected to the d end of transistor mn11 and the output signal SEL, and the s ends of transistor mp10 and transistor mp11 are connected to the input-output voltage VDDIO; the comparator 824 realizes the voltage comparison of the input signal VREF and VC, when the input voltage VREF is greater than VC, the comparator 824 outputs a low level; when the input voltage VREF is less than VC, the comparator 824 outputs a high level.
[0035] The working principle of the dual power output circuit to prevent abnormal jumps during power-off is as follows: 1) Working principle of the level converter 821 with holding function: The level converter with holding function is a dual-channel level conversion circuit, which realizes dual-path control of the power input signal VIN. When the core logic voltage VDDC and the input-output unit voltage VDDIO are both powered, the SEL signal is high, the level converter is in a normal working mode, and the output first signal VA2 and the second signal VB2 change with the power input signal VIN; when the input-output unit voltage VDDIO is powered and the core logic voltage VDDC is not powered, the SEL signal is low, the level converter is in an output voltage holding working mode, and the output first signal VA2 and the second signal VB2 maintain the most recent state without jumping; 2) Working principle of the driving circuit 822: The driving circuit 822 is powered by the input-output unit voltage VDDC to achieve driving enhancement of the internal signal. When the input first signal VA2 and the second signal VB2 are both high, the output voltage signal VOUT is high; when the input first signal VA2 and the second signal VB2 are both low, the output voltage signal VOUT is low. 3) Working principle of the core logic voltage monitoring circuit 823: The core logic voltage monitoring circuit 823 is powered by the core logic voltage VDDC. It monitors the voltage VDDC and outputs the voltage VC after voltage division. The output voltage VC increases as the core logic voltage VDDC increases. 4) Working principle of comparator 824: comparator 824 is powered by input-output unit voltage VDDIO to compare input voltage VC and VREF. When voltage VC is less than voltage VREF, comparator output signal SEL is low level; when voltage VC is greater than voltage VREF, comparator output signal SEL is high level. 5) Normal working mode: When the core logic voltage VDDC and the input and output unit voltage VDDIO are both powered, the dual power supply output circuit 811 for preventing abnormal jumps during the power-off process operates in the normal working mode, and the output voltage signal VOUT changes with the power input signal VIN; 6) Output hold mode: When the input-output unit voltage VDDIO is powered and the core logic voltage VDDC is not powered, the dual power supply output circuit 811 that prevents abnormal jumps during the power-off process operates in the output hold mode, and the output voltage signal VOUT is stably maintained at the last state; 7) No-drive mode: When the input-output unit voltage VDDIO is not powered, the dual-power output circuit 811 for preventing abnormal jumps during the power-off process operates in the no-drive mode, and the output voltage signal VOUT is at a low level.
[0036] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any ordinary technician in the industry can smoothly implement the present invention as shown in the drawings and described above. However, any equivalent changes, modifications and evolutions made by technicians familiar with the profession without departing from the scope of the technical solution of the present invention using the technical content disclosed above are all equivalent embodiments of the present invention. At the same time, any equivalent changes, modifications and evolutions made to the above embodiments based on the essential technology of the present invention are still within the protection scope of the technical solution of the present invention.
Claims
1. A dual power supply output circuit for preventing abnormal jumps during power-off, characterized in that: include, Level converter 821, driver circuit 822, core logic voltage monitoring circuit 823 and comparator 824; The input end of the level converter 821 is connected to the power input signal VIN; The input terminal of the comparator 824 is connected to the input reference voltage VREF and the input bias voltage VB; The output signal VC of the core logic voltage monitoring circuit 823 is connected to the input end of the comparator 824, the output signal SEL of the comparator 824 is connected to the input end of the level converter 821, the first signal VA2 and the second signal VB2 of the output end of the level converter 821 are connected to the input end of the driving circuit 822, and the output voltage signal VOUT of the driving circuit 822; the level conversion circuit 821 is powered by the core logic voltage VDDC and the input-output unit voltage VDDIO; The driving circuit 822 is powered by the input-output unit voltage VDDIO, the core logic voltage monitoring circuit 823 is powered by the core logic voltage VDDC, and the comparator 824 is powered by the input-output unit voltage VDDIO.
2. A dual power supply output circuit for preventing abnormal jumps during power-off according to claim 1, characterized in that: When the core logic voltage VDDC and the input-output unit voltage VDDIO are both powered, the dual power output circuit 811 for preventing abnormal jumps during power-off operates in a normal working mode, and the output voltage signal VOUT changes with the power input signal VIN.
3. A dual power supply output circuit for preventing abnormal jumps during power-off according to claim 1, characterized in that: When the input-output unit voltage VDDIO is powered and the core logic voltage VDDC is not powered, the dual power output circuit 811 for preventing abnormal jumps during power-off works in the output holding mode, and the output voltage signal VOUT is stably maintained at the last state.
4. A dual power supply output circuit for preventing abnormal jumps during power-off according to claim 1, characterized in that: When the input-output unit voltage VDDIO is not powered, the dual power output circuit 811 for preventing abnormal jumps during the power-off process operates in a non-driving mode, and the output voltage signal VOUT is at a low level.
5. A dual power supply output circuit for preventing abnormal jumps during power-off according to claim 1, characterized in that: The level converter 821 includes 5 inverters, 4 selectors, 6 pmos transistors and 6 nmos transistors.
6. A dual power supply output circuit for preventing abnormal jumps during power-off according to claim 1, characterized in that: The driving circuit 822 includes 3 pmos transistors and 3 nmos transistors.
7. A dual power output circuit for preventing abnormal jumps during power-off according to claim 1, characterized in that: The comparator 824 includes 2 pmos transistors and 3 nmos transistors.
8. A dual power supply output circuit for preventing abnormal jumps during power-off according to claim 1, characterized in that: The core logic voltage monitoring circuit 823 includes two resistors.
9. A working method for a dual power output circuit for preventing abnormal jumps during power-off according to any one of claims 1 to 8, characterized in that: include, The working process of the level converter 821 is as follows: When the core logic voltage VDDC and the input-output unit voltage VDDIO are both powered, the output signal SEL of the comparator 824 is at a high level, the level converter 821 is in a normal working mode, and the first signal VA2 and the second signal VB2 change with the power input signal VIN; When the input-output unit voltage VDDIO is powered and the core logic voltage VDDC is not powered, the output signal SEL of the comparator 824 is at a low level, the level converter 821 is in an output voltage holding working mode, and the first signal VA2 and the second signal VB2 maintain the most recent state without jumping; The working process of the driving circuit 822 is: The driving circuit 822 is powered by the input-output unit voltage VDDC to achieve driving enhancement of the internal signal. When the input first signal VA2 and the second signal VB2 are both high, the output voltage signal VOUT is high; when the first signal VA2 and the second signal VB2 are both low, the output voltage signal VOUT is low. The working process of the core logic voltage monitoring circuit 823 is as follows: The core logic voltage monitoring circuit 823 is powered by the core logic voltage VDDC, and outputs a voltage VC after monitoring the voltage VDDC and dividing the voltage. The output voltage VC increases as the core logic voltage VDDC increases. The working process of the comparator 824 is as follows: The comparator 824 is powered by the input-output unit voltage VDDIO to compare the input voltages VC and VREF. When the voltage VC is less than the voltage VREF, the comparator output signal SEL is low level; when the voltage VC is greater than the voltage VREF, the comparator output signal SEL is high level.
10. An integrated circuit based on a dual power supply output circuit for preventing abnormal jumps during power-off, based on the dual power supply output circuit for preventing abnormal jumps during power-off as claimed in any one of claims 1 to 8, characterized in that: It includes a dual power supply output circuit 811 for preventing abnormal jumps during power-off, a bandgap reference 812, and a signal input unit 813 of an integrated circuit; The output signals VB and VREF of the bandgap reference 812 and the power input signal VIN are connected to the input end of the dual power output circuit 811 for preventing abnormal jumps during the power-off process. The output voltage signal VOUT of the dual power output circuit 811 for preventing abnormal jumps during the power-off process is connected to the input end of the signal input unit 813 of the integrated circuit. The signal input unit 813 of the integrated circuit outputs the signal SIG.