Level shift circuit

Abstract

The invention relates to a level shift circuit. A level shifter includes a first input having a low voltage switch and configured to receive an input voltage and generate a second voltage that varies between a first low voltage and a first high voltage. The level shifter also includes a first output having a medium voltage switch and configured to receive the second voltage and generate a third voltage that varies between the first low voltage and the second high voltage. The level shifter also includes a second input having a medium voltage switch and configured to receive the third voltage and generate a fourth voltage that varies between a second low voltage and a second high voltage. The level shifter also includes a second output having a medium voltage switch and configured to receive a fourth voltage and generate a fifth voltage that varies between a second low voltage and a third high voltage.

Description

Technical Field

[0001] The present disclosure generally relates to level shifting circuits and methods for level shifting signals. Background Art

[0002] Some electronic systems benefit from level shifter circuits. For example, some electronic systems have a digital control circuit, such as a processor or controller, that generates an output signal with a lower voltage range (e.g., 0V to 1V) where another circuit uses an input signal with a higher voltage range (e.g., 2V to 5V). These types of electronic systems can use a level shifter circuit to convert the lower voltage range output signal from the controller to a higher voltage range input signal for the other circuit. Summary of the invention

[0003] One embodiment is a level shifter circuit, the level shifter circuit comprising a first stage input circuit configured to receive an input voltage and generate a second voltage, wherein the second voltage varies between a first low voltage and a first high voltage, and wherein the first stage input circuit comprises a plurality of low voltage threshold switches. The level shifter also comprises a first stage output circuit configured to receive the second voltage and generate a third voltage, wherein the third voltage varies between a first low voltage and a second high voltage, and wherein the first stage output circuit comprises a first plurality of medium voltage switches. The level shifter also comprises a second stage input circuit configured to receive the third voltage and generate a fourth voltage, wherein the fourth voltage varies between a second low voltage and a second high voltage, and wherein the second stage output circuit comprises a second plurality of medium voltage switches. The level shifter also comprises a second stage output circuit configured to receive the fourth voltage and generate a fifth voltage, wherein the fifth voltage varies between a second low voltage and a third high voltage, and wherein the second stage output circuit comprises a third plurality of medium voltage switches. The level shifter also comprises a buffer circuit configured to receive the fifth voltage and generate an output voltage, wherein the output voltage varies between a third low voltage and a third high voltage.

[0004] Another embodiment is an array circuit. The array circuit includes a device array, wherein each of the plurality of devices in the array includes at least one high voltage switch. The array circuit also includes a controller configured to generate a plurality of first control signals for controlling the device array. The array circuit also includes an array of level shifters, each of which is configured to receive a first control signal from the controller as an input voltage, generate a second control signal from a plurality of second control signals as an output voltage, and provide the output voltage to a device in the device array. Each of the level shifters includes a first-stage input circuit configured to receive an input voltage and generate a second voltage, wherein the second voltage varies between a first low voltage and a first high voltage, and wherein the first-stage input circuit includes a plurality of low-voltage threshold switches. Each of the level shifters also includes a first-stage output circuit configured to receive a second voltage and generate a third voltage, wherein the third voltage varies between a first low voltage and a second high voltage, and wherein the first-stage output circuit includes a first plurality of medium voltage switches. Each of the level shifters also includes a second-stage input circuit configured to receive a third voltage and generate a fourth voltage, wherein the fourth voltage varies between a second low voltage and a second high voltage, and wherein the second-stage output circuit includes a second plurality of medium voltage switches. The level shifters each further include a second stage output circuit configured to receive a fourth voltage and generate a fifth voltage, wherein the fifth voltage varies between a second low voltage and a third high voltage, and wherein the second stage output circuit includes a third plurality of medium voltage switches. The level shifters each further include a buffer circuit configured to receive the fifth voltage and generate an output voltage, wherein the output voltage varies between a third low voltage and a third high voltage.

[0005] Another embodiment is a method of using a level shifter circuit. The method includes using a first-stage input circuit including a plurality of low-voltage threshold switches to receive an input voltage and generate a second voltage based in part on the input voltage, wherein the second voltage varies between a first low voltage and a first high voltage. The method also includes using a first-stage output circuit including a first plurality of medium-voltage switches to receive a second voltage and generate a third voltage based in part on the second voltage, wherein the third voltage varies between a first low voltage and a second high voltage. The method also includes using a second-stage input circuit including a second plurality of medium-voltage switches to receive a third voltage and generate a fourth voltage based in part on the third voltage, wherein the fourth voltage varies between a second low voltage and a second high voltage. The method also includes using a second-stage output circuit including a third plurality of medium-voltage switches to receive a fourth voltage and generate a fifth voltage based in part on the fourth voltage, wherein the fifth voltage varies between a second low voltage and a third high voltage. The method also includes using a buffer circuit to receive a fifth voltage and generate an output voltage based in part on the fifth voltage, wherein the output voltage varies between a third low voltage and a third high voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] For a more complete understanding of one or more embodiments of the present disclosure and advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0007] Figure 1 shows a schematic circuit diagram of an electronic system according to some embodiments;

[0008] Figure 2 shows a block diagram of a level shifter circuit according to some embodiments;

[0009] Figure 3 shows a schematic circuit diagram of a level shifter circuit according to some embodiments;

[0010] Figure 4 shows a schematic circuit diagram of a level shifter circuit according to some embodiments;

[0011] Figure 5 shows a schematic circuit diagram of a level shifter circuit according to some embodiments;

[0012] Figure 6 shows a schematic circuit diagram of a level shifter circuit according to some embodiments;

[0013] Figure 7 A schematic circuit diagram showing an electronic system according to some embodiments; and

[0014] Figure 8 A flow chart of a method of using an electronic system according to some embodiments is shown.

[0015] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to corresponding parts. These figures are drawn to illustrate relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily represent the end of the range of the features. DETAILED DESCRIPTION

[0016] Illustrative embodiments of the systems and methods of the present disclosure are described below. For the sake of clarity, not all features of an actual implementation may be described in this specification. Of course, it will be appreciated that in the development of any such actual embodiment, many implementation-specific decisions may be made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which may vary from implementation to implementation. Furthermore, it will be appreciated that such development work may be complex and time-consuming, but will be a routine task for a person of ordinary skill in the art having the benefit of the present disclosure.

[0017] As shown in the accompanying drawings, reference may be made herein to the spatial relationship between various components and the spatial orientation of various aspects of the components. However, as will be appreciated by those skilled in the art after a thorough reading of this disclosure, the devices, components, apparatuses, etc. described herein may be positioned in any desired orientation. Therefore, the use of terms such as "above," "below," "upper," "lower," or other similar terms to describe the spatial relationship between various components or to describe the spatial orientation of various aspects of such components should be understood to describe the relative relationship between components or the spatial orientation of various aspects of such components, respectively, as the devices described herein may be oriented in any desired direction.

[0018] The making and using of various embodiments are discussed in detail below. However, it should be understood that the various embodiments described herein are applicable to various specific contexts. The specific embodiments discussed merely illustrate specific ways to make and use the various embodiments and should not be interpreted in a limited sense. Unless otherwise indicated, the expressions "approximately," "approximately," and "substantially" mean within 10% of a given value, preferably within 5% thereof, or, such as in the case of substantially zero, less than 10%, preferably less than 5% of a comparable quantity.

[0019] The embodiments discussed herein illustrate various aspects of level shifter circuit techniques that are implemented using minimal die area and that provide accurate, fast, and low power consumption signal level shifting.

[0020] High voltage logic signals are often required to control circuits, such as non-volatile memory arrays, which are commonly found in general-purpose microcontrollers or pixel arrays (e.g., in image sensor circuits). A large number of high voltage signals (e.g., >4V) can be controlled with low voltage signals (e.g., 1V). Voltage conversion can be performed by level shifter circuits, which are placed in large numbers depending on the number of signals to be controlled. The embodiments discussed use a small amount of area, thereby reducing the size of the overall system.

[0021] Some manufacturing processes have options for forming switches, such as MOSFETs or other different types of transistors. For example, a manufacturing process may have a low voltage switch, a medium voltage switch, and a high voltage switch. In various embodiments, the low voltage transistor operates at 40% to 80% of the operating Vds / Vgs of the medium voltage transistor, which operates at 40% to 80% of the operating Vds / Vgs of the high voltage transistor. The threshold voltage of the medium voltage transistor is about 1.5 to 2.5 times the threshold voltage of the low voltage transistor, while the threshold voltage of the high voltage transistor is about 3 to 5 times the threshold voltage of the medium voltage transistor. In some embodiments, the low voltage switch has a maximum allowable voltage of about 1V Vds and Vgs, the medium voltage switch has a minimum allowable voltage of about 2V Vds and Vgs, and the high voltage switch has a maximum allowable voltage greater than about 4V Vds and Vgs. In some embodiments, the gate turn-on threshold of the low voltage switch is about 0.2V or 0.3V. In some embodiments, the gate turn-on threshold of the medium voltage switch is about 0.4V. In some embodiments, the gate turn-on threshold of the high voltage switch is about 0.6 V or 0.7 V. In some embodiments, the low voltage switch uses less area than the medium voltage switch, and the medium voltage switch uses less area than the high voltage switch.

[0022] The shifting of logic signal voltage levels from a low voltage (typically 1V) input to a high voltage (typically >4V) output typically results in the voltage across the low voltage switch exceeding its maximum voltage tolerance threshold. Specific level shifter architectures can be used to ensure proper functionality while protecting individual transistors from overvoltage stress. This functionality can be described as generating an output signal that varies within a desired output voltage level range based on an input signal that varies within a specific input voltage level range, wherein the output signal maintains the input signal encoding such that a logic 0 input signal results in the generation of a logic 0 output signal and a logic 1 input signal results in the generation of a logic 1 output signal.

[0023] Sometimes individual transistors can be protected through careful design to ensure that they are not exposed to voltages or currents greater than their allowed limits, allowing the product to function properly throughout its lifetime.

[0024] Figure 1 1 is a schematic circuit diagram of an electronic system 100 according to some embodiments. The electronic system 100 includes a controller 110, a level shifting circuit 120, and a controlled circuit 130.

[0025] The controller 110 generates a control signal for the controlled circuit 130 using, for example, a low voltage switch, wherein the control signal generated by the controller 110 has a lower level voltage range (such as from 0V to 1V) or another voltage range. In some embodiments, the controller 110 is or includes a controller or processor for a system including a device array, such as a memory, a display, or an image capture device.

[0026] The controlled circuit 130 performs its function using a circuit having, for example, a high voltage switch that generates a signal having a higher voltage range (such as 2V to 5V) or another voltage range. In addition, the controlled circuit 130 generates a signal in response to an input control signal having a higher voltage range. In some embodiments, the controlled circuit 130 includes a unit cell device array, such as a memory cell array, a display cell array, or an image capture cell array.

[0027] The level shifting circuit 120 includes one or more level shifter circuits, examples of which are described in more detail below. The level shifting circuit 120 receives a lower voltage control signal from the controller 110 and generates a higher voltage control signal for the controlled circuit 130 .

[0028] Figure 2 A block diagram of a level shifter circuit 200 according to some embodiments is shown. The level shifter circuit 200 may be used in or as the level shifter circuit 120. For example, for each of a plurality of control signals generated by the controller 110 for the controlled circuit 130, the level shifter circuit 120 may include an embodiment of the level shifter circuit 200. Thus, in some embodiments, the level shifter circuit 200 may include many instances of a level shifter circuit such as the level shifter circuit 200. The level shifter circuit 200 includes a first stage input portion 210, a first stage output portion 220, a second stage input portion 230, a second stage output portion 240, and a second stage buffer portion 250.

[0029] In the illustrated embodiment of the level shifter circuit 200, each component receives a differential input signal and generates a differential output signal. In some embodiments, one or more or all components of the level shifter circuit 200 receive a single-ended input. In some embodiments, one or more or all components of the level shifter circuit 200 generate a single-ended output. In some embodiments, one or more or all components of the level shifter circuit 200 receive a single-ended input and generate a single-ended output.

[0030] The first stage input portion 210 includes switches that receive input signals at input nodes 212 and 214 from, for example, a controller, such as controller 110. In some embodiments, the switches of the first stage input portion 210 include low voltage switches. In some embodiments, the switches of the first stage input portion 210 include medium voltage switches. In some embodiments, the switches of the first stage input portion 210 include high voltage switches.

[0031] The input signals at input nodes 212 and 214 may have a lower level voltage range (such as from 0V to 1V) or another voltage range. Based on the input signals, first stage input portion 210 generates signals for first stage output portion 220 at nodes 216 and 218, where the signals of first stage output portion 220 may also have a lower level voltage range. In some embodiments, the signals of first stage output portion 220 have different voltage ranges.

[0032] In some embodiments, the first stage input portion 210 is inverting so that the output signal and the input signal have opposite polarities. In some embodiments, the first stage input portion is non-inverting so that the input signal and the output signal have the same polarity.

[0033] The first stage output portion 220 includes switches that receive input signals from the first stage input portion 210 at input nodes 216 and 218. In some embodiments, the switches of the first stage output portion 220 include low voltage switches. In some embodiments, the switches of the first stage output portion 220 include medium voltage switches. In some embodiments, the switches of the first stage output portion 220 include high voltage switches.

[0034] The input signals at nodes 216 and 218 may have a lower level voltage range (such as from 0V to 1V) or another voltage range. Based on the input signals at nodes 216 and 218, the first stage output portion 220 generates a signal for the second stage input portion 230 at nodes 226 and 228, wherein the signal of the second stage output portion 230 may have a voltage range different from the lower level voltage range. For example, the signal of the second stage input portion 230 has a range greater than the lower level voltage range. In some embodiments, the signal of the second stage input portion 230 has a second voltage range (such as from 0V to 4V) or another voltage range.

[0035] In some embodiments, the first stage output portion 220 is inverting, such that the output signal and the input signal have opposite polarities. In some embodiments, the first stage input portion is non-inverting, such that the input signal and the output signal have the same polarity.

[0036] The second stage input section 230 includes switches that receive input signals from the first stage output section 220 at input nodes 226 and 228. In some embodiments, the switches of the second stage input section 230 include low voltage switches. In some embodiments, the switches of the second stage input section 230 include medium voltage switches. In some embodiments, the switches of the second stage input section 230 include high voltage switches.

[0037] Based on the input signals at nodes 226 and 228, the second stage input portion 230 generates signals for the second stage output portion 240 at nodes 236 and 238. The signal of the second stage output portion 240 may have a voltage range different from the voltage range of the input signals at nodes 226 and 228. In some embodiments, the signal of the second stage output portion 240 may have the same voltage range as the voltage range of the input signals at nodes 226 and 228. For example, the signal of the second stage output portion 240 has a range greater than the lower level voltage range. In some embodiments, the signal of the second stage output portion 240 has a voltage range such as from 2V to 4V or another voltage range.

[0038] In some embodiments, the second stage input portion 230 is inverting so that the output signal and the input signal have opposite polarities. In some embodiments, the first stage input portion is non-inverting so that the input signal and the output signal have the same polarity.

[0039] The second stage output portion 240 includes switches that receive input signals from the second stage input portion 230 at input nodes 236 and 238. In some embodiments, the switches of the second stage output portion 240 include low voltage switches. In some embodiments, the switches of the second stage output portion 240 include medium voltage switches. In some embodiments, the switches of the second stage output portion 240 include high voltage switches.

[0040] Based on the input signals at nodes 236 and 238, the second stage output portion 240 generates a signal for the second stage buffer portion 250 at nodes 246 and 248. The signal of the second stage buffer portion 250 may have the same voltage range as the voltage range of the input signals at nodes 236 and 238. In some embodiments, the signal of the second stage buffer portion 250 may have a voltage range different from the voltage range of the input signals at nodes 236 and 238. For example, the signal of the second stage buffer portion 250 has a range greater than the voltage range of the input signals at nodes 236 and 238. In some embodiments, the signal of the second stage buffer portion 250 has a voltage range of 2V to 5V, or another voltage range.

[0041] In some embodiments, the second stage output portion 240 is inverting, such that the output signal and the input signal have opposite polarities. In some embodiments, the first stage input portion is non-inverting, such that the input signal and the output signal have the same polarity.

[0042] The second stage buffer portion 250 includes switches that receive input signals from the second stage output portion 240 at input nodes 246 and 248. In some embodiments, the switches of the second stage buffer portion 250 include low voltage switches. In some embodiments, the switches of the second stage buffer portion 250 include medium voltage switches. In some embodiments, the switches of the second stage buffer portion 250 include high voltage switches.

[0043] Based on the input signals at nodes 246 and 248, the second stage buffer portion 250 generates an output signal of the level shifter circuit 200 at nodes 256 and 258. The output signal of the level shifter circuit 200 may have the same voltage range as the voltage range of the input signals at nodes 246 and 248. In some embodiments, the output signal of the level shifter circuit 200 has a voltage range of 2V to 5V, or another voltage range.

[0044] In some embodiments, the second stage buffer portion 250 is inverting so that the output signal and the input signal have opposite polarities. In some embodiments, the first stage input portion is non-inverting so that the input signal and the output signal have the same polarity.

[0045] Figure 3 A schematic circuit diagram of a level shifter circuit 300 according to some embodiments is shown. The level shifter circuit 300 is a non-limiting example of the level shifter circuit 200 and includes a first stage input portion 310, a first stage output portion 320, a second stage input portion 330, a second stage output portion 340, and a second stage buffer portion 350.

[0046] The first stage input section 310 includes switches that receive input signals at input nodes 312 and 314 from, for example, a controller, such as controller 110. In an alternative embodiment, node 316 is connected to node 314 and the input signal from the controller is single-ended. In the illustrated embodiment, the switches of the first stage input section 310 are low voltage switches.

[0047] The input signals at nodes 312 and 314 may have a first voltage range (such as from 0V to 1V) or another voltage range between voltage VinLO and voltage VinHI. Based on the input signals, first stage input portion 310 generates signals for first stage output portion 320 at nodes 316 and 318, where the signals of first stage output portion 320 may also have a first voltage range. In some embodiments, the signals of first stage output portion 320 have another voltage range.

[0048] In some embodiments, the first stage input portion 310 is inverting so that the output signal and the input signal have opposite polarities. In some embodiments, the first stage input is non-inverting so that the input signal and the output signal have the same polarity.

[0049] The first stage output portion 320 includes switches that receive input signals from the first stage input portion 310 at input nodes 316 and 318. In some embodiments, the switches of the first stage output portion 320 include low voltage switches. In some embodiments, the switches of the first stage output portion 320 include medium voltage switches. In some embodiments, all switches of the first stage output portion 320 are medium voltage switches. In some embodiments, the switches of the first stage output portion 320 include high voltage switches.

[0050] In the illustrated embodiment, the input signals at nodes 316 and 318 may have a first voltage range (such as from 0V to 1V) or another voltage range. Based on the input signals at nodes 316 and 318, the first stage output portion 320 generates a signal for the second stage input portion 330 at nodes 326 and 328, wherein the signal of the second stage input portion 330 may have a second voltage range between a voltage VinLO and a voltage VinterHI, which is different from the first voltage range. For example, the signal of the second stage input portion 330 has a range greater than the first voltage range (such as from 0V to 4V) or another voltage range.

[0051] In some embodiments, the first stage output portion 320 is inverting, such that the output signal and the input signal have opposite polarities. In some embodiments, the first stage output portion 320 is non-inverting, such that the input signal and the output signal have the same polarity.

[0052] The second stage input section 330 includes switches that receive input signals from the first stage output section 320 at input nodes 326 and 328. In some embodiments, the switches of the second stage input section 330 include low voltage switches. In some embodiments, the switches of the second stage input section 330 include medium voltage switches. In some embodiments, the switches of the second stage input section 330 include high voltage switches. In some embodiments, all switches of the second stage input section 330 are high voltage switches.

[0053] Based on the input signal at nodes 326 and 328, the second stage input portion 330 generates a signal for the second stage output portion 340 at nodes 336 and 338. The signal of the second stage output portion 340 may have a third voltage range between a voltage VinterLO and a voltage VinterHI, which is different from the voltage range of the input signal at nodes 326 and 328. In some embodiments, the third voltage range is the same as the voltage range of the input signal at nodes 326 and 328. For example, the signal of the second stage output portion 340 has a range greater than the first voltage range, such as a voltage range equal to the second voltage range. In some embodiments, the signal of the second stage output portion 340 has a voltage range such as from 0V to 2V or another voltage range. In some embodiments, the signal of the second stage output portion 340 has a third voltage range (such as from 2V to 4V) or another voltage range different from the first voltage range and the second voltage range.

[0054] In some embodiments, the second stage input portion 330 is inverting so that the output signal and the input signal have opposite polarities. In some embodiments, the first stage input portion is non-inverting so that the input signal and the output signal have the same polarity.

[0055] The second stage output portion 340 includes switches that receive input signals from the second stage input portion 330 at input nodes 336 and 338. In some embodiments, the switches of the second stage output portion 340 include low voltage switches. In some embodiments, the switches of the second stage output portion 340 include medium voltage switches. In some embodiments, the switches of the second stage output portion 340 include high voltage switches. In some embodiments, all switches of the second stage output portion 340 are high voltage switches.

[0056] Based on the input signals at nodes 336 and 338, second stage output portion 340 generates signals for second stage buffer portion 350 at nodes 346 and 348. The signal of second stage buffer portion 350 may have a fourth voltage range between voltage VinterLO and voltage VoutHI, e.g., different from the voltage range of the input signals at nodes 336 and 338. For example, the signal of second stage buffer portion 350 has a range greater than the voltage range of the input signals at nodes 336 and 338. In some embodiments, the signal of second stage buffer portion 350 has a voltage range of 2V to 5V, or another voltage range.

[0057] In some embodiments, the second stage output portion 340 is inverting, such that the output signal and the input signal have opposite polarities. In some embodiments, the first stage input portion is non-inverting, such that the input signal and the output signal have the same polarity.

[0058] The second stage buffer portion 350 includes switches that receive input signals from the second stage output portion 340 at input nodes 346 and 348. In some embodiments, the switches of the second stage buffer portion 350 include low voltage switches. In some embodiments, the switches of the second stage buffer portion 350 include medium voltage switches. In some embodiments, the switches of the second stage buffer portion 350 include high voltage switches. In some embodiments, all switches of the second stage buffer portion 350 are high voltage switches.

[0059] Based on the input signals at nodes 346 and 348, the second stage buffer portion 350 generates an output signal of the level shifter circuit 300 at nodes 356 and 358. The output signal of the level shifter circuit 300 may have a fifth voltage range between the voltage VoutLO and the voltage VoutHI, for example, the fifth voltage range is the same as the voltage range of the input signals at nodes 346 and 348. In some embodiments, the output signal of the level shifter circuit 300 has a voltage range of 2V to 5V, or another voltage range. In some embodiments, the output signal of the level shifter circuit 300 may have a fifth voltage range that is different from the voltage range of the input signals at nodes 346 and 348.

[0060] In some embodiments, the second stage buffer portion 350 is inverting so that the output signal and the input signal have opposite polarities. In some embodiments, the first stage input portion is non-inverting so that the input signal and the output signal have the same polarity.

[0061] For example, the following examples of configurations and relationships between various voltages may be used to ensure or maximize functionality while preventing or minimizing voltage stress or overstress of the various transistors.

[0062] In some embodiments, the cascode voltage at node 344 is equal to voltage VinterHI. In some embodiments, the cascode voltage at node 344 is less than voltage VinterHI + Vgs threshold voltage of cascode switches N6 and N7, for example, to limit leakage. In some embodiments, the cascode voltage at node 344 is greater than voltage VinterLO + Vgs threshold voltage of switches N2 and N3 + overdrive margin voltage of switches N2 and N3. In some embodiments, the overdrive margin voltage is sufficient to turn on switches N2 and N3 enough to discharge nodes 336 and 338.

[0063] In some embodiments, voltage VinterLO is equal to voltage VoutLO. In some embodiments, voltage VinterLO is less than voltage VoutLO + Vgs threshold voltage of buffer switches N8 and N9, for example, to limit leakage. In some embodiments, voltage VinterLO is greater than voltage VoutHI - the maximum voltage allowed on the high voltage switch.

[0064] In some embodiments, switches P3 and P2 are omitted. When used, switches P3 and P2 increase speed by increasing the voltage at nodes 336 and 338. In embodiments where voltage VoutHI is not always greater than voltage VinterHI, switches P2 and P3 may be omitted, for example, to avoid leakage from voltage VinterHI to voltage VoutHI or from voltage VoutHI to voltage VinterHI through cascode switches N6 and N7.

[0065] In some embodiments, switches P6 and P7 are omitted. For example, in an embodiment where the voltage VoutHI is greater than the voltage VinterHI by a voltage greater than a limit, switches P6 and P7 can be used to increase speed. Also, in an embodiment where the voltage VoutHI is greater than the voltage VinterHI by a voltage less than a limit, switches P6 and P7 can be omitted.

[0066] In some embodiments, switches P4 and P5 are omitted. For example, in embodiments where the voltage VinterHI is greater than the voltage VinLO by a voltage amount greater than a limit, switches P4 and P5 can be used to increase speed. Also, in embodiments where the voltage VinterHI is greater than the voltage VinLO by a voltage amount less than a limit, switches P6 and P7 can be omitted.

[0067] In some embodiments, switches PL1 and PL2 are omitted. When used, switches PL1 and PL2 increase speed by increasing the voltage at nodes 316 and 318. In embodiments where voltage VinterHI is not always greater than voltage VinHI, switches PL1 and PL2 may be omitted, for example, to avoid leakage from voltage VinterHI to voltage VinHI or from voltage VinHI to voltage VinterHI through cascode switches N4 and N5.

[0068] In some embodiments, one of the outputs VOUT and VOUT_N is not required, and switches N9 and P11 are omitted or switches N8 and P10 are omitted, for example, to save area and increase speed.

[0069] Figure 42 is a schematic circuit diagram of a level shifter circuit 400 according to some embodiments. The level shifter circuit 400 may include aspects similar or identical to those described above with reference to the level shifter circuit 300.

[0070] The level shifter circuit 400 is a non-limiting example of the level shifter circuit 200 , and includes a first stage input portion 410 , a first stage output portion 420 , a second stage input portion 430 , a second stage output portion 440 , and a second stage buffer portion 450 .

[0071] The first stage input section 410 includes switches that receive input signals at input nodes 412 and 414 from, for example, a controller, such as controller 110. In an alternative embodiment, node 416 is connected to node 414 and the input signal from the controller is single-ended. In the illustrated embodiment, the switches of the first stage input section 410 are low voltage switches.

[0072] The input signals at nodes 412 and 414 may have a first voltage range (such as from 0V to 1V) or another voltage range between voltage VinLO and voltage VinHI. Based on the input signals, first stage input portion 410 generates signals for first stage output portion 420 at nodes 416 and 418, where the signals of first stage output portion 420 may also have a first voltage range. In some embodiments, the signals of first stage output portion 420 have different voltage ranges.

[0073] In some embodiments, the first stage input portion 410 is inverting so that the output signal and the input signal have opposite polarities. In some embodiments, the first stage input portion is non-inverting so that the input signal and the output signal have the same polarity.

[0074] The first stage output portion 420 includes switches that receive input signals from the first stage input portion 410 at input nodes 416 and 418. In some embodiments, the switches of the first stage output portion 420 include low voltage switches. In some embodiments, the switches of the first stage output portion 420 include medium voltage switches. In some embodiments, all switches of the first stage output portion 420 are high voltage switches. In some embodiments, the switches of the first stage output portion 420 include high voltage switches.

[0075] In the illustrated embodiment, the input signals at nodes 416 and 418 may have a first voltage range (such as from 0V to 1V) or another voltage range. Based on the input signals at nodes 416 and 418, the first stage output portion 420 generates a signal for the second stage input portion 430 at nodes 426 and 428, wherein the signal of the second stage input portion 430 may have a second voltage range between a voltage VinLO and a voltage VinterHI, which is different from the first voltage range. For example, the signal of the second stage input portion 430 has a range greater than the first voltage range (such as from 0V to 4V) or another voltage range.

[0076] In some embodiments, the first stage output portion 420 is inverting, such that the output signal and the input signal have opposite polarities. In some embodiments, the first stage output portion 420 is non-inverting, such that the input signal and the output signal have the same polarity.

[0077] The second stage input section 430 includes switches that receive input signals from the first stage output section 420 at input nodes 426 and 428. In some embodiments, the switches of the second stage input section 430 include low voltage switches. In some embodiments, the switches of the second stage input section 430 include medium voltage switches. In some embodiments, all switches of the second stage input section 430 are medium voltage switches. In some embodiments, the switches of the second stage input section 430 include high voltage switches.

[0078] Based on the input signal at nodes 426 and 428, the second stage input portion 430 generates a signal for the second stage output portion 440 at nodes 436 and 438. The signal of the second stage output portion 440 may have a third voltage range between a voltage VinterLO and a voltage VinterHI, which is different from the voltage range of the input signal at nodes 426 and 428. In some embodiments, the third voltage range is the same as the voltage range of the input signal at nodes 426 and 428. For example, the signal of the second stage output portion 440 has a range greater than the first voltage range, such as a voltage range equal to the second voltage range. In some embodiments, the signal of the second stage output portion 440 has a voltage range such as from 0V to 2V or another voltage range. In some embodiments, the signal of the second stage output portion 440 has a third voltage range (such as from 2V to 4V) or another voltage range different from the first voltage range and the second voltage range.

[0079] In some embodiments, the second stage input portion 430 is inverting so that the output signal and the input signal have opposite polarities. In some embodiments, the first stage input portion 430 is non-inverting so that the input signal and the output signal have the same polarity.

[0080] The second stage output portion 440 includes switches that receive input signals from the second stage input portion 430 at input nodes 436 and 438. In some embodiments, the switches of the second stage output portion 440 include low voltage switches. In some embodiments, the switches of the second stage output portion 440 include medium voltage switches. In some embodiments, all switches of the second stage output portion 440 are medium voltage switches. In some embodiments, the switches of the second stage output portion 440 include high voltage switches. In some embodiments, the switches of the second stage output portion 440 include more than one of a low voltage switch, a medium voltage switch, and a high voltage switch, for example, as shown.

[0081] Based on the input signals at nodes 436 and 438, second stage output portion 440 generates signals for second stage buffer portion 450 at nodes 446 and 448. The signal of second stage buffer portion 450 may have a fourth voltage range between voltage VinterLO and voltage VoutHI, e.g., different from the voltage range of the input signals at nodes 436 and 438. For example, the signal of second stage buffer portion 450 has a range greater than the voltage range of the input signals at nodes 436 and 438. In some embodiments, the signal of second stage buffer portion 450 has a voltage range of 2V to 5V, or another voltage range.

[0082] In some embodiments, the second stage output portion 440 is inverting, such that the output signal and the input signal have opposite polarities. In some embodiments, the first stage output portion 440 is non-inverting, such that the input signal and the output signal have the same polarity.

[0083] The second stage buffer portion 450 includes switches that receive input signals from the second stage output portion 440 at input nodes 446 and 448. In some embodiments, the switches of the second stage buffer portion 450 include low voltage switches. In some embodiments, the switches of the second stage buffer portion 450 include medium voltage switches. In some embodiments, the switches of the second stage buffer portion 450 include high voltage switches. In some embodiments, all switches of the second stage buffer portion 450 are high voltage switches.

[0084] Based on the input signals at nodes 446 and 448, the second stage buffer portion 450 generates an output signal of the level shifter circuit 400 at nodes 456 and 458. The output signal of the level shifter circuit 400 may have a fifth voltage range between the voltage VoutLO and the voltage VoutHI, for example, the fifth voltage range is the same as the voltage range of the input signals at nodes 446 and 448. In some embodiments, the output signal of the level shifter circuit 400 has a voltage range of 2V to 5V, or another voltage range. In some embodiments, the output signal of the level shifter circuit 400 may have a fifth voltage range that is different from the voltage range of the input signals at nodes 446 and 448.

[0085] In some embodiments, the second stage buffer portion 450 is inverting so that the output signal and the input signal have opposite polarities. In some embodiments, the first stage output 450 portion is non-inverting so that the input signal and the output signal have the same polarity.

[0086] For example, the following examples of configurations and relationships between various voltages may be used to ensure or maximize functionality while preventing or minimizing voltage stress or overstress of the various transistors.

[0087] In some embodiments, the voltage VcascN1 may be connected to the voltage VinHI, or may be otherwise the same or substantially the same as the voltage VinHI. In some embodiments, for example, if the first-stage input section 410 is used, the voltage VcascN1 is less than the voltage VinHI+the Vgs threshold voltage of switches N4d and N5d to limit leakage. In some embodiments, the voltage VcascN1 is less than the maximum voltage allowed by the low voltage switch+the Vgs threshold voltage of switches N4d and N5d. In some embodiments, the voltage VcascN1 is greater than the voltage VcascN2-the Vgs threshold of switches N4u and N5u+the maximum voltage allowed by the medium voltage switch. In some embodiments, the voltage VcascN2 is the average of the voltage VinterHI and the voltage VinLO. In some embodiments, the voltage VcascN2 is less than the voltage VinLO+the maximum voltage allowed by the medium voltage switch. In some embodiments, the voltage VcascN2 is greater than the voltage VinterHI-the maximum voltage allowed by the medium voltage switch.

[0088] In some embodiments, when the voltage VinterHI-voltage VinHI is not greater than the maximum voltage allowed by the medium voltage switch, the cascode switches N4u and N5u are omitted. In some embodiments, the voltage VcascN2 can be connected to the voltage VinHI, or otherwise be the same or substantially the same as the voltage VinHI. In some embodiments, for example, if the first-stage input section 410 is used, the voltage VcascN2 is less than the voltage VinHI+the Vgs threshold voltage of switches N4d and N5d to limit leakage. In some embodiments, the voltage VcascN1 is less than the maximum voltage allowed by the low voltage switch+the Vgs threshold voltage of switches N4d and N5d. In some embodiments, the voltage VcascN2 is the average of the voltage VinterHI and the voltage VinLO. In some embodiments, the voltage VcascN2 is less than the voltage VinLO+the maximum voltage allowed by the medium voltage switch. In some embodiments, the voltage VcascN2 is greater than the voltage VinterHI-the maximum voltage allowed by the medium voltage switch.

[0089] In some embodiments, the voltage VcascP may be equal to the voltage VoutLO. In some embodiments, for example, the voltage VcascP is reduced to increase the switching speed. In some embodiments, the voltage VcascP is greater than the voltage VinterHI-the maximum voltage allowed by the medium voltage switch.

[0090] In some embodiments, switches N3d and N2d are omitted. In some embodiments, switches N3d and N2d are used to limit leakage, for example, if the gate voltages of switches N3u and N2u are not sufficiently discharged (eg, equal to or less than voltage VinterLO).

[0091] In some embodiments, voltage VinterLO may be connected to voltage VoutLO, or otherwise be the same or substantially the same as voltage VoutLO. In some embodiments, voltage VinterLO is less than voltage VoutLO + the Vgs threshold voltage of buffer switches N8 and N9, for example, to limit leakage. In some embodiments, voltage VinterLO is greater than voltage VoutHI - the maximum voltage allowed on the high voltage switch.

[0092] In some embodiments, the cascode voltage VcascN3 is equal to the voltage VinterHI. In some embodiments, the cascode voltage VcascN3 is less than the voltage VinterHI + the Vgs threshold voltage of the cascode switches N6 and N7, for example, to limit leakage. In some embodiments, the cascode voltage VcascN3 is greater than the voltage VinterLO + the Vgs threshold voltage of the switches N2 and N3 + the overdrive margin voltage of the switches N2 and N3. In some embodiments, the overdrive margin voltage is sufficient to turn on the switches N2 and N3 enough to discharge the nodes 436 and 438.

[0093] In some embodiments, switches P3 and P2 are omitted. When used, switches P3 and P2 can increase speed by increasing the voltage at nodes 436 and 438, and can reduce the drain-source voltage of switches N6 and N7. In embodiments where voltage VoutHI is not always greater than voltage VinterHI, switches P2 and P3 can be omitted, for example, to avoid leakage from voltage VinterHI to voltage VoutHI or from voltage VoutHI to voltage VinterHI through cascode switches N6 and N7.

[0094] In some embodiments, one of the outputs VOUT and VOUT_N is not required, and switches N9 and P11 are omitted or switches N8 and P10 are omitted, for example, to save area and increase speed.

[0095] In some embodiments, switches PL1 and PL2 are omitted. When used, switches PL1 and PL2 increase speed by increasing the voltage at nodes 416 and 418. In embodiments where voltage VinterHI is not always greater than voltage VinHI, switch P may be omitted, for example, to avoid leakage from voltage VinterHI to voltage VinHI or from voltage VinHI to voltage VinterHI through cascode switches N4u, N4d, N4u, and N5d.

[0096] Figure 5 2 is a schematic circuit diagram of a level shifter circuit 500 according to some embodiments. The level shifter circuit 500 may include aspects similar to or identical to those described above with reference to the level shifter circuit 300 and / or the reference level shifter circuit 400 .

[0097] The level shifter circuit 500 is a non-limiting example of the level shifter circuit 200 , and includes a first stage input portion 510 , a first stage output portion 520 , a second stage input portion 530 , a second stage output portion 540 , and a second stage buffer portion 550 .

[0098] The first stage input section 510 includes switches that receive input signals at input nodes 512 and 514 from, for example, a controller, such as controller 110. In the illustrated embodiment, the switches of the first stage input section 510 are low voltage switches. In an alternative embodiment, node 516 is connected to node 514, and the input signal from the controller is single ended.

[0099] The input signals at nodes 512 and 514 may have a first voltage range (such as from 0V to 1V) or another voltage range between voltage VinLO and voltage VinHI. Based on the input signals, first stage input portion 510 generates signals for first stage output portion 520 at nodes 516 and 518, where the signals of first stage output portion 520 may also have a first voltage range. In some embodiments, the signals of first stage output portion 520 have another voltage range.

[0100] In some embodiments, the first stage input portion 510 is inverting so that the output signal and the input signal have opposite polarities. In some embodiments, the first stage input portion is non-inverting so that the input signal and the output signal have the same polarity.

[0101] The first stage output portion 520 includes switches that receive input signals from the first stage input portion 510 at input nodes 516 and 518. In some embodiments, the switches of the first stage output portion 520 include low voltage switches. In some embodiments, the switches of the first stage output portion 520 include medium voltage switches. In some embodiments, the switches of the first stage output portion 520 include high voltage switches. In some embodiments, the switches of the first stage output portion 520 include more than one of a low voltage switch, a medium voltage switch, and a high voltage switch, for example, as shown.

[0102] In the illustrated embodiment, the input signals at nodes 516 and 518 may have a first voltage range (such as from 0V to 1V) or another voltage range. Based on the input signals at nodes 516 and 518, the first stage output portion 520 generates a signal for the second stage input portion 530 at nodes 526 and 528, wherein the signal of the second stage input portion 530 may have a second voltage range between a voltage VinLO and a voltage VinterHI, which is different from the first voltage range. For example, the signal of the second stage input portion 530 has a range greater than the first voltage range (such as from 0V to 4V) or another voltage range.

[0103] In some embodiments, the first stage output portion 520 is inverting, such that the output signal and the input signal have opposite polarities. In some embodiments, the first stage output portion 520 is non-inverting, such that the input signal and the output signal have the same polarity.

[0104] The second stage input portion 530 includes switches that receive input signals from the first stage output portion 520 at input nodes 526 and 528. In some embodiments, the switches of the second stage input portion 530 include low voltage switches. In some embodiments, the switches of the second stage input portion 530 include medium voltage switches. In some embodiments, all switches of the second stage input portion 530 are medium voltage switches. In some embodiments, the switches of the second stage input portion 530 include low voltage switches and medium voltage switches. In some embodiments, the switches of the second stage input portion 530 include high voltage switches.

[0105] Based on the input signal at nodes 526 and 528, the second stage input portion 530 generates a signal for the second stage output portion 540 at nodes 536 and 538. The signal of the second stage output portion 540 may have a third voltage range between the voltage VinterLO and the voltage VinterHI, which is different from the voltage range of the input signal at nodes 526 and 528. In some embodiments, the third voltage range is the same as the voltage range of the input signal at nodes 526 and 528. For example, the signal of the second stage output portion 540 has a range greater than the first voltage range, such as a voltage range equal to the second voltage range. In some embodiments, the signal of the second stage output portion 540 has a voltage range such as from 0V to 2V or another voltage range. In some embodiments, the signal of the second stage output portion 540 has a third voltage range (such as from 2V to 4V) or another voltage range different from the first voltage range and the second voltage range.

[0106] In some embodiments, the second stage input portion 530 is inverting, such that the output signal and the input signal have opposite polarities. In some embodiments, the second stage input portion 530 is non-inverting, such that the input signal and the output signal have the same polarity.

[0107] The second stage output portion 540 includes a switch that receives an input signal from the second stage input portion 530 at input nodes 536 and 538. In some embodiments, the switch of the second stage output portion 540 includes a low voltage switch. In some embodiments, the switch of the second stage output portion 540 includes a medium voltage switch. In some embodiments, the switch of the second stage output portion 540 includes a high voltage switch. In some embodiments, the switch of the second stage output portion 540 includes more than one of a low voltage switch, a medium voltage switch, and a high voltage switch, for example, as shown.

[0108] Based on the input signals at nodes 536 and 538, the second stage output portion 540 generates a signal for the second stage buffer portion 550 at nodes 546 and 548. The signal of the second stage buffer portion 550 can have a fourth voltage range between the voltage VinterLO and the voltage VoutHI, for example, which is different from the voltage range of the input signals at nodes 536 and 538. For example, the signal of the second stage buffer portion 550 has a range greater than the voltage range of the input signals at nodes 536 and 538. In some embodiments, the signal of the second stage buffer portion 550 has a voltage range of 2V to 5V, or another voltage range.

[0109] In some embodiments, the second stage output portion 540 is inverting, such that the output signal and the input signal have opposite polarities. In some embodiments, the second stage output portion 540 is non-inverting, such that the input signal and the output signal have the same polarity.

[0110] The second stage buffer portion 550 includes switches that receive input signals from the second stage output portion 540 at input nodes 546 and 548. In some embodiments, the switches of the second stage buffer portion 550 include low voltage switches. In some embodiments, the switches of the second stage buffer portion 550 include medium voltage switches. In some embodiments, the switches of the second stage buffer portion 550 include high voltage switches. In some embodiments, the switches of the second stage buffer portion 550 include more than one of a low voltage switch, a medium voltage switch, and a high voltage switch, for example, as shown.

[0111] Based on the input signals at nodes 546 and 548, the second stage buffer portion 550 generates an output signal of the level shifter circuit 500 at nodes 556 and 558. The output signal of the level shifter circuit 500 may have a fifth voltage range between the voltage VoutLO and the voltage VoutHI, for example, the fifth voltage range is the same as the voltage range of the input signals at nodes 546 and 548. In some embodiments, the output signal of the level shifter circuit 500 has a voltage range of 2V to 5V, or another voltage range. In some embodiments, the output signal of the level shifter circuit 500 may have a fifth voltage range that is different from the voltage range of the input signals at nodes 546 and 548.

[0112] In some embodiments, the second stage buffer portion 550 is inverting so that the output signal and the input signal have opposite polarities. In some embodiments, the first stage buffer portion 550 is non-inverting so that the input signal and the output signal have the same polarity.

[0113] For example, the following examples of configurations and relationships between various voltages may be used to ensure or maximize functionality while preventing or minimizing voltage stress or overstress of the various transistors.

[0114] In some embodiments, the voltage VcascN1 may be connected to the voltage VinHI, or may be otherwise the same or substantially the same as the voltage VinHI. In some embodiments, for example, if the first-stage input section 510 is used, the voltage VcascN1 is less than the voltage VinHI+the Vgs threshold voltage of switches N4d and N5d to limit leakage. In some embodiments, the voltage VcascN1 is less than the maximum voltage allowed by the low voltage switch+the Vgs threshold voltage of switches N4d and N5d. In some embodiments, the voltage VcascN1 is greater than the voltage VcascN2-the Vgs threshold of switches N4u and N5u+the maximum voltage allowed by the medium voltage switch. In some embodiments, the voltage VcascN2 is the average of the voltage VinterHI and the voltage VinLO. In some embodiments, the voltage VcascN2 is less than the voltage VinLO+the maximum voltage allowed by the medium voltage switch. In some embodiments, the voltage VcascN2 is greater than the voltage VinterHI-the maximum voltage allowed by the medium voltage switch.

[0115] In some embodiments, when the voltage VinterHI-voltage VinHI is not greater than the maximum voltage allowed by the medium voltage switch, the cascode switches N4u and N5u are omitted. In some embodiments, the voltage VcascN2 can be connected to the voltage VinHI, or otherwise be the same or substantially the same as the voltage VinHI. In some embodiments, for example, if the first-stage input section 510 is used, the voltage VcascN2 is less than the voltage VinHI+the Vgs threshold voltage of switches N4d and N5d to limit leakage. In some embodiments, the voltage VcascN1 is less than the maximum voltage allowed by the low voltage switch+the Vgs threshold voltage of switches N4d and N5d. In some embodiments, the voltage VcascN2 is the average of the voltage VinterHI and the voltage VinLO. In some embodiments, the voltage VcascN2 is less than the voltage VinLO+the maximum voltage allowed by the medium voltage switch. In some embodiments, the voltage VcascN2 is greater than the voltage VinterHI-the maximum voltage allowed by the medium voltage switch.

[0116] In some embodiments, the voltage VcascP may be equal to the voltage VoutLO. In some embodiments, for example, the voltage VcascP is reduced to increase the switching speed. In some embodiments, the voltage VcascP is greater than the voltage VinterHI-the maximum voltage allowed by the medium voltage switch.

[0117] In some embodiments, switches N3d and N2d are omitted. In some embodiments, switches N3d and N2d are used to limit leakage, for example, if the gate voltages of switches N3u and N2u are not sufficiently discharged (eg, equal to or less than voltage VinterLO).

[0118] In some embodiments, voltage VinterLO may be connected to voltage VoutLO, or otherwise be the same or substantially the same as voltage VoutLO. In some embodiments, voltage VinterLO is less than voltage VoutLO + the Vgs threshold voltage of buffer switches N8 and N9, for example, to limit leakage. In some embodiments, voltage VinterLO is greater than voltage VoutHI - the maximum voltage allowed on the high voltage switch.

[0119] In some embodiments, the cascode voltage VcascN3 is equal to the voltage VinterHI. In some embodiments, the cascode voltage VcascN3 is less than the voltage VinterHI + the Vgs threshold voltage of the cascode switches N6 and N7, for example, to limit leakage. In some embodiments, the cascode voltage VcascN3 is greater than the voltage VinterLO + the Vgs threshold voltage of the switches N2 and N3 + the overdrive margin voltage of the switches N2 and N3. In some embodiments, the overdrive margin voltage is sufficient to turn on the switches N2 and N3 enough to discharge the nodes 536 and 538.

[0120] In some embodiments, switches P3 and P2 are omitted. When used, switches P3 and P2 can increase speed by increasing the voltage at nodes 536 and 538, and can reduce the drain-source voltage of switches N6 and N7. In embodiments where voltage VoutHI is not always greater than voltage VinterHI, switches P2 and P3 can be omitted, for example, to avoid leakage from voltage VinterHI to voltage VoutHI or from voltage VoutHI to voltage VinterHI through cascode switches N6 and N7.

[0121] In some embodiments, switches P12 and P13 are omitted. In some embodiments, for example, switches P12 and P13 are used to speed up the switching of the sources of switches N8u and N9u and / or reduce the drain-source voltage of switches N8u and N9u.

[0122] In some embodiments, switches PL1 and PL2 are omitted. When used, switches PL1 and PL2 increase speed by increasing the voltage at nodes 516 and 518. In embodiments where voltage VinterHI is not always greater than voltage VinHI, switch P may be omitted, for example, to avoid leakage from voltage VinterHI to voltage VinHI or from voltage VinHI to voltage VinterHI through cascode switches N4u, N4d, N4u, and N5d.

[0123] In some embodiments, one of the outputs VOUT and VOUT_N is not required, and switches N9 and P11 are omitted or switches N8 and P10 are omitted, for example, to save area and increase speed.

[0124] In some embodiments, voltage VcascN2 is less than the Vgs threshold voltage of switches N4u and N5u + voltage VinHI + maximum voltage allowed on the low voltage switch, for example, in embodiments where first stage input section 510 is used.

[0125] In some embodiments, voltage VcascN2 is less than the Vgs threshold voltage of switches N4u and N5u + 2× the maximum voltage allowed on the low voltage switches, for example, in embodiments where switch P in first stage input section 510 is omitted.

[0126] In some embodiments, voltage VcascN1 may be connected to voltage VinHI or otherwise be the same or substantially the same as voltage VinHI. In some embodiments, voltage VcascN1 is less than the Vgs voltage threshold of switches N4d and N5d + voltage VinHI, for example, in embodiments where first stage input section 510 is used.

[0127] In some embodiments, voltage VcascN1 is less than the Vgs voltage threshold of switches N4 d and N5 d ​​+ the maximum allowed voltage of the low voltage switches, for example, in embodiments where switch P in first stage input section 510 is omitted.

[0128] Figure 6 2 is a schematic circuit diagram of a level shifter circuit 600 according to some embodiments. The level shifter circuit 600 may include aspects similar or identical to those described above with reference to the level shifter circuits 300, 400, and / or 500.

[0129] The level shifter circuit 600 is a non-limiting example of the level shifter circuit 200 , and includes a first stage input portion 610 , a first stage output portion 620 , a second stage input portion 630 , a second stage output portion 640 , and a second stage buffer portion 650 .

[0130] First level input portion 610 has aspects similar or identical to those described above with reference to first level input portion 510. First level output portion 620 has aspects similar or identical to those described above with reference to first level output portion 520. Second level input portion 630 has aspects similar or identical to those described above with reference to second level input portion 530.

[0131] The second stage output portion 640 includes switches that receive input signals from the second stage input portion 630 at input nodes 636 and 638. In some embodiments, the switches of the second stage output portion 640 include low voltage switches. In some embodiments, all switches of the second stage output portion 640 are low voltage switches. In some embodiments, the switches of the second stage output portion 640 include medium voltage switches. In some embodiments, the switches of the second stage output portion 640 include high voltage switches. In some embodiments, the switches of the second stage output portion 640 include more than one of a low voltage switch, a medium voltage switch, and a high voltage switch, for example, as shown.

[0132] Based on the input signals at nodes 636 and 638, the second stage output portion 640 generates a signal for the second stage buffer portion 650 at nodes 646 and 648. The signal of the second stage buffer portion 650 can have a fourth voltage range between the voltage VinterLO and the voltage VoutHI, for example, the fourth voltage range is different from the voltage range of the input signals at nodes 636 and 638. For example, the signal of the second stage buffer portion 650 has a range greater than the voltage range of the input signals at nodes 636 and 638. In some embodiments, the signal of the second stage buffer portion 650 has a voltage range of 2V to 5V, or another voltage range.

[0133] In some embodiments, the second stage output portion 640 is inverting, such that the output signal and the input signal have opposite polarities. In some embodiments, the second stage output portion 640 is non-inverting, such that the input signal and the output signal have the same polarity.

[0134] The second stage buffer portion 650 includes switches that receive input signals from the second stage output portion 640 at input nodes 646 and 648. In some embodiments, the switches of the second stage buffer portion 650 include low voltage switches. In some embodiments, all switches of the second stage buffer portion 650 are low voltage switches. In some embodiments, the switches of the second stage buffer portion 650 include medium voltage switches. In some embodiments, the switches of the second stage buffer portion 650 include high voltage switches. In some embodiments, the switches of the second stage buffer portion 650 include more than one of a low voltage switch, a medium voltage switch, and a high voltage switch, for example, as shown.

[0135] Based on the input signals at nodes 646 and 648, the second stage buffer portion 650 generates an output signal of the level shifter circuit 600 at nodes 656 and 658. The output signal of the level shifter circuit 600 may have a fifth voltage range between the voltage VoutLO and the voltage VoutHI, for example, the fifth voltage range is the same as the voltage range of the input signals at nodes 646 and 648. In some embodiments, the output signal of the level shifter circuit 600 has a voltage range of 2V to 5V, or another voltage range. In some embodiments, the output signal of the level shifter circuit 600 may have a fifth voltage range that is different from the voltage range of the input signals at nodes 646 and 648.

[0136] In some embodiments, the second stage buffer portion 650 is inverting so that the output signal and the input signal have opposite polarities. In some embodiments, the second stage buffer portion 650 is non-inverting so that the input signal and the output signal have the same polarity.

[0137] For example, the following examples of configurations and relationships between various voltages may be used to ensure or maximize functionality while preventing or minimizing voltage stress or overstress of the various transistors.

[0138] In some embodiments, the voltage VcascN1 may be connected to the voltage VinHI, or may be otherwise the same or substantially the same as the voltage VinHI. In some embodiments, for example, if the first-stage input section 610 is used, the voltage VcascN1 is less than the voltage VinHI+the Vgs threshold voltage of switches N4d and N5d to limit leakage. In some embodiments, the voltage VcascN1 is less than the maximum voltage allowed by the low voltage switch+the Vgs threshold voltage of switches N4d and N5d. In some embodiments, the voltage VcascN1 is greater than the voltage VcascN2-the Vgs threshold of switches N4u and N5u+the maximum voltage allowed by the medium voltage switch. In some embodiments, the voltage VcascN2 is the average of the voltage VinterHI and the voltage VinLO. In some embodiments, the voltage VcascN2 is less than the voltage VinLO+the maximum voltage allowed by the medium voltage switch. In some embodiments, the voltage VcascN2 is greater than the voltage VinterHI-the maximum voltage allowed by the medium voltage switch.

[0139] In some embodiments, when the voltage VinterHI-voltage VinHI is not greater than the maximum voltage allowed by the medium voltage switch, the cascode switches N4u and N5u are omitted. In some embodiments, the voltage VcascN2 can be connected to the voltage VinHI, or otherwise be the same or substantially the same as the voltage VinHI. In some embodiments, for example, if the first-stage input section 610 is used, the voltage VcascN2 is less than the voltage VinHI+the Vgs threshold voltage of switches N4d and N5d to limit leakage. In some embodiments, the voltage VcascN1 is less than the maximum voltage allowed by the low voltage switch+the Vgs threshold voltage of switches N4d and N5d. In some embodiments, the voltage VcascN2 is the average of the voltage VinterHI and the voltage VinLO. In some embodiments, the voltage VcascN2 is less than the voltage VinLO+the maximum voltage allowed by the medium voltage switch. In some embodiments, the voltage VcascN2 is greater than the voltage VinterHI-the maximum voltage allowed by the medium voltage switch.

[0140] In some embodiments, the voltage VcascP may be equal to the voltage VoutLO. In some embodiments, for example, the voltage VcascP is reduced to increase the switching speed. In some embodiments, the voltage VcascP is greater than the voltage VinterHI-the maximum voltage allowed by the medium voltage switch.

[0141] In some embodiments, switches N3d and N2d are omitted. In some embodiments, switches N3d and N2d are used to limit leakage, for example, if the gate voltages of switches N3u and N2u are not sufficiently discharged (eg, equal to or less than voltage VinterLO).

[0142] In some embodiments, voltage VinterLO may be connected to voltage VoutLO, or otherwise be the same or substantially the same as voltage VoutLO. In some embodiments, voltage VinterLO is less than voltage VoutLO + the Vgs threshold voltage of buffer switches N8 and N9, for example, to limit leakage. In some embodiments, voltage VinterLO is greater than voltage VoutHI - the maximum voltage allowed on the high voltage switch.

[0143] In some embodiments, the cascode voltage VcascN3 is equal to the voltage VinterHI. In some embodiments, the cascode voltage VcascN3 is less than the voltage VinterHI + the Vgs threshold voltage of the cascode switches N6 and N7, for example, to limit leakage. In some embodiments, the cascode voltage VcascN3 is greater than the voltage VinterLO + the Vgs threshold voltage of the switches N2 and N3 + the overdrive margin voltage of the switches N2 and N3. In some embodiments, the overdrive margin voltage is sufficient to turn on the switches N2 and N3 enough to discharge the nodes 636 and 638.

[0144] In some embodiments, switches P3 and P2 are omitted. When used, switches P3 and P2 can increase speed by increasing the voltage at nodes 636 and 638, and can reduce the drain-source voltage of switches N6 and N7. In embodiments where voltage VoutHI is not always greater than voltage VinterHI, switches P2 and P3 can be omitted, for example, to avoid leakage from voltage VinterHI to voltage VoutHI or from voltage VoutHI to voltage VinterHI through cascode switches N6 and N7.

[0145] In some embodiments, switches P12 and P13 are omitted. In some embodiments, for example, switches P12 and P13 are used to speed up the switching of the sources of switches N8u and N9u and / or reduce the drain-source voltage of switches N8u and N9u.

[0146] In some embodiments, switch P is omitted. When used, switch P2 increases speed by increasing the voltage at nodes 616 and 618. In embodiments where voltage VinterHI is not always greater than voltage VinHI, switch P may be omitted, for example, to avoid leakage from voltage VinterHI to voltage VinHI or from voltage VinHI to voltage VinterHI through cascode switches N4u, N4d, N4u, and N5d.

[0147] In some embodiments, one of the outputs VOUT and VOUT_N is not required, and switches N9 and P11 are omitted or switches N8 and P10 are omitted, for example, to save area and increase speed.

[0148] In some embodiments, voltage VcascN2 is less than the Vgs threshold voltage of switches N4u and N5u + voltage VinHI + maximum voltage allowed on the low voltage switch, for example, in embodiments where first stage input section 610 is used.

[0149] In some embodiments, voltage VcascN2 is less than the Vgs threshold voltage of switches N4u and N5u + 2× the maximum voltage allowed on the low voltage switches, for example, in embodiments where switch P in first stage input section 610 is omitted.

[0150] In some embodiments, voltage VcascN1 may be connected to voltage VinHI or otherwise be the same or substantially the same as voltage VinHI. In some embodiments, voltage VcascN1 is less than the Vgs voltage threshold of switches N4d and N5d + voltage VinHI, for example, in embodiments where first stage input section 610 is used.

[0151] In some embodiments, voltage VcascN1 is less than the Vgs voltage threshold of switches N4 d and N5 d ​​+ the maximum allowed voltage of the low voltage switch, for example, in embodiments where switch P in first stage input section 610 is omitted.

[0152] In some embodiments, the voltage VcascP2 may be equal to the voltage VoutHI-the maximum voltage allowed by the medium voltage switch. In some embodiments, the voltage VcascP2 is reduced, for example, to increase the switching speed.

[0153] Figure 7 A schematic circuit diagram of an electronic system 700 having a level shift circuit 720 according to some embodiments is shown. In the illustrated embodiment, the electronic system 700 is a memory system 700 that includes a controller 710, a level shift circuit 720, and a controlled circuit that is a switch array 730, i.e., an array of switches. The memory system 700 also includes a bit line driver and sensing circuitry 740 and a memory array 750. Other electronic systems may use a level shifter circuit having characteristics similar or identical to those of the level shift circuit 720.

[0154] The memory array 750 includes a memory bit cell array 758. The illustrated bit cells 758 are examples and are not meant to be limiting. Each bit cell 758 is located at or near an intersection 756 of a particular one of the bit lines 752 and a particular one of the word lines 754.

[0155] The bit line driver and sense circuitry 740 is used to store data in the memory bit cells 758 connected thereto through the switch array 730. In addition, the bit line driver and sense circuitry 740 can be used to retrieve data from the memory bit cells 758 connected thereto through the switch array 730. Which memory bit cells 758 are connected to the bit line driver and sense circuitry 740 is determined by control signals generated by the controller 710.

[0156] The controller 710 generates control switch signals for the switch array 730 using, for example, low voltage switches, wherein the control signals generated by the controller 710 have a lower level voltage range (such as from 0V to 1V) or another voltage range.

[0157] The switch array 730 performs its switching function using a circuit having, for example, a high voltage switch that generates or conducts a signal having a higher voltage range, such as 2 V to 5 V, or another voltage range. In addition, the switch array 730 generates or conducts a signal in response to an input control signal having a higher voltage range.

[0158] The level shift circuit 720 includes one or more level shifter circuits, examples of which are described elsewhere herein. The level shift circuit 720 receives a lower voltage control signal from the controller 710 and generates a higher voltage control signal for the switch array 730. In response to the higher voltage control signal, the switches of the switch array 730 selectively connect or disconnect the bit lines 752 of the memory array 750 to or from the bit line driver and sensing circuit system 740.

[0159] Figure 8 A flow chart of a method 800 of using an electronic system according to some embodiments is shown. The method 800 may be performed, for example, by the electronic system 100 or 700 or by any of the level shifter circuits described.

[0160] At 810, the first circuit receives the first voltage and generates a second voltage. In some embodiments, the second voltage varies between a VinLO low voltage (eg, 0V) and a VinHI high voltage (eg, 1V). In some embodiments, the first circuit includes a plurality of low voltage threshold switches.

[0161] At 820, the second circuit receives the second voltage and generates a third voltage. In some embodiments, the third voltage varies between a VinLO low voltage and a VinterHI high voltage (e.g., 4V). In some embodiments, the second circuit includes a plurality of high voltage threshold switches. In some embodiments, the second circuit includes a plurality of medium voltage threshold switches.

[0162] At 830, the third circuit receives the third voltage and generates a fourth voltage. In some embodiments, the fourth voltage varies between a VinterLO low voltage and a VinterHI high voltage (such as 2V to 4V) or another voltage range. In some embodiments, the third circuit includes a plurality of high voltage threshold switches. In some embodiments, the third circuit includes a plurality of medium voltage threshold switches.

[0163] At 840, the fourth circuit receives the fourth voltage and generates a fifth voltage, wherein the fifth voltage varies between the VinterLO voltage and the VoutHI high voltage (e.g., 5V). In some embodiments, the fourth circuit includes a plurality of high voltage threshold switches. In some embodiments, the fourth circuit includes a plurality of medium voltage threshold switches. In some embodiments, the fourth circuit includes a plurality of high voltage threshold switches and a plurality of medium voltage threshold switches.

[0164] At 850, the fifth circuit receives the fifth voltage and generates a sixth voltage. In some embodiments, the sixth voltage varies between a VoutLO low voltage and a VoutHI high voltage (such as 2V to 5V) or another voltage range. In some embodiments, the fifth circuit includes a plurality of high voltage threshold switches. In some embodiments, the fifth circuit includes a plurality of medium voltage threshold switches. In some embodiments, the fifth circuit includes a plurality of high voltage threshold switches and a plurality of medium voltage threshold switches.

[0165] Examples of the invention are summarized here. Other examples can also be understood from the entire content of the specification and claims submitted herein.

[0166] Example 1. One embodiment is a level shifter circuit, the level shifter circuit comprising a first stage input circuit configured to receive an input voltage and generate a second voltage, wherein the second voltage varies between a first low voltage and a first high voltage, and wherein the first stage input circuit comprises a plurality of low voltage threshold switches. The level shifter also comprises a first stage output circuit configured to receive the second voltage and generate a third voltage, wherein the third voltage varies between the first low voltage and the second high voltage, and wherein the first stage output circuit comprises a first plurality of medium voltage switches. The level shifter also comprises a second stage input circuit configured to receive the third voltage and generate a fourth voltage, wherein the fourth voltage varies between a second low voltage and the second high voltage, and wherein the second stage output circuit comprises a second plurality of medium voltage switches. The level shifter also comprises a second stage output circuit configured to receive the fourth voltage and generate a fifth voltage, wherein the fifth voltage varies between the second low voltage and the third high voltage, and wherein the second stage output circuit comprises a third plurality of medium voltage switches. The level shifter also comprises a buffer circuit configured to receive the fifth voltage and generate an output voltage, wherein the output voltage varies between a third low voltage and the third high voltage.

[0167] Example 2. The level shifter circuit of Example 1, wherein the second high voltage is greater than the first low voltage, and wherein the second high voltage is less than the third high voltage.

[0168] Example 3. The level shifter circuit of any of Examples 1 or 2, wherein the second low voltage is greater than the first low voltage.

[0169] Example 4. The level shifter circuit of any of Examples 1 to 3, wherein the second low voltage is equal to the third low voltage.

[0170] Example 5. The level shifter circuit of any of Examples 1 to 4, wherein the first stage output circuit comprises a second plurality of low voltage switches.

[0171] Example 6. The level shifter circuit of any of Examples 1 to 5, wherein the first high voltage is greater than the first low voltage and less than the third high voltage.

[0172] Example 7. The level shifter circuit of any of Examples 1 to 6, wherein the buffer circuit comprises a fourth plurality of medium voltage switches.

[0173] Example 8. The level shifter circuit of any one of Examples 1 to 7, wherein each of the switches of the level shifter is a low voltage switch or a medium voltage switch.

[0174] Example 9. Another embodiment is an array circuit. The array circuit includes a device array, wherein each of the plurality of devices in the array includes at least one high voltage switch. The array circuit also includes a controller configured to generate a plurality of first control signals for controlling the device array. The array circuit also includes an array of level shifters, each level shifter being configured to receive one of the first control signals as an input voltage from the controller, generate one of the plurality of second control signals as an output voltage, and provide the output voltage to one of the devices in the device array. Each of the level shifters includes a first stage input circuit configured to receive the input voltage and generate a second voltage, wherein the second voltage varies between a first low voltage and a first high voltage, and wherein the first stage input circuit includes a plurality of low voltage threshold switches. Each of the level shifters also includes a first stage output circuit configured to receive the second voltage and generate a third voltage, wherein the third voltage varies between the first low voltage and a second high voltage, and wherein the first stage output circuit includes a first plurality of medium voltage switches. Each of the level shifters further includes a second-stage input circuit configured to receive the third voltage and generate a fourth voltage, wherein the fourth voltage varies between a second low voltage and the second high voltage, and wherein the second-stage output circuit includes a second plurality of medium voltage switches. Each of the level shifters further includes a second-stage output circuit configured to receive the fourth voltage and generate a fifth voltage, wherein the fifth voltage varies between the second low voltage and the third high voltage, and wherein the second-stage output circuit includes a third plurality of medium voltage switches. Each of the level shifters further includes a buffer circuit configured to receive the fifth voltage and generate the output voltage, wherein the output voltage varies between a third low voltage and the third high voltage.

[0175] Example 10. The array circuit of Example 9, wherein the second high voltage is greater than the first low voltage, and wherein the second high voltage is less than the third high voltage.

[0176] Example 11. The array circuit of any of Examples 9 or 10, wherein the second low voltage is greater than the first low voltage.

[0177] Example 12. The array circuit of any of Examples 9 to 11, wherein the second low voltage is equal to the third low voltage.

[0178] Example 13. The array circuit of any of Examples 9 to 12, wherein the first stage output circuit comprises a fourth plurality of low voltage switches.

[0179] Example 14. The array circuit of any of Examples 9 to 13, wherein the first high voltage is greater than the first low voltage and less than the third high voltage.

[0180] Example 15. The array circuit of any one of Examples 9 to 14, wherein the snubber circuit comprises a plurality of medium voltage switches.

[0181] Example 16. The array circuit of any one of Examples 9 to 15, wherein each of the switches of the level shifter is a low voltage switch or a medium voltage switch.

[0182] Example 17. Another embodiment is a method of using a level shifter circuit. The method includes using a first-stage input circuit including a plurality of low-voltage threshold switches to receive an input voltage and generate a second voltage based in part on the input voltage, wherein the second voltage varies between a first low voltage and a first high voltage. The method also includes using a first-stage output circuit including a first plurality of medium-voltage switches to receive the second voltage and generate a third voltage based in part on the second voltage, wherein the third voltage varies between the first low voltage and a second high voltage. The method also includes using a second-stage input circuit including a second plurality of medium-voltage switches to receive the third voltage and generate a fourth voltage based in part on the third voltage, wherein the fourth voltage varies between a second low voltage and the second high voltage. The method also includes using a second-stage output circuit including a third plurality of medium-voltage switches to receive the fourth voltage and generate a fifth voltage based in part on the fourth voltage, wherein the fifth voltage varies between the second low voltage and a third high voltage. The method also includes using a buffer circuit to receive the fifth voltage and generate an output voltage based in part on the fifth voltage, wherein the output voltage varies between a third low voltage and the third high voltage.

[0183] Example 18. The method of Example 17, wherein the second high voltage is greater than the first low voltage, and wherein the second high voltage is less than the third high voltage.

[0184] Example 19. The method of any of Examples 17 or 18, wherein the second low voltage is greater than the first low voltage.

[0185] Example 20. A method according to any one of Examples 17 to 19, wherein the second low voltage is equal to the third low voltage. Although the present invention has been described with reference to illustrative implementations, this specification is not intended to be interpreted in a limiting sense. By reference to the specification, various modifications and combinations of the illustrative implementations, as well as other implementations of the present invention, will be apparent to those skilled in the art. Therefore, the appended claims are intended to cover any such modifications or implementations.

Claims

1. A level shifter circuit, comprising: a first stage input circuit configured to receive an input voltage and generate a second voltage, wherein the second voltage varies between a first low voltage and a first high voltage, and wherein the first stage input circuit includes a plurality of low voltage threshold switches; a first stage output circuit configured to receive the second voltage and generate a third voltage, wherein the third voltage varies between the first low voltage and a second high voltage, and wherein the first stage output circuit comprises a first plurality of medium voltage switches; a second stage input circuit configured to receive the third voltage and generate a fourth voltage, wherein the fourth voltage varies between a second low voltage and the second high voltage, and wherein the second stage input circuit comprises a second plurality of medium voltage switches; a second stage output circuit configured to receive the fourth voltage and generate a fifth voltage, wherein the fifth voltage varies between the second low voltage and a third high voltage, and wherein the second stage output circuit comprises a third plurality of medium voltage switches; as well as The buffer circuit is configured to receive the fifth voltage and generate an output voltage, wherein the output voltage varies between a third low voltage and the third high voltage. 2 . The level shifter circuit of claim 1 , wherein the second high voltage is greater than the first low voltage, and wherein the second high voltage is less than the third high voltage. 3 . The level shifter circuit of claim 1 , wherein the second low voltage is greater than the first low voltage.

4. The level shifter circuit of claim 1, wherein the second low voltage is equal to the third low voltage.

5. The level shifter circuit of claim 1, wherein the first stage output circuit comprises a second plurality of low voltage switches. 6 . The level shifter circuit of claim 1 , wherein the first high voltage is greater than the first low voltage and less than the third high voltage.

7. The level shifter circuit of claim 1, wherein the buffer circuit comprises a fourth plurality of medium voltage switches.

8. The level shifter circuit of claim 1, wherein each of the switches of the level shifter is a low voltage switch or a medium voltage switch.

9. An array circuit comprising: An array of devices, wherein a plurality of devices in the array each include at least one high voltage switch; a controller configured to generate a plurality of first control signals for controlling the device array; as well as an array of level shifters, each level shifter being configured to receive one of the first control signals from the controller as an input voltage to generate one of a plurality of second control signals as an output voltage, and to provide the output voltage to a device in the device array, wherein the level shifters each comprise: a first stage input circuit configured to receive the input voltage and generate a second voltage, wherein the second voltage varies between a first low voltage and a first high voltage, and wherein the first stage input circuit comprises a plurality of low voltage threshold switches, a first stage output circuit configured to receive the second voltage and generate a third voltage, wherein the third voltage varies between the first low voltage and a second high voltage, and wherein the first stage output circuit comprises a first plurality of medium voltage switches, a second stage input circuit configured to receive the third voltage and generate a fourth voltage, wherein the fourth voltage varies between a second low voltage and the second high voltage, and wherein the second stage input circuit comprises a second plurality of medium voltage switches, a second stage output circuit configured to receive the fourth voltage and generate a fifth voltage, wherein the fifth voltage varies between the second low voltage and a third high voltage, and wherein the second stage output circuit comprises a third plurality of medium voltage switches, and The buffer circuit is configured to receive the fifth voltage and generate the output voltage, wherein the output voltage varies between a third low voltage and the third high voltage. 10 . The array circuit of claim 9 , wherein the second high voltage is greater than the first low voltage, and wherein the second high voltage is less than the third high voltage.

11. The array circuit of claim 9, wherein the second low voltage is greater than the first low voltage.

12. The array circuit according to claim 9, wherein the second low voltage is equal to the third low voltage.

13. The array circuit of claim 9, wherein the first stage output circuit comprises a fourth plurality of low voltage switches.

14. The array circuit of claim 9, wherein the first high voltage is greater than the first low voltage and less than the third high voltage.

15. The array circuit of claim 9, wherein the snubber circuit comprises a plurality of medium voltage switches.

16. The array circuit of claim 9, wherein each of the switches of the level shifter is a low voltage switch or a medium voltage switch.

17. A method of using a level shifter circuit, the method comprising: Utilizing a first stage input circuit comprising multiple low voltage threshold switches: receives an input voltage, and generating a second voltage based in part on the input voltage, wherein the second voltage varies between a first low voltage and a first high voltage; Using a first stage output circuit comprising a first plurality of medium voltage switches: receiving the second voltage, and generating a third voltage based in part on the second voltage, wherein the third voltage varies between the first low voltage and a second high voltage; Utilizing a second input circuit comprising a second plurality of medium voltage switches: receiving the third voltage, and generating a fourth voltage based in part on the third voltage, wherein the fourth voltage varies between a second low voltage and the second high voltage; Using a second output circuit comprising a third plurality of medium voltage switches: receiving the fourth voltage, and generating a fifth voltage based in part on the fourth voltage, wherein the fifth voltage varies between the second low voltage and a third high voltage; and Using a buffer circuit: receiving the fifth voltage, and An output voltage is generated based in part on the fifth voltage, wherein the output voltage varies between a third low voltage and the third high voltage. 18 . The method of claim 17 , wherein the second high voltage is greater than the first low voltage, and wherein the second high voltage is less than the third high voltage. The method of claim 17 , wherein the second low voltage is greater than the first low voltage.

20. The method of claim 17, wherein the second low voltage is equal to the third low voltage.

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