Analog-to-digital conversion circuit based on boost module, chip and electronic equipment

Abstract

The invention relates to the field of analog-to-digital conversion, and provides an analog-to-digital conversion circuit based on a boost module, a chip and electronic equipment. The circuit comprises a boosting module, a clock buffer module, a conversion module and a feedback module, power supply voltages of the boosting module, the conversion module and the feedback module are smaller than or equal to a first threshold value, and the boosting module is used for generating at least one voltage signal with the voltage value larger than the power supply voltage to supply power to the clock buffer module; the clock buffer module is used for generating at least one pair of clock signals with the swing larger than a first threshold value and outputting the clock signals to the conversion module so as to drive at least one unit in the conversion module. The conversion module is used for obtaining a digital output signal according to the analog input signal and the feedback signal; the feedback module is used for generating a feedback signal according to the latest digital output signal and outputting the feedback signal to the conversion module. The analog-to-digital conversion circuit disclosed by the embodiment of the invention occupies a smaller chip area, is lower in power consumption, and can realize high-quality analog-to-digital conversion under low voltage.

Description

Technical Field

[0001] The present disclosure relates to the field of analog-to-digital conversion, and in particular to an analog-to-digital conversion circuit, a chip, and an electronic device based on a boost module. Background Art

[0002] With the application and development of the Internet of Things (IoT), it has become indispensable to obtain real-time information and data from IoT devices. The power supply of IoT devices is an important aspect in the design of IoT systems because it directly affects the reliability, durability and cost of the devices. IoT devices are generally powered by batteries, solar power, cable power, wireless charging and energy harvesting (Energy Harvesting, EH). Among them, energy harvesting refers to the use of ambient energy such as solar energy, wind energy, mechanical vibration or temperature difference to provide power, reducing dependence on batteries.

[0003] However, in some environments, the density of energy that can be collected is often low, and the voltage that can be generated is also low, so that IoT devices must operate at low voltage. This poses a great challenge to the performance of some circuits in IoT devices (such as analog-to-digital conversion circuits). Some analog-to-digital conversion circuits proposed in the prior art cannot maintain high-quality analog-to-digital conversion when the power supply voltage is low. Although some analog-to-digital conversion circuits proposed in the prior art can maintain high-quality analog-to-digital conversion when the power supply voltage is low, they will greatly increase the power consumption of the analog-to-digital conversion circuit and the chip area occupied. Summary of the invention

[0004] In view of this, the present disclosure proposes an analog-to-digital conversion circuit, chip, and electronic device based on a boost module. The analog-to-digital conversion circuit of the present disclosure occupies a smaller chip area and has lower power consumption, and can achieve high-quality analog-to-digital conversion at low voltage.

[0005] According to one aspect of the present disclosure, there is provided an analog-to-digital conversion circuit based on a boost module, the circuit comprising a boost module, a clock buffer module, a conversion module and a feedback module, the power supply voltage of the boost module, the conversion module and the feedback module being less than or equal to a first threshold value, the boost module being used to generate at least one voltage signal having a voltage value greater than the power supply voltage, the voltage signal being used to power the clock buffer module; the clock buffer module being used to generate at least one pair of clock signals having a swing greater than the first threshold value, and outputting the clock signals to the conversion module to drive at least one unit in the conversion module; the conversion module being used to obtain a digital output signal according to an analog input signal and a feedback signal; and the feedback module being used to generate the feedback signal according to the latest digital output signal and output it to the conversion module.

[0006] In a possible implementation, the conversion module includes a first chopping unit, a capacitor filtering unit, a dead zone control unit, a voltage-current conversion unit, a second chopping unit, an integration unit, a quantization unit, and an output unit. The analog input signal includes a differential first input signal and a second input signal. The feedback signal includes a differential first feedback signal and a second feedback signal. The first end of the first chopping unit receives the first input signal, and the second end of the first chopping unit receives the second input signal. The third end of the first chopping unit is connected to the first end of the capacitor filtering unit, and the fourth end of the first chopping unit is connected to the second end of the capacitor filtering unit; the third end of the capacitor filtering unit is connected to the first end of the dead zone control unit and the third end of the feedback module, the fourth end of the capacitor filtering unit is connected to the second end of the dead zone control unit and the fourth end of the feedback module, and the third end of the feedback module The first feedback signal is output, and the fourth end of the feedback module outputs the second feedback signal; the third end of the dead zone control unit is connected to the first end of the voltage-current conversion unit, and the fourth end of the dead zone control unit is connected to the second end of the voltage-current conversion unit; the third end of the voltage-current conversion unit is connected to the first end of the second chopping unit, and the fourth end of the voltage-current conversion unit is connected to the second end of the second chopping unit; the third end of the second chopping unit is connected to the first end of the integration unit, and the fourth end of the second chopping unit is connected to the second end of the integration unit; the third end of the integration unit is connected to the first end of the quantization unit, the fourth end of the integration unit is connected to the second end of the quantization unit, the third end of the quantization unit is connected to the first end of the output unit, and the fourth end of the quantization unit is connected to the second end of the output unit; the third end of the output unit outputs the digital output signal.

[0007] In a possible implementation manner, the quantization unit is a time-domain quantization unit, the integration unit is a time-domain integration unit, and the quantization unit and the integration unit are implemented by digital circuits.

[0008] In a possible implementation manner, the clock signal is used to drive the first chopping unit, the dead zone control unit, and the second chopping unit.

[0009] In a possible implementation, the boost module includes multiple DCDC converters, the power supply voltage is respectively input into the multiple DCDC converters, the clock buffer module includes multiple clock buffers, each DCDC converter is connected to a clock buffer, each DCDC converter boosts the input voltage signal to obtain the boosted voltage signal and outputs it to the clock buffer connected to itself, and each clock buffer generates a pair of clock signals according to the received voltage signal and outputs them.

[0010] In a possible implementation, the swing of the clock signal used to drive the dead zone control unit is greater than or equal to a second threshold, the swing of the clock signal used to drive the first chopping unit and the second chopping unit is greater than or equal to a third threshold, and the second threshold is greater than the third threshold.

[0011] In one possible implementation, the boost module includes a DCDC converter, the clock buffer module includes a clock buffer, the DCDC converter is connected to the clock buffer, the DCDC converter boosts the input voltage signal to obtain the boosted voltage signal and outputs it to the clock buffer, and the clock buffer generates a pair of clock signals according to the received voltage signal and outputs them.

[0012] In a possible implementation, the feedback module includes a logic control unit, a third chopping unit, and a capacitive digital-to-analog conversion unit, the first end of the logic control unit serves as the first end of the feedback module, the second end of the logic control unit serves as the second end of the feedback module, the third end of the logic control unit is connected to the first end of the third chopping unit, and the fourth end of the logic control unit is connected to the second end of the third chopping unit; the third end of the third chopping unit is connected to the first end of the capacitive digital-to-analog conversion unit, and the fourth end of the third chopping unit is connected to the second end of the capacitive digital-to-analog conversion unit; the third end of the capacitive digital-to-analog conversion unit serves as the third end of the feedback module, and the fourth end of the capacitive digital-to-analog conversion unit serves as the fourth end of the feedback module.

[0013] According to another aspect of the present disclosure, a chip is provided, comprising any one of the above analog-to-digital conversion circuits.

[0014] According to another aspect of the present disclosure, an electronic device is provided, comprising the chip described above.

[0015] According to the analog-to-digital conversion circuit of the embodiment of the present disclosure, by setting a boost module and a clock buffer module, a clock signal with a swing higher than the first threshold can be obtained, and the conversion module is driven by a clock signal with a higher swing. The conversion module obtains a digital output signal according to the analog input signal and the feedback signal, and the feedback module generates a feedback signal according to the latest digital output signal and outputs it to the conversion module, thereby achieving high-quality analog-to-digital conversion. In the analog-to-digital conversion circuit, only some units in the conversion module are driven by a clock signal with a high swing, and only the clock buffer module needs to be powered by a voltage signal with a voltage value greater than the first threshold. The boost module, other units of the conversion module, and the feedback module can still be powered by a power supply voltage lower than the first threshold, so the power consumption of the analog-to-digital conversion circuit as a whole is relatively low. And the voltage signal obtained by boosting is not provided to the entire analog-to-digital conversion circuit, so there is no need to set a large area of ​​capacitors to store additional charges, and the chip area occupied is smaller. In summary, the chip area occupied by the analog-to-digital conversion circuit of the embodiment of the present disclosure is smaller, the power consumption is also lower, and high-quality analog-to-digital conversion can be achieved at low voltage.

[0016] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0018] Figure 1 Schematic showing an energy harvesting system powering circuits in an IoT device.

[0019] Figure 2 A working scheme of the ADC when the supply voltage is low is shown.

[0020] Figure 3 Another working scheme of the ADC when the supply voltage is low is shown.

[0021] Figure 4 An exemplary application scenario of the analog-to-digital conversion circuit according to an embodiment of the present disclosure is shown.

[0022] Figure 5 A schematic diagram showing the structure of an analog-to-digital conversion circuit according to an embodiment of the present disclosure.

[0023] Figure 6a A schematic diagram showing the structure of a conversion module according to an embodiment of the present disclosure.

[0024] Figure 6b A schematic diagram showing the structure of a conversion module according to an embodiment of the present disclosure.

[0025] Figure 7 A schematic diagram showing the structures of a boost module and a clock buffer module according to an embodiment of the present disclosure.

[0026] Figure 8 A schematic diagram showing the structures of a boost module and a clock buffer module according to an embodiment of the present disclosure.

[0027] Fig. 9 A schematic diagram showing the structure of a feedback module according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0029] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0030] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0031] Figure 1 Schematic showing an energy harvesting system powering circuits in an IoT device.

[0032] like Figure 1 As shown in the figure, the energy harvesting system can collect energy from an external energy source, convert it into a power supply voltage (VDD) and output it to the data transceiver module, digital signal processor (DSP), analog to digital converter (ADC) and other devices in the Internet of Things. The energy density collected by the energy harvesting system is often less than 100uW / cm 2 , and its corresponding output voltage is generally less than 300mV. This voltage is used to power the ADC, DSP, data transceiver module, etc. in the system. For the ADC, it is very difficult to achieve high-quality analog-to-digital conversion at such a low voltage.

[0033] Figure 2 A working scheme of the ADC when the supply voltage is low is shown.

[0034] like Figure 2As shown in the figure, a DC-DC converter can be used to directly increase the low voltage VDD output by the energy harvesting system to a high voltage VDD' that can enable the ADC to work normally, and then provide it to the ADC as the power supply voltage. The ADC converts the input analog signal V IN Converted into digital signal D OUT And output. But this will cause the overall power consumption of ADC to increase a lot. In addition, the voltage signal output by the DC-DC converter is provided to the entire ADC as the power supply voltage, so it is necessary to add a very large capacitor on the chip to store the charge, which increases the chip area and thus increases the cost of the chip.

[0035] Figure 3 Another working scheme of the ADC when the supply voltage is low is shown.

[0036] like Figure 3 As shown in the figure, another method is to use some ADCs that can still work normally under low voltage, such as oversampling ADC based on inverter amplifier, oversampling ADC based on ring oscillator, successive approximation register (SAR) ADC based on well-designed comparator, etc., to directly realize analog-to-digital conversion under the low voltage VDD output by the energy harvesting system, and convert the input analog signal V IN Converted to digital signal D OUT However, the circuit modules in these ADCs are often very sensitive to the power supply voltage, and the quality of analog-to-digital conversion fluctuates greatly. In addition, the analog-to-digital conversion quality of these ADCs at low voltages, such as conversion linearity and conversion accuracy, is significantly different from that of ADCs that perform analog-to-digital conversion at normal voltages.

[0037] In summary, some analog-to-digital conversion circuits proposed in the prior art cannot maintain high-quality analog-to-digital conversion when the power supply voltage is low. Although some analog-to-digital conversion circuits proposed in the prior art can maintain high-quality analog-to-digital conversion when the power supply voltage is low, the power consumption and chip area occupied by the analog-to-digital conversion circuit will be increased. How to reduce the power consumption and chip area occupied by the analog-to-digital conversion circuit and maintain high-quality analog-to-digital conversion has become a technical problem to be solved in this field.

[0038] In view of this, the present disclosure proposes an analog-to-digital conversion circuit, chip, and electronic device based on a boost module. The analog-to-digital conversion circuit of the present disclosure occupies a smaller chip area and has lower power consumption, and can achieve high-quality analog-to-digital conversion at low voltage.

[0039] Figure 4 An exemplary application scenario of the analog-to-digital conversion circuit according to an embodiment of the present disclosure is shown.

[0040] like Figure 4 As shown, the electronic device may include an energy harvesting system and a chip. The analog-to-digital conversion circuit of the embodiment of the present disclosure may be arranged on the chip. The energy harvesting system may power the chip. The value of the power supply voltage output by the energy harvesting system may be less than the first threshold value, that is, the energy harvesting system outputs an ultra-low voltage. The value of the first threshold value may be set according to the application scenario requirements, for example, set to 0.3V. The embodiment of the present disclosure does not limit the specific value of the first threshold value.

[0041] The analog-to-digital conversion circuit can receive an analog input signal to be converted, perform analog-to-digital conversion to obtain a digital output signal, and then output it.

[0042] A data transceiver module (not shown) and a digital signal processor (not shown) may be further provided on the chip. The analog input signal may be a signal received by the data transceiver module, and then transmitted to the analog-to-digital conversion circuit by the data transceiver module. The digital output signal may be output to the digital signal processor for processing, or may be transmitted to the data transceiver module, and then transmitted to other devices / modules by the data transceiver module, which is not limited in the embodiments of the present disclosure.

[0043] Those skilled in the art should understand that if the electronic device itself carries a power supply, the chip can also be powered by the power supply, and when the power supply is insufficient and outputs a voltage signal with a voltage value less than the first threshold, the analog-to-digital conversion circuit on the chip can also achieve high-quality analog-to-digital conversion. The embodiments of the present disclosure do not limit the power source of the chip.

[0044] Figure 5 A schematic diagram showing the structure of an analog-to-digital conversion circuit according to an embodiment of the present disclosure.

[0045] like Figure 5 As shown, in a possible implementation, the circuit includes a boost module, a clock buffer module, a conversion module and a feedback module, and the power supply voltage of the boost module, the conversion module and the feedback module is less than or equal to a first threshold,

[0046] The boost module is used to generate at least one voltage signal with a voltage value greater than the power supply voltage, and the voltage signal is used to supply power to the clock buffer module;

[0047] The clock buffer module is used to generate at least one pair of clock signals with a swing greater than a first threshold, and output the clock signals to the conversion module to drive at least one unit in the conversion module;

[0048] The conversion module is used to obtain a digital output signal according to an analog input signal and a feedback signal;

[0049] The feedback module is used to generate a feedback signal according to the latest digital output signal and output it to the conversion module.

[0050] For example, the analog-to-digital conversion circuit may include a boost module, a clock buffer module, a conversion module, and a feedback module, wherein the boost module, the conversion module, and the feedback module are all powered by a power supply voltage that is less than a first threshold.

[0051] The boost module can generate a voltage signal with a voltage value greater than the power supply voltage, and the voltage signal is used to power the clock buffer module. The clock buffer module is powered by a voltage greater than the first threshold, so it can generate a clock signal with a swing greater than the first threshold. On the premise that the boost module generates at least one voltage signal, the clock buffer module can generate at least one pair of clock signals, each pair of clock signals includes two differential clock signals.

[0052] The clock buffer module can output the clock signal to the conversion module to drive at least one unit in the conversion module. The conversion module may include multiple units, and some key units can maintain high performance under the drive of a high-swing clock signal. In this case, the clock signal generated by the clock buffer module can be used to drive these key units.

[0053] The embodiments of the present disclosure do not limit the specific structures of the boost module, the clock buffer module, and the conversion module, as long as the boost module, the clock buffer module, and the conversion module can achieve the above functions. Examples of the structures of the boost module, the clock buffer module, and the conversion module and examples of key units are given later.

[0054] The analog-to-digital conversion process can include three main stages: voltage-current conversion, integration, and quantization, all of which can be completed by the conversion module. Before the analog input signal enters the voltage-current conversion stage, it can also be subjected to chopping and other operations to optimize the signal quality. When performing the voltage-current conversion operation, the higher the swing of the analog input signal, the greater the deviation of the final digital output signal. Therefore, the conversion module can use the feedback signal to adjust the swing of the analog input signal, and then perform voltage-current conversion, integration, quantization and other operations on the adjusted analog input signal to obtain a digital output signal.

[0055] The analog input signal is periodically input to the conversion module, so the conversion module may output a digital output signal more than once. The feedback signal can be generated by the feedback module based on the latest digital output signal. In this way, the accuracy of the analog-to-digital conversion process regulated by the feedback signal can be improved. The embodiment of the present disclosure does not limit the specific structure of the feedback module, as long as the feedback module can achieve the above functions. An example of the structure of the feedback module is given later.

[0056] According to the analog-to-digital conversion circuit of the embodiment of the present disclosure, by setting a boost module and a clock buffer module, a clock signal with a swing higher than the first threshold can be obtained, and the conversion module is driven by a clock signal with a higher swing. The conversion module obtains a digital output signal according to the analog input signal and the feedback signal, and the feedback module generates a feedback signal according to the latest digital output signal and outputs it to the conversion module, thereby achieving high-quality analog-to-digital conversion. In the analog-to-digital conversion circuit, only some units in the conversion module are driven by a clock signal with a high swing, and only the clock buffer module needs to be powered by a voltage signal with a voltage value greater than the first threshold. The boost module, other units of the conversion module, and the feedback module can still be powered by a power supply voltage lower than the first threshold, so the power consumption of the analog-to-digital conversion circuit as a whole is relatively low. And the voltage signal obtained by boosting is not provided to the entire analog-to-digital conversion circuit, so there is no need to set a large area of ​​capacitors to store additional charges, and the chip area occupied is smaller. In summary, the chip area occupied by the analog-to-digital conversion circuit of the embodiment of the present disclosure is smaller, the power consumption is also lower, and high-quality analog-to-digital conversion can be achieved at low voltage.

[0057] Figure 6a and Figure 6b A schematic diagram showing the structure of a conversion module according to an embodiment of the present disclosure.

[0058] like Figure 6a and Figure 6b As shown, in a possible implementation, the conversion module includes a first chopping unit 10, a capacitor filtering unit 20, a dead zone control unit 30, a voltage-current conversion unit 40, a second chopping unit 50, an integration unit 60, a quantization unit 70, and an output unit 80.

[0059] The analog input signal includes a differential first input signal VINP and a second input signal VINN, the feedback signal includes a differential first feedback signal VFP and a second feedback signal VFN,

[0060] The first end a1 of the first chopping unit receives the first input signal VINP, the second end a2 of the first chopping unit receives the second input signal VINN, the third end a3 of the first chopping unit is connected to the first end b1 of the capacitor filter unit, and the fourth end a4 of the first chopping unit is connected to the second end b2 of the capacitor filter unit;

[0061] The third terminal b3 of the capacitor filter unit is connected to the first terminal d1 of the dead zone control unit and the fourth terminal n4 of the feedback module, the fourth terminal b4 of the capacitor filter unit is connected to the second terminal d2 of the dead zone control unit and the third terminal n3 of the feedback module, the fourth terminal n4 of the feedback module outputs the first feedback signal VFP, and the third terminal n3 of the feedback module outputs the second feedback signal VFN;

[0062] The third terminal d3 of the dead zone control unit is connected to the first terminal e1 of the voltage-current conversion unit, and the fourth terminal d4 of the dead zone control unit is connected to the second terminal e2 of the voltage-current conversion unit;

[0063] The third terminal e3 of the voltage-current conversion unit is connected to the first terminal f1 of the second chopping unit, and the fourth terminal e4 of the voltage-current conversion unit is connected to the second terminal f2 of the second chopping unit;

[0064] The third end f3 of the second chopping unit is connected to the first end g1 of the integration unit, and the fourth end f4 of the second chopping unit is connected to the second end g2 of the integration unit;

[0065] The third terminal g3 of the integration unit is connected to the first terminal h1 of the quantization unit, the fourth terminal g4 of the integration unit is connected to the second terminal h2 of the quantization unit, the third terminal h3 of the quantization unit is connected to the first terminal j1 of the output unit and the first terminal n1 of the feedback unit, and the fourth terminal h4 of the quantization unit is connected to the second terminal j2 of the output unit and the second terminal n2 of the feedback unit;

[0066] The third terminal j3 of the output unit outputs the digital output signal DOUT.

[0067] For example, the conversion module may include a first chopping unit, a capacitor filtering unit, a dead zone control unit, a voltage-current conversion unit, a second chopping unit, an integration unit, a quantization unit, and an output unit.

[0068] The first chopping unit may receive an analog input signal input from the outside. The analog input signal may be a differential signal, including a first input signal and a second input signal. In this case, the first chopping unit, the capacitor filter unit, the dead zone control unit, the voltage-current conversion unit, the second chopping unit, the integration unit, and the quantization unit may include two input terminals and two output terminals respectively; the output unit may include two input terminals and one output terminal.

[0069] The first end of the first chopping unit receives a first input signal, the second end receives a second input signal, the third end outputs a signal VAP obtained by chopping the first input signal, and the fourth end outputs a signal VAN obtained by chopping the second input signal.

[0070] like Figure 6b As shown, the first chopping unit may include switches S1-S4. The first end s11 of S1 is connected to the first end s31 of S3 and serves as the first end of the first chopping unit. The second end s12 of S1 is connected to the first end s41 of S4 and serves as the third end of the first chopping unit. The first end s21 of S2 is connected to the second end s42 of S4 and serves as the second end of the first chopping unit. The second end s22 of S2 is connected to the second end s32 of S3 and serves as the fourth end of the first chopping unit.

[0071] Those skilled in the art should understand that the first chopping unit may also be implemented using other structures, as long as it has a chopping function and can chop the differential input signal to obtain a differential output signal. The embodiments of the present disclosure do not limit the specific structure of the first chopping unit.

[0072] After being outputted by the first chopping unit, the signal VAP and the signal VAN are inputted to the first end and the second end of the capacitor filtering unit. Figure 6b As shown, the capacitive filter unit may include a capacitor C3 and a capacitor C4. One end of the capacitor C3 serves as the first end of the capacitive filter unit, and the other end of the capacitor C3 serves as the third end of the capacitive filter unit; one end of the capacitor C4 serves as the second end of the capacitive filter unit, and the other end of the capacitor C4 serves as the fourth end of the capacitive filter unit.

[0073] Capacitor C3 can be used to filter out interference components in signal VAP. Capacitor C4 can be used to filter out interference components in signal VAN. Since the third end of the capacitor filter unit is also connected to the fourth end of the feedback module, and the fourth end of the capacitor filter unit is also connected to the third end of the feedback module, the feedback signal output by the feedback module is a differential signal and includes a first feedback signal VFP and a second feedback signal VFN. The fourth end and the third end of the feedback module output the first feedback signal VFP and the second feedback signal VFN respectively. Therefore, after the interference components in signal VAP are filtered out, the swing amplitude is adjusted by the first feedback signal VFP to obtain signal VBP and output to the first end of the dead zone control unit. After the interference components in signal VAN are filtered out, the swing amplitude is adjusted by the second feedback signal VFN to obtain signal VBN and output to the second end of the dead zone control unit.

[0074] like Figure 6b As shown, the dead zone control unit may include a switch S5 and a switch S6. One end of the switch S5 serves as the first end of the dead zone control unit, and the other end serves as the third end of the dead zone control unit; one end of the switch S6 serves as the second end of the dead zone control unit, and the other end serves as the fourth end of the dead zone control unit. The third end of the dead zone control unit is connected to the first end of the voltage-current conversion unit, and the fourth end is connected to the second end of the voltage-current conversion unit. After the signal VBP and the signal VBN enter the voltage-current conversion unit, they enter the voltage-current conversion stage described above. Therefore, the switch S5 and the switch S6 can be controlled to be disconnected within a short period of time in each cycle (the cycle frequency can be the sampling frequency of the analog-to-digital conversion circuit) to prevent the signal VBP and the signal VBN from entering the voltage-current conversion unit, so as to optimize the quality of the signal output by the voltage-current conversion unit (for example, to remove the burrs in the signal output by the voltage-current conversion unit). The time period for controlling the switch S5 and the switch S6 to be disconnected can be set according to the application scenario requirements, and the embodiment of the present disclosure is not limited to this.

[0075] The voltage-to-current conversion unit can convert the input signal VBP into a current signal IEP and the input signal VBN into a current signal IEN. The function of the voltage-to-current conversion unit can be realized by a transconductance amplifier in the prior art, which will not be described in detail here.

[0076] The current signal IEP can be input to the first end of the second chopping unit, and the current signal IEN can be input to the second end of the second chopping unit. The structure and function of the second chopping unit can be the same as those of the first chopping unit, and will not be repeated here. The third end of the second chopping unit outputs the signal IEP after chopping to obtain the signal IFP, and the fourth end outputs the signal IEN after chopping to obtain the signal IFN.

[0077] like Figure 6b As shown, the integration unit may include a first integrator and a second integrator. The signal IFP may be input to one end of the first integrator (the first end of the integration unit), the first integrator integrates the signal IFP, and outputs the signal IGP through the other end (the third end of the integration unit). The signal IFN may be input to one end of the second integrator (the second end of the integration unit), the second integrator integrates the signal IFN, and outputs the signal IGN through the other end (the fourth end of the integration unit). The first integrator and the second integrator may be implemented based on the prior art, and the structures of the first integrator and the second integrator will not be described in detail herein.

[0078] The signal IGP can be input to the first terminal of the quantization unit, and the signal IGN can be input to the second terminal of the quantization unit. The quantization unit can quantize the signal IGP into a value A and quantize the signal IGN into a value B. The value A can be output through the third terminal of the quantization unit, and the value B can be output through the fourth terminal of the quantization unit. The quantization unit can be implemented based on the existing technology, and the structure of the quantization unit will not be described in detail here.

[0079] The value A can be input to the first terminal of the output unit, and the value B can be input to the second terminal of the output unit. Figure 6b As shown, the output unit can perform a subtraction operation on the value A and the value B, and use the operation result as a digital output signal DOUT. The digital output signal DOUT can be output from the third terminal of the output unit. The output unit can be implemented based on the existing technology, and the specific structure of the output unit will not be repeated here.

[0080] See also Figure 6a , the value A and the value B are also input to the feedback module. The feedback module can output a first feedback signal VFP and a second feedback signal VFN according to the value A and the value B. The structure of the feedback module and the example of the feedback module implementing the above functions can be found in Fig. 9 .

[0081] In a possible implementation manner, the quantization unit is a time-domain quantization unit, the integration unit is a time-domain integration unit, and the quantization unit and the integration unit are implemented using digital circuits.

[0082] For example, since the characteristics of the time domain integration unit and the time domain quantization unit are to process signals in the time domain instead of in the analog domain, the time domain integration unit and the time domain quantization unit can be implemented by digital circuits. Digital circuits can work at low voltages (especially digital circuits under advanced processes, the more advanced the process, the lower the voltage at which they can work), so the time domain integration unit and the time domain quantization unit can maintain high performance at a power supply voltage lower than the first threshold. This further increases the proportion of digital circuits in the analog-to-digital converter circuit and further reduces the power consumption of the analog-to-digital conversion circuit.

[0083] In a possible implementation, the clock signal is used to drive the first chopping unit, the dead zone control unit, and the second chopping unit.

[0084] For example, the clock signal output by the clock buffer module mentioned above can be used to drive at least one unit in the conversion module. In one example, the driven units may be the first chopping unit, the dead zone control unit, and the second chopping unit.

[0085] The swing amplitudes of the clock signals driving the first chopping unit, the dead zone control unit, and the second chopping unit may be the same or different, and the present disclosure does not impose any limitation on this.

[0086] In a possible implementation, the swing of the clock signal used to drive the dead zone control unit is greater than or equal to the second threshold, the swing of the clock signal used to drive the first chopping unit and the second chopping unit is greater than or equal to the third threshold, and the second threshold is greater than the third threshold.

[0087] For example, the higher the swing of the clock signal, the better the effect of driving the first chopping unit, the dead zone control unit, and the second chopping unit, but the greater the power consumption. Therefore, the clock signal driving the first chopping unit, the dead zone control unit, and the second chopping unit can be determined according to the requirements of the first chopping unit, the dead zone control unit, and the second chopping unit for the swing of the clock signal.

[0088] In one example, the first chopping unit and the second chopping unit may have a clock signal swing requirement equal to a third threshold value (e.g., 0.9V). The dead zone control unit has a higher clock signal swing requirement, which may be equal to a second threshold value (e.g., 1.1V). Assuming that the swing of the first pair of clock signals output by the clock buffer module is 0.9V, the swing of the second pair of clock signals is 1V, and the swing of the third pair of clock signals is 1.1V, in this case, the first pair of clock signals may be used to drive the first chopping unit and the second chopping unit, and the third pair of clock signals may be used to drive the dead zone control unit.

[0089] If the swing of the pair of clock signals with the lowest swing output by the clock buffer module exceeds the second threshold, the pair of clock signals with the lowest swing can be used to drive the first chopping unit, the dead zone control unit and the second chopping unit.

[0090] That is, the swing of the clock signal used to drive the dead zone control unit is greater than or equal to the second threshold, the swing of the clock signal used to drive the first chopping unit and the second chopping unit is greater than or equal to the third threshold, and the second threshold is greater than the third threshold.

[0091] The third threshold may be greater than the first threshold, and the embodiment of the present disclosure does not limit the specific value of the third threshold.

[0092] In this way, the power consumption of the analog-to-digital conversion circuit can be reduced while ensuring the quality of the analog-to-digital conversion.

[0093] Figure 7 A schematic diagram showing the structures of a boost module and a clock buffer module according to an embodiment of the present disclosure.

[0094] like Figure 7 As shown, in a possible implementation, the boost module includes a DCDC converter, the clock buffer module includes a clock buffer, the DCDC converter is connected to the clock buffer,

[0095] The DCDC converter boosts the input voltage signal to obtain the boosted voltage signal and outputs it to the clock buffer. The clock buffer generates a pair of clock signals according to the received voltage signal and outputs them.

[0096] For example, if the voltage value of the voltage signal after the single DCDC converter boosts the voltage is greater than or equal to the first threshold, the boost module only needs to include one DCDC converter. Accordingly, the clock buffer module may also include only one clock buffer. The output end of the DCDC converter is connected to the input end of the clock buffer, and the DCDC converter boosts the input voltage signal to obtain the boosted voltage signal and outputs it to the clock buffer. The clock buffer generates a pair of clock signals according to the received voltage signal and outputs them. The clock signal generated by the clock buffer may be a differential clock signal, and the low level of the clock signal may be 0, and the high level may be equal to the voltage value of the received voltage signal.

[0097] Both the DCDC converter and the clock buffer can be implemented based on the existing technology, and the structures of the DCDC converter and the clock buffer will not be described in detail here.

[0098] In this way, the structures of the boost module and the clock buffer module are made simpler.

[0099] Figure 8 A schematic diagram showing the structures of a boost module and a clock buffer module according to an embodiment of the present disclosure.

[0100] like Figure 8 As shown, in a possible implementation, the boost module includes a plurality of DCDC converters, the power supply voltage is respectively input into the plurality of DCDC converters, the clock buffer module includes a plurality of clock buffers, each DCDC converter is connected to a clock buffer,

[0101] Each DCDC converter boosts the input voltage signal to obtain the boosted voltage signal and outputs it to a clock buffer connected to itself. Each clock buffer generates a pair of clock signals according to the received voltage signal and outputs them.

[0102] For example, as described above, different units to be driven by the clock signal may have different requirements for the swing of the clock signal, so the boost module can include multiple DCDC converters with different boost capabilities. The power supply voltage is input into multiple DCDC converters respectively, and each DCDC converter outputs a voltage signal. The voltage value of the voltage signal output by each DCDC converter is different, and for each unit to be driven, there is a DCDC converter outputting a voltage signal whose voltage value is the same as the swing of the clock signal required by the unit. Correspondingly, the clock buffer module can also include multiple clock buffers, and the output end of each DCDC converter is connected to the input end of a clock buffer. Each clock buffer generates and outputs a pair of clock signals according to the received voltage signal. The clock signal generated by the clock buffer can be a differential clock signal, and the low level of the clock signal can be 0, and the high level can be equal to the voltage value of the received voltage signal, thereby obtaining multiple pairs of clock signals with different swings. In this case, multiple pairs of clock signals with different swings can meet the requirements of all units to be driven for the swing of the clock signal.

[0103] In this way, the clock buffer module can output a clock signal that meets the requirements of the application scenario.

[0104] Fig. 9 A schematic diagram showing the structure of a feedback module according to an embodiment of the present disclosure.

[0105] like Fig. 9 As shown, in a possible implementation, the feedback module includes a logic control unit, a third chopping unit, and a capacitive digital-to-analog conversion unit.

[0106] The first end of the logic control unit serves as the first end of the feedback module, the second end of the logic control unit serves as the second end of the feedback module, the third end of the logic control unit is connected to the first end of the third chopping unit, and the fourth end of the logic control unit is connected to the second end of the third chopping unit;

[0107] The third end of the third chopping unit is connected to the first end of the capacitive digital-to-analog conversion unit, and the fourth end of the third chopping unit is connected to the second end of the capacitive digital-to-analog conversion unit;

[0108] The third terminal of the capacitive digital-to-analog conversion unit serves as the third terminal of the feedback module, and the fourth terminal of the capacitive digital-to-analog conversion unit serves as the fourth terminal of the feedback module.

[0109] For example, the entire feedback module can be implemented using a digital circuit, and may include a logic control unit 11 , a third chopping unit 21 , and a capacitive digital-to-analog conversion unit 31 .

[0110] The first terminal n1 of the logic control unit serves as the first terminal of the feedback module to receive the value A, and the second terminal n2 of the logic control unit serves as the second terminal of the feedback module to receive the value B. According to the values ​​A and B, the logic control unit can obtain a digital control signal, which can be a differential signal, including a signal ctrl1 and a signal ctrl2. The digital control signal is used to control the degree of regulation of the analog input signal by the feedback module. The logic control unit can be implemented based on the prior art, and the specific implementation method of the logic control unit will not be repeated here.

[0111] The third terminal p3 of the logic control unit can be connected to the first terminal q1 of the third chopping unit, and the fourth terminal p4 of the logic control unit can be connected to the second terminal q2 of the third chopping unit, and the signal ctrl1 and the signal ctrl2 are input to the third chopping unit for chopping. The signal ctrl1 is chopped to obtain the signal ctrl11, and the signal ctrl2 is chopped to obtain the signal ctrl22. The third chopping unit can be implemented based on the prior art, and the specific implementation method of the third chopping unit will not be repeated here.

[0112] The third terminal q3 of the third chopping unit can input the signal ctrl11 to the first terminal p1 of the capacitive digital-to-analog conversion unit, and the fourth terminal q4 of the third chopping unit can input the signal ctrl22 to the second terminal p2 of the capacitive digital-to-analog conversion unit. The capacitive digital-to-analog conversion unit can perform digital-to-analog conversion on the signal ctrl11 to obtain the signal VFN, and perform digital-to-analog conversion on the signal ctrl22 to obtain the signal VFP, and the signal VFP and the signal VFN can be analog signals. In this case, the signal VFP can be operated with the signal VAP, and the signal VFN can be operated with the signal VAN. The third terminal n3 of the capacitive digital-to-analog conversion unit can output the signal VFN, and the fourth terminal n4 can output the signal VFP. The capacitive digital-to-analog conversion unit can be implemented based on the prior art, and the specific implementation method of the capacitive digital-to-analog conversion unit will not be repeated here.

[0113] The present disclosure also provides a chip, including the analog-to-digital conversion circuit described above. The schematic diagram of the chip structure can be found in Figure 4 .

[0114] The embodiment of the present disclosure also provides an electronic device, comprising the chip described above. The electronic device may be a terminal device or a server, and the embodiment of the present disclosure does not limit the specific type of the electronic device.

[0115] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0116] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An analog-to-digital conversion circuit based on a boost module, characterized in that: The circuit comprises a boost module, a clock buffer module, a conversion module and a feedback module, wherein the power supply voltages of the boost module, the conversion module and the feedback module are less than or equal to a first threshold, The boost module is used to generate at least one voltage signal whose voltage value is greater than the power supply voltage, and the voltage signal is used to supply power to the clock buffer module; The clock buffer module is used to generate at least one pair of clock signals with a swing greater than the first threshold, and output the clock signals to the conversion module to drive at least one unit in the conversion module; The conversion module is used to obtain a digital output signal according to the analog input signal and the feedback signal; The feedback module is used to generate the feedback signal according to the latest digital output signal and output the feedback signal to the conversion module.

2. The circuit according to claim 1, characterized in that The conversion module includes a first chopping unit, a capacitor filtering unit, a dead zone control unit, a voltage-current conversion unit, a second chopping unit, an integration unit, a quantization unit, and an output unit. The analog input signal includes a differential first input signal and a second input signal, and the feedback signal includes a differential first feedback signal and a second feedback signal. The first end of the first chopping unit receives the first input signal, the second end of the first chopping unit receives the second input signal, the third end of the first chopping unit is connected to the first end of the capacitor filtering unit, and the fourth end of the first chopping unit is connected to the second end of the capacitor filtering unit; The third end of the capacitor filtering unit is connected to the first end of the dead zone control unit and the third end of the feedback module, the fourth end of the capacitor filtering unit is connected to the second end of the dead zone control unit and the fourth end of the feedback module, the third end of the feedback module outputs the first feedback signal, and the fourth end of the feedback module outputs the second feedback signal; The third end of the dead zone control unit is connected to the first end of the voltage-current conversion unit, and the fourth end of the dead zone control unit is connected to the second end of the voltage-current conversion unit; The third end of the voltage-current conversion unit is connected to the first end of the second chopping unit, and the fourth end of the voltage-current conversion unit is connected to the second end of the second chopping unit; The third end of the second chopping unit is connected to the first end of the integration unit, and the fourth end of the second chopping unit is connected to the second end of the integration unit; The third end of the integration unit is connected to the first end of the quantization unit, the fourth end of the integration unit is connected to the second end of the quantization unit, the third end of the quantization unit is connected to the first end of the output unit, and the fourth end of the quantization unit is connected to the second end of the output unit; The third terminal of the output unit outputs the digital output signal.

3. The circuit according to claim 2, characterized in that The quantization unit is a time domain quantization unit, the integration unit is a time domain integration unit, and the quantization unit and the integration unit are implemented by digital circuits.

4. The circuit according to claim 2, characterized in that The clock signal is used to drive the first chopping unit, the dead zone control unit, and the second chopping unit.

5. The circuit according to claim 1, characterized in that The boost module includes a plurality of DCDC converters, the power supply voltage is respectively input into the plurality of DCDC converters, the clock buffer module includes a plurality of clock buffers, each DCDC converter is connected to a clock buffer, Each DCDC converter boosts the input voltage signal to obtain the boosted voltage signal and outputs it to a clock buffer connected to itself. Each clock buffer generates a pair of clock signals according to the received voltage signal and outputs them.

6. The circuit according to claim 4, characterized in that The swing of the clock signal used to drive the dead zone control unit is greater than or equal to a second threshold, the swing of the clock signal used to drive the first chopping unit and the second chopping unit is greater than or equal to a third threshold, and the second threshold is greater than the third threshold.

7. The circuit according to claim 1, characterized in that The boost module includes a DCDC converter, the clock buffer module includes a clock buffer, and the DCDC converter is connected to the clock buffer. The DCDC converter boosts the input voltage signal to obtain the boosted voltage signal and outputs it to the clock buffer. The clock buffer generates and outputs a pair of clock signals according to the received voltage signal.

8. The circuit according to claim 5, characterized in that The feedback module includes a logic control unit, a third chopping unit, and a capacitive digital-to-analog conversion unit. The first end of the logic control unit serves as the first end of the feedback module, the second end of the logic control unit serves as the second end of the feedback module, the third end of the logic control unit is connected to the first end of the third chopping unit, and the fourth end of the logic control unit is connected to the second end of the third chopping unit; The third end of the third chopping unit is connected to the first end of the capacitive digital-to-analog conversion unit, and the fourth end of the third chopping unit is connected to the second end of the capacitive digital-to-analog conversion unit; The third terminal of the capacitive digital-to-analog conversion unit serves as the third terminal of the feedback module, and the fourth terminal of the capacitive digital-to-analog conversion unit serves as the fourth terminal of the feedback module.

9. A chip, characterized in that: The analog-to-digital conversion circuit comprises the analog-to-digital conversion circuit described in any one of claims 1-8.

10. An electronic device, characterized in that: Comprising the chip as claimed in claim 9.

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