Configurable digital-to-analog converter calibration

Abstract

The invention relates to configurable digital-to-analog converter calibration. A digital-to-analog converter includes an impedance network and a transfer function modification circuit. The transfer function modification circuit includes a DAC and a demultiplexer. A demultiplexer may be used to selectively connect the output of the DAC to different respective nodes of the impedance network, allowing positive or negative current to be injected into the nodes and modifying the transfer function. By selectively coupling to different nodes using a demultiplexer, the nodes of the injected current may be modified after fabrication, allowing for modification of the transfer function.

Description

Technical Field

[0001] The present disclosure relates to an apparatus and method for digital-to-analog conversion. In particular, the present invention relates to an apparatus and method for digital-to-analog conversion, including modifying a transfer function of a digital-to-analog converter. Background Art

[0002] A digital-to-analog converter (DAC) converts a digital input code into an analog output signal. DACs are widely used in a variety of applications such as signal processing, control, and biasing. A DAC typically consists of a switched resistor or impedance string. For example, both string and ladder DACs include a resistor network. The resistor network acts as a voltage divider, producing a different voltage at each node of the network. The resistor network can operate in voltage or current mode for voltage and current outputs, respectively. A voltage-mode resistor network is connected to an array of switches that can be opened and closed to change the voltage supplied to the output. The switches are typically controlled by a decoder, which receives the input digital code and determines which node is connected to the output (for a string DAC) or which node is connected to a voltage reference (for example, a voltage-mode R-2R DAC) to generate the appropriate analog voltage.

[0003] An important performance parameter of a DAC is accuracy, including nonlinearity. Assuming that all resistors are identical and the other characteristics of the DAC are ideal, the relationship between the input code and the voltage output should be linear. However, due to differences between resistor values, for example due to process variations and resistor tolerances, voltage errors may occur at the nodes. In other words, for a particular input code, the voltage produced is slightly different from the ideal voltage due to variations in the resistors. The DAC interconnects also affect nonlinearity and need to be properly matched and scaled if necessary. Errors may also occur due to other manufacturing variations.

[0004] Therefore, it may be desirable to provide a DAC with improved accuracy. Summary of the invention

[0005] The present invention relates to a digital-to-analog converter, which includes an impedance network and a transfer function modification circuit. The transfer function modification circuit includes a DAC and a demultiplexer. The demultiplexer can be used to selectively connect the output of the DAC to different corresponding nodes of the impedance network, allowing positive or negative current to be injected into the node and modifying the transfer function. By selectively coupling to different nodes using a demultiplexer, the node into which the current is injected can be modified after manufacturing, thereby allowing the variable transfer function to be modified.

[0006] According to a first aspect of the present disclosure, a digital-to-analog converter DAC is provided, comprising: an impedance network, comprising a plurality of impedance elements coupled together via a plurality of nodes, wherein the impedance network is configured to be coupled to a reference voltage and to generate a plurality of voltage values ​​at the plurality of nodes; and a transfer function modification circuit, comprising: a fine-tuning current DAC, the fine-tuning current DAC comprising an input and an output for receiving a fine-tuning code; and a demultiplexer, the demultiplexer comprising an input and a plurality of outputs, wherein the output of the fine-tuning current DAC is coupled to the input of the demultiplexer, wherein each of the plurality of outputs of the demultiplexer is coupled to a corresponding node among the plurality of nodes, and wherein the fine-tuning current DAC is configured to modify the transfer function of the DAC by injecting current into or draining current from a selected node among the plurality of nodes via a selected output of the demultiplexer.

[0007] According to a second aspect of the present disclosure, a digital-to-analog converter DAC is provided, comprising: an impedance network, comprising a plurality of impedance elements coupled together via a plurality of nodes, wherein the impedance network is configured to be coupled to a reference voltage and to generate a plurality of voltage values ​​at the plurality of nodes; and a transfer function modification circuit, comprising: a current injection component, wherein the current injection component is configured to be coupled to a subset of the plurality of nodes; wherein the current injection component is configured to modify the transfer function of the DAC by selecting a node in the subset of the plurality of nodes and injecting current into a selected node of the plurality of sub-nodes or discharging current from the selected node.

[0008] According to a third aspect of the present disclosure, a method for modifying a transfer function of a digital-to-analog converter (DAC) including an impedance network is provided, wherein the impedance network includes a plurality of resistor elements coupled together via a plurality of nodes, wherein the impedance network is configured to be coupled to a reference voltage and to generate a plurality of voltage values ​​at the plurality of nodes, the method comprising: selecting a corresponding node among the plurality of nodes to inject current into or drain current from; injecting current into or draining current from a selected node of the impedance string to modify the transfer function of the DAC. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Aspects of the present disclosure will now be described, by way of example only, with reference to the accompanying drawings, wherein like reference numerals represent like parts, and wherein:

[0010] Figure 1 is an example representation of the DAC analog output error;

[0011] Figure 2a is the representation of the string DAC;

[0012] Figure 2b It is the second representation of string DAC;

[0013] Figure 3 is a schematic diagram of a ladder DAC;

[0014] Figure 4 is a representation of the impedance network used in the DAC;

[0015] Figure 5 is a representation of a DAC including a transfer function modification circuit according to an example of the present disclosure;

[0016] Figure 6 is a representation of a DAC including a calibration circuit according to an example of the present disclosure;

[0017] Figure 7 is a method of determining a demultiplexer output and a DAC trim code according to an example of the present disclosure;

[0018] Figure 8a is a machine learning method for determining a machine learning model according to an example of the present disclosure;

[0019] Figure 8b is a method for determining a demultiplexer output and a DAC trim code using a machine learning model according to an example of the present disclosure;

[0020] Fig. 9 is a signal chain including a DAC according to an example of the present disclosure;

[0021] Fig.10 is a representation of a DAC including a plurality of multiplexers and a current DAC according to an example of the present disclosure;

[0022] Fig.11 is a second representation of a DAC including a plurality of multiplexers and a current DAC according to an example of the present disclosure;

[0023] Fig.12 is a representation of a DAC including a multi-impedance network;

[0024] Fig.13 is a representation of a DAC including multiple impedance networks and transfer function modification circuits according to an example of the present disclosure. DETAILED DESCRIPTION

[0025] The impedance network used in a DAC typically includes a plurality of resistors connected in series between a first voltage reference level and a second voltage reference level. Each node of the impedance network generates a voltage, the node is located between the resistors, and these voltages are used to generate the analog output voltage. Different forms of DACs can use impedance networks that are only coupled to a single reference voltage. The second reference can be provided by ground, analog ground, or a 0V level. Alternatively, a DAC can include multiple impedance networks.

[0026] Ideally, the unit resistors in an impedance network should all have the same value so that the voltage at the node is evenly distributed along the impedance network. However, DACs have various nonlinearities that cause voltage errors at the nodes. Nonlinearities can be caused by various properties and manufacturing variations, such as nonideal resistor values, nonideal switches, parasitic impedances, and layout-related effects. Voltage coefficients and voltage coefficient variations can also cause mismatches, which can lead to nonlinearities. Other parts of the signal chain to which the DAC belongs may also introduce nonlinearities. Using resistors specified for higher precision can improve the accuracy or linearity of the DAC. For example, the impedance network can be built using thin-film resistors. Alternatively, the resistors can be designed to occupy a larger area, as the accuracy of the resistor generally increases with the area of ​​the resistor until distance- or gradient-related mismatches become more prominent.

[0027] Another way to improve system accuracy is to use a calibration circuit to inject positive or negative currents into various nodes of the impedance network. Multiple current DACs can be connected to certain nodes, with each current DAC receiving an input trim code corresponding to the current it should source or sink from the various nodes. The injected current changes the voltage at the node. Changing the voltage at the node changes the transfer function of the DAC.

[0028] A DAC is often part of a larger signal chain. Devices or components of the signal chain may be nonlinear, for example due to voltage dependence or other dependencies. The larger signal chain may have a nonlinear output caused by manufacturing variations in the DAC's impedance network and nonlinearities introduced by other parts of the signal chain, such as pre- or post-amplification circuits or buffers. Therefore, the current injected into the impedance network nodes can be configured to linearize the signal chain to which the DAC belongs, or can be used to linearize the DAC itself.

[0029] Including a current DAC connected to each node of the impedance network may be uneconomical, both in terms of the financial cost of including a large number of current DACs and in terms of the area used to provide the current DACs. Therefore, some systems inject current into only a limited number of nodes. For example, when the impedance network is an eight-resistor string, current may only be injected into three nodes. Therefore, the system may include three current DACs, each with its output coupled to one of the three nodes.

[0030] However, when designing a DAC system using nanometer processes, it is difficult to predict the nonlinearities introduced by the impedance network. For example, parasitic impedances as well as cross-chip and local layout-related effects can differ significantly between simulations of a DAC system and the actual manufactured DAC system. When multiple instances of a DAC exist in different integrated circuit (IC) locations, they often have different dependencies and different non-ideal photolithography mask limitations. Therefore, having a limited number of current injection points (e.g., three of eight nodes within an eight-resistor string) may provide suboptimal calibration options.

[0031] In this case, providing eight current DACs, one coupled to each of the eight nodes, would allow for improved calibration of the DAC system. However, this would significantly increase the area required to implement the DAC system. It is also unclear how to optimize the choice of nodes, since the effects described above cannot be accurately predicted in simulations, and there are additional variations when multiple DACs coexist.

[0032] It would therefore be desirable to provide a system that allows for increased configurability of the impedance network compensation so that the compensation can be varied to account for these less predictable effects, including process related effects, die location, and component related effects, while ensuring that the DAC system remains compact.

[0033] The inventors have recognized that one or more demultiplexers can be coupled between the output of a current DAC and multiple nodes, allowing the nodes where current is injected or discharged to be configured after manufacturing. A "demultiplexer" can be defined as a circuit with a single input signal that selects one of multiple outputs based on a control signal. Therefore, the use of a demultiplexer in a DAC circuit requires much less area than providing a dedicated current DAC for each node, while improving the ability of the system to compensate for errors. In addition, the use of a demultiplexer in a DAC circuit allows the DAC circuit to be configured in a more flexible manner, so that nonlinearities that cause voltage errors at nodes can be corrected after manufacturing. The DAC transfer function modification capability provided by the demultiplexing function can be achieved through new post-manufacturing optimization freedoms for different demultiplexer circuit configurations for different dies or different DAC instances on the same chip, low cost, and low design effort.

[0034] Figure 1 A graph showing the ideal DC transfer function performance and an example of the actual performance of a DAC. The example is a single supply or unipolar case where the 0V or ground reference, the lower reference level is seen at the zero scale code, and a positive voltage level results in a positive output full scale voltage level. DACs can be used to convert signals in industrial, instrumentation, consumer, healthcare, current measurement, voltammetry, audio, and video applications. The DAC receives a digital input. Ideally, the analog output of the DAC should be proportional to the code input or digital input to the DAC. The ideal output is as follows: Figure 1 102 of . However, due to nonlinearities in the system, such as nonideal resistor properties and various manufacturing system errors and variations (nonideal resistor values, nonideal switches, parasitic impedances, and layout related effects), the analog output of the DAC may not be linear with the code input to the DAC. This is shown by the example of the real response 104 of the DAC. Figure 1 The graphs in Figure 1 relate to unipolar DACs, where the output of the DAC is always positive, however bipolar DACs, where the output can be either positive or negative, may also show similar differences between ideal and actual responses.

[0035] Various DAC types use impedance networks formed by multiple resistors connected together in a string. These impedance networks include multiple nodes, each capable of providing a different voltage output. For example, both string DACs and ladder DACs use resistor networks to provide analog outputs. An R / 2R DAC is an example of a ladder network.

[0036] Figure 1 The response shown is a simplified response because the relationship between code input and analog output is continuous and linear. However, in reality the response of the DAC is stepped, or quantized by the DAC resolution, because a step change in code input results in a step change in analog output.

[0037] Figure 2a A digital-to-analog converter (DAC) 200 is shown. DAC 200 is a string DAC that includes an impedance network. In this example, the impedance network includes a plurality of resistors 202a–202h. However, in alternative embodiments, the impedance network may be an impedance string that includes active devices, such as field effect transistors (FETs). For purposes of the present disclosure, each figure will be described in the context of a resistor network, however, it will be appreciated that other types of impedances may be used in place of resistors. Thus, the impedance network may be viewed as a plurality of impedance elements coupled together at a plurality of nodes. Parasitic interconnections between impedances may also be viewed as a sub-portion of a unit impedance. Furthermore, while the present embodiment is described in the context of a single-stage DAC, it will be appreciated that the present disclosure may also be applied to multi-stage DACs as well as multi-channel multi-stage DACs.

[0038] The impedance network includes eight resistors 202A to 202H connected in series. Figure 2a The DACs are arranged to provide 2 NOutput voltages, where N=3. One end of the impedance network is coupled to a first voltage reference VREF and the other end is connected to a second voltage reference, in this case ground. Although the impedance network is shown as being connected to ground, it is clear that this may take the form of a second voltage reference rather than ground. Ideally, each resistor takes the same value and during operation, the device operates in a linear manner. However, due to manufacturing tolerances, resistors 202A to 202H are not always the same, and systematic and random nonlinearities may be introduced during the manufacturing process. Resistors 202a-202h are coupled together via multiple nodes 204a-204h. If all resistors take the same value, the voltage at each of nodes 204a-204h will be evenly distributed between the reference voltage and ground. The resistors and surrounding circuits will include various parasitic elements, such as interconnect resistances between resistors. In addition, this assumes that the resistors have a zero voltage coefficient (the voltage across the resistor terminals and the common-mode voltage). In order to make the voltage evenly distributed throughout the impedance network, these effects must also be considered. Therefore, it is difficult to provide a linear DAC by passive means.

[0039] DAC 200 also includes a plurality of switches 206a to 206h. Each switch is coupled to a node on the impedance network. At the end of the impedance network, the switches are coupled between the terminal resistors 202a and 202h, and between VREF and ground, respectively. The remaining switches are connected to the node between the two series coupled resistors. Then, each switch is coupled to the output VOUT. Switches 206a to 206h are controlled by a decoder 208. The decoder 208 is connected to a digital input terminal that provides a digital code DIN. Although the DAC includes only one set of switches, the system is arranged to provide a differential output or a multi-string architecture including multiple impedance networks, and a differential output can be selected, and two switches are opened to provide a differential output.

[0040] The impedance network acts as a voltage divider, producing a different voltage at each node 204a-204i on the network. By using one of the switches 206a-206h to connect one of these nodes to V OUT , generating an analog output voltage. The decoder 108 generates an analog output voltage based on the digital code D IN Determines which switch is enabled.

[0041] like Figure 1As shown, it is usually desired that there is a linear relationship 102 between the input digital code Din and the analog output voltage Vout. Typically, additionally or alternatively, it is desired that there is a linear relationship between the input and output of the signal chain to which the DAC belongs. In other words, the transfer function of the DAC should be linear, or the transfer function of the signal chain containing the DAC should be linear. However, a real DAC introduces nonlinearity, for example, due to manufacturing tolerances. In a DAC, nonlinearity can be manifested as differential nonlinearity (DNL) error and integral nonlinearity (INL) error. DNL and INL are endpoint adjustment errors that do not include or describe zero-scale or full-scale errors, which can also be described by offset and gain errors. The error in the DAC can be expressed as a voltage error at each of the multiple nodes 204a-204i in the impedance network.

[0042] In addition to providing a linear transfer function, it may be desirable to modify the transfer function of the DAC so that the relationship between the input code DIN and the analog output voltage VOUT is designed to be nonlinear and follow a specific characteristic curve. This can be used to linearize different parts of the system that the DAC 200 comprises, such as ensuring that the entire signal chain has a linear output.

[0043] Figure 2b Another type of string DAC is shown. Figure 2b The string DAC consists of two serially coupled N - 1 resistor. Figure 2b The operation of the string DAC is similar to Figure 2a Operation. Figure 2a Compared to the system of FIG. 1 , all the resistor terminals in the string are coupled to the output, with one terminal of resistor 202a not coupled to the output. The number of resistors in the string may vary depending on the encoding scheme of the digital input.

[0044] Figure 3A digital-to-analog converter (DAC) 300 is shown. The DAC 300 is a ladder DAC including an impedance network, more specifically an R-2R DAC. The R-2R DAC includes an impedance network including a first plurality of resistors 302a-302f. The resistors 302a-302h are coupled in series through a plurality of nodes 304a-304h. The impedance network includes a second plurality of resistors 310a-310h. The nominal values ​​of 302a-302f and 310a-310f are scaled relative to each other, for example, in a binary scaled R-2R DAC, the values ​​of 310a-310f are 2R compared to the values ​​R of 302a-302f, and the resistors are implemented using unit R resistors known to those skilled in the art. The second plurality of resistors 310a-310h are coupled between nodes of the plurality of nodes 304a-304h and switches of the plurality of switches 306a-306g. A variation of this architecture uses multiple parallel instances of 310h and 306g as a unary scaling network to provide additional DAC resolution and reduce the DNL sensitivity of the architecture.

[0045] The switch 306a is arranged to couple the second plurality of resistors 310a-310h between a reference voltage or ground, thereby coupling the plurality of nodes 304a-304g. Figure 2a As shown in the DAC, ground can be replaced by a second reference voltage or terminal.

[0046] The impedance network acts as a voltage divider, producing different voltages at the output nodes depending on how switches 310a-310h are coupled. By using one of switches 310a-310h to connect one of these nodes to V ref , generating an analog output voltage at Vout. The decoder 308 generates an analog output voltage at Vout based on the digital code D received by the decoder 308. IN to determine which switch is coupled to the reference voltage.

[0047] The resistor 310a of the DAC 300 is shown coupled to ground or a second reference voltage via a switch 306h. This is typical in the design of an R-2R DAC, and the switch 310a is permanently closed. Alternatively, the switch 306h may be omitted, and the resistor 310a may be directly connected to ground.

[0048] As with DAC 200, voltage errors may occur at nodes 304a-304g due to non-linearities in the system, such as due to manufacturing variations.

[0049] Both DAC 200 and DAC 300 include an impedance network including a plurality of resistors connected in series. Both DACs are subject to the same errors introduced by manufacturing tolerances, and these errors appear at a plurality of nodes 204a-204i of DAC 200 or a plurality of nodes 302a-302f of DAC 300. Therefore, it can be considered that errors appear at the nodes connecting the plurality of serially coupled resistors or impedance elements.

[0050] Other types of DACs that include impedance networks may also suffer from the same voltage errors that occur at the nodes of the impedance network. For example, an interpolating DAC may also benefit from the transfer function modification circuits listed below. In addition, a DAC that includes multiple stages may be used. For example, a DAC that includes a first stage that includes an impedance network and a second stage that includes a switched capacitor network may be used.

[0051] Figure 4 A simplified impedance network is shown, including multiple resistor elements 402a-402h coupled together through multiple nodes 404a-404i. When connected as part of a DAC, such as a string DAC or a ladder DAC, the impedance network produces multiple voltage values ​​at the multiple nodes 404a-404i. In a DAC, errors appear as voltage errors at one or more of the multiple nodes 404a-404i. The voltage error is the difference between the desired or target voltage at a particular node and the voltage achieved in the actual circuit. These errors occur in string and ladder DACs and can be severe for DAC resolutions greater than 8 bits. As described above, the desired voltage at the node can be a voltage that achieves a linear transfer function or other voltages that achieve or approximate the desired transfer function. Figure 4 The number of resistors shown in the figure below is for example only, and the number of resistors used depends on the implementation of the DAC. For example, the impedance network may include 2 N Resistors, 2 N -1 resistor, where N is the length of the binary digital input. Any other number of resistors can be used in the impedance network.

[0052] The calibration circuit can be used to modify the transfer function of the DAC by injecting current into or draining current from one or more nodes. Typically, current will be injected into multiple nodes because this allows greater control over the voltage modification of the entire impedance network, and thus greater control over the transfer function of the system.

[0053] Figure 5 A DAC 500 including an impedance network and a transfer function modification circuit 502 is shown.

[0054] The transfer function modification circuit 502 includes a current DAC 504 and a demultiplexer 506. The current DAC 504 is configured to receive a trim code and output a current based on the trim code. The current output of the current DAC 504 can be a positive current or a negative current, and thus, the current DAC 504 can be viewed as a current source or a current sink depending on the trim code received. The trim code provided to the DAC can be an encoded trim code, such as encoded in straight binary, one's complement binary, two's complement binary, or minimum change encoding, including grayscale encoding.

[0055] The output of the current DAC 504 is coupled to a demultiplexer 506. The demultiplexer 506 is a form of a multiplexer including a single input and multiple outputs. Therefore, the demultiplexer 506 can be changed to a single-input multiple-output multiplexer. The demultiplexer 506 is configured to receive the output of the DAC 504. The demultiplexer 506 outputs the received signal to each output terminal of the demultiplexer 506. The output is selected based on the value of the selection signal received by the demultiplexer 506.

[0056] Each output of the demultiplexer 506 is coupled to a corresponding node of the plurality of nodes of the impedance network. The demultiplexer 506 shown in the DAC 500 is coupled to three nodes of the plurality of nodes, but this is merely an example and the demultiplexer 506 may be coupled to any number of the plurality of nodes. The demultiplexer 506 may have two or more outputs coupled to two or more corresponding nodes of the plurality of nodes 404a-404i. The system may also include a plurality of demultiplexers, the outputs of the demultiplexers may also be coupled to a common node such that each demultiplexer is coupled to at least one node to which another demultiplexer is coupled. The set of nodes of one demultiplexer may also overlap with the set of notes of a second multiplexer; the ranges of the node sets need not be independent.

[0057] like Figure 5 As shown, the first output terminal of demultiplexer 506 is connected to node 404c, the second output terminal is connected to node 404e, and the third output terminal is connected to node 404h. The demultiplexer need not be connected to each node in a plurality of nodes 404a-404i, and a plurality of resistors can be coupled between the nodes to which the demultiplexer is connected. For example, there are two resistors between node 404c and node 404e. Demultiplexer 506 is not coupled to node 404d.

[0058] During operation, the demultiplexer 506 is configured to output to one of the multiple nodes via one of its outputs. This causes current to be supplied to or drained from one of the nodes 404c, 404e, 404h. Due to the connection of the resistors, this changes the voltage of each node and all other nodes. This changes the transfer function of the DAC circuit 500 by changing the voltage at each node. Therefore, it is desirable to reduce or eliminate errors in the DAC.

[0059] Although Figure 5 The demultiplexer included in is shown as a single demultiplexer, but multiple demultiplexers can be coupled to the same DAC. This can allow current to be injected into multiple nodes of the impedance network.

[0060] While injecting current into a single node may change the voltage at that node, when current is injected into multiple nodes, the voltage at one of the nodes may not change significantly or substantially. This is because the injected currents at multiple nodes interact with each other to produce an overall change in the transfer function of the impedance network. The voltage at a node is affected not only by the current injected into that node, but also by the current injected into any other node of the impedance network.

[0061] Demultiplexer 506 may be implemented by cascaded multiplexers and / or row / column decoding multiplexer variants.

[0062] Figure 5 The DAC 500 shown includes eight resistors in the impedance network. Coupling a separate DAC to each node will provide improved configurability because more nodes can be adjusted or calibrated. In a DAC including nine nodes, nine DACs would be required to couple to each node. However, typically a DAC will include a larger impedance network consisting of more resistors. For example, a string DAC configured to receive an N-bit binary digital input word may require 2 DACs to be coupled between series coupled resistors. N -1 nodes, each separated by at least one resistor. This is because the impedance network must provide 2 N different output voltages to represent the 2 N possible inputs. An eight-bit DAC might require 256 impedance elements, with 256 nodes including the bottom terminal, 255 nodes between each resistor, and each node separated by at least one resistor. Although not completely conventional, a string could also use 2 N -1 or 255 resistors, in which case all resistor terminals are connected to the output, as in Figure 2bAs shown. The number of resistors in the string may vary depending on the encoding scheme of the digital input. Providing a separate DAC coupled to each of the 256 nodes would not require a very large circuit. Providing a DAC coupled to each of a subset of nodes (such as 20 nodes) would also require a larger circuit size. Therefore, it is necessary to provide or couple circuits to calibrate the DAC at a limited number of nodes. The inventors realized that providing a multiplexer allows DAC specific optimization, which can make DAC calibration achieved by calibrating or fine-tuning the DAC more efficient by selecting the best node as a device specific selection.

[0063] When DACs are manufactured using nanometer processes, there can be large differences between DACs using the same design due to the lack of predictability of mismatch and parasitics (including mask effects) at these process geometries. Therefore, providing calibration at a limited number of nodes may not allow for sufficient calibration to provide the required level of accuracy in the target circuit area.

[0064] Providing a system including a demultiplexer 506 between the output of the current DAC 504 and the plurality of impedance network nodes 404a-404i allows the point of current injection or discharge to be modified after manufacturing without requiring a large circuit area. This allows calibration to be configured during use without requiring a large number of DACs. This is Figure 5 The DAC 500 shown is provided because the node into which current is injected or drained can be modified using a multiplexer post-manufacturing. During operation, the system selects one of multiple nodes to inject current into or drain current from. The current injected into or drained from the node changes the transfer function of the DAC. A system is provided in which the node into which current is injected or drained is selectable, allowing extensive control over the transfer function of the DAC. During operation, the system selects one of multiple nodes to inject current into or drain current from. The current injected into or drained from the node changes the transfer function of the DAC. A system is provided in which the node into which current is injected or drained is selectable, allowing extensive control over the transfer function of the DAC.

[0065] Figure 6 A DAC 600 is shown that is similar to DAC 500. Transfer function modification circuit 502 also includes calibration circuit 608. Calibration circuit 608 provides a trim code 610 to current DAC 504 and provides a multiplexer select signal 612 to demultiplexer 506.

[0066] The trim current DAC 504 and the demultiplexer 506 may be separate components, such as Figure 6As shown. However, alternatively, the functions of the trim current DAC and the demultiplexer can be provided by a single circuit. The current injection device 614 can combine the functions of the trim current DAC 504 and the demultiplexer 506. The current injection device can receive the trim code 610 and the output selection signal 612. By combining the functions of the trim current DAC 504 and the demultiplexer 506, the size of the circuit can be reduced. It may also be desirable to separate them to optimize and implement a DAC circuit separate from the switching circuit.

[0067] The calibration circuit 608 may include a control system configured to determine the value of a trim code 610 and a multiplexer select signal 612. The trim code 610 sets the current value that the current DAC 504 is configured to source or sink. The multiplexer select signal 612 sets the output of the demultiplexer 506 configured to output. The control system may include a memory configured to store a library of trim codes and multiplexer select signals 612 that may be used. As known to those skilled in the art, the data may be compressed or digitally converted. If compressed, lossless compression is generally preferred to maintain accuracy and data quality.

[0068] The control system can be configured to use one of a number of different methods to determine the trim code for the DAC and the selected output of the multiplexer.

[0069] Figure 7 A method that the control system may perform to determine the trim code of the DAC 504 and the selected output of the demultiplexer 506 is shown. The method may include testing multiple configurations of the trim code and the demultiplexer output. In the case where the current DAC and demultiplexer are provided as a single system, such as in the current injection device 614, the system may determine the trim code and the node of the plurality of nodes into which the current should be injected or drained.

[0070] In a first step 702, the control system selects the output of the demultiplexer 506. The control system provides a selection signal 612 to the demultiplexer 504. Selecting a demultiplexer output may also be considered as selecting a configuration of the demultiplexer or selecting a demultiplexer selection.

[0071] In a second step 704, the control system selects a trim code for the DAC 504. The control system provides the trim code to the DAC 504. Selecting a trim code for the DAC can also be thought of as selecting the magnitude of current injected or drained using the current DAC.

[0072] The first step 702 and the second step 704 can be performed simultaneously or in any order. By selecting the fine-tuning code and the demultiplexer output, the DAC system selects a corresponding node among multiple nodes to inject current or drain current from. The fine-tuning code and the demultiplexer output can be regarded as a DAC configuration because they configure the operating mode of the transfer function modification. Although steps 702 and 704 are defined as separate steps, they can be regarded as one step, that is, selecting a node to inject or drain a certain amount of current. In the case where the fine-tuning current DAC 504 and the demultiplexer are provided as a single system or circuit, such as the current injection device 614, steps 702 and 704 may include determining the node to which the current is to be injected or discharged and the magnitude of the current.

[0073] The output of the demultiplexer 506 and the fine-tuning code can be selected by the control system from a database of demultiplexer 506 outputs and corresponding fine-tuning codes stored in a memory of the control system. During the manufacturing process of the DAC 600, the database can be pre-populated with DAC configurations, including the output of the demultiplexer 506 and the fine-tuning code. For example, testing of a large number of DACs 600 can determine that a subset of configurations provides the lowest residual or sufficiently low residuals for the system. These can be stored in a library. The database can be populated with pre-production characterization and / or yield analysis data. If necessary, the library can also be continuously added to continue learning and reducing residuals. Federated learning can be used.

[0074] Once the control system selects the output of the demultiplexer 506 and the fine-tuning code of the current DAC 504 and applies it to the current DAC 504 and the demultiplexer 506, the control system can determine the residual error of the DAC 600 in step 706. The residual error can be the difference between the ideal output of the digital code input of the DAC 600 and the analog output of the DAC 600. Therefore, the control system can receive the digital input and the analog output and calculate the residual. Alternatively, the residual can be the difference between the transfer function of the DAC 600 and the expected transfer function of the DAC 600. The transfer function can be determined based on the digital input and the analog output received by the control system. The system can determine the residual error using an on-chip measurement system that is part of the DAC or an off-chip measurement system that is not part of the DAC. The residual error is determined to a level of accuracy that depends on the accuracy of the measurement system. Therefore, multiple DAC configurations may appear to have the same residual because the difference between the tested residuals is less than the system noise or repeatability threshold.

[0075] In the case where the measurement system is a system on chip, the chip may include an ADC. If the measurement system is off-chip, the measurement system may be a digital voltmeter or use an ADC.

[0076] In step 708, the control system may save the residual error for the DAC 600 configuration to a library, associating the residual error with the tested DAC 600 configuration.

[0077] In step 710, the control system may determine whether to test further DAC configurations or exit the process. For example, in the event that the residual error of the most recently tested DAC 600 configuration is within the target error tolerance of the system, the control system may move to step 712. This allows the system to apply a configuration to the DAC 600 in step 712 once a configuration is determined that satisfies the residual error condition, thereby providing faster DAC 600 calibration.

[0078] Alternatively, the control system can repeat the process of steps 702-708 until all or a sufficient number of DAC configurations stored in the database have been tested. This can be determined by evaluating the effectiveness of the calibration and ensuring that the system has been checked in a sufficient number of representative cases to ensure manufacturability. Once all DAC 600 configurations have been tested, the system can proceed to step 712 and apply the DAC configuration that provides the lowest residual error among the tested DAC configurations. Alternatively, a sufficient number of DAC configurations can be tested to achieve a sufficiently low residual, such as a residual below a residual threshold. In the event that multiple configurations appear to provide the same residual, for example due to the precision of determining the residual, a random one of the configurations can be selected.

[0079] While method 700 characterizes the performance of the DAC under different configurations, it may be desirable to first measure the DAC without injected trimming current and determine the residual. Method 700 may then continue by applying various trimming currents to different nodes of the impedance network and checking whether the different nodes meet the expected current injection accuracy within the measurement repeatability limits compared to the case without injected current. It is desirable to design the trimming DACs to be sufficiently accurate that their errors do not need to be checked prior to system calibration, but if the trimming DACs are not accurate enough so that the injected current is different than expected, the inaccuracies of the trimming DACs may be measured and accounted for when determining the residual and injected current. In the latter case, the constancy or stability of the inaccuracy after calibration is still important to achieve an accurate calibration that is robust to environmental and use case variations. The calibration method 700 may be iterated to account for these inaccuracies.

[0080] Before or after the configuration is applied to the transfer function modification circuit in step 712, the configuration can be saved as a preferred configuration in a memory of the control system. The memory can be a non-volatile memory. This preferred configuration can be applied to future digital-to-analog conversions without repeating the process of method 700.

[0081] Figure 8aAnother method of determining the DAC configuration is shown, including the current DAC 504 trim code and the demultiplexer 506 select signal.

[0082] Step 802 includes accessing or receiving a data or information library. The data or information library may include characteristics of multiple DACs, such as transfer functions between multiple DACs. The data or information library may also include multiple previously tested DAC configurations or historical DAC configurations. These may include the initial or uncorrected transfer function of the DAC, a tested DAC configuration applied to the DAC (including fine-tuning codes and demultiplexer outputs applied to the DAC), and the transfer function of the DAC modified by the transfer function. In some cases, a user may manually pre-calibrate or perform a certain level of DAC, DAC signal chain, or system calibration before providing data to a machine learning model or calibrating the DAC using a machine learning model. Therefore, the data or information library may also include transfer functions of calibrated or partially calibrated DACs. Although the DC accuracy of data converters typically focuses on the transfer function of the data converter, most commonly endpoint adjustments, input and output data representations may also be useful forms of the same information in machine learning. Therefore, the data or information library may represent different DAC configurations and the effects of these configurations on the transfer function. The data or information library may use something like Figure 7 The iterative process described in , by testing a large number of different DAC configurations to see the impact on the DAC transfer function. Accessing the library can include the DAC retrieving data or information from a co-located memory. Alternatively, the access can be performed off-chip, such as during the manufacturing process.

[0083] The database may be generated from or using a sample DAC (e.g., a pre-production DAC system). Using a sampled DAC system in this way allows real-world effects to be included in the data, such as data that simulations may not be able to capture. The database may also include simulated data, which allows the database to contain large amounts of data at a low cost. Data augmentation may also be used, where data acquired from the real world or a sample DAC system is augmented using, for example, simulated data.

[0084] The quality of the information or database is important to the quality of the developed machine learning model. Figure 8a Another optional step between steps 802 and 804, namely step 808, can check the data quality. Exploratory data analysis (EDA) can be used to check the quality, entropy and any assumptions or biases contained in the library. In the event that EDA confirms that the data quality is sufficient, the method can continue to step 804. In the event that EDA results in the data quality being deemed insufficient, the method can return to step 802, where new data can be received or data augmentation can be used.

[0085] Step 804 includes performing a machine learning operation on the data or information base to determine the effect of the DAC configuration on the DAC transfer function.

[0086] Step 806 includes training the machine learning model using the provided data or information library. The machine learning model learns from the provided library and can be considered to embody or include the library because the machine learning model is adjusted and improved by the provided data.

[0087] Steps 802 to 806 can be performed off-chip during the initial manufacturing process. It should be understood that digital processing can be implemented in different parts of the system design and can be divided into sub-parts that are completed in different parts of the system. This includes on-chip digital, multi-chip solutions, and off-chip DSPs, including microcontrollers, FPGAs, and cloud processing. For example, data or information libraries can be generated for a large number of DACs, and machine learning can be used to analyze the impact of DAC configuration on the transfer function. From this, a trained machine learning model can be generated that correlates the impact of DAC configuration on the DAC transfer function. The model can be provided to the control system of the DAC, such as stored in the memory of the control system, hard-coded into the design, or can be configured to allow further or iterative optimization.

[0088] Alternatively, steps 802-806 may be performed on-chip, for example, using initial random machine learning model coefficients and a library of data or information provided to the control system, included in calibration circuit 608 of DAC system 600. The control system of DAC system 600 may then train the machine learning model.

[0089] Once the machine learning model is trained, either off-chip and then provided to the control system of DAC system 600, or trained using the control system in DAC system 600, the machine learning model can be used to determine the DAC configuration of the transfer function modification circuit.

[0090] Figure 8b Determination of the optimal DAC configuration in method 810 is shown after the machine learning model is trained.

[0091] In step 812 , the transfer function of the DAC is received by the control system of the calibration circuit 608 .

[0092] In step 814, a machine learning model is applied to the received transfer function to determine the optimal DAC configuration. For each DAC, many different configurations may be optimal. For example, any configuration that provides a residual below a threshold residual may be considered optimal.

[0093] Optionally, once the optimal DAC configuration is determined, it can be applied to the transfer function modification circuit. After applying the DAC configuration, the machine learning model can receive the transfer function of the DAC in step 816. The received transfer function allows the calibration circuit to determine the effect of the applied DAC configuration. The received transfer function can be determined by measuring the relationship between the output of the DAC and the input data.

[0094] In optional step 818, the machine learning model can use continuous learning based on the updated transfer function received from step 816. The machine learning model can be trained based on the effect of the applied DAC configuration. This enables the machine learning model to continuously improve, update, and adapt to changes.

[0095] Alternatively or additionally, in step 820, the system can iterate the DAC configuration by using a machine learning model to determine an updated optimal DAC configuration. Step 820 can be used in situations where there is a large residual error between the initial transfer function of the DAC and the updated transfer function of the DAC. The large residual error can be a residual error that is above a residual error threshold of the DAC system.

[0096] Step 806 includes determining an optimal configuration of the DAC based on the machine learning algorithm of step 804. This may include the control system selecting a DAC based on the transfer function of the DAC, the target transfer function, and the machine learning algorithm to confirm. The selected DAC configuration may be applied to the transfer function modification circuit.

[0097] When using Figure 7 or Figure 8b When the method selects and applies a DAC configuration, the system can be configured to test the performance and residual error of the DAC configuration.

[0098] Figure 5 DAC 500 and Figure 6 The DAC 600 can be used as part of a larger system or signal chain.

[0099] For example, Fig. 9 As shown, the signal chain 900 may include Figure 6DAC 600. The digital input provided to DAC 600 may be pre-processed by circuit 902. Circuit 902 may include any number of systems, such as amplifiers or buffers. The analog output of DAC 600 may be provided to circuit 904 and post-processed. Circuit 904 may also include any number of systems, such as amplifiers or buffers. Other components may cause nonlinearity in the signal chain, such as a voltage or current reference provided to the DAC. The buffer circuit may include a range scaling and offset circuit. The signal chain 900 including circuit 902, DAC 600, and circuit 904 may have a signal chain transfer function that introduces nonlinearity into the output. Nonlinearity may be caused by errors in DAC 600, such as errors caused by voltage errors at multiple nodes of the impedance network. However, nonlinearity may also be introduced by circuit 902 and circuit 904. Therefore, when determining the fine-tuning code and the output of the demultiplexer 506, it may be necessary to linearize the transfer function of the signal chain 900 instead of the transfer function of the DAC 500, 600.

[0100] Therefore, the target transfer function of the DAC 500, 600 may be non-linear and determined to compensate for the non-linear effects of the signal chain 900 so that the signal chain 900 has a linear transfer function. The target transfer function may also be non-linear.

[0101] Figure 6 The DAC 600 includes a single current DAC 504 and a single demultiplexer 506. However, the DAC may include multiple current DACs coupled to multiple demultiplexers.

[0102] Fig.10 A DAC 1000 is shown, which includes a transfer function modification circuit 1002, which includes a plurality of current DACs, each current DAC including an input and an output for receiving a trim code. Each current DAC can receive a current reference. The current DACs can use the current reference to reference the output current they provide relative to the trim code. All current DACs can receive the same current reference or different current references. The system also includes a plurality of demultiplexers, each of the plurality of demultiplexers including an input and a plurality of outputs.

[0103] DAC 1000 includes a first current DAC 1004 having an input and an output. The output of the first current DAC 1004 is coupled to the input of a first demultiplexer 1006. DAC 1000 also includes a second current DAC 1010 having an input and an output. The output of the second current DAC 1010 is coupled to the input of a second demultiplexer 1012.

[0104] The calibration circuit 1008 is configured to provide a first trim code 1014 to the first current DAC 1004 and a second trim code 1016 to the second current DAC 1010. The calibration circuit is also configured to provide a first multiplexer select signal 1018 to the first demultiplexer 1006 and a second multiplexer select signal 1020 to the second demultiplexer 1012. The calibration circuit 1008 may determine multiple trim codes and signals using the method 700 or 800 in the same manner as it may be configured to determine a single trim code and select signal.

[0105] By having two demultiplexers 1006, 1012, the system can source current to or sink current from two of the plurality of nodes 404a-404i of the impedance network. This allows for better control of the transfer function of the DAC 1000 by coupling trim current to a point that optimizes the effect of the current on the transfer function.

[0106] The output of each demultiplexer is coupled to a different node in the plurality of nodes 404a-404i. They may be connected to a different number of nodes in the plurality of nodes or the same number of nodes.

[0107] Although Fig.10 The system includes two current DACs 1004, 1010 and two demultiplexers 1006, 1012, but it may include more than two current DACs and more than two demultiplexers.

[0108] Each current DAC in DAC 1000 is coupled to one of the plurality of nodes via a demultiplexer. However, the system may include additional current DACs that are connected to a single one of the plurality of nodes and are not coupled via a demultiplexer. This may be beneficial in situations where there are known nodes in the impedance network that typically or periodically require adjustment.

[0109] Fig.11 The DAC 1100 is shown including a transfer function modification circuit 1102. In addition to the first current DAC 1004 and the second current DAC 1010, the DAC 1100 also includes a third current DAC 1122 and a fourth current DAC 1124.

[0110] The impedance network used in the string DAC can be coupled to a reference voltage terminal Vref at a first end and to a second reference voltage terminal, which can be ground, at a second end. The impedance network can be coupled to the reference voltage Vref through a variable resistor 1126. The variable resistor 1126 allows the headroom to be created and changed between the voltage reference and the first end of the impedance network. Similarly, the impedance network can be coupled to a second reference voltage through a second variable resistor 1128.

[0111] The output of the third current DAC 1122 is coupled to the node 404a of the impedance network. The node 404a may be an endpoint of the impedance network, so it is coupled to a reference voltage. The node 404a is coupled to the reference voltage through the variable resistor 1126. Therefore, the third current DAC 1122 is an endpoint trimming DAC. The third current DAC 1122 is arranged to receive a trimming code 1130 from the calibration circuit 1008. Based on the value of the trimming code 1130, the third current DAC 1122 will source or sink current from the node 404a, providing endpoint calibration for the circuit.

[0112] Similarly, the fourth current DAC 1124 is arranged to receive the trim code 1132 from the calibration circuit 1008. The fourth current DAC 1124 is an endpoint current DAC configured to provide endpoint calibration for the node 404i of the impedance network.

[0113] Although DACs can be directly coupled to nodes to provide endpoint calibration, they can also be directly connected to nodes in other parts of the impedance network. For example, it can be determined that certain nodes of the impedance network often require current injection to provide the required transfer function. A dedicated current DAC can be coupled or directly connected to the node. The current DAC can be calibrated in the same manner as the DAC demultiplexer combination described in method 700. However, it will be clear to those skilled in the art that it is not necessary to select the demultiplexer output as in step 702, but only to select the fine-tuning code of the DAC.

[0114] The transfer function modification circuits described in the previous figures can be applied to any DAC system that uses an impedance network consisting of multiple resistors coupled together through nodes, such as the string DAC of Figure 2 or Figure 3 The transfer function modification circuit can also be applied to more complex DACs that include multiple impedance networks.

[0115] Figure 2a The binary string DAC shown consists of 2 N series resistors, where N is the length of the binary digital input word. Other numbers of resistors may be used, such as Figure 2b 2 shown N-1 resistors. Other configurations with different numbers of resistors can also be used. For medium and high resolution DACs, this requires large resistor strings and large system area. Figure 5 and Figure 6 The space-saving demultiplexer compensation system shown, combined with an alternative DAC impedance network design, can further reduce the size of the DAC system while still allowing compensation and calibration.

[0116] Fig.12DAC 1200 is shown. DAC 1200 includes a plurality of impedance networks. DAC 1200 is an N-bit DAC capable of receiving an input digital codeword of N bits. The digital word can be viewed as a segmented DAC input comprising M least significant bits and NM most significant bits. A segmented DAC is a DAC that divides the DAC word into multiple segments, such as for a multi-impedance string DAC where one string converts the MSB of the DAC and one string converts the LSB of the DAC. There are many known types of segmented DACs, so they will not be described in detail here. An example of a segmented DAC is shown in FIG. Fig.12 As shown, however, applied to Fig.12 The transfer function modification of the segmented DAC can also be applied to other segmented DACs.

[0117] The first impedance network 10 includes resistors Ra1 to Ra2 N / 2 -1. The second impedance network 12 includes resistors Rb1 to Rb2 N / 2 -1. The first 10 and second 12 impedance networks are most significant bit (MSB) impedance networks. The first impedance network 10 is coupled to a first reference voltage Vref+, and the second impedance network 12 is coupled to a second reference voltage Vref-. The DAC 1200 also includes a third impedance network 40, which includes resistors Rc1 to Rc2 N / 2 -1. The third impedance network is a least significant bit or LSB impedance network. DAC1200 is a three string DAC. The first and second impedance networks are also coupled to a high impedance node or terminal or floating terminal. The two strings are preferably implemented so that the resistors in the two strings are matched within the string and between the two strings. Therefore, there are corresponding impedance elements and nodes in both the first and second impedance networks, which are coupled in series with the end nodes terminated at the high impedance node. Therefore, the first or bottom nodes of the two strings correspond to each other, and so on, all the way to the other end of the string.

[0118] Each impedance network is coupled to a corresponding plurality of switches Sa, Sb and Sc. These switches are controlled using a decoder according to the input digital code. An analog output is provided at an output node 24.

[0119] US Patent 6416616B1 provides such Fig.12 An explanation of the working principle of the three-string DAC is shown in FIG. 1 and is incorporated herein by reference in its entirety. Three-string DACs are well known in the art, and thus the operation of DAC 1200 will not be described in detail here.

[0120] Similar to the impedance networks described for the single string DAC, voltage errors may appear at the nodes connecting the resistors of the first impedance network 10 and the second impedance network 12. Therefore, a transfer function modification circuit may be used to inject current into these nodes in a similar manner as described above for the DAC.

[0121] Fig.13 The DAC 1300 is shown. The DAC 1300 includes Fig.12 Three strings of DACs and a transfer function modification circuit 1302 are shown. The transfer function modification circuit includes a calibration circuit 1308 and a plurality of current DACs 1304, 1310 and multiplexers 1306, 1312.

[0122] The transfer function modification circuit 1302 includes a first current DAC 1304. An output terminal of the first current DAC 1304 is coupled to an input terminal of a demultiplexer 1306. A plurality of output terminals of the demultiplexer 1306 are coupled to nodes of a plurality of nodes of the first impedance network 10.

[0123] The transfer function modification circuit 1302 includes a second current DAC 1310. The output of the second current DAC 1310 is coupled to the input of a demultiplexer 1312. The multiple outputs of the demultiplexer 1312 are coupled to nodes of the multiple nodes of the second impedance network 12. Although the figure includes two DACs, one DAC or more than two DACs may be used.

[0124] The current DACs 1304, 1310 receive respective digital input capacitors 1314, 1315 from the calibration circuit 1308. The demultiplexers 1306, 1312 receive respective selection signals 1318, 1320 from the calibration circuit 1308.

[0125] Thus, the transfer function modification circuit 1302 includes a plurality of multiplexers and a plurality of current DACs arranged to inject current into or sink current from a plurality of nodes in a plurality of impedance networks.

[0126] Although Fig.13 The transfer function modification circuit 1302 includes two current DACs and two demultiplexers, but the transfer function modification circuit 1302 may include multiple current DACs and multiplexers. Alternatively, it may include one current DAC and one demultiplexer, wherein the output of the single demultiplexer is coupled to a node in one or both of the first impedance network 10 and the second impedance network 12.

[0127] In this binary example implementation, the first impedance network 10 and the second impedance network 12 include the same number of resistors (2 N / 2 -1). As mentioned earlier, the impedance network used in a DAC may include different numbers of resistors, such as 2 N. Non-binary implementations may also use different numbers of resistors. Therefore, the impedance network includes the same number of nodes connecting resistors. The first impedance network 10 and the second impedance network 12 differ only in that they are coupled to different reference voltages. Therefore, the first impedance network 10 and the second impedance network 12 have corresponding resistors and nodes. For example, the first resistor Ra1 corresponds to the resistor Rb1, and the second resistor Ra2 corresponds to the resistor Rb2. Similarly, the node between resistors Ra1 and Ra2 corresponds to the node between resistors Rb1 and Rb2. Therefore, the nodes in the first impedance network and the second impedance network. The output of the demultiplexer can be coupled to the nodes in the first impedance network 10 and the second impedance network 12, because errors may occur in both impedance networks.

[0128] The nodes of the first impedance network 10 to which the demultiplexer 1306 is coupled may correspond to the nodes of the second impedance network 12 to which the second demultiplexer is coupled. The current will be injected into or drained from the corresponding nodes in the first and second impedance networks 12.

[0129] The voltage reference terminals described with reference to the preceding figures are typically coupled to a voltage source or voltage level, but the reference level may also be provided by a current source, for example using a voltage to current converter circuit which may use the same type of impedance element to produce the current track impedance variation.

[0130] Although a MOS implementation is described, it will be appreciated that a BiCMOS implementation may also be used, including the use of bipolar and / or JFET devices.

[0131] Alternative trim DAC implementations may also be used, such as using resistor degeneration. Cascode devices may also be used, but are not included here for clarity of explanation.

[0132] The impedance network in the DAC described in this application includes a plurality of resistors coupled in series. However, the impedance network may use alternative impedance components or elements, such as switched capacitors, instead of resistors.

[0133] Various modifications may be made to the above-described examples, whether by adding, deleting, or substituting features, to provide further examples, any and all of which should be encompassed by the following claims.

[0134] aspect:

[0135] Aspects of the invention are included below.

[0136] 1. A digital-to-analog converter DAC, comprising:

[0137] an impedance network comprising a plurality of impedance elements coupled together via a plurality of nodes, wherein the impedance network is configured to couple to a reference voltage and produce a plurality of voltage values ​​at the plurality of nodes; and

[0138] Transfer function modification circuits, including:

[0139] a trim current DAC comprising an input for receiving a trim code and an output; and

[0140] a demultiplexer, the demultiplexer comprising an input and a plurality of outputs,

[0141] wherein the output of the fine current DAC is coupled to the input of the demultiplexer,

[0142] wherein each of the plurality of outputs of the demultiplexer is coupled to a corresponding node of the plurality of nodes, and

[0143] Wherein the trim current DAC is configured to modify a transfer function of the DAC by injecting current into or draining current from a selected node of the plurality of nodes via a selected output of the demultiplexer.

[0144] 2. The DAC of aspect 1, wherein the transfer function modification circuit further comprises a calibration circuit configured to provide a trim code to the trim current DAC and select the demultiplexer configuration to modify the transfer function of the DAC.

[0145] 3. The DAC of clause 2, wherein the calibration circuit selects the trim code and the demultiplexer configuration to reduce a difference between a transfer function of the DAC and a target transfer function of the DAC.

[0146] 4. The DAC according to aspect 2 or aspect 3, wherein the calibration circuit is configured to select the fine tuning code and the demultiplexer configuration in the following manner:

[0147] A plurality of configurations of the transfer function modification circuit are tested, wherein a configuration is a combination of the trim code and the demultiplexer configuration.

[0148] 5. The DAC of clause 4, wherein testing multiple configurations of the transfer function modification circuit comprises repeating:

[0149] Select the demux configuration;

[0150] Select the fine-tuning code for the DAC;

[0151] Determine the residual between the DAC's transfer function and the configured target transfer function.

[0152] 6. The DAC of clause 5, wherein selecting the output of the demultiplexer and a trim code for trimming the DAC comprises:

[0153] comparing the residuals of the plurality of configurations;

[0154] The configuration with the lowest measured residual error is applied.

[0155] 7. The DAC of clause 5, wherein selecting the output of the demultiplexer and a trim code for trimming the DAC comprises:

[0156] Repeating the steps of claim 5 until the determined residual is less than a specified residual;

[0157] Apply a configuration that has a determined residual that is smaller than the specified residual.

[0158] 8. A DAC according to any one of clauses 5 to 7, wherein:

[0159] Selecting an output of the demultiplexer and selecting a trim code for the DAC includes selecting from a database of the demultiplexer output and the trim code.

[0160] 9. The DAC of clause 3, wherein the calibration circuit is configured to select the trim code and select the output of the demultiplexer by:

[0161] The fine tuning code and the output of the demultiplexer are selected from the database based on the transfer function of the DAC and the target transfer function.

[0162] 10. The DAC of clause 3, wherein the calibration circuit is configured to select the trim code and select the output of the demultiplexer by:

[0163] The transfer function of the receiving DAC and the target transfer function of the DAC;

[0164] performing a machine learning operation using the machine learning model to determine an optimal DAC configuration;

[0165] Apply the optimal DAC configuration as described.

[0166] 11. A DAC according to any one of clauses 3 to 10, wherein the target transfer function is a linear relationship between an input of the DAC and an output of the DAC.

[0167] 12. A DAC according to any one of clauses 3 to 10, wherein the target transfer function is a non-linear relationship between an input of the DAC and an output of the DAC.

[0168] 13. A DAC according to any preceding aspect, further comprising:

[0169] a plurality of fine-tuning current DACs, each of the plurality of fine-tuning current DACs comprising an input for receiving a fine-tuning code and an output;

[0170] a plurality of demultiplexers, each demultiplexer of the plurality of demultiplexers comprising an input and a plurality of outputs;

[0171] The output of each fine-tuning current DAC is coupled to the input of a corresponding demultiplexer,

[0172] wherein each of the plurality of outputs of each demultiplexer is coupled to a corresponding node of the plurality of nodes, and

[0173] Wherein each of the plurality of fine-tuning current DACs is configured to modify a transfer function of the DAC by injecting current into or draining current from a selected node of the plurality of nodes via a selected output of each demultiplexer.

[0174] 14. The DAC according to any preceding aspect, further comprising: an additional fine-tuning current DAC, the additional fine-tuning current DAC comprising an output, wherein the output is coupled to a node of the plurality of nodes of the impedance network.

[0175] 15. The DAC of clause 14, wherein the trim DAC is coupled to endpoints of the impedance network and configured to provide endpoint calibration.

[0176] 16. A DAC according to any preceding aspect, wherein the DAC comprises a string DAC.

[0177] 17. The DAC according to aspect 16, further comprising:

[0178] a second impedance network comprising a second plurality of resistor elements coupled together via a second plurality of nodes, wherein the second plurality of impedance networks are configured to couple to a second reference voltage and to produce a plurality of voltage values ​​at the second plurality of nodes, wherein each node of the second plurality of nodes corresponds to a node of the first plurality of nodes; and

[0179] Wherein each of the plurality of outputs of the demultiplexer is coupled to a respective node of the second plurality of nodes that corresponds to a respective node of the first plurality of nodes.

[0180] 18. A DAC according to any one of clauses 1-15, wherein the DAC comprises a ladder DAC.

[0181] 19. A DAC according to any preceding aspect, wherein the DAC is configured to select an output node from a plurality of nodes to generate an analog output voltage.

[0182] 20. The DAC of any preceding aspect, wherein the fine current DAC and the demultiplexer are combined within a single integrated circuit.

[0183] 21. A digital-to-analog converter DAC, comprising:

[0184] an impedance network comprising a plurality of impedance elements coupled together via a plurality of nodes, wherein the impedance network is configured to couple to a reference voltage and produce a plurality of voltage values ​​at the plurality of nodes; and

[0185] Transfer function modification circuits, including:

[0186] a current injection component configured to be coupled to a subset of the plurality of nodes;

[0187] The current injection component is configured to modify a transfer function of the DAC by selecting a node from a subset of the plurality of nodes and injecting current into or draining current from the selected node of the plurality of nodes.

[0188] 22. A DAC according to aspect 21, wherein the current injection means comprises a function of a fine-tuning current DAC and a demultiplexer.

[0189] 23. A method of modifying a transfer function of a digital-to-analog converter (DAC) comprising an impedance network, the impedance network comprising a plurality of resistor elements coupled together via a plurality of nodes, wherein the impedance network is configured to couple to a reference voltage and produce a plurality of voltage values ​​at the plurality of nodes, the method comprising:

[0190] selecting a corresponding node of the plurality of nodes to inject current into or drain current from;

[0191] Injects current into or drains current from selected nodes of the impedance string to modify the transfer function of the DAC.

[0192] 24. The method of clause 23, wherein selecting a respective node of the plurality of nodes to inject current into or drain current from comprises:

[0193] receiving a database comprising characteristics of a plurality of DACs;

[0194] providing the database to a machine learning model;

[0195] The machine learning model is trained using the database.

[0196] 25. The method according to aspect 24, further comprising:

[0197] The transfer function of the receiving DAC and the target transfer function of the DAC;

[0198] performing a machine learning operation using the machine learning model to determine an optimal DAC configuration, the optimal DAC configuration comprising a selected node of the plurality of nodes to inject current into or drain current from;

[0199] Apply the optimal DAC configuration as described.

[0200] 26. The method according to aspect 25, further comprising:

[0201] receiving an updated transfer function of the DAC after applying the optimal DAC configuration; and

[0202] The machine learning model is trained based on the impact of the optimal DAC configuration on the updated transfer function.

[0203] 27. The method according to aspect 25, further comprising:

[0204] receiving an updated transfer function of the DAC after applying the optimal DAC configuration; and

[0205] The DAC configuration is iterated using a machine learning model to determine an updated optimal DAC configuration.

[0206] 28. The method of clause 23, wherein selecting a respective node of the plurality of nodes to inject current into or drain current from comprises:

[0207] Test multiple DAC configurations by following these steps:

[0208] selecting a corresponding node of the plurality of nodes to inject current into or drain current from;

[0209] determining the residual between the transfer function of the DAC and the configured target transfer function;

[0210] comparing the residuals of the plurality of configurations;

[0211] The configuration with the lowest residual is applied.

[0212] 29. A method of modifying a transfer function of a digital-to-analog converter (DAC) including an impedance network, the method comprising:

[0213] receiving a database of DAC configurations for providing a target transfer function to the DAC;

[0214] performing machine learning operations on the database to determine a machine learning model associated with the DAC configuration and the target transfer function;

[0215] selecting a DAC configuration using the machine learning model and a target transfer function of the DAC;

[0216] Applies the selected DAC configuration to the DAC.

Claims

1. A digital-to-analog converter DAC, comprising: an impedance network comprising a plurality of impedance elements coupled together via a plurality of nodes, wherein the impedance network is configured to couple to a reference voltage and produce a plurality of voltage values ​​at the plurality of nodes; and Transfer function modification circuits, including: a trim current DAC comprising an input for receiving a trim code and an output; and a demultiplexer, the demultiplexer comprising an input and a plurality of outputs, wherein the output of the fine current DAC is coupled to the input of the demultiplexer, wherein each of the plurality of outputs of the demultiplexer is coupled to a corresponding node of the plurality of nodes, and Wherein the fine-tuning current DAC is configured to modify a transfer function of the DAC by injecting current into or draining current from a selected node among the plurality of nodes via a selected output of the demultiplexer.

2. The DAC of claim 1 , wherein the transfer function modification circuit further comprises a calibration circuit configured to provide a trim code to the trim current DAC and select the demultiplexer configuration to modify the transfer function of the DAC.

3. The DAC of claim 2, wherein the calibration circuit is configured to select the trim code and the demultiplexer configuration to reduce a difference between a transfer function of the DAC and the DAC target transfer function.

4. The DAC of claim 2 , wherein the calibration circuit is configured to select the trim code and the demultiplexer configuration by: A plurality of configurations of the transfer function modification circuit are tested, wherein a configuration is a combination of the trim code and the demultiplexer configuration.

5. The DAC of claim 4 , wherein testing multiple configurations of the transfer function modification circuit comprises repeating: Select the demux configuration; Select the fine-tuning code for the DAC; Determine the residual between the DAC's transfer function and the configured target transfer function.

6. The DAC of claim 5, wherein selecting the output of the demultiplexer and a trim code for trimming the DAC comprises: comparing the residuals of the plurality of configurations; The configuration with the lowest residual error is applied.

7. The DAC of claim 5, wherein selecting the output of the demultiplexer and a trim code for trimming the DAC comprises: Repeating the operation of claim 5 until the determined residual is less than a specified residual; Apply a configuration that has a determined residual that is smaller than the specified residual.

8. The DAC of claim 5, wherein: Selecting the output of the demultiplexer and selecting a trim code for the DAC includes selecting from a database of the output of the demultiplexer and the trim codes.

9. The DAC of claim 3 , wherein the calibration circuit is configured to select the trim code and select the output of the demultiplexer by: The transfer function of the receiving DAC and the target transfer function of the DAC; performing a machine learning operation using the machine learning model to determine an optimal DAC configuration; Apply the optimal DAC configuration as described.

10. The DAC of claim 3, wherein the target transfer function is a linear relationship between an input of the DAC and an output of the DAC.

11. The DAC of claim 2, wherein the target transfer function is a non-linear relationship between an input of the DAC and an output of the DAC.

12. The DAC of claim 1 , further comprising: a plurality of fine-tuning current DACs, each of the plurality of fine-tuning current DACs comprising an input for receiving a fine-tuning code and an output; a plurality of demultiplexers, each demultiplexer of the plurality of demultiplexers comprising an input and a plurality of outputs; The output of each fine-tuning current DAC is coupled to the input of a corresponding demultiplexer, wherein each of the plurality of outputs of each demultiplexer is coupled to a corresponding node of the plurality of nodes, and Wherein each of the plurality of fine-tuning current DACs is configured to modify a transfer function of the DAC by injecting current into or draining current from a selected node of the plurality of nodes via a selected output of each demultiplexer.

13. The DAC of claim 1, further comprising an additional fine-tuning current DAC comprising an output, wherein the output is coupled to a node of the plurality of nodes of the impedance network.

14. The DAC of claim 1 , further comprising: a second impedance network comprising a second plurality of resistor elements coupled together via a second plurality of nodes, wherein the second plurality of impedance networks are configured to be coupled to a second reference voltage and to produce a plurality of voltage values ​​at the second plurality of nodes, wherein each node of the second plurality of nodes corresponds to a node of the plurality of nodes of the impedance network; and Wherein each of the plurality of outputs of the demultiplexer is coupled to a respective node of the second plurality of nodes corresponding to a respective node of the plurality of nodes.

15. The DAC of claim 1, wherein the fine current DAC and the demultiplexer are combined within a single integrated circuit.

16. A digital-to-analog converter DAC, comprising: an impedance network comprising a plurality of impedance elements coupled together via a plurality of nodes, wherein the impedance network is configured to couple to a reference voltage and produce a plurality of voltage values ​​at the plurality of nodes; and Transfer function modification circuits, including: a current injection component configured to be coupled to a subset of the plurality of nodes; The current injection component is configured to modify the transfer function of the DAC by selecting a node from a subset of the plurality of nodes and injecting current into or draining current from the selected node of the plurality of sub-nodes.

17. The DAC of claim 16, wherein the current injection means comprises the functionality of a fine current DAC and a demultiplexer.

18. A method of modifying a transfer function of a digital-to-analog converter (DAC) comprising an impedance network, the impedance network comprising a plurality of resistor elements coupled together via a plurality of nodes, wherein the impedance network is configured to couple to a reference voltage and produce a plurality of voltage values ​​at the plurality of nodes, the method comprising: selecting a corresponding node of the plurality of nodes to inject current into or drain current from; Current is injected into or drained from selected nodes of the impedance network to modify the transfer function of the DAC.

19. The method of claim 18, wherein selecting a corresponding node of the plurality of nodes to inject current into or drain current from comprises: receiving a database comprising characteristics of a plurality of DACs; providing the database to a machine learning model; The machine learning model is trained using the database.

20. The method according to claim 19, further comprising: The transfer function of the receiving DAC and the target transfer function of the DAC; performing a machine learning operation using the machine learning model to determine an optimal DAC configuration, the optimal DAC configuration comprising a selected node of the plurality of nodes to inject current into or drain current from; Apply the optimal DAC configuration as described.

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