Method for testing messages with normal and abnormal formats based on PCIe Switch equipment

Abstract

The invention provides a test method for messages with normal and abnormal formats based on PCIe Switch equipment, and the method comprises the steps: building a test environment through employing a PCIe protocol analyzer and a PCIe simulator, and verifying the functions of the PCIe Switch equipment through employing the PCIe simulator as RC and EP equipment to send messages; and according to a preset test scene, executing a message test with a normal format and an abnormal format. The method for testing the messages with the normal and abnormal formats based on the PCIe Switch equipment has the beneficial effects that the messages with the normal and abnormal formats can be tested on the PCIe Switch equipment before tape-out through an FPGA prototype verification system, design defects can be found as soon as possible, and risks are reduced.

Description

Technical Field

[0001] The present invention belongs to the field of communication technology, and in particular relates to a method for testing messages with normal and abnormal formats based on a PCIe Switch device. Background Art

[0002] As a high-speed data interface, PCIe Switch devices are widely used in various scenarios that require high-bandwidth data transmission, such as servers, data centers, and high-performance computing. Its main function is to route and switch PCIe signals to achieve data interconnection between multiple PCIe devices. However, as the scale and complexity of PCIe Switch devices continue to increase, their internal message paths are becoming more and more complex.

[0003] In actual application testing, due to the complexity of the internal structure of PCIe Switch devices, many types of message paths cannot be intuitively presented to testers. Testers can usually only judge whether the device functions normally by observing the final output results, but cannot understand the transmission path and processing process of the message inside the device in detail.

[0004] Therefore, there is an urgent need for a method that can effectively test the normal and abnormal message paths of PCIe Switch devices, so as to timely discover design defects before tape-out, improve test efficiency and coverage, and ensure the stability and reliability of the device. Summary of the invention

[0005] In view of this, the present invention aims to propose a testing method based on normal and abnormal messages of PCIe Switch device format, so as to at least solve one problem in the background technology.

[0006] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0007] A method for testing messages with normal and abnormal formats based on a PCIe Switch device, comprising:

[0008] A PCIe protocol analyzer is interconnected with at least two PCIe simulators, wherein a first PCIe simulator simulates an RC device and a second PCIe simulator simulates an EP device, and a virtual topology mapping of a PCIe Switch device is established based on an FPGA prototype verification system, wherein the RC is a Root Complex and the EP is an Endpoint;

[0009] Dynamically generate test messages with normal and abnormal formats according to a preset abnormal type library, wherein the abnormal type library is obtained by traversing abnormal scenarios defined in the PCIe protocol specification through a finite state machine;

[0010] Inject test packets into the PCIe Switch device, capture the packet flow of the input / output port through a protocol analyzer, and reconstruct the transmission path of the packet inside the Switch based on the timestamp synchronization mechanism and the path tag field;

[0011] According to the captured message path and content, the path coverage and exception handling response time indicators are calculated, and the message type and injection frequency of the test scenario are adjusted in real time until the preset coverage threshold is reached.

[0012] Furthermore, the construction of the FPGA prototype verification system includes:

[0013] Dynamically instrument the RTL code of the PCIe Switch device and insert path tracing probes to capture the message jump events between virtual channels and ports;

[0014] Generate engineering constraints based on coverage-driven constrained random testing, where the constraints include clock domain crossing coverage and path branch coverage;

[0015] The RTL code after the insertion is synthesized into an FPGA programmable file and burned into the FPGA chip to form a prototype verification platform that supports message path backtracing.

[0016] Furthermore, the preset exception type library includes TLP header field error, ECRC check error, and address out-of-bounds error.

[0017] Furthermore, the method for generating the exception type library includes:

[0018] Parse the PCIe protocol specification and extract the legal field value range of the TLP layer and data link layer;

[0019] The mutation test strategy based on protocol perception generates format-abnormal messages, performs bit flipping, boundary value crossing, and sequence disorder operations on legal fields to generate format-abnormal messages;

[0020] An error injection label is added to each abnormal message, where the label includes the type of error handling mechanism that is expected to be triggered by the Switch device.

[0021] Furthermore, the protocol-aware mutation test strategy generates format-abnormal messages, including:

[0022] The fields are prioritized according to the TLP header field criticality weights defined in the PCIe protocol specification. The criticality weights are calculated as follows:

[0023] = × ;

[0024] in, is the weight of the i-th field;

[0025] Perform bit flip mutation on high-weight fields, flipping the number of bits N= ×Field length;

[0026] Perform boundary value mutation on medium and low weight fields, setting the field value to the legal maximum value +1 or the legal minimum value -1;

[0027] Among them, the definition ≥0.5 is a high-weight field, defined <0.5 is a medium-low weight field.

[0028] Furthermore, the preset test scenarios include cross-level path verification:

[0029] Path test from RC to EP: Configure the Bar space attribute of the EP device to be readable and writable, and set the remapping rules of the address translation table to verify the compliance of the Switch device with address translation;

[0030] EP-to-EP path test: Inject packets with virtual function labels between EP devices to verify the switch device's support for SR-IOV virtualized paths.

[0031] Path test from EP to RC: Simulate MSI-X interrupt messages in the EP device to verify the accuracy of the Switch device's response to the priority arbitration and interrupt forwarding mechanism.

[0032] Furthermore, the calculation method of the coverage threshold includes:

[0033] Path coverage: Calculates the ratio of tested paths to total paths based on the port connection relationship of the crossbar switch inside the Switch device;

[0034] Exception handling coverage: The percentage of error handling mechanism types triggered by statistics to the types defined in the protocol specification;

[0035] Dynamic adjustment strategy: if the path coverage is lower than the first preset threshold, add a multi-hop forwarding test scenario from EP to EP; if the exception handling coverage is lower than the second preset threshold, increase the bit flip density of the mutation test;

[0036] The first preset threshold includes 90%, and the second preset threshold includes 85%.

[0037] Furthermore, the present solution discloses an electronic device, including a processor and a memory connected to the processor for storing executable instructions of the processor, wherein the processor is used to execute the above-mentioned test method for messages with normal and abnormal formats based on a PCIe Switch device.

[0038] Furthermore, the present solution discloses a server, comprising at least one processor and a memory communicatively connected to the processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the processor so that the at least one processor executes a testing method based on normal and abnormal messages in the PCIe Switch device format.

[0039] Furthermore, the present solution discloses a computer-readable storage medium storing a computer program, which, when executed by a processor, implements a method for testing messages in normal and abnormal formats based on a PCIe Switch device.

[0040] Compared with the prior art, the testing method of the PCIe Switch device-based normal and abnormal message formats according to the present invention has the following beneficial effects:

[0041] (1) The present invention discloses a method for testing messages with normal and abnormal formats based on a PCIe Switch device. Through an FPGA prototype verification system, the PCIe Switch device can be tested for messages with normal and abnormal formats before tape-out, thereby discovering design defects early and reducing risks.

[0042] (2) The present invention provides a method for testing messages with normal and abnormal formats based on a PCIe Switch device. By constructing three test scenarios covering the transmission paths of messages with normal and abnormal formats in different directions, the method can more comprehensively verify the processing functions of the PCIe Switch device with normal and abnormal formats.

[0043] (3) The present invention discloses a test method for messages with normal and abnormal formats based on a PCIe Switch device, which uses a PCIe protocol analyzer to collect and analyze messages, and can more accurately determine the behavior of the PCIe Switch device and improve test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0045] Figure 1A schematic diagram of a FPGA prototype verification system according to an embodiment of the present invention;

[0046] Figure 2 A schematic diagram of a test flow in which the simulator according to an embodiment of the present invention acts as an RC device to send a poisoned message to an EP device;

[0047] Figure 3 A schematic diagram of a test flow of using a simulator as an EP device to send a poisoned message to an EP device according to an embodiment of the present invention;

[0048] Figure 4 The figure is a schematic diagram of a test process of using a simulator as an EP device to send a poisoned message to an RC device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0050] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0051] This solution discloses a test method for normal and abnormal messages based on PCIe Switch device formats. In this embodiment, taking the test method for poisoned messages as an example, in the early stage of chip development, an effective FPGA prototype verification environment and PCIe test instruments are used to test poisoned messages, providing an effective test method:

[0052] like Figure 1 As shown in the figure, according to the RTL code designed, after the Founder verification in the UVM stage, a phased TAG file is formed for FPGA prototype verification test. Through the engineering constraints of different FPGA prototype verification platforms, the RTL code is formed into an FPGA testable bit file and burned into the FPGA prototype verification platform for testing. If it is a molded chip, it needs to be combined with the hardware board according to the design requirements to form a chip verification platform (i.e., FPGA molding board) for testing;

[0053] like Figure 2 As shown in the figure, build a test environment, use a PCIe simulator as an RC device, and use the EP device as a device that can be edited and read in the Bar space to receive messages. Connect a PCIe protocol analyzer between the Switch device and the EP device to collect the message status transmitted in the channel:

[0054] ① Enumeration process: Send Cfg messages through the configuration simulator to configure the Bus Number, Memory Base and Limit, PCI Command / status, and Bridge control of the Switch device. In this test, the simulator sends cfg messages to configure the Bus Number of the UP (Upstream Port) port of the Switch device to 0x030201, MemoryBase and Limit to 0xEF00EA00, PCI Command / status to 0x100547, and Bridgecontrol to 0x10000; the Bus Number of the DP (Downstream Port) port of the Switch device is configured to 0x030302, Memory Base and Limit to 0xEF00ED00, PCI Command / status to 0x100547, and Bridge control to 0x10000; the PCI Command / status of the EP (Endpoint) port of the Switch device is configured to 0x100547 and Bar Address to 0xEF000000, so that the space is within the address space allocation of the Switch;

[0055] ②Sending poisoned messages: Configure the simulator to send Mem type messages with the address EF000000, and enable the poison bit of the message to make it a poisoned message. The poisoned message sent to the EP device is collected by the analyzer, and the address of the constructed message is compared with the message status collected by the analyzer to confirm that the poisoned message has passed the exchange verification. This process is the sending and receiving of poisoned messages through the PCIe Switch device. The processing of the Switch message requires register reading according to different design methods;

[0056] like Figure 3 As shown in the figure, use the PCIe simulator as the EP device, and use the simulator attribute to simulate the Nvme hard disk to make it an EP as an Nvme device. Connect the PCIe protocol analyzer between the Switch device and the EP device to collect the message status transmitted in the channel:

[0057] ① Enumeration process: Complete the link by configuring the Switch device, EP and simulator devices. At this time, open the RC device to automatically complete the enumeration operation through the commercial RC. After the enumeration is completed, you can view the mounting status of the Switch and EP devices through the lspci command.

[0058] ② Send poisoned messages: Use the lspci command to view the Bar space allocation of the EP, and you can get the readable and writable address of the Bar space. Configure the simulator to send a Mem type message to the address, and enable the poison bit of the message to make the message a poisoned message. Use the analyzer to collect the poisoned message sent to the EP device, and compare the address of the constructed sending message with the message status collected by the analyzer to confirm that the poisoned message has passed the exchange verification.

[0059] like Figure 4 As shown in the figure, use the PCIe simulator as the EP device, and use the simulator attribute to simulate the Nvme hard disk to make it an EP as an Nvme device. Connect the PCIe protocol analyzer between the Switch device and the RC device to collect the message status transmitted in the channel:

[0060] ① Enumeration process: Complete the link by configuring the Switch device simulator. At this time, open the RC device to automatically complete the enumeration operation through the commercial RC. After the enumeration is completed, you can view the mounting status of the Switch and the simulator through the lspci command.

[0061] ②Sending poisoned messages: Allocate a memory address of RC through software (for example, the address is FA000000-FB000000), configure the simulator to send Mem type messages within the address range, and enable the poison bit of the message to make the message a poisoned message. Collect the poisoned messages sent to the EP device through the analyzer, and compare the address of the constructed sending message with the message status collected by the analyzer to confirm that the poisoned message passes the exchange verification.

[0062] Those of ordinary skill in the art will appreciate that the units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0063] In the several embodiments provided in the present application, it should be understood that the disclosed methods and systems can be implemented in other ways. For example, the division of the units described above is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. The above-mentioned units may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of the present invention.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and specification of the present invention.

[0065] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for testing normal and abnormal messages based on PCIe Switch device format, characterized in that: include: A PCIe protocol analyzer is interconnected with at least two PCIe simulators, wherein a first PCIe simulator simulates an RC device and a second PCIe simulator simulates an EP device, and a virtual topology mapping of a PCIe Switch device is established based on an FPGA prototype verification system, wherein the RC is a Root Complex and the EP is an Endpoint; Dynamically generate test messages with normal and abnormal formats according to a preset abnormal type library, wherein the abnormal type library is obtained by traversing abnormal scenarios defined in the PCIe protocol specification through a finite state machine; Inject test packets into the PCIe Switch device, capture the packet flow of the input / output port through a protocol analyzer, and reconstruct the transmission path of the packet inside the Switch based on the timestamp synchronization mechanism and the path tag field; Based on the captured message path and content, the path coverage and exception handling response time indicators are calculated, and the message type and injection frequency of the test scenario are adjusted in real time until the preset coverage threshold is reached.

2. A method for testing messages with normal and abnormal formats based on PCIe Switch devices according to claim 1, characterized in that: The construction of the FPGA prototype verification system includes: Dynamically instrument the RTL code of the PCIe Switch device and insert path tracing probes to capture the message jump events between virtual channels and ports; Generate engineering constraints based on coverage-driven constrained random testing, where the constraints include clock domain crossing coverage and path branch coverage; The RTL code after the insertion is synthesized into an FPGA programmable file and burned into the FPGA chip to form a prototype verification platform that supports message path backtracing.

3. A method for testing messages with normal and abnormal formats based on PCIe Switch devices according to claim 1, characterized in that: The preset exception type library includes TLP header field error, ECRC check error, and address out-of-bounds error.

4. A method for testing messages with normal and abnormal formats based on PCIe Switch devices according to claim 1, characterized in that: The method for generating the exception type library comprises: Parse the PCIe protocol specification and extract the legal field value range of the TLP layer and data link layer; The mutation test strategy based on protocol perception generates format-abnormal messages, performs bit flipping, boundary value crossing, and sequence disorder operations on legal fields to generate format-abnormal messages; An error injection label is added to each abnormal message, where the label includes the type of error handling mechanism that is expected to be triggered by the Switch device.

5. A method for testing messages with normal and abnormal formats based on PCIe Switch devices according to claim 4, characterized in that: The protocol-aware mutation test strategy generates format-abnormal messages, including: According to the TLP header field criticality weight defined in the PCIe protocol specification, the fields are prioritized. The criticality weight calculation formula is: = × ； in, is the weight of the i-th field; Perform bit flip mutation on high-weight fields, flipping the number of bits N= ×Field length; Perform boundary value mutation on medium and low weight fields, setting the field value to the legal maximum value +1 or the legal minimum value -1; Among them, the definition ≥0.5 is a high-weight field, defined <0.5 is a medium-low weight field.

6. A method for testing messages with normal and abnormal formats based on PCIe Switch devices according to claim 1, characterized in that: The preset test scenarios include cross-level path verification: Path test from RC to EP: Configure the Bar space attribute of the EP device to be readable and writable, and set the remapping rules of the address translation table to verify the compliance of the Switch device with address translation; EP-to-EP path test: Inject packets with virtual function labels between EP devices to verify the switch device's support for SR-IOV virtualized paths. Path test from EP to RC: Simulate MSI-X interrupt messages in the EP device to verify the accuracy of the Switch device's response to the priority arbitration and interrupt forwarding mechanism.

7. A method for testing messages with normal and abnormal formats based on PCIe Switch devices according to claim 1, characterized in that: The calculation method of the coverage threshold includes: Path coverage: Calculates the ratio of tested paths to total paths based on the port connection relationship of the crossbar switch inside the Switch device; Exception handling coverage: The percentage of error handling mechanism types triggered by statistics to the types defined in the protocol specification; Dynamic adjustment strategy: If the path coverage is lower than the first preset threshold, add a multi-hop forwarding test scenario from EP to EP; if the exception handling coverage is lower than the second preset threshold, increase the bit flip density of the mutation test.

8. An electronic device, comprising a processor and a memory connected to the processor for storing instructions executable by the processor, characterized in that: The processor is used to execute a test method based on normal and abnormal messages in PCIe Switch device format as described in any one of claims 1-7 above.

9. A server, characterized in that: The invention comprises at least one processor and a memory in communication connection with the processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the processor so that the at least one processor executes a test method based on normal and abnormal messages in PCIe Switch device format as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method for testing messages based on normal and abnormal formats of a PCIe Switch device according to any one of claims 1 to 7 is implemented.

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