LOFIC pixel circuit and image sensor

Abstract

The embodiment of the invention provides a LOFIC pixel circuit. The LOFIC pixel circuit comprises a photodiode, a transmission transistor, a floating diffusion node, a switch transistor, a first reset transistor, a first power supply, a first overflow charge storage capacitor, a second overflow charge storage capacitor and a charge sharing transistor, wherein the drain electrode of the switch transistor is connected with the upper electrode plate of the first overflow charge storage capacitor; the source electrode of the charge sharing transistor is connected with the upper electrode plate of the first overflow charge storage capacitor and the source electrode of the first reset transistor; the drain electrode of the charge sharing transistor is connected with the upper electrode plate of the second overflow charge storage capacitor; a lower pole plate of the first overflow charge storage capacitor and a lower pole plate of the second overflow charge storage capacitor are connected with a power supply or the ground. According to the LOFIC pixel circuit, a traditional LOFIC capacitor is divided into two parts, and dynamic range expansion can be effectively achieved through charge distribution and dynamic refreshing.

Description

Technical Field

[0001] The present application relates to the field of image sensor circuits, and in particular to a LOFIC pixel circuit and an image sensor. Background Art

[0002] Dynamic range is an important indicator to measure the performance of image sensors, which directly affects the image detail capture capability and imaging quality.

[0003] The pixel structure based on lateral overflow integration capacitor (LOFIC) can effectively collect the photogenerated charge overflowing from the photodiode (PD), so that the full well capacity (FWC) of the pixel is no longer limited by the PD, effectively expanding the dynamic range of the pixel. However, in the LOFIC pixel structure, achieving a high dynamic range requires a large LOFIC capacitor.

[0004] However, increasing the LOFIC capacitor will occupy a large amount of pixel area, making it difficult to miniaturize the pixel. Secondly, the three-dimensional capacitor structure in the pixel requires a complex multi-step process, which increases the manufacturing cost. Therefore, it is very necessary to expand the dynamic range without increasing the complex process and pixel area. Summary of the invention

[0005] The embodiments of the present application provide a LOFIC pixel circuit and an image sensor, which can effectively expand the dynamic range of pixels and thus improve pixel quality.

[0006] In a first aspect, an embodiment of the present application provides a pixel structure, the LOFIC pixel circuit comprising: a photodiode, a transfer transistor, a floating diffusion node, a switch transistor, a first reset transistor, a first power supply, a first overflow charge storage capacitor, a second overflow charge storage capacitor and a charge sharing transistor;

[0007] Among them, the anode of the photodiode is connected to the ground; the cathode of the photodiode is connected to the source of the transfer transistor; the drain of the transfer transistor is connected to the floating diffusion node and the source of the switching transistor; the drain of the switching transistor is connected to the upper plate of the first overflow charge storage capacitor; the source of the charge sharing transistor is connected to the upper plate of the first overflow charge storage capacitor and the source of the first reset transistor; the drain of the charge sharing transistor is connected to the upper plate of the second overflow charge storage capacitor; the drain of the first reset transistor is connected to the first power supply; the lower plate of the first overflow charge storage capacitor and the lower plate of the second overflow charge storage capacitor are connected to the first power supply or the ground.

[0008] This embodiment proposes a LOFIC pixel structure based on charge distribution, which divides the traditional LOFIC capacitor into two parts. The detection upper limit of the saturation signal can be effectively improved through charge distribution and dynamic refresh. By controlling the number of dynamic refreshes and the capacitance ratio of the two parts of the LOFIC capacitor, different degrees of dynamic range expansion can be achieved; the signal loss problem caused by saturation can be reduced, and the imaging quality of pixels in high-contrast scenes can be improved. In addition, the pixel circuit does not require additional capacitors, which can simplify the complexity of the pixel layout and reduce manufacturing costs.

[0009] In one possible implementation, the LOFIC pixel circuit further includes a first overflow transfer transistor and a second overflow transfer transistor;

[0010] Among them, the drain of the switching transistor is connected to the source of the first overflow transfer transistor and the source of the second overflow transfer transistor; the drain of the first overflow transfer transistor is connected to the upper plate of the first overflow charge storage capacitor; the drain of the second overflow transfer transistor is connected to the upper plate of the second overflow charge storage capacitor.

[0011] In the embodiment of the present application, by providing a first overflow transfer transistor and a second overflow transfer transistor, two split overflow charge storage capacitors are connected in parallel, thereby improving the stability of the overflow signal and enhancing the pixel quality.

[0012] In one possible implementation, the LOFIC pixel circuit further includes a direct overflow transistor; wherein the source of the DC overflow transistor is connected to the cathode of the photodiode; and the drain of the DC overflow transistor is the upper plate of the first overflow charge storage capacitor.

[0013] In an embodiment of the present application, a direct overflow channel is set to ensure that the saturated photogenerated charges in the photodiode can be directly collected by the first overflow charge storage capacitor and the second overflow charge storage capacitor node, allowing the overflow signal to be processed separately, reducing the saturated photogenerated charge loss, and obtaining higher signal quality, thereby improving pixel quality.

[0014] In one possible implementation, the LOFIC pixel circuit further includes a second reset transistor; wherein the source of the second reset transistor is connected to the upper plate of the second overflow charge storage capacitor; and the drain of the second reset transistor is connected to the first power supply.

[0015] In the embodiments of the present application, according to actual application requirements, the second overflow charge storage capacitor can be reset by additionally setting a reset operation, and the dynamic refresh mechanism and charge distribution strategy can be adjusted to obtain the corresponding pixel dynamic range, thereby providing developers with greater design freedom.

[0016] In one implementation, the dynamic range of the pixel circuit is related to the capacitance ratio, the number of dynamic refreshes and the effective exposure ratio of the first overflow charge storage capacitor; wherein the capacitance ratio represents the ratio of the second overflow charge storage capacitor to the sum of the first overflow charge storage capacitor and the second overflow charge storage capacitor; the number of dynamic refreshes represents the number of repeated exposure cycles in the entire exposure period; and the effective exposure ratio of the first overflow charge storage capacitor represents the ratio of the total exposure time to the charge collection time of the first overflow charge storage capacitor.

[0017] In the embodiments of the present application, the dynamic range can be significantly expanded without increasing the metal-insulator-metal capacitance by optimizing the parameter capacitance ratio, the dynamic refresh number and the effective exposure ratio of the first overflow charge storage capacitor.

[0018] In one implementation, the dynamic range of the LOFIC pixel circuit is negatively correlated with the value of the second overflow charge storage capacitor. Ideally, the smaller the capacitance value of CS2, the higher the expansion ratio of the final signal.

[0019] In one possible implementation, the dynamic range of the LOFIC pixel circuit is positively correlated with the number of dynamic refreshes. The more refreshes there are, the more significant the improvement in dynamic range is.

[0020] In one implementation, the dynamic range of the LOFIC pixel circuit is positively correlated with the effective exposure ratio of the first overflow charge storage capacitor. The higher the effective exposure ratio k value, the greater the improvement in the final dynamic range.

[0021] In one implementable embodiment, the LOFIC pixel circuit also includes a source follower, a row selection transistor and a second power supply; wherein the gate of the source follower is connected to the floating diffusion node; the drain of the source follower is connected to the second power supply; the source of the source follower is connected to the drain of the row selection transistor; and the source of the row selection transistor is connected to the column output bus of the LOFIC pixel circuit.

[0022] In a second aspect, an embodiment of the present application provides an image sensor, comprising: a pixel circuit as provided in the above-mentioned first aspect or any possible implementation of the first aspect.

[0023] The technical effects related to the second aspect can refer to the above-mentioned first aspect or any possible technical effects of the first aspect that can be achieved, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 It is a schematic diagram of a conventional LOFIC pixel circuit;

[0026] Figure 2 A schematic diagram of a partial working process of a LOFIC pixel circuit provided in an embodiment of the present application is shown;

[0027] Figure 3 Another schematic diagram of a LOFIC pixel circuit diagram provided by an embodiment of the present application is shown;

[0028] Figure 4 Shows Figure 3 The working timing diagram of the LOFIC pixel circuit shown in ;

[0029] Figure 5 Another schematic diagram of a LOFIC pixel circuit diagram provided by an embodiment of the present application is shown;

[0030] Figure 6 Shows Figure 5 The working timing diagram of the LOFIC pixel circuit shown in ;

[0031] Figure 7 Another schematic diagram of a LOFIC pixel circuit diagram provided by an embodiment of the present application is shown;

[0032] Figure 8 Another schematic diagram of a LOFIC pixel circuit diagram provided by an embodiment of the present application is shown;

[0033] Fig. 9A Another schematic diagram of a LOFIC pixel circuit diagram provided by an embodiment of the present application is shown;

[0034] Fig. 9B Another schematic diagram of a LOFIC pixel circuit diagram provided by an embodiment of the present application is shown;

[0035] Fig. 9C Another schematic diagram of a LOFIC pixel circuit diagram provided by an embodiment of the present application is shown;

[0036] Fig.9D Another schematic diagram of a LOFIC pixel circuit diagram provided by an embodiment of the present application is shown;

[0037] Fig.10A simulation diagram of dynamic range expansion of a LOFIC pixel circuit provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0039] In the description of this application, it should be noted that the terms "inside", "outside", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0040] It should also be noted that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0041] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0042] First, in order to facilitate understanding of the embodiments of the present application, the technical problems that need to be solved by the embodiments of the present application are analyzed in detail below.

[0043] See also Figure 1 , Figure 1 A schematic diagram of a conventional LOFIC pixel circuit is shown.

[0044] like Figure 1 As shown, the conventional LOFIC pixel circuit includes a photodiode PD, a transfer transistor TG, a floating diffusion node (FD), a switch transistor DCG, a reset transistor RST, an overflow charge storage capacitor CS, a first power supply Vddrst, a second power supply Vddsf, a source follower SF, a row selection transistor SEL, and a column output bus Vpixout. It should be noted that the overflow charge storage capacitor CS can also be referred to as a LOFIC capacitor.

[0045] Among them, the anode of the photodiode PD is connected to the ground; the cathode of the photodiode PD is connected to the source of the transfer transistor TG; the drain of the transfer transistor TG is connected to the floating diffusion node FD and the source of the switching transistor DCG; the drain of the switching transistor DCG is connected to the upper plate of the overflow charge storage capacitor Cs; the drain of the reset transistor RST is connected to the first power supply Vddrst; and the lower plate of the overflow charge storage capacitor Cs is connected to the ground.

[0046] It should be noted that in Figure 1 In the LOFIC pixel circuit shown in FIG. 1 , the floating diffusion node FD has an equivalent floating diffusion capacitance Cfd; therefore, Figure 1 In the circuit topology shown, the drain of the transfer transistor TG is connected to the floating diffusion node FD and also appears as the drain of the transfer transistor TG is also connected to the capacitance Cfd of the floating diffusion node FD.

[0047] The gate of the source follower SF is connected to the floating diffusion node FD; the drain of the source follower is connected to the second power supply Vddsf; the source of the source follower SF is connected to the drain of the row selection transistor SEL; the source of the row selection transistor SEL is connected to the column output bus Vpixout of the LOFIC pixel circuit.

[0048] Based on the conventional LOFIC pixel circuit, it can be seen that the pixel structure of the lateral overflow integrated capacitor LOFIC can effectively collect the photogenerated charge overflowing from the photodiode PD, so that the full well capacity FWC of the pixel is no longer limited by the PD, effectively expanding the dynamic range of the pixel. However, in the LOFIC pixel structure, the calculation method of the dynamic range (DR) is as follows:

[0049] DR=20*log(Ns+Nfd+Npd) / RN (1)

[0050] Ns=CS*Vadc / q (2)

[0051] Wherein, Ns is the amount of charge in the LOFIC capacitor (capacitor CS); Nfd is the amount of charge in the diffusion node capacitor (capacitor Cfd); Npd is the amount of charge in the photodiode; RN (random noise) is the random noise; CS is the LOFIC capacitor value; Vadc is the sampled value of the voltage swing of capacitor CS; and q is the basic charge of a single charge.

[0052] Based on the above dynamic range calculation, it can be seen that to achieve a high dynamic range, a larger LOFIC capacitor is required ( Figure 1In other words, the dynamic range of this design is limited by the LOFIC capacitor capacity, and the design of the capacitor is constrained by the pixel pitch and manufacturing process. However, as the pixel size continues to shrink, it becomes increasingly difficult to increase the LOFIC capacitor capacity. Traditional methods usually expand the dynamic range by increasing the area of ​​the capacitor or improving the material process, but these methods are limited by cost and technical complexity.

[0053] To this end, an embodiment of the present application provides an improved LOFIC pixel circuit. The improved LOFIC pixel circuit adopts a segmented exposure cycle design, dividing the entire exposure cycle into multiple small cycles. Figure 2 , Figure 2 A schematic diagram of part of the working process of the LOFIC pixel circuit in an embodiment of the present application is shown in FIG.

[0054] In each small cycle: Figure 2 As shown in the figure, in the first stage, the overflowed charge is transferred from FD to CS1 and CS2, and CS1 and CS2 jointly store the overflowed charge. In the second stage, CS1 and CS2 are separated by a transistor, CS1 is reset, the remaining charge in CS1 is drained and reset, and the charge in CS2 is stored.

[0055] A comprehensive readout of the total charge is then performed. At the end of the exposure cycle, the amount of charge stored in CS2 is read. The total charge in CS2 represents the total of all overflowing charge, including the charge transferred through CS1 and the charge stored in CS2.

[0056] The above scheme uses dynamic refresh technology to control the duty cycle of the period when the overflow charge is collected in multiple small cycles, and optimizes the charge distribution and reset operations to ensure efficient use of the charge storage space and further improve the dynamic range.

[0057] See also Figure 3 , Figure 3 A schematic diagram of a LOFIC pixel circuit in an embodiment of the present application is shown.

[0058] The LOFIC pixel circuit includes a photodiode PD, a transfer transistor TG, a floating diffusion node FD, a switch transistor DCG, a first reset transistor RST1, a first power supply Vddrst, a first overflow charge storage capacitor CS1, a second overflow charge storage capacitor CS2 and a charge sharing transistor CSG.

[0059] Among them, the anode of the photodiode PD is connected to the ground; the cathode of the photodiode PD is connected to the source of the transfer transistor TG; the drain of the transfer transistor TG is connected to the floating diffusion node FD and the source of the switching transistor DCG; the drain of the switching transistor DCG is connected to the upper plate of the first overflow charge storage capacitor CS1; the source of the charge sharing transistor CSG is connected to the upper plate of the first overflow charge storage capacitor Cs1 and the source of the first reset transistor RST1; the drain of the charge sharing transistor CSG is connected to the upper plate of the second overflow charge storage capacitor CS2; the drain of the first reset transistor RST1 is connected to the first power supply Vddrst; the lower plate of the first overflow charge storage capacitor CS1 and the lower plate of the second overflow charge storage capacitor CS2 are connected to the ground.

[0060] It should be noted that in Figure 3 In the LOFIC pixel circuit shown in FIG. 1 , the floating diffusion node FD has an equivalent floating diffusion capacitance Cfd; therefore, Figure 3 In the circuit topology shown, the drain of the transfer transistor TG is connected to the floating diffusion node FD, which means that the drain of the transfer transistor TG is also connected to the capacitor Cfd of the floating diffusion node FD. Other subsequent embodiments will not be described in detail.

[0061] In some embodiments, the LOFIC pixel circuit further includes a source follower SF, a row selection transistor SEL, a column output bus Vpixout and a second power supply Vddsf. The gate of the source follower SF is connected to the floating diffusion node FD; the drain of the source follower is connected to the second power supply Vddsf; the source of the source follower SF is connected to the drain of the row selection transistor SEL; and the source of the row selection transistor SEL is connected to the column output bus Vpixout of the LOFIC pixel circuit.

[0062] It should be noted that, in various embodiments of the present application, the first power source Vddrst and the second power source Vddsf may be the same power source or different power sources, which is not limited in the embodiments of the present application.

[0063] See also Figure 4 , Figure 4 Shows Figure 3 The working timing diagram of the LOFIC pixel circuit is shown.

[0064] Exposure phase: During the t1 period, the charge in CS1 is drained and the overflowing charge flows to the power supply, and the CSG gate is closed; during the t2 period, the charge is collected in CS1 and shared with CS2.

[0065] Reading phase: Before reading high gain (HR, HS) or medium gain (MS), in the t3 period, turn on the first reset transistor RST1, turn off the charge sharing transistor CSG, and reset CS1 first; in the t4 period, turn on the first reset transistor RST1 and the switching transistor DCG, turn off the charge sharing transistor CSG, reset FD and CS1, and then read other gains (MR, LS and LR).

[0066] The pixel circuit divides the LOFIC capacitor into two parts, and effectively improves the detection upper limit of the saturation signal through charge distribution and dynamic refresh. By controlling the number of dynamic refreshes and the capacitance ratio of the two parts of the LOFIC capacitor, different degrees of dynamic range expansion can be achieved on the basis of the original capacitance; at the same time, the pixel circuit does not require additional capacitance, which can simplify the complexity of the pixel layout and reduce manufacturing costs. In addition, the pixel circuit can reduce the signal loss problem caused by saturation and improve the imaging quality of the pixel in high-contrast scenes.

[0067] See also Figure 5 , Figure 5 A schematic diagram of a LOFIC pixel circuit in an embodiment of the present application is shown.

[0068] The LOFIC pixel circuit includes a photodiode PD, a transfer transistor TG, a floating diffusion node FD, a switch transistor DCG, a first reset transistor RST1, a first power supply Vddrst, a first overflow charge storage capacitor CS1, a second overflow charge storage capacitor CS2, a charge sharing transistor CSG and a direct overflow transistor OF.

[0069] Among them, the anode of the photodiode PD is connected to the ground; the cathode of the photodiode PD is connected to the source of the transfer transistor TG; the drain of the transfer transistor TG is connected to the floating diffusion node FD and the source of the switching transistor DCG; the drain of the switching transistor DCG is connected to the upper plate of the first overflow charge storage capacitor CS1; the source of the charge sharing transistor CSG is connected to the upper plate of the first overflow charge storage capacitor CS1 and the source of the first reset transistor RST1; the drain of the charge sharing transistor CSG is connected to the upper plate of the second overflow charge storage capacitor CS2; the drain of the first reset transistor RST1 is connected to the first power supply Vddrst; the lower plate of the first overflow charge storage capacitor Cs1 and the lower plate of the second overflow charge storage capacitor CS2 are connected to the ground.

[0070] The source of the DC overflow transistor OF is connected to the cathode of the photodiode PD; the drain of the DC overflow transistor OF is connected to the upper plate of the first overflow charge storage capacitor Cs1.

[0071] In some embodiments, the LOFIC pixel circuit further includes a source follower SF and a row selection transistor SEL, a column output bus Vpixout and a second power supply Vddsf. The gate of the source follower SF is connected to the floating diffusion node FD; the drain of the source follower is connected to the second power supply Vddsf; the source of the source follower SF is connected to the drain of the row selection transistor SEL; and the source of the row selection transistor SEL is connected to the column output bus Vpixout of the LOFIC pixel circuit.

[0072] See also Figure 6 , Figure 6 Shows Figure 5 The working timing diagram of the LOFIC pixel circuit is shown.

[0073] Exposure stage: During the t1' period, the charge sharing transistor CSG is turned off, the first reset transistor RST1 is turned on, the charge in the first overflow charge storage capacitor Cs1 is drained, and the overflowed charge flows to the power supply; during the t2' period, the charge sharing transistor CSG is turned on, the charge is collected in the first overflow charge storage capacitor CS1 and shared with the second overflow charge storage capacitor CS2. During the exposure period, the transmission transistor TG remains turned off, the DC overflow transistor OF maintains an intermediate level, and the charge in PD overflows to the first overflow charge storage capacitor CS1 and the second overflow charge storage capacitor CS2 through the DC overflow transistor OF.

[0074] Reading phase: first read the overflow signal (LS), then in the t3' period, turn on the first reset transistor RST1, the switch transistor DCG and the charge sharing transistor CSG, reset FD, the first overflow charge storage capacitor CS1 and the second overflow charge storage capacitor CS2. Then read the low gain LR, high gain HR, HS and medium gain MS; in the t4' period, turn on the first reset transistor RST1 and the switch transistor DCG, turn off the charge sharing transistor CSG, reset FD, and then read the medium gain MR.

[0075] This pixel circuit also divides the LOFIC capacitor into two parts, and effectively improves the detection upper limit of the saturated signal through charge distribution and dynamic refresh. By controlling the number of dynamic refreshes and the capacitance ratio of the two parts of the LOFIC capacitor, different degrees of dynamic range expansion can be achieved on the basis of the original capacitance; at the same time, the pixel circuit does not require additional capacitance, which can simplify the complexity of the pixel layout and reduce manufacturing costs. In addition, the pixel circuit can reduce the signal loss problem caused by saturation and improve the imaging quality of pixels in high-contrast scenes; and the time control of this solution is simpler. The overflow channel can be directly overflowed through the direct overflow transistor to ensure that the saturated photogenerated charge in the PD can be directly collected by CS1 and CS2, with low overflow charge loss and higher signal quality.

[0076] See also Figure 7 , Figure 7 A schematic diagram of a LOFIC pixel circuit in an embodiment of the present application is shown.

[0077] This embodiment is in Figure 3 The LOFIC pixel circuit shown or Figure 5 A second reset transistor RST2 is added on the basis of the LOFIC pixel circuit shown in the figure, wherein the drain of the second reset transistor RST2 is connected to the first power supply Vddrst.

[0078] It should be noted that Figure 7 The circuit structure of the rest of the LOFIC pixel circuit shown can be found in Figure 3 The corresponding description of the LOFIC pixel circuit in the embodiment will not be repeated in this embodiment.

[0079] The LOFIC pixel circuit can not only achieve dynamic range expansion, but also increase the flexibility of pixel timing control through an additional refresh mechanism.

[0080] See also Figure 8 , Figure 8 A schematic diagram of a LOFIC pixel circuit in an embodiment of the present application is shown.

[0081] The LOFIC pixel circuit includes a photodiode PD, a transfer transistor TG, a floating diffusion node FD, a switching transistor DCG, a first reset transistor RST1, a first power supply Vddrst, a first overflow charge storage capacitor CS1, a second overflow charge storage capacitor CS2, a charge sharing transistor CSG, a first overflow transfer transistor and a second overflow transfer transistor.

[0082] Among them, the anode of the photodiode PD is connected to the ground; the cathode of the photodiode PD is connected to the source of the transfer transistor TG; the drain of the transfer transistor TG is connected to the floating diffusion node FD and the source of the switching transistor DCG; the drain of the switching transistor DCG is connected to the source of the first overflow transfer transistor VG1 and the source of the second overflow transfer transistor VG2; the drain of the first overflow transfer transistor VG1 is connected to the upper plate of the first overflow charge storage capacitor CS1; the drain of the second overflow transfer transistor VG2 is connected to the upper plate of the second overflow charge storage capacitor CS1; the source of the charge sharing transistor CSG is connected to the upper plate of the first overflow charge storage capacitor CS1 and the source of the first reset transistor RST1; the drain of the charge sharing transistor CSG is connected to the upper plate of the second overflow charge storage capacitor CS2; the drain of the first reset transistor RST1 is connected to the first power supply Vddrst; the lower plate of the first overflow charge storage capacitor CS1 and the lower plate of the second overflow charge storage capacitor CS2 are connected to the ground.

[0083] The LOFIC pixel circuit can not only achieve dynamic range expansion and reduce manufacturing costs, but also, by providing a first overflow transfer transistor and a second overflow transfer transistor, the two split overflow charge storage capacitors are connected in parallel, thereby improving the stability of the overflow signal and enhancing the pixel quality.

[0084] See also Figures 9A-9D , Figures 9A-9D Schematic diagrams of four LOFIC pixel circuits in the embodiments of the present application are shown.

[0085] The four embodiments corresponding to 9A-9D are respectively Figure 3 , Figure 5 , Figure 7 and Figure 8 On the basis of the LOFIC pixel circuit shown in the figure, the lower plates of the first overflow charge storage capacitor CS1 and the second overflow charge storage capacitor CS2 are changed from being grounded to being connected to the first power supply Vddrst.

[0086] It should be noted that Figures 9A-9D The circuit structure of the rest of the LOFIC pixel circuit shown can be found in Figure 3 , Figure 5 , Figure 7 and Figure 8 The corresponding description of the LOFIC pixel circuit shown is not repeated in this embodiment.

[0087] The four LOFIC pixel circuits can not only achieve dynamic range expansion and reduce manufacturing costs, but also, by connecting the lower plate of the overflow storage capacitor to a power source, changing the voltage difference between the upper and lower plates of the overflow storage capacitor, optimizing noise, and thus improving the expansion of the dynamic range.

[0088] The expansion of the dynamic range is analyzed below based on the LOFIC pixel circuit provided in each embodiment of the present application.

[0089] If the number of charge distribution and dynamic refresh is set to n, the entire exposure cycle is divided into n+1 segments.

[0090] Assuming the overflow charge in the first small exposure period is Q (accumulated in CS1 and CS2), in the first cycle, the charge in CS2 will be:

[0091]

[0092] The same analysis applies to the second cycle. At the end of the second cycle, the charge in CS2 will be:

[0093]

[0094] If the total number of small cycles is n+1, and the charge in CS1 is not reset after the nth cycle, the total charge accumulated in CS1 and CS2 can be expressed as:

[0095]

[0096]

[0097] Among them, It means capacitance ratio.

[0098] Based on the above formula (3), the original total overflow charge during the entire exposure time can be expressed as:

[0099]

[0100] Therefore, the total charge number Qtot can be calculated from the measured charge number Qmeas, applying a magnification factor as follows:

[0101]

[0102] Further using the exposure ratio k of CS1, the dynamic range expansion considering only the increase in full well charge capacity (FWC) is:

[0103]

[0104] Based on the above formula (4), it can be known that the capacitance ratio m, the number of dynamic refreshes n, and the exposure ratio k of the first overflow charge storage capacitor CS1 can directly affect the dynamic range of the pixel. In other words, the dynamic range expansion of the LOFIC pixel circuit is related to the capacitance ratio m, the number of dynamic refreshes n, and the effective exposure ratio k of the first overflow charge storage capacitor CS1. Among them, the dynamic range of the LOFIC pixel circuit is negatively correlated with the capacitance value Cs2 of the second overflow charge storage capacitor CS2; the dynamic range of the LOFIC pixel circuit is positively correlated with the number of dynamic refreshes n, and the dynamic range of the LOFIC pixel circuit is positively correlated with the effective exposure ratio k of the first overflow charge storage capacitor.

[0105] See also Fig.10 , Fig.10 A simulation diagram of dynamic range expansion of a LOFIC pixel circuit provided in an embodiment of the present application is provided.

[0106] In this simulation, k is set to 2; the sum of the capacitance value Cs1 of the first overflow charge storage capacitor CS1 and the capacitance value Cs2 of the second overflow charge storage capacitor CS2 is 50 fF.

[0107] It should be noted that the simulation method is applicable to the pixel circuits mentioned in the embodiments of the present application.

[0108] Based on the simulation diagram, it can be seen that, ideally, the smaller the second overflow charge storage capacitor CS2 is, the higher the expansion ratio of the final signal is. Dynamic refresh times n: indicates the number of exposure cycles repeated in the entire exposure period. The more refresh times, the more significant the improvement in dynamic range. Effective exposure ratio k of the first overflow charge storage capacitor CS1: indicates the ratio of the total exposure time to the charge collection time of CS1. The higher the value, the greater the improvement in the final dynamic range.

[0109] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0110] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A LOFIC pixel circuit, characterized in that: The LOFIC pixel circuit includes: a photodiode, a transfer transistor, a floating diffusion node, a switch transistor, a first reset transistor, a first power supply, a first overflow charge storage capacitor, a second overflow charge storage capacitor and a charge sharing transistor; Among them, the anode of the photodiode is connected to the ground; the cathode of the photodiode is connected to the source of the transfer transistor; the drain of the transfer transistor is connected to the floating diffusion node and the source of the switching transistor; the drain of the switching transistor is connected to the upper plate of the first overflow charge storage capacitor; the source of the charge sharing transistor is connected to the upper plate of the first overflow charge storage capacitor and the source of the first reset transistor; the drain of the charge sharing transistor is connected to the upper plate of the second overflow charge storage capacitor; the drain of the first reset transistor is connected to the first power supply; the lower plate of the first overflow charge storage capacitor and the lower plate of the second overflow charge storage capacitor are connected to the first power supply or ground.

2. The LOFIC pixel circuit according to claim 1, characterized in that: The LOFIC pixel circuit further includes a first overflow transfer transistor and a second overflow transfer transistor; the drain of the switch transistor is connected to the upper plate of the first overflow charge storage capacitor, including: The drain of the switching transistor is connected to the source of the first overflow transfer transistor and the source of the second overflow transfer transistor; the drain of the first overflow transfer transistor is connected to the upper plate of the first overflow charge storage capacitor; the drain of the second overflow transfer transistor is connected to the upper plate of the second overflow charge storage capacitor.

3. The LOFIC pixel circuit according to claim 1 or 2, characterized in that: The LOFIC pixel circuit also includes a direct overflow transistor; Wherein, the source of the direct current overflow transistor is connected to the cathode of the photodiode; and the drain of the direct overflow transistor is connected to the upper plate of the first overflow charge storage capacitor.

4. The LOFIC pixel circuit according to claim 3, characterized in that: The LOFIC pixel circuit also includes a second reset transistor; The source of the second reset transistor is connected to the upper plate of the second overflow charge storage capacitor; and the drain of the second reset transistor is connected to the first power supply.

5. The LOFIC pixel circuit according to claim 4, characterized in that: The dynamic range of the pixel circuit is related to the capacitance ratio, the number of dynamic refreshes and the effective exposure ratio of the first overflow charge storage capacitor; wherein the capacitance ratio represents the ratio of the second overflow charge storage capacitor to the sum of the first overflow charge storage capacitor and the second overflow charge storage capacitor; the number of dynamic refreshes represents the number of repeated exposure cycles in the entire exposure period; and the effective exposure ratio of the first overflow charge storage capacitor represents the ratio of the total exposure time to the charge collection time of the first overflow charge storage capacitor.

6. The LOFIC pixel circuit according to claim 5, characterized in that: The dynamic range of the LOFIC pixel circuit is negatively correlated with the value of the second overflow charge storage capacitor.

7. The LOFIC pixel circuit according to claim 5, characterized in that: The dynamic range of the LOFIC pixel circuit is positively correlated with the dynamic refresh times.

8. The LOFIC pixel circuit according to claim 5, characterized in that: The dynamic range of the LOFIC pixel circuit is positively correlated with the effective exposure ratio of the first overflow charge storage capacitor.

9. The LOFIC pixel circuit according to claim 1, characterized in that: The LOFIC pixel circuit also includes a source follower, a row selection transistor and a second power supply; wherein the gate of the source follower is connected to the floating diffusion node; the drain of the source follower is connected to the second power supply; the source of the source follower is connected to the drain of the row selection transistor; and the source of the row selection transistor is connected to the column output bus of the LOFIC pixel circuit.

10. An image sensor, characterized in that: The image sensor comprises the LOFIC pixel circuit according to any one of claims 1 to 9.

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