Semiconductor structure and manufacturing method thereof, memory array, memory and electronic equipment

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof, a memory array, a memory and electronic equipment, and aims to solve the problem that the thickness of a semiconductor structure is relatively large, in the semiconductor structure, a through hole penetrates through a first cavity in a first dielectric layer, a conductive column penetrates through the through hole, a first channel layer is arranged between the conductive column and the hole wall of the through hole, and a second channel layer is arranged between the conductive column and the hole wall of the through hole; the cavity wall of the first cavity is covered with the second channel layer, and the second channel layer is in contact with the first channel layer; a gate structure and an electrode structure of the transistor structure are both in contact with the second channel layer. The thin-wall-shaped second channel layer enables the gate structure to have good control capability, gate structures do not need to be arranged on the two sides of the channel in the direction of the center line of the through hole, and the thickness of the semiconductor structure in the direction of the center line of the through hole can be reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and specifically to a semiconductor structure and a manufacturing method thereof, a storage array, a memory, and an electronic device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory. The dynamic random access memory includes a capacitor and a transistor connected to the capacitor. The transistor is used to obtain the charge stored in the capacitor and then obtain the stored data. The transistor includes a channel and a gate arranged on both sides of the channel. The gates on both sides are used to control the conduction and cutoff of the transistor. However, gates are arranged on both sides of the channel, resulting in a larger thickness of the dynamic random access memory. Summary of the invention

[0003] The embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, a storage array, a memory and an electronic device, which can reduce the thickness of the semiconductor structure.

[0004] In a first aspect, an embodiment of the present application provides a semiconductor structure, which includes: a first dielectric layer and a transistor structure, wherein a through hole penetrates a first cavity in the first dielectric layer; the transistor structure includes: a conductive column, a first channel layer, a second channel layer, a gate structure and an electrode structure, wherein the conductive column is disposed in the through hole; the first channel layer is disposed between the conductive column and the hole wall of the through hole; the second channel layer covers the cavity wall of the first cavity, and the second channel layer contacts the first channel layer; the gate structure and the electrode structure are both in contact with the second channel layer, and the conductive column and the electrode structure are each other's source and drain.

[0005] Through the above arrangement, the through hole passes through the first cavity in the first dielectric layer, the conductive column is arranged in the through hole, the first channel layer is arranged between the conductive column and the hole wall of the through hole, the second channel layer covers the cavity wall of the first cavity, and the second channel layer is in contact with the first channel layer; the gate structure and the electrode structure of the transistor structure are in contact with the second channel layer. The thin-walled second channel layer enables the gate structure to have good control ability, and there is no need to arrange the gate structure on both sides of the channel along the center line direction of the through hole, which can reduce the thickness of the semiconductor structure along the center line direction of the through hole.

[0006] In some embodiments that may include the above embodiments, the semiconductor structure also includes a second dielectric layer stacked with the first dielectric layer, a second cavity is provided in the second dielectric layer, a through hole penetrates the second cavity, a gate structure is provided in the second cavity, the gate structure contacts the second channel layer on the cavity wall of the first cavity close to the second cavity, and the gate structure is insulated and connected to the conductive column; the electrode structure is provided in the first dielectric layer, and the electrode structure contacts the second channel layer on the cavity wall of the first cavity away from the through hole.

[0007] In some embodiments that may include the above embodiments, the second channel layer covers each cavity wall of the first cavity. In this way, the area of ​​the second channel layer is larger, and the second channel layer on the second cavity wall and the third cavity wall is connected to the first channel layer, which increases the connection area between the second channel layer and the first channel layer.

[0008] In some embodiments that may include the above embodiments, the second channel layer covers the cavity wall close to the second cavity and the cavity wall away from the through hole in the first cavity. In this way, the volume of the second channel layer can be reduced, and at the same time, only the second channel layer on the cavity wall close to the second cavity contacts the first channel layer, so that the contact area between the second channel layer and the first channel layer is not too large.

[0009] In some embodiments that may include the above embodiments, the second channel layer also covers a portion of the cavity wall in the first cavity away from the second cavity, and a first gap exists between the second channel layer on the portion of the cavity wall in the first cavity away from the second cavity and the through hole. With such an arrangement, the volume of the second channel layer can be reduced to a certain extent, and at the same time, only the second channel layer on the cavity wall close to the second cavity contacts the first channel layer, so that the contact area between the second channel layer and the first channel layer is not too large.

[0010] In some embodiments that may include the above embodiments, an insulator is disposed in the first cavity, and the second channel layer is located between the insulator and the cavity wall of the first cavity. In this way, the insulator can fill the first cavity to play a supporting role, thereby improving the strength of the semiconductor structure.

[0011] In some embodiments that may include the above embodiments, the second dielectric layer may be disposed on the upper portion of the first dielectric layer, and accordingly, the gate structure contacts the upper surface of the second channel layer. Alternatively, the second dielectric layer is disposed on the lower portion of the first dielectric layer, and accordingly, the gate structure contacts the lower surface of the second channel layer.

[0012] In some embodiments that may include the above embodiments, the gate structure is disposed in the first cavity, and the second channel layer is located between the gate structure and the cavity wall of the first cavity; the electrode structure is disposed on the side of the first cavity away from the through hole, and the electrode structure contacts the second channel layer on the cavity wall of the first cavity away from the through hole. In this way, the gate structure is disposed in the first cavity, which can reduce the thickness of the transistor structure along the center line of the through hole, further reduce the thickness of the semiconductor structure along the center line of the through hole, and improve the structural compactness of the semiconductor structure; in addition, the gate structure fills the first cavity, which can play a supporting role to improve the strength of the semiconductor structure, and there is no need to set an insulator to fill the first cavity, which can reduce the mass of the semiconductor structure; at the same time, the contact area between the gate structure and the second channel layer can also be increased.

[0013] In some embodiments that may include the above embodiments, the first cavity includes a first cavity wall away from the through hole, and a second cavity wall and a third cavity wall located between the first cavity wall and the through hole, and the second cavity wall and the third cavity wall are arranged opposite to each other; the second channel layer covers the first cavity wall, the second cavity wall and the third cavity wall, and the second channel layer on the second cavity wall and the third cavity wall is in contact with the first channel layer. In this way, the area of ​​the second channel layer is larger, which increases the contact area between the second channel layer and the gate layer, and also increases the contact area between the second channel layer and the first channel layer.

[0014] In some embodiments that may include the above embodiments, the first cavity includes a first cavity wall away from the through hole, and a second cavity wall and a third cavity wall located between the first cavity wall and the through hole, and the second cavity wall and the third cavity wall are arranged opposite to each other; the second channel layer covers the first cavity wall, the second cavity wall and the third cavity wall, the second channel layer on the second cavity wall contacts the first channel layer, and there is a second gap between the second channel layer on the third cavity wall and the first channel layer. Such an arrangement can reduce the volume of the second channel layer to a certain extent, and at the same time, only the second channel layer on the second cavity wall contacts the first channel layer, so that the contact area between the second channel layer and the first channel layer is not too large.

[0015] In some embodiments that may include the above embodiments, the gate structure includes a gate body and a gate dielectric layer wrapped around the gate body, and the gate dielectric layer is in contact with the second channel layer.

[0016] In a second aspect, an embodiment of the present application further provides a storage array, comprising: a storage unit, the storage unit comprising a storage structure and the semiconductor structure as described above, the electrode structure being connected to the storage structure, and the storage structure being used to store data.

[0017] The storage array provided in the embodiments of the present application includes the semiconductor structure in any of the above embodiments, so the two can solve the same technical problems and achieve the same technical effects.

[0018] In some embodiments that may include the above embodiments, the random access memory may be a ferroelectric random access memory (FeRAM), and accordingly, the storage structure may include a ferroelectric capacitor, which stores data based on the ferroelectric effect. The ferroelectric capacitor is connected to the transistor structure to write and read data through the transistor structure.

[0019] In some embodiments that may include the above embodiments, the random access memory may be a magnetoresistive random access memory (MRAM), and accordingly, the storage structure may be a magnetic tunnel junction (MTJ), which has a tunnel magnetoresistance (TMR) effect, making it readable. The magnetic tunnel junction is connected to a transistor structure to write and read data through the transistor structure.

[0020] In some embodiments that may include the above-mentioned embodiments, the random access memory may be a phase change memory (PCRAM for short), which utilizes current to drive the crystallization and amorphization of phase change materials to store information. Accordingly, the storage structure may include a phase change unit composed of phase change materials, and the phase change unit is connected to a transistor structure to write and read data through the transistor structure.

[0021] In some embodiments that may include the above-mentioned embodiments, the random access memory may be a resistive random access memory (ReRAM), which uses the resistance change phenomenon of resistive materials to store data. Accordingly, the storage structure may include two metal plates arranged in parallel and at intervals, and a resistive layer composed of resistive materials arranged between the two metal plates. One of the two metal plates is connected to the transistor structure to write and read data through the transistor structure.

[0022] In some embodiments that may include the above embodiments, the storage structure includes a storage capacitor, the storage capacitor includes a capacitor plate and a storage medium, the storage medium is located between the electrode structure and the capacitor plate, the capacitor plate serves as one plate of the storage capacitor, and the electrode structure serves as another plate of the storage capacitor. Accordingly, the random access memory may be a dynamic random access memory (DRAM). The storage capacitor and the transistor structure share an electrode structure. In this way, the structure of the storage array can be simplified, and the volume of the storage array can also be reduced.

[0023] In some embodiments that may include the above embodiments, the capacitor plate and the storage medium are both located in the first dielectric layer. That is, the capacitor plate and the storage medium are both arranged on the side of the first cavity away from the through hole. In this way, the storage capacitor and the transistor structure are arranged in a direction perpendicular to the center line of the through hole, which can reduce the thickness of the storage array.

[0024] In some embodiments that may include the above embodiments, the electrode structure is surrounded by a receiving cavity in the first dielectric layer, the capacitor plate may include a first capacitor plate and a second capacitor plate, the first capacitor plate is located in the receiving cavity, and a storage medium is arranged between the first capacitor plate and the side wall of the receiving cavity, the second capacitor plate is located outside the receiving cavity, the second capacitor plate is located on the side of the electrode structure away from the through hole, a storage medium may also be arranged between the second capacitor plate and the electrode structure, and the first capacitor plate and the second capacitor plate are connected. In this way, the area of ​​the capacitor plate can be increased in a limited space, thereby improving the stability of the storage capacitor.

[0025] In some embodiments that may include the above embodiments, the storage unit includes a first storage unit and a second storage unit, and the first storage unit and the second storage unit are stacked along the center line of the through hole to form a storage string; the conductive pillars of the first storage unit and the second storage unit are an integrated structure. The first storage unit and the second storage unit can store and read data separately, thereby increasing the capacity of the storage array; in addition, the conductive pillars of the first storage unit and the second storage unit are an integrated structure, and when power is supplied to the conductive pillar, power can be supplied to the first storage unit and the second storage unit corresponding to the conductive pillar at the same time, which can simplify the power supply structure of the storage array and also simplify the structure of the storage array.

[0026] In some embodiments that may include the above embodiments, each storage string may include a third storage unit, a fourth storage unit, etc. in addition to the first storage unit and the second storage unit to increase the capacity of the storage string and the capacity of the storage array.

[0027] In some embodiments that may include the above embodiments, the storage string includes a first storage string and a second storage string, the first storage string and the second storage string are arranged in a direction perpendicular to the center line of the through hole, the first storage cell in the first storage string is arranged on the same layer as the first storage cell in the second storage string, and the gate structure of the first storage cell in the first storage string is connected to the gate structure of the first storage cell in the second storage string; the second storage cell in the first storage string is arranged on the same layer as the second storage cell in the second storage string, and the gate structure of the second storage cell in the first storage string is connected to the gate structure of the second storage cell in the second storage string.

[0028] Such an arrangement can further improve the capacity of the storage array; in addition, the gate structure of the first storage cell in the first storage string is connected to the gate structure of the first storage cell in the second storage string, and the gate structure of the second storage cell in the first storage string is connected to the gate structure of the second storage cell in the second storage string, which can simplify the structure of the storage array.

[0029] In some embodiments that may include the above embodiments, the gate structure of the first storage cell in the first storage string and the gate structure of the first storage cell in the second storage string are an integrated structure, and the gate structure of the second storage cell in the first storage string and the gate structure of the second storage cell in the second storage string are an integrated structure. This arrangement is simple in structure and easy to manufacture.

[0030] In some embodiments that may include the above embodiments, the gate structure of the first storage cell in the first storage string is connected to the gate structure of the first storage cell in the second storage string through the first conductive portion, and the gate structure of the second storage cell in the first storage string is connected to the gate structure of the second storage cell in the second storage string through the second conductive portion. In this way, the distance between the first storage string and the second storage string can be appropriately increased, thereby avoiding leakage.

[0031] In a third aspect, an embodiment of the present application further provides a memory, comprising: a controller and the storage array as described above, wherein the controller is connected to the storage array.

[0032] The memory provided in the embodiments of the present application includes the storage array in any of the above embodiments, so the two can solve the same technical problems and achieve the same technical effects.

[0033] In a fourth aspect, an embodiment of the present application further provides an electronic device, comprising: a circuit board and the memory as described above, wherein the memory is arranged on the circuit board.

[0034] The electronic device provided in the embodiments of the present application includes the memory in any of the above embodiments, so the two can solve the same technical problems and achieve the same technical effects.

[0035] In a fifth aspect, the present application also provides a method for manufacturing a semiconductor structure, including:

[0036] A first insulating layer, a first dielectric layer and a second dielectric layer are stacked, wherein the first dielectric layer is located between the first insulating layer and the second dielectric layer; an electrode structure is disposed in the first dielectric layer, a second cavity is disposed in the second dielectric layer, and a gate structure is disposed in the second cavity;

[0037] forming a through hole, the through hole penetrating the first insulating layer, the first dielectric layer and the second cavity;

[0038] A first cavity is formed in the first dielectric layer through a through hole, and the first cavity extends to the electrode structure; the first cavity is connected to the second cavity;

[0039] forming a second channel layer on the cavity wall of the first cavity, wherein the second channel layer is in contact with both the gate structure and the electrode structure;

[0040] Filling an insulator in the first cavity;

[0041] forming a first channel layer on the hole wall of the through hole, wherein the first channel layer is in contact with the second channel layer;

[0042] A conductive column is formed in the through hole; the conductive column and the electrode structure serve as a source and a drain to each other.

[0043] In the semiconductor structure manufactured by the above method, the through hole passes through the first cavity in the first dielectric layer, the conductive column is arranged in the through hole, the first channel layer is arranged between the conductive column and the hole wall of the through hole, the second channel layer covers the cavity wall of the first cavity, and the second channel layer is in contact with the first channel layer; the gate structure and the electrode structure of the transistor structure are in contact with the second channel layer. The thin-walled second channel layer enables the gate structure to have good control ability, and there is no need to arrange the gate structure on both sides of the channel along the center line direction of the through hole, which can reduce the thickness of the semiconductor structure along the center line direction of the through hole.

[0044] In some embodiments that may include the above embodiments, the first cavity includes a first cavity wall away from the through hole, and a second cavity wall and a third cavity wall located between the first cavity wall and the through hole, the second cavity wall and the third cavity wall are arranged opposite to each other, and the second cavity wall is in contact with the first insulating layer; before forming the first channel layer on the hole wall of the through hole, it also includes: removing at least a portion of the first insulating layer corresponding to the second cavity wall through the through hole to form a first gap to expose a portion of the second channel layer; removing the exposed portion of the second channel layer through the through hole; and forming a third insulating layer in the first gap.

[0045] Through the above arrangement, the volume of the second channel layer can be reduced. Meanwhile, only the second channel layer close to the cavity wall of the second cavity contacts the first channel layer, so that the contact area between the second channel layer and the first channel layer is not too large.

[0046] In a sixth aspect, an embodiment of the present application further provides a method for manufacturing a semiconductor structure, comprising:

[0047] A first insulating layer and a first dielectric layer are formed in a stacked manner; an electrode structure is disposed in the first dielectric layer;

[0048] forming a through hole, the through hole penetrating the first insulating layer and the first dielectric layer;

[0049] A first cavity is formed in the first dielectric layer through the through hole, and the first cavity extends to the electrode structure;

[0050] forming a second channel layer on the cavity wall of the first cavity, wherein the second channel layer is in contact with the electrode structure;

[0051] forming a gate structure in the first cavity;

[0052] forming a first channel layer on the hole wall of the through hole, wherein the first channel layer is in contact with the second channel layer;

[0053] A conductive column is formed in the through hole; the conductive column and the electrode structure serve as a source and a drain to each other.

[0054] In the semiconductor structure manufactured by the above method, the through hole passes through the first cavity in the first dielectric layer, the conductive column is arranged in the through hole, the first channel layer is arranged between the conductive column and the hole wall of the through hole, the second channel layer covers the cavity wall of the first cavity, and the second channel layer is in contact with the first channel layer; the gate structure and the electrode structure of the transistor structure are in contact with the second channel layer. The thin-walled second channel layer enables the gate structure to have good control ability, and there is no need to arrange the gate structure on both sides of the gate structure along the center line direction of the through hole, which can reduce the thickness of the semiconductor structure along the center line direction of the through hole.

[0055] In some embodiments that may include the above embodiments, forming a gate structure in the first cavity includes: forming a first gate dielectric layer on the second channel layer and the hole wall of the through hole; forming a gate body in the first cavity and the through hole; removing the through hole and part of the gate body in the first cavity; forming a second gate dielectric layer in the first cavity, the second gate dielectric layer contacting the first gate dielectric layer; removing the first gate dielectric layer located on the hole wall of the through hole. Through the above arrangement, a gate dielectric layer including a gate body can be formed to form a gate structure.

[0056] In some embodiments that may include the above embodiments, the first cavity includes a first cavity wall away from the through hole, and a second cavity wall and a third cavity wall located between the first cavity wall and the through hole, the second cavity wall and the third cavity wall are arranged opposite to each other, and the second cavity wall is in contact with the first insulating layer; after forming the second channel layer on the cavity wall of the first cavity, it also includes: removing at least a portion of the first insulating layer corresponding to the second cavity wall through the through hole to form a first gap to expose a portion of the second channel layer; removing the exposed portion of the second channel layer through the through hole; and forming a third insulating layer in the first gap.

[0057] Through the above arrangement, the volume of the second channel layer can be reduced. Meanwhile, only the second channel layer close to the cavity wall of the second cavity contacts the first channel layer, so that the contact area between the second channel layer and the first channel layer is not too large. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 1 ;

[0059] Figure 2 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 2 ;

[0060] Figure 3 It is a structural schematic diagram of a semiconductor structure in the related art;

[0061] Figure 4 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 3 ;

[0062] Figure 5 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 4 ;

[0063] Figure 6 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 5 ;

[0064] Figure 7 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 6 ;

[0065] Figure 8 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 7 ;

[0066] Fig. 9 A schematic diagram of a semiconductor structure provided in an embodiment of the present application Figure 8 ;

[0067] Fig.10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0068] Fig.11 A schematic diagram of the structure of a storage unit in a storage array provided in an embodiment of the present application Figure 1 ;

[0069] Fig.12 Schematic diagram of the structure of the storage string in the storage array provided in the embodiment of the present application Figure 1 ;

[0070] Fig.13 It is the cross-sectional view along the AA direction in 11;

[0071] Fig.14 for Fig.13 Cross-sectional view along the BB direction;

[0072] Fig.15 for Fig.13 Sectional view along CC direction;

[0073] Fig.16 Schematic diagram of the structure of the storage string in the storage array provided in the embodiment of the present application Figure 2 ;

[0074] Fig.17 A schematic diagram of the structure of a storage unit in a storage array provided in an embodiment of the present application Figure 2 ;

[0075] Fig.18 for Fig.17 Cross-sectional view along the DD direction;

[0076] Fig.19 for Fig.18 Sectional view along EE direction;

[0077] Fig. 20 for Fig.18 Sectional view along the FF axis;

[0078] Fig.21 The process of the semiconductor structure manufacturing method provided in the embodiment of the present application Figure 1 ;

[0079] Fig. 22 Schematic diagram of the structure after forming a through hole in the semiconductor structure manufacturing method provided in the embodiment of the present application Figure 1 ;

[0080] Fig.23 A schematic diagram of a structure after a first gap is formed in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0081] Fig.24 A schematic diagram of a structure after a portion of the second channel layer is removed in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0082] Fig.25 A schematic diagram of the structure after a third insulating layer is formed in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0083] Fig.26 A schematic diagram of the structure after a conductive column is formed in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0084] Fig. 27 The process of the semiconductor structure manufacturing method provided in the embodiment of the present application Figure 2 ;

[0085] Fig.28 Schematic diagram of the structure after forming a through hole in the semiconductor structure manufacturing method provided in the embodiment of the present application Figure 2 ;

[0086] Fig.29 A schematic diagram of the structure after a gate body is formed in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0087] Fig.30 A schematic diagram of the structure after removing the gate body in the through hole in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0088] Fig.31 A schematic diagram of the structure after forming a second gate dielectric layer in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0089] Fig.32 A schematic diagram of the structure after the first gate dielectric layer on the side wall of the through hole is removed in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0090] Fig.33 A schematic diagram of the structure after a conductive column is formed in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0091] Fig.34 for Fig.33 Sectional view along the GG axis;

[0092] Fig.35 A schematic diagram of a structure after a portion of the first channel layer is removed and a portion of the first gate dielectric layer of the first storage string is exposed in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0093] Fig.36 A schematic diagram of a structure after a first insulating material is formed in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0094] Fig.37 A schematic diagram of a structure after a second notch is formed in the semiconductor structure manufacturing method provided in an embodiment of the present application;

[0095] Fig.38 This is a schematic diagram of the structure after the first conductive portion is formed in the semiconductor structure manufacturing method provided in an embodiment of the present application.

[0096] Explanation of reference numerals: 1: electronic device; 2: memory; 3: circuit board; 11: first storage unit; 12: second storage unit; 20: storage array; 21: first notch; 22: first insulating material; 23: second notch; 30: controller; 100: transistor structure; 110: first dielectric layer; 111: electrode structure; 120: first cavity; 121: first cavity wall; 122: second cavity wall; 123: third cavity wall; 130: gate structure; 131: gate body; 132: gate dielectric layer; 133: first conductive portion; 134: notch; 135: insulating filler; 137: insulating ring; 138: first cavity wall; A gate dielectric layer; 139: a second gate dielectric layer; 140: a first channel layer; 150: a second channel layer; 151: a first gap; 152: a second gap; 155: an insulator; 160: a through hole; 161: a conductive column; 170: a second dielectric layer; 171: a second cavity; 180: a first insulating layer; 181: a first gap; 182: a third insulating layer; 190: a channel layer; 200: a storage capacitor; 210: a storage medium; 220: a capacitor plate; 221: a first capacitor plate; 222: a second capacitor plate; 300: a storage string; 310: a first storage string; 320: a second storage string; 400: a storage column. DETAILED DESCRIPTION

[0097] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0098] In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features.

[0099] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left", "right", "horizontal" and "vertical" are defined relative to the orientation of the components schematically placed in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they may change accordingly according to changes in the orientation of the components placed in the drawings.

[0100] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, an electrical connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0101] The embodiment of the present application provides a semiconductor structure, which can be applied to a memory, a central processing unit (CPU), etc. The semiconductor structure includes a transistor structure. When the semiconductor structure is applied to the central processing unit, the transistor structure can be used as a logic circuit of the central processing unit. When the semiconductor structure is applied to the memory, the memory may include a random access memory (RAM), which is a memory between the central processing unit and an external memory (ROM) for storing temporary data; of course, the memory may also include an external memory, which is not limited by the embodiment of the present application. The following will be introduced using the semiconductor structure applied to a random access memory as an example, but the embodiment of the present application is not limited to this.

[0102] In the above implementation, the random access memory includes a controller and at least one storage array, the controller is connected to the storage array, and the controller is used to control the storage array to store and read data. The storage array may include at least one storage unit, the storage unit includes a storage structure and the above semiconductor structure connected to the storage structure, and the transistor structure in the semiconductor structure is connected to the storage structure to store data in the storage structure or read data stored in the storage structure through the transistor structure.

[0103] Please refer to Figure 1 In the embodiment of the present application, the semiconductor structure includes a first dielectric layer 110 and a transistor structure 100. A first cavity 120 is disposed in the first dielectric layer 110, and a through hole 160 runs through the first cavity 120. Exemplarily, the center line of the through hole 160 may be substantially perpendicular to the first dielectric layer 110. The transistor structure 100 includes a conductive pillar 161, and the conductive pillar 161 is disposed in the through hole 160. Exemplarily, the material of the first dielectric layer 110 may include insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx), and the material of the conductive pillar 161 may include tungsten (W), copper (Cu), titanium nitride (TiN), etc.

[0104] In the above implementation, the transistor structure 100 further includes a first channel layer 140 and a second channel layer 150, wherein the first channel layer 140 is disposed between the conductive pillar 161 and the hole wall of the through hole 160. Exemplarily, the first channel layer 140 may cover the entire hole wall of the through hole 160, that is, the first channel layer 140 may be tubular, the first channel layer 140 is sleeved outside the conductive pillar 161, and the first channel layer 140 is located in the through hole 160. The second channel layer 150 covers the cavity wall of the first cavity 120, and the second channel layer 150 contacts the first channel layer 140, wherein the second channel layer 150 is thin-walled, and the second channel layer 150 does not fill the entire first cavity 120; one end of the second channel layer 150 facing the through hole 160 contacts the first channel layer 140 at the hole wall of the through hole 160.

[0105] In some embodiments, the materials of the first channel layer 140 and the second channel layer 150 may be the same. Accordingly, after the first channel layer 140 and the second channel layer 150 are formed, the first channel layer 140 and the second channel layer 150 form an integrated structure. Of course, the materials of the first channel layer 140 and the second channel layer 150 may also be different, and the embodiments of the present application are not limited to this. Exemplarily, the materials of the first channel layer 140 and the second channel layer 150 may include high dielectric constant (High-K) materials such as indium gallium zinc oxide (IGZO), doped polysilicon, doped single crystal silicon, and oxide semiconductors.

[0106] Continue to refer to Figure 1 In the embodiment of the present application, the transistor structure 100 further includes a gate structure 130 and an electrode structure 111, and both the gate structure 130 and the electrode structure 111 are in contact with the second channel layer 150. The gate structure 130 serves as the gate of the transistor structure 100, and the first channel layer 140 and the second channel layer 150 serve as the channel of the transistor structure 100. The conductive pillar 161 and the electrode structure 111 are the source and drain of each other. It can be understood that the conductive pillar 161 can serve as the drain of the transistor structure 100, and correspondingly, the electrode structure 111 serves as the source of the transistor structure 100; or, the electrode structure 111 serves as the drain of the transistor structure 100, and correspondingly, the conductive pillar 161 serves as the source of the transistor structure 100.

[0107] In some embodiments, the electrode structure 111 is disposed in the first dielectric layer 110, and the electrode structure 111 contacts the second channel layer 150 on the cavity wall of the first cavity 120 away from the through hole 160. The gate structure 130 can be disposed on one side of the second channel layer 150 along the center line direction of the through hole 160 (the upper side or the lower side of the second channel layer 150), and accordingly, the semiconductor structure further includes a second dielectric layer 170 stacked with the first dielectric layer 110, a second cavity 171 is disposed in the second dielectric layer 170, the through hole 160 penetrates the second cavity 171, and the gate structure 130 is disposed in the second cavity 171, and the gate structure 130 contacts the second channel layer 150 on the cavity wall of the first cavity 120 close to the second cavity 171. It can be understood that the second cavity 171 can be connected with the first cavity 120 in a direction parallel to the center line of the through hole 160, so that the second channel layer 150 at the connection point can contact the gate structure 130.

[0108] like Figure 1 As shown, the second dielectric layer 170 may be disposed on the upper portion of the first dielectric layer 110, and accordingly, the gate structure 130 is in contact with the upper surface of the second channel layer 150. Alternatively, as shown in FIG. Figure 2 As shown, the second dielectric layer 170 is disposed at the lower portion of the first dielectric layer 110 , and accordingly, the gate structure 130 is in contact with the lower surface of the second channel layer 150 .

[0109] In the semiconductor structure provided by the embodiment of the present application, the through hole 160 passes through the first cavity 120 in the first dielectric layer 110, the conductive pillar 161 is disposed in the through hole 160, the first channel layer 140 is disposed between the conductive pillar 161 and the hole wall of the through hole 160, the second channel layer 150 covers the cavity wall of the first cavity 120, and the second channel layer 150 is in contact with the first channel layer 140; the gate structure 130 and the electrode structure 111 of the transistor structure 100 are both in contact with the second channel layer 150. The thin-walled second channel layer 150 enables the gate structure 130 to have good control capability, and there is no need to dispose the gate structure 130 on both sides of the channel along the center line direction of the through hole 160, so that the thickness of the semiconductor structure along the center line direction of the through hole 160 can be reduced.

[0110] like Figure 3As shown, in the related art, the channel layer 190 is in a block shape, and the gate structure 130 is provided on the upper and lower surfaces of the channel layer 190. The through hole 160 passes through the channel layer 190 and the two gate structures 130. The conductive column 161 is penetrated in the through hole 160, and the conductive column 161 is insulated and connected to the gate structure 130, and part of the conductive column 161 is in contact with the channel layer 190. The side of the channel layer 190 away from the through hole 160 is in contact with the electrode structure 111. Among them, the electrode structure 111 can be used as the source of the transistor structure, the conductive column 161 is used as the drain of the transistor structure, the channel layer 190 is used as the channel of the transistor structure, and the gate structure 130 is used as the gate of the transistor structure. During operation, the conduction or cutoff of the transistor structure is simultaneously controlled by the two gate structures 130 to ensure sufficient control capability. In comparison, in the embodiment of the present application, Figure 1 As shown, the second channel layer 150 is thin-walled, and the second channel layer 150 covers the cavity wall of the first cavity 120. The second channel layer 150 does not fill the first cavity 120. Due to the thin-walled second channel layer 150, the gate structure 130 has good control ability, and there is no need to set the gate structure 130 on both sides of the channel along the center line direction of the through hole 160, which can reduce the thickness of the semiconductor structure along the center line direction of the through hole 160.

[0111] Please refer to Figure 4 In some implementations, the second channel layer 150 may cover each cavity wall of the first cavity 120. Exemplarily, the first cavity 120 may include a first cavity wall 121 away from the through hole 160, and a second cavity wall 122 and a third cavity wall 123 located between the first cavity wall 121 and the through hole 160, the second cavity wall 122 and the second cavity wall 122 are arranged opposite to and spaced apart, and the second channel layer 150 covers the first cavity wall 121, the second cavity wall 122 and the third cavity wall 123. In this way, the area of ​​the second channel layer 150 is large, and the second channel layer 150 on the second cavity wall 122 and the third cavity wall 123 are connected to the first channel layer 140, thereby increasing the connection area between the second channel layer 150 and the first channel layer 140.

[0112] like Figure 5As shown, in other implementations, the second channel layer 150 covers the cavity wall near the second cavity 171 and the cavity wall away from the through hole 160 in the first cavity 120; wherein the second channel layer 150 on the cavity wall away from the through hole 160 contacts the electrode structure 111, and the second channel layer 150 on the cavity wall near the second cavity 171 contacts both the gate structure 130 and the first channel layer 140. In this way, the volume of the second channel layer 150 can be reduced, and at the same time, only the second channel layer 150 on the cavity wall near the second cavity 171 contacts the first channel layer 140, so that the contact area between the second channel layer 150 and the first channel layer 140 is not too large.

[0113] Please refer to Figure 6 and Figure 7 In the implementation mode in which the second channel layer 150 covers the cavity wall of the first cavity 120 close to the second cavity 171 and the cavity wall far from the through hole 160, the second channel layer 150 also covers the part of the cavity wall of the first cavity 120 far from the second cavity 171, and there is a first gap 151 between the second channel layer 150 on the part of the cavity wall of the first cavity 120 far from the second cavity 171 and the through hole 160. Such a configuration can reduce the volume of the second channel layer 150 to a certain extent, and at the same time, only the second channel layer 150 on the cavity wall close to the second cavity 171 contacts the first channel layer 140, so that the contact area between the second channel layer 150 and the first channel layer 140 is not too large.

[0114] In the above embodiment, an insulator 155 is disposed in the first cavity 120, and the second channel layer 150 is located between the insulator 155 and the cavity wall of the first cavity 120. In this way, the insulator 155 can fill the first cavity 120 to play a supporting role, thereby improving the strength of the semiconductor structure. Exemplarily, the material of the insulator 155 may include silicon oxide, silicon nitride, silicon oxynitride, etc., which is not limited in the embodiment of the present application.

[0115] Please refer to Figure 8In other embodiments, the electrode structure 111 is disposed in the first dielectric layer 110, and the electrode structure 111 contacts the second channel layer 150 on the cavity wall (first cavity wall 121) on the side of the first cavity 120 away from the through hole 160. The gate structure 130 can be disposed in the first cavity 120, and accordingly, the second channel layer 150 is located between the gate structure 130 and the cavity wall of the first cavity 120, that is, the gate structure 130 contacts the surface of the second channel layer 150 facing the inside of the first cavity 120. In this way, the gate structure 130 is disposed in the first cavity 120, which can reduce the thickness of the transistor structure 100 along the center line direction of the through hole 160, further reduce the thickness of the semiconductor structure along the center line direction of the through hole 160, and also improve the structural compactness of the semiconductor structure; in addition, the gate structure 130 fills the first cavity 120, which can play a supporting role to improve the strength of the semiconductor structure, and there is no need to provide an insulator 155 (such as a dielectric) filling the first cavity 120. Figure 1 As shown), the mass of the semiconductor structure can be reduced.

[0116] Continue to refer to Figure 8 In some implementations, the first cavity 120 includes a first cavity wall 121 away from the through hole 160, and a second cavity wall 122 and a third cavity wall 123 located between the first cavity wall 121 and the through hole 160, the second cavity wall 122 and the third cavity wall 123 are arranged opposite to each other and spaced apart, the second channel layer 150 covers the first cavity wall 121, the second cavity wall 122 and the third cavity wall 123, and the second channel layer 150 on the second cavity wall 122 and the third cavity wall 123 are in contact with the first channel layer 140. In this way, the area of ​​the second channel layer 150 is large, which increases the contact area between the second channel layer 150 and the gate layer, and also increases the contact area between the second channel layer 150 and the first channel layer 140.

[0117] Please refer to Fig. 9 In other implementations, the first cavity 120 includes a first cavity wall 121 away from the through hole 160, and a second cavity wall 122 and a third cavity wall 123 located between the first cavity wall 121 and the through hole 160, the second cavity wall 122 and the third cavity wall 123 are arranged opposite to each other and spaced apart, the second channel layer 150 covers the first cavity wall 121, the second cavity wall 122 and the third cavity wall 123, the second channel layer 150 on the second cavity wall 122 contacts the first channel layer 140, and a second gap 152 is provided between the second channel layer 150 on the third cavity wall 123 and the first channel layer 140. Such an arrangement can reduce the volume of the second channel layer 150 to a certain extent, and at the same time, only the second channel layer 150 on the second cavity wall 122 contacts the first channel layer 140, so that the contact area between the second channel layer 150 and the first channel layer 140 is not too large.

[0118] Continue to refer to Figure 1 and Figure 8 In the embodiment of the present application, the gate structure 130 may include a gate body 131 and a gate dielectric layer 132 wrapped on the gate body 131, and the gate dielectric layer 132 is in contact with the second channel layer 150. Exemplarily, the material of the gate body 131 may include tungsten (W), copper (Cu), titanium nitride (TiN), etc., and the material of the gate dielectric layer 132 may include hafnium oxide (HfOx), zirconium oxide (ZrOx), silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide (AlOx), hafnium oxide zirconium (HZOx), etc. The embodiment of the present application does not limit the materials of the gate body 131 and the gate dielectric layer 132.

[0119] Please refer to Fig.10 The embodiment of the present application also provides an electronic device 1, which may include a mobile phone, a computer, a tablet computer, a smart bracelet, a smart watch, etc. The embodiment of the present application does not limit the electronic device 1. In the embodiment of the present application, the electronic device 1 includes a circuit board 3 and a memory 2 and a central processing unit (CPU) disposed on the circuit board 3. The memory 2 is used to store data, and the central processing unit is used to control the electronic device 1.

[0120] In some embodiments, the memory 2 may include a random access memory (Random Access Memory, RAM for short), which is a memory between the central processing unit and an external memory (Read-Only Memory, ROM for short) for storing temporary data; of course, the memory 2 may also include an external memory, which is not limited in the embodiments of the present application.

[0121] In the embodiment of the present application, the memory 2 includes a controller 30 and at least one storage array 20 , and the controller 30 is connected to the storage array 20 so as to control the storage array 20 to read and write data through the controller 30 .

[0122] In the above implementation, the memory array 20 includes at least one memory cell, the memory cell includes a memory structure and the semiconductor structure in the above embodiment, the transistor structure 100 (such as Figure 4 The electrode structure 111 (shown) is connected to the storage structure to store data in the storage structure or read data stored in the storage structure through the transistor structure 100.

[0123] It is understandable that random access memory can be divided into multiple categories according to the storage principle of the storage structure:

[0124] Please refer to Fig.11 In some embodiments, the random access memory may be a dynamic random access memory (DRAM). Accordingly, the storage structure may include a storage capacitor 200, which is connected to the transistor structure 100, and the storage capacitor 200 is used to store data. Exemplarily, when the storage capacitor 200 has a high level, data "1" may be stored, and correspondingly, when the storage capacitor 200 has a low level, data "0" may be stored; or, when the storage capacitor 200 has a high level, data "0" may be stored, and correspondingly, when the storage capacitor 200 has a low level, data "1" may be stored. When reading or writing data, the transistor structure 100 connected to the storage capacitor 200 may be turned on, and then the data of the storage capacitor 200 may be read or written through an external circuit.

[0125] In some embodiments, the random access memory may be a ferroelectric random access memory (FeRAM), and accordingly, the storage structure may include a ferroelectric capacitor, which stores data based on the ferroelectric effect. Figure 1 ) are connected to perform writing and reading of data through the transistor structure 100.

[0126] In some embodiments, the random access memory may be a magnetoresistive random access memory (MRAM), and the storage structure may be a magnetic tunnel junction (MTJ). The magnetic tunnel junction has a tunnel magnetoresistance (TMR) effect, which makes it readable. The magnetic tunnel junction and the transistor structure 100 (such as Figure 1 ) are connected to perform writing and reading of data through the transistor structure 100.

[0127] In some embodiments, the random access memory may be a phase change memory (PCRAM for short). The PCRAM uses current to drive the crystallization and amorphization of a phase change material to store information. Accordingly, the storage structure may include a phase change unit composed of a phase change material. The phase change unit and the transistor structure 100 (such as Figure 1 ) are connected to perform writing and reading of data through the transistor structure 100.

[0128] In some embodiments, the random access memory may be a resistive random access memory (ReRAM), which uses the resistance change phenomenon of a resistive material to store data. Accordingly, the storage structure may include two metal plates arranged in parallel and spaced apart, and a resistive layer composed of a resistive material arranged between the two metal plates. One of the two metal plates is connected to the transistor structure 100 (such as Figure 1 ) are connected to perform writing and reading of data through the transistor structure 100.

[0129] In the embodiments of the present application, a random access memory is taken as a dynamic random access memory (DRAM) as an example for introduction. It is understandable that the embodiments of the present application are not limited to this.

[0130] Continue to refer to Fig.11 In some implementations, the storage capacitor 200 includes a capacitor plate 220 and a storage medium 210, and the storage medium 210 is located between the electrode structure 111 and the capacitor plate 220, wherein the capacitor plate 220 serves as one plate of the storage capacitor 200, and the electrode structure 111 serves as the other plate of the storage capacitor 200, that is, the storage capacitor 200 and the transistor structure 100 share the electrode structure 111. Such a configuration can simplify the structure of the storage array 20 and also reduce the volume of the storage array 20. It can be understood that Fig.11 The random access memory is only shown as a 1T1C structure. In the embodiment of the present application, the storage unit of the random access memory may include multiple transistor structures and multiple capacitors, which is not limited in the embodiment of the present application.

[0131] Exemplarily, the material of the capacitor plate 220 may include tungsten (W), copper (Cu), titanium nitride (TiN), etc. The material of the capacitor plate 220 may be the same as or different from the material of the electrode structure 111. The material of the storage medium 210 may also include zirconium oxide (ZrOx), hafnium oxide (HfOx), hafnium zirconium oxide (ZrHfOx), aluminum zirconium oxide (ZrAlOx), aluminum oxide (AlOx) and other materials and their dopants or stacks.

[0132] In some embodiments, the conductive pillar 161 can be used as a bit line or connected to a word line, the gate structure 130 can be used as a word line or connected to a word line, and the capacitor plates 220 in multiple memory cells are connected to simplify the circuit structure.

[0133] Continue to refer to Fig.11In the above implementation, the capacitor plate 220 and the storage medium 210 can be both disposed in the first dielectric layer 110, that is, the capacitor plate 220 and the storage medium 210 are both disposed on the side of the first cavity 120 away from the through hole 160. In this way, the storage capacitor 200 and the transistor structure 100 are disposed in a direction perpendicular to the center line of the through hole 160, which can reduce the thickness of the storage array 20.

[0134] In some embodiments, the electrode structure 111 is surrounded by a receiving cavity in the first dielectric layer 110, and the capacitor plate 220 may include a first capacitor plate 221 and a second capacitor plate 222, the first capacitor plate 221 is located in the receiving cavity, and a storage medium 210 is arranged between the first capacitor plate 221 and the side wall of the receiving cavity, the second capacitor plate 220 is located outside the receiving cavity, the second capacitor plate 222 is located on the side of the electrode structure 111 away from the through hole 160, and a storage medium 210 may also be arranged between the second capacitor plate 222 and the electrode structure 111, and the first capacitor plate 221 and the second capacitor plate 222 are connected. In this way, the area of ​​the capacitor plate 220 can be increased in a limited space, thereby improving the stability of the storage capacitor 200.

[0135] Please refer to Fig.12 In the embodiment of the present application, the storage unit includes a first storage unit 11 and a second storage unit 12, and the first storage unit 11 and the second storage unit 12 are stacked along the center line of the through hole 160 to form a storage string 300; the conductive pillars 161 of the first storage unit 11 and the second storage unit 12 are an integrated structure. The first storage unit 11 and the second storage unit 12 can store and read data separately, which improves the capacity of the storage array 20; in addition, the conductive pillars 161 of the first storage unit 11 and the second storage unit 12 are an integrated structure, when power is supplied to the conductive pillar 161, power can be supplied to the first storage unit 11 and the second storage unit 12 corresponding to the conductive pillar 161 at the same time, which can simplify the power supply structure of the storage array 20, and also simplify the structure of the storage array 20.

[0136] It is understandable that each storage string 300 may include a third storage unit, a fourth storage unit, etc. in addition to the first storage unit 11 and the second storage unit 12 to increase the capacity of the storage string 300 and the capacity of the storage array 20 .

[0137] In the above implementation, the storage array 20 (such as Fig.10 and Fig.12160 ) further includes a first insulating layer 180, which is stacked and arranged between the first storage unit 11 and the second storage unit 12, so as to achieve insulation between the first storage unit 11 and the second storage unit 12 through the first insulating layer 180. Exemplarily, the material of the first insulating layer 180 may include silicon oxide, silicon nitride, etc. It can be understood that the first insulating layer 180 is also provided at the top and bottom of the storage array along the center line direction of the through hole 160 to achieve insulation between the storage string 300 and other external devices.

[0138] Please refer to Fig.13 and Fig.14 In some embodiments, the storage string 300 includes a first storage string 310 and a second storage string 320, and the first storage string 310 and the second storage string 320 are arranged along a direction perpendicular to the center line of the through hole 160 ( Fig.13 The first storage unit 11 (as shown in the vertical direction) in the first storage string 310 is arranged Fig.12 The first storage cell 11 in the first storage string 310 is arranged in the same layer as the first storage cell 11 in the second storage string 320, and the gate structure 130 of the first storage cell 11 in the first storage string 310 is connected to the gate structure 130 of the first storage cell 11 in the second storage string 320; the second storage cell 12 in the first storage string 310 is arranged in the same layer as the second storage cell 12 in the second storage string 320, and the gate structure 130 of the second storage cell 12 in the first storage string 310 is connected to the gate structure 130 of the second storage cell 12 in the second storage string 320. Such an arrangement can further increase the capacity of the storage array; in addition, the gate structure 130 of the first storage cell 11 in the first storage string 310 is connected to the gate structure 130 of the first storage cell 11 in the second storage string 320, and the gate structure 130 of the second storage cell 12 in the first storage string 310 is connected to the gate structure 130 of the second storage cell 12 in the second storage string 320, which can simplify the structure of the storage array.

[0139] In some implementations, the transistor structure 100 may include an insulating ring 137, the gate structure 130 may be ring-shaped, and the gate structure 130 is arranged around the conductive column 161. In order to achieve insulation between the gate structure 130 and the conductive column 161, the insulating ring 137 may be arranged between the gate body 131 of the gate structure 130 and the first channel layer 140. The material of the insulating ring 137 may include silicon oxide, silicon nitride, etc.

[0140] Continue to refer to Fig.13 and Fig.14In some embodiments, the gate structure 130 of the first storage cell 11 in the first storage string 310 and the gate structure 130 of the first storage cell 11 in the second storage string 320 are an integrated structure, and the gate structure 130 of the second storage cell 12 in the first storage string 310 and the gate structure 130 of the second storage cell 12 in the second storage string 320 are an integrated structure. This arrangement is simple in structure and easy to manufacture.

[0141] The distance between the center line of the through hole 160 of the first storage string 310 and the center line of the through hole 160 of the second storage string 320 can be smaller than the outer diameter of the gate structure 130 to increase the connection area of ​​the gate structure 130 of the first storage cell 11 in the first storage string 310 and the gate structure 130 of the first storage cell 11 in the second storage string 320, and at the same time increase the connection area of ​​the gate structure 130 of the second storage cell 12 in the first storage string 310 and the gate structure 130 of the second storage cell 12 in the second storage string 320 to reduce the connection resistance.

[0142] It can be understood that along the first direction perpendicular to the through hole 160 ( Fig.13 The storage string 300 includes the first storage string 310 and the second storage string 320, and may further include a third storage string, a fourth storage string, etc., to form a storage column 400. Fig.13 and Fig.15 In some embodiments, the memory array 20 includes a plurality of memory columns 400, and the plurality of memory columns 400 are arranged along a second direction ( Fig.13 The gate structures 130 disposed in the same layer in adjacent storage columns 400 may be disposed at intervals. Such an arrangement may further increase the capacity of the storage array.

[0143] Please refer to Fig.16 In an implementation in which the gate structure 130 is located in the first cavity 120, the storage unit includes a first storage unit 11 and a second storage unit 12, and the first storage unit 11 and the second storage unit 12 are stacked along the center line of the through hole 160 to form a storage string 300; the conductive pillars 161 of the first storage unit 11 and the second storage unit 12 are an integrated structure.

[0144] Please refer to Fig.17 and Fig.18In some embodiments, the gate structure 130 of the first storage cell 11 in the first storage string 310 is connected to the gate structure 130 of the first storage cell 11 in the second storage string 320 through the first conductive portion 133, and the gate structure 130 of the second storage cell 12 in the first storage string 310 is connected to the gate structure 130 of the second storage cell 12 in the second storage string 320 through the second conductive portion. In this way, the distance between the first storage string 310 and the second storage string 320 can be appropriately increased, thereby avoiding leakage.

[0145] The distance between the center line of the through hole 160 of the first storage string 310 and the center line of the through hole 160 of the second storage string 320 is greater than the outer diameter of the gate structure 130. The first conductive portion 133 is disposed between the gate structure 130 of the first storage unit 11 in the first storage and the gate structure 130 of the first storage unit 11 in the second storage string 320, and is connected to both gate structures 130. Similarly, the second conductive portion is disposed between the gate structure 130 of the second storage unit 12 in the first storage and the gate structure 130 of the second storage unit 12 in the second storage string 320, and is connected to both gate structures 130.

[0146] Please refer to Figure 17-Figure 19 In the implementation mode where the gate structure 130 is located in the first cavity 120, a gap 134 is provided in the second channel layer 150 and the gate dielectric layer 132 at a position corresponding to the first conductive portion 133, and the gap 134 is filled with an insulating filler 135 to achieve isolation between the second channel layer 150. Exemplarily, the material of the insulating filler 135 may include silicon oxide, silicon nitride, and the like.

[0147] It can be understood that along the first direction perpendicular to the through hole 160 ( Fig.18 The storage string (in the vertical direction shown in FIG. 1 ) may include a third storage string, a fourth storage string, etc. in addition to the first storage string 310 and the second storage string 320 to form a storage column 400. Fig.18 and Fig. 20 As shown, in some embodiments, the storage array 20 includes a plurality of storage columns 400, and the plurality of storage columns 400 are arranged along a second direction ( Fig.18 The gate structures 130 disposed in the same layer in adjacent storage columns 400 may be disposed at intervals. Such an arrangement may further increase the capacity of the storage array 20.

[0148] The present application also provides a method for manufacturing a semiconductor structure, which is used to manufacture the semiconductor structure in the above embodiment. Fig.21 As shown, the semiconductor structure manufacturing method includes:

[0149] S101: forming a first insulating layer, a first dielectric layer and a second dielectric layer in a stacked manner, wherein the first dielectric layer is located between the first insulating layer and the second dielectric layer; an electrode structure is disposed in the first dielectric layer, a second cavity is disposed in the second dielectric layer, and a gate structure is disposed in the second cavity.

[0150] Please refer to Fig. 22 , illustratively, a first insulating layer 180, a first dielectric layer 110, and a second dielectric layer 170 may be formed in a stacked manner, and then an electrode structure 111 is formed in the first dielectric layer 110, and a gate structure 130 is formed in the second dielectric layer 170. It is understood that in the implementation of the semiconductor structure applied to a dynamic random access memory, before or after the electrode structure 111 is formed, a storage capacitor 200 may be formed in the first dielectric layer 110, and the electrode structure 111 is connected to the storage capacitor 200; wherein the storage capacitor 200 is used to store data.

[0151] In some embodiments, there may be two first insulating layers 180 , one first insulating layer 180 is disposed on a side of the first dielectric layer 110 away from the second dielectric layer 170 , and the other first insulating layer 180 is disposed on a side of the second dielectric layer 170 away from the first dielectric layer 110 .

[0152] After forming the first insulating layer 180, the first dielectric layer 110 and the second dielectric layer 170, continue to refer to Fig.21 , the semiconductor structure manufacturing method further includes:

[0153] S102: forming a through hole, wherein the through hole penetrates the first insulating layer, the first dielectric layer and the second cavity.

[0154] Continue to refer to Fig. 22 For example, the through hole 160 can be formed by dry etching, wet etching, etc. The embodiment of the present application does not limit the formation method of the through hole 160.

[0155] After forming the through hole 160, continue to refer to Fig.21 , the semiconductor structure manufacturing method further includes:

[0156] S103: forming a first cavity in the first dielectric layer through a through hole, wherein the first cavity extends to the electrode structure; and the first cavity is connected to the second cavity.

[0157] Please refer to Fig.23 For example, a portion of the first dielectric layer 110 may be removed by etching to form a first cavity 120 in the first dielectric layer 110, wherein the electrode structure 111 and the gate structure 130 may serve as an etching stop layer to facilitate controlling the etching depth.

[0158] After forming the first cavity 120, continue to refer to Fig.21 , the semiconductor structure manufacturing method further includes:

[0159] S104: forming a second channel layer on the cavity wall of the first cavity, wherein the second channel layer is in contact with both the gate structure and the electrode structure.

[0160] Continue to refer to Fig.23 For example, the second channel layer 150 may be formed by deposition, evaporation, etc., so that the second channel layer 150 only covers the cavity wall of the first cavity 120 , and the second channel layer 150 does not fill the first cavity 120 .

[0161] After forming the second channel layer 150, continue to refer to Fig.21 , the semiconductor structure manufacturing method further includes:

[0162] S105: Filling an insulator in the first cavity.

[0163] Continue to refer to Fig.23 It can be understood that the second channel layer 150 is located between the insulator 155 and the cavity wall of the first cavity 120, and the insulator 155 can play a supporting role to improve the strength of the semiconductor structure.

[0164] After forming the insulator 155, continue to refer to Fig.21 , the semiconductor structure manufacturing method further includes:

[0165] S106: forming a first channel layer on the hole wall of the through hole, wherein the first channel layer is in contact with the second channel layer.

[0166] like Fig.26 As shown, illustratively, the first channel layer 140 can be formed by deposition or evaporation in equal parts, and the first channel layer 140 covers the hole wall of the through hole 160 so that the end of the second channel layer 150 close to the through hole 160 is connected to the first channel layer 140 .

[0167] After forming the first channel layer 140, continue to refer to Fig.21 , the semiconductor structure manufacturing method further includes:

[0168] S107: forming a conductive column in the through hole.

[0169] like Fig.26 As shown, illustratively, the conductive pillar 161 may be formed by evaporation or deposition, and the conductive pillar 161 fills the through hole 160 .

[0170] In the above implementation, the gate structure 130 serves as the gate of the transistor structure 100, and the second channel structure serves as the channel of the transistor structure 100. The conductive pillar 161 and the electrode structure 111 are mutually the source and the drain. It can be understood that the conductive pillar 161 can serve as the drain of the transistor structure 100, and correspondingly, the electrode structure 111 serves as the source of the transistor structure 100; or, the electrode structure 111 serves as the drain of the transistor structure 100, and correspondingly, the conductive pillar 161 serves as the source of the transistor structure 100.

[0171] In some implementations, the through hole 160 may penetrate the gate structure 130, and the gate structure 130 includes a gate body 131 and a gate dielectric layer 132 wrapped around the gate body 131; accordingly, Fig.24 As shown, after forming the through hole 160 , part of the gate body 131 can be removed through the through hole 160 to form a groove, and then an insulating ring 137 is formed in the groove to achieve insulation between the gate body 131 and the conductive pillar 161 through the insulating ring 137 .

[0172] In the semiconductor structure manufactured by the semiconductor structure manufacturing method provided in the embodiment of the present application, the through hole 160 penetrates the first cavity 120 in the first dielectric layer 110, the conductive column 161 is arranged in the through hole 160, the first channel layer 140 is arranged between the conductive column 161 and the hole wall of the through hole 160, the second channel layer 150 covers the cavity wall of the first cavity 120, and the second channel layer 150 is in contact with the first channel layer 140; the gate structure 130 and the electrode structure 111 of the transistor structure are both in contact with the second channel layer 150. The thin-walled second channel layer 150 enables the gate structure 130 to have good control ability, and there is no need to arrange the gate structure 130 on both sides of the gate structure 130 along the center line direction of the through hole 160, so that the thickness of the semiconductor structure along the center line direction of the through hole 160 can be reduced.

[0173] Continue to refer to Fig. 22 and Fig.23 In some embodiments, the first cavity 120 includes a first cavity wall 121 away from the through hole 160, and a second cavity wall 122 and a third cavity wall 123 located between the first cavity wall 121 and the through hole 160, the second cavity wall 122 and the third cavity wall 123 are arranged opposite to each other, and the second cavity wall 122 is in contact with the first insulating layer 180. Accordingly, before forming the first channel layer 140 on the hole wall of the through hole 160, the method further includes: removing at least a portion of the first insulating layer 180 corresponding to the second cavity wall 122 through the through hole 160 to form a first slit 181 to expose a portion of the second channel layer 150; and then, as shown in FIG. Fig.24 As shown, the exposed portion of the second channel layer 150 is removed through the through hole 160 , that is, at least a portion of the second channel layer 150 on the second cavity wall 122 is removed.

[0174] like Fig.25 As shown, after removing part of the second channel layer 150, a third insulating layer 182 is formed in the first gap 181. The third insulating layer 182 fills the first gap 181 and can play a supporting role. Exemplarily, the material of the third insulating layer 182 may include silicon oxide, silicon nitride, etc.

[0175] Through the above arrangement, compared with the second channel layer 150 covering the cavity walls in the first cavity 120, the volume of the second channel layer 150 can be reduced. At the same time, only the second channel layer 150 on the cavity wall close to the second cavity 171 is in contact with the first channel layer 140, so that the contact area between the second channel layer 150 and the first channel layer 140 is not too large.

[0176] It can be understood that all the first insulating layers 180 corresponding to the second cavity wall 122 can be removed through the through hole 160 to form a first gap 181 to expose the second channel layer 150 corresponding to the second cavity wall 122; then, the exposed second channel layer 150 is removed through the through hole 160, that is, all the second channel layers 150 on the second cavity wall 122 are removed. Of course, all the first insulating layers 180 corresponding to part of the second cavity wall 122 can also be removed through the through hole 160 to form a first gap 181 to expose part of the second channel layer 150 corresponding to the second cavity wall 122; then, the exposed second channel layer 150 is removed through the through hole 160, that is, part of the second channel layer 150 on the second cavity wall 122 is removed, and there is a first gap 151 (such as Figure 6 shown).

[0177] The present application also provides a method for manufacturing a semiconductor structure, which is used to manufacture the semiconductor structure in the above embodiment. Fig. 27 , the semiconductor structure manufacturing method comprises:

[0178] S201: forming a first insulating layer and a first dielectric layer in a stacked manner; an electrode structure is disposed in the first dielectric layer.

[0179] Please refer to Fig.28 , illustratively, the first insulating layer 180 and the first dielectric layer 110 may be stacked, and then the electrode structure 111 may be formed in the first dielectric layer 110. It is understood that in the implementation of the semiconductor structure being applied to a dynamic random access memory, before or after the electrode structure 111 is formed, a storage capacitor 200 is formed, and the electrode structure 111 is connected to the storage capacitor 200; wherein the storage capacitor 200 is used to store data.

[0180] In some embodiments, there may be two first insulating layers 180 , one first insulating layer 180 is disposed on one surface of the first dielectric layer 110 , and the other first insulating layer 180 is disposed on the other surface of the first dielectric layer 110 .

[0181] After forming the first insulating layer 180 and the first dielectric layer 110, continue to refer to Fig. 27 , the semiconductor structure manufacturing method further includes:

[0182] S202: forming a through hole, wherein the through hole penetrates the first insulating layer and the first dielectric layer.

[0183] Continue to refer to Fig.28 For example, the through hole 160 can be formed by dry etching, wet etching, etc. The embodiment of the present application does not limit the formation method of the through hole 160.

[0184] After forming the through hole 160, continue to refer to Fig. 27 , the semiconductor structure manufacturing method further includes:

[0185] S203: forming a first cavity in the first dielectric layer through a through hole, wherein the first cavity extends to the electrode structure.

[0186] Exemplarily, a portion of the first dielectric layer 110 may be removed by etching to form the first cavity 120 in the first dielectric layer 110 , wherein the electrode structure 111 may serve as an etching stop layer to facilitate controlling the etching depth.

[0187] After forming the first cavity 120, continue to refer to Fig. 27 , the semiconductor structure manufacturing method further includes:

[0188] S204: forming a second channel layer on the cavity wall of the first cavity, wherein the second channel layer is in contact with the electrode structure.

[0189] Continue to refer to Fig.28 For example, the second channel layer 150 may be formed by deposition, evaporation, etc., so that the second channel layer 150 only covers the cavity wall of the first cavity 120 , and the second channel layer 150 does not fill the first cavity 120 .

[0190] After forming the second channel layer 150, continue to refer to Fig. 27 , the semiconductor structure manufacturing method further includes:

[0191] S205: forming a gate structure in the first cavity.

[0192] Please refer to Fig.29, illustratively, forming a gate structure in the first cavity 120 includes: forming a first gate dielectric layer 138 on the second channel layer 150 and the hole wall of the through hole 160; then forming a gate body 131 in the first cavity 120 and the through hole 160, and the gate body 131 fills the remaining space in the first cavity 120. It can be understood that when forming the gate body 131, part of the gate body 131 will cover the first gate dielectric layer 138 in the through hole 160. Therefore, Fig.30 As shown in FIG. 1 , after the gate body 131 is formed, the through hole 160 and a portion of the gate body 131 in the first cavity 120 are removed. Fig.31 As shown, a second gate dielectric layer 139 is formed in the first cavity 120 . The second gate dielectric layer 139 contacts the first gate dielectric layer 138 . The second gate dielectric layer 139 may cover the exposed gate body 131 .

[0193] Exemplarily, the materials of the first gate dielectric layer 138 and the second gate dielectric layer 139 may be the same, so that when the second gate dielectric layer 139 is formed, the second gate dielectric layer 139 and the first gate dielectric layer 138 may form an integrated structure to form a gate dielectric layer that wraps the gate body 131 .

[0194] like Fig.32 As shown, thereafter, the first gate dielectric layer 138 and the second gate dielectric layer 139 located on the wall of the through hole 160 can be removed by etching; wherein, when removing the first gate dielectric layer 138 on the wall of the through hole 160, part of the second gate dielectric layer 139 is removed, and accordingly, a reasonable selection of etching time can ensure that the second gate dielectric layer 139 will not be completely removed to avoid exposing the gate body 131.

[0195] After forming the gate structure 130, continue to refer to Fig. 27 , the semiconductor structure manufacturing method further includes:

[0196] S206: forming a first channel layer on the hole wall of the through hole, wherein the first channel layer is in contact with the second channel layer.

[0197] Please refer to Fig.33 For example, the first channel layer 140 can be formed by deposition or evaporation in equal parts, and the first channel layer 140 covers the hole wall of the through hole 160 so that the end of the second channel layer 150 close to the through hole 160 is connected to the first channel layer 140.

[0198] After forming the first channel layer 140, continue to refer to Fig. 27 , the semiconductor structure manufacturing method further includes:

[0199] S207: forming a conductive column in the through hole.

[0200] Continue to refer to Fig.33 , illustratively, the conductive pillar 161 may be formed by evaporation or deposition, and the conductive pillar 161 fills the through hole 160 .

[0201] In the above implementation, the gate structure 130 serves as the gate of the transistor structure 100, and the second channel structure serves as the channel of the transistor structure 100. The conductive pillar 161 and the electrode structure 111 are mutually the source and the drain. It can be understood that the conductive pillar 161 can serve as the drain of the transistor structure 100, and correspondingly, the electrode structure 111 serves as the source of the transistor structure 100; or, the electrode structure 111 serves as the drain of the transistor structure 100, and correspondingly, the conductive pillar 161 serves as the source of the transistor structure 100.

[0202] In the semiconductor structure manufactured by the semiconductor structure manufacturing method provided in the embodiment of the present application, the through hole 160 penetrates the first cavity 120 in the first dielectric layer 110, the conductive column 161 is arranged in the through hole 160, the first channel layer 140 is arranged between the conductive column 161 and the hole wall of the through hole 160, the second channel layer 150 covers the cavity wall of the first cavity 120, and the second channel layer 150 is in contact with the first channel layer 140; the gate structure 130 and the electrode structure 111 of the transistor are both in contact with the second channel layer 150. The thin-walled second channel layer 150 enables the gate structure 130 to have good control ability, and there is no need to arrange the gate structure 130 on both sides of the channel along the center line direction of the through hole 160, so that the thickness of the semiconductor structure along the center line direction of the through hole 160 can be reduced.

[0203] In some embodiments, the first cavity 120 includes a first cavity wall 121 away from the through hole 160, and a second cavity wall 122 and a third cavity wall 123 located between the first cavity wall 121 and the through hole 160, the second cavity wall 122 and the third cavity wall 123 are arranged opposite to each other, and the second cavity wall 122 is in contact with the first insulating layer 180. Accordingly, after forming the second channel layer 150 on the cavity wall of the first cavity 120, it also includes: removing at least part of the first insulating layer 180 corresponding to the second cavity wall 122 through the through hole 160 to form a first gap to expose part of the second channel layer 150; removing the exposed part of the second channel layer 150 through the through hole 160; forming a third insulating layer in the first gap, the third insulating layer fills the first gap, and the third insulating layer can play a supporting role. Exemplarily, the material of the third insulating layer may include silicon oxide, silicon nitride, etc.

[0204] Through the above arrangement, compared with the second channel layer 150 covering the cavity walls in the first cavity 120, the volume of the second channel layer 150 can be reduced. At the same time, only the second channel layer 150 on the cavity wall close to the second cavity 171 is in contact with the first channel layer 140, so that the contact area between the second channel layer 150 and the first channel layer 140 is not too large.

[0205] It can be understood that all the first insulating layers 180 corresponding to the second cavity wall 122 can be removed through the through hole 160 to form a first gap to expose the second channel layer 150 corresponding to the second cavity wall 122; then, the exposed second channel layer 150 is removed through the through hole 160, that is, all the second channel layer 150 on the second cavity wall 122 is removed. Of course, all the first insulating layers 180 corresponding to part of the second cavity wall 122 can also be removed through the through hole 160 to form a first gap to expose part of the second channel layer 150 corresponding to the second cavity wall 122; then, the exposed second channel layer 150 is removed through the through hole 160, that is, part of the second channel layer 150 on the second cavity wall 122 is removed, and there is a second gap 152 between the remaining second channel layer 150 on the second cavity wall 122 and the through hole 160.

[0206] In the implementation of semiconductor structures applied to dynamic random access memory, such as Fig.18 As shown, the memory string 300 includes a first memory string 310 and a second memory string 320, and the gate structure 130 of the memory cell in the first memory string 310 is connected to the gate structure 130 of the memory cell in the second memory string 320 through the first conductive portion 133. Fig.34 As shown, after the conductive pillar 161 is formed, the first insulating layer 180 between the first memory string 310 and the second memory string 320 is removed to form a first notch 21 ( Fig.34 The dashed area). Fig.35 As shown, the first channel layer 140 of the first storage string 310 facing the second storage string 320 is then removed through the first notch 21, and the first gate dielectric layer 138 of the first storage string 310 is partially exposed; similarly, the first channel layer 140 of the second storage string 320 facing the first storage string 310 is removed through the first notch 21, and the first gate dielectric layer 138 of the second storage string 320 is partially exposed. Fig.36 As shown, the first notch 21 is filled with a first insulating material 22, and a second notch 23 is formed on the first insulating material 22 (as shown in FIG. Fig.37 As shown, the first notch 21 is removed to remove the first gate dielectric layer 138 in the first memory string 310 and the second memory string 320, and the gate bodies 131 in the first memory string 310 and the second memory string 320 are exposed. Fig.38As shown, a first conductive portion 133 is formed in the second notch 23, and the first conductive portion 133 is connected to both exposed gate bodies 131, thereby realizing the connection between the first storage string 310 and the second storage string 320. After the first conductive portion 133 is formed, a second insulating material can be formed in the second notch 23, so that the second insulating material and the first insulating material 22 form a Fig.19 Insulation filler shown.

[0207] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0208] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor structure, characterized in that: include: A first dielectric layer, wherein a first cavity is disposed in the first dielectric layer; a through hole, wherein the through hole passes through the first cavity; A transistor structure, the transistor structure comprising: A conductive column, wherein the conductive column is inserted into the through hole; A first channel layer, wherein the first channel layer is disposed between the conductive pillar and a hole wall of the through hole; a second channel layer, wherein the second channel layer covers the cavity wall of the first cavity, and the second channel layer contacts the first channel layer; A gate structure and an electrode structure, wherein both the gate structure and the electrode structure are in contact with the second channel layer; The conductive column and the electrode structure are mutually a source and a drain.

2. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further includes a second dielectric layer stacked with the first dielectric layer, a second cavity is provided in the second dielectric layer, the through hole penetrates the second cavity, the gate structure is provided in the second cavity, the gate structure contacts the second channel layer on the cavity wall of the first cavity close to the second cavity, and the gate structure is insulated and connected to the conductive pillar; The electrode structure is disposed in the first dielectric layer, and the electrode structure contacts the second channel layer on a cavity wall of the first cavity at a side away from the through hole.

3. The semiconductor structure according to claim 2, characterized in that: The second channel layer covers a cavity wall in the first cavity close to the second cavity and a cavity wall away from the through hole.

4. The semiconductor structure according to claim 3, characterized in that: The second channel layer covers each cavity wall of the first cavity.

5. The semiconductor structure according to claim 3, characterized in that: The second channel layer also covers a portion of the cavity wall in the first cavity away from the second cavity, and a first gap exists between the second channel layer on the portion of the cavity wall in the first cavity away from the second cavity and the through hole.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that: An insulator is disposed in the first cavity, and the second channel layer is located between the insulator and a cavity wall of the first cavity.

7. The semiconductor structure according to claim 1, characterized in that: The gate structure is disposed in the first cavity, and the second channel layer is located between the gate structure and a cavity wall of the first cavity.

8. The semiconductor structure according to claim 7, characterized in that: The electrode structure is disposed on a side of the first cavity away from the through hole, and the electrode structure contacts the second channel layer on a cavity wall of the first cavity away from the through hole.

9. The semiconductor structure according to claim 7 or 8, characterized in that: The first cavity body includes a first cavity wall away from the through hole, and a second cavity wall and a third cavity wall located between the first cavity wall and the through hole, and the second cavity wall and the third cavity wall are arranged opposite to each other; the second channel layer covers the first cavity wall, the second cavity wall and the third cavity wall, and the second channel layer on the second cavity wall and the third cavity wall are in contact with the first channel layer.

10. The semiconductor structure according to claim 7 or 8, characterized in that: The first cavity includes a first cavity wall away from the through hole, and a second cavity wall and a third cavity wall located between the first cavity wall and the through hole, and the second cavity wall and the third cavity wall are arranged opposite to each other; the second channel layer covers the first cavity wall, the second cavity wall and the third cavity wall, the second channel layer on the second cavity wall is in contact with the first channel layer, and a second gap is provided between the second channel layer on the third cavity wall and the first channel layer.

11. The semiconductor structure according to any one of claims 1 to 10, characterized in that: The gate structure includes a gate body and a gate dielectric layer wrapped on the gate body, and the gate dielectric layer is in contact with the second channel layer.

12. A storage array, characterized in that: include: A storage unit, comprising a storage structure and the semiconductor structure according to any one of claims 1 to 10, wherein the electrode structure is connected to the storage structure, and the storage structure is used to store data.

13. The storage array according to claim 12, characterized in that: The storage structure includes a storage capacitor, which includes a capacitor plate and a storage medium. The storage medium is located between the electrode structure and the capacitor plate. The capacitor plate serves as one plate of the storage capacitor, and the electrode structure serves as another plate of the storage capacitor.

14. The storage array according to claim 13, characterized in that: The capacitor plate and the storage medium are both located in the first dielectric layer.

15. The storage array according to claim 13 or 14, characterized in that: The storage unit includes a first storage unit and a second storage unit, and the first storage unit and the second storage unit are stacked along the center line of the through hole to form a storage string; the conductive pillars of the first storage unit and the second storage unit are an integrated structure.

16. The storage array according to claim 15, characterized in that: The storage string includes a first storage string and a second storage string, the first storage string and the second storage string are arranged in a direction perpendicular to the center line of the through hole, the first storage cell in the first storage string is arranged on the same layer as the first storage cell in the second storage string, and the gate structure of the first storage cell in the first storage string is connected to the gate structure of the first storage cell in the second storage string; the second storage cell in the first storage string is arranged on the same layer as the second storage cell in the second storage string, and the gate structure of the second storage cell in the first storage string is connected to the gate structure of the second storage cell in the second storage string.

17. The storage array according to claim 16, characterized in that: The gate structure of the first storage cell in the first storage string and the gate structure of the first storage cell in the second storage string are an integrated structure, and the gate structure of the second storage cell in the first storage string and the gate structure of the second storage cell in the second storage string are an integrated structure.

18. The storage array according to claim 16, wherein: The gate structure of the first storage cell in the first storage string is connected to the gate structure of the first storage cell in the second storage string through a first conductive part, and the gate structure of the second storage cell in the first storage string is connected to the gate structure of the second storage cell in the second storage string through a second conductive part.

19. A memory, characterized in that: include: A controller and a storage array as described in any one of claims 12 to 18, wherein the controller is connected to the storage array.

20. An electronic device, characterized in that: include: A circuit board and the memory as claimed in claim 19, wherein the memory is arranged on the circuit board.

21. A method for manufacturing a semiconductor structure, characterized in that: include: forming a first insulating layer, a first dielectric layer and a second dielectric layer in a stacked manner, wherein the first dielectric layer is located between the first insulating layer and the second dielectric layer; An electrode structure is disposed in the first dielectric layer, a second cavity is disposed in the second dielectric layer, and a gate structure is disposed in the second cavity; forming a through hole, wherein the through hole penetrates the first insulating layer, the first dielectric layer, and the second cavity; A first cavity is formed in the first dielectric layer through the through hole, and the first cavity extends to the electrode structure; the first cavity is connected to the second cavity; forming a second channel layer on a cavity wall of the first cavity, wherein the second channel layer is in contact with both the gate structure and the electrode structure; Filling an insulator in the first cavity; forming a first channel layer on a hole wall of the through hole, wherein the first channel layer is in contact with the second channel layer; A conductive column is formed in the through hole; the conductive column and the electrode structure serve as a source and a drain for each other.

22. The method for manufacturing a semiconductor structure according to claim 21, characterized in that: The first cavity body comprises a first cavity wall away from the through hole, and a second cavity wall and a third cavity wall located between the first cavity wall and the through hole, the second cavity wall and the third cavity wall are arranged opposite to each other, and the second cavity wall is in contact with the first insulating layer; Before forming the first channel layer on the hole wall of the through hole, the method further includes: removing at least a portion of the first insulating layer corresponding to the second cavity wall through the through hole to form a first gap to expose a portion of the second channel layer; removing the exposed portion of the second channel layer through the through hole; A third insulating layer is formed in the first gap.

23. A method for manufacturing a semiconductor structure, characterized in that: include: forming a first insulating layer and a first dielectric layer in a stacked manner; An electrode structure is arranged in the first dielectric layer; forming a through hole, wherein the through hole penetrates the first insulating layer and the first dielectric layer; A first cavity is formed in the first dielectric layer through the through hole, wherein the first cavity extends to the electrode structure; forming a second channel layer on the cavity wall of the first cavity, wherein the second channel layer is in contact with the electrode structure; forming a gate structure in the first cavity; forming a first channel layer on a hole wall of the through hole, wherein the first channel layer is in contact with the second channel layer; A conductive column is formed in the through hole; the conductive column and the electrode structure serve as a source and a drain for each other.

24. The method for manufacturing a semiconductor structure according to claim 23, characterized in that: Forming a gate structure in the first cavity includes: forming a first gate dielectric layer on the second channel layer and the hole wall of the through hole; forming a gate body in the first cavity and the through hole; removing the through hole and a portion of the gate body in the first cavity; forming a second gate dielectric layer in the first cavity, wherein the second gate dielectric layer contacts the first gate dielectric layer; The first gate dielectric layer located on the wall of the through hole is removed.

25. The method for manufacturing a semiconductor structure according to claim 23 or 24, characterized in that: The first cavity body comprises a first cavity wall away from the through hole, and a second cavity wall and a third cavity wall located between the first cavity wall and the through hole, the second cavity wall and the third cavity wall are arranged opposite to each other, and the second cavity wall is in contact with the first insulating layer; After forming a second channel layer on the cavity wall of the first cavity, the method further includes: removing at least a portion of the first insulating layer corresponding to the second cavity wall through the through hole to form a first gap to expose a portion of the second channel layer; removing the exposed portion of the second channel layer through the through hole; A third insulating layer is formed in the first gap.

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