Semiconductor memory device

Abstract

A semiconductor memory device includes: a substrate including a cell region and a peripheral region defined around the cell region; a peripheral gate on the peripheral region and including a peripheral gate conductive film; a peripheral wiring line on the peripheral gate; peripheral wiring cover films in contact with the peripheral wiring lines, respectively, in which each peripheral wiring cover film includes an upper surface and a lower surface; and a peripheral wiring isolation pattern that isolates adjacent peripheral wiring lines, and that contacts sidewalls of the peripheral wiring lines, in which the lower surface of each of the peripheral wiring cover films faces the substrate and contacts an upper surface of a peripheral wiring extension line, and in which the peripheral wiring extension line has a lower surface facing the substrate and a lower surface facing the upper surface of the peripheral wiring cover film. A height from an upper surface of the substrate to the upper surface of each of the peripheral wiring extension lines is smaller than a height from the upper surface of the substrate to an upper surface of the peripheral wiring isolation pattern.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a plurality of wiring lines and buried contacts intersecting each other. Background Art

[0002] As semiconductor devices become increasingly highly integrated, individual circuit patterns are becoming smaller and smaller in order to implement a greater number of semiconductor devices in the same area. That is, as the integration of semiconductor devices increases, the design rules for each component of the semiconductor device decrease.

[0003] In high-scale semiconductor devices, the process of forming multiple wiring lines and multiple buried contacts (BCs) therebetween is becoming increasingly complex and sophisticated. Summary of the invention

[0004] A technical objective to be achieved by the present disclosure is to provide a semiconductor memory device with improved reliability and performance.

[0005] The purpose according to the present disclosure is not limited to the purpose mentioned above. Other purposes and advantages according to the present disclosure that are not mentioned can be understood based on the following description, and can be more clearly understood based on the embodiments according to the present disclosure. In addition, it should be easily understood that the purposes and advantages according to the present disclosure can be achieved using the means shown in the claims or their combination.

[0006] According to one aspect of the present disclosure, a semiconductor device is provided, the semiconductor memory device comprising: a substrate, the substrate comprising a cell region and a peripheral region defined around the cell region, wherein the cell region comprises a cell active region defined by a cell element isolation film; a bit line, the bit line being located on the cell region of the substrate; a peripheral gate, the peripheral gate being located on the peripheral region of the substrate and comprising a peripheral gate conductive film; a peripheral wiring line, the peripheral wiring line being located on the peripheral gate, wherein each of the peripheral wiring lines comprises a peripheral wiring extension line made of metal; and a peripheral wiring covering film, the peripheral wiring covering films respectively comprising: in contact with the peripheral wiring lines, wherein each of the peripheral wiring covering films includes an upper surface and a lower surface opposite to the upper surface; and a peripheral wiring isolation pattern, the peripheral wiring isolation pattern isolates adjacent peripheral wiring lines from each other, and the peripheral wiring isolation pattern contacts the side walls of the isolated peripheral wiring lines, wherein the lower surface of each of the peripheral wiring covering films faces the substrate and contacts the upper surface of the corresponding peripheral wiring extension line, and wherein the height from the upper surface of the substrate to the upper surface of each of the peripheral wiring extension lines is less than the height from the upper surface of the substrate to the upper surface of the peripheral wiring isolation pattern.

[0007] According to one aspect of the present disclosure, a semiconductor memory device is provided, the semiconductor memory device comprising: a substrate, the substrate comprising a cell region and a peripheral region defined around the cell region, wherein the cell region comprises a cell active region defined by a cell element isolation film; a bit line, the bit line being located on the cell region of the substrate; a peripheral gate, the peripheral gate being located on the peripheral region of the substrate and comprising a peripheral gate conductive film; a peripheral wiring line, the peripheral wiring line being located on the peripheral gate, wherein each of the peripheral wiring lines comprises a peripheral wiring extension line made of metal; a peripheral wiring covering film, the peripheral wiring covering film being in contact with the peripheral wiring extension lines, respectively, wherein each of the peripheral wiring covering films comprises an upper surface and a lower surface opposite to the upper surface; and a peripheral wiring isolation pattern, the peripheral wiring isolation pattern isolating adjacent peripheral wiring lines from each other, and the peripheral wiring isolation pattern contacts a side wall of the isolated peripheral wiring line, wherein the lower surface of each of the peripheral wiring covering films faces the substrate and contacts an upper surface of the corresponding peripheral wiring extension line without contacting an upper surface of the peripheral wiring isolation pattern.

[0008] According to one aspect of the present disclosure, a semiconductor memory device is provided, the semiconductor memory device comprising: a substrate, the substrate comprising a cell region and a peripheral region defined around the cell region, wherein the cell region comprises a cell active region defined by a cell element isolation film; a bit line, the bit line being located on the cell region of the substrate; a peripheral gate, the peripheral gate being located on the peripheral region of the substrate and comprising a peripheral gate conductive film; a peripheral wiring line, the peripheral wiring line being located on the peripheral gate, wherein each of the peripheral wiring lines comprises a peripheral wiring extension line made of metal; a peripheral wiring covering film, the peripheral wiring covering film being in contact with the peripheral wiring extension line, respectively, wherein each of the peripheral wiring covering films comprises an upper surface and a lower surface opposite to the upper surface; a peripheral wiring isolation pattern, the peripheral wiring isolation pattern isolating adjacent peripheral wiring lines from each other, and the peripheral wiring isolation pattern contacts the sidewalls of the isolated peripheral wiring lines; a storage contact, the A storage contact is connected to the cell active area; a storage pad, the storage pad is connected to the storage contact, wherein each of the storage pads includes a storage pad plug film, wherein each of the storage pad plug films is made of the same metal as the metal of the peripheral wiring extension line; a pad isolation pattern, the pad isolation pattern isolates adjacent storage pads from each other; an etch stop film, the etch stop film extends along the upper surface of the peripheral wiring isolation pattern, the upper surface of each of the peripheral wiring covering films and the upper surface of the pad isolation pattern; and a data storage pattern, the data storage pattern extends through the etch stop film to be connected to the storage pad plug film, wherein the lower surface of each of the peripheral wiring covering films faces the substrate and contacts the upper surface of the corresponding peripheral wiring extension line, and wherein the height from the upper surface of the substrate to the upper surface of each of the peripheral wiring covering films is equal to the height from the upper surface of the substrate to the upper surface of the peripheral wiring isolation pattern.

[0009] However, the aspects of the present disclosure are not limited to those described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure relates by referring to the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of the present disclosure will become more apparent by describing in detail some embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0011] Figure 1 is a schematic layout diagram of a semiconductor memory device according to some embodiments.

[0012] Figure 2 As Figure 1 Layout diagram of region R, a portion of the unit region.

[0013] Figure 3 It only shows Figure 2 Layout diagram of the word lines and active areas.

[0014] Figure 4 It is along Figure 1 A cross-sectional view taken along line AA in FIG.

[0015] Figure 5 and Figure 6 Along the Figure 2 A cross-sectional view taken along lines BB and CC.

[0016] Figure 7 and Figure 8 They are Figure 4 Magnified view of part P.

[0017] Figures 9 to 11 is a diagram for illustrating a semiconductor memory device according to some embodiments.

[0018] Fig.12 is a diagram for illustrating a semiconductor memory device according to some embodiments.

[0019] Figures 13 to 16 is a diagram for illustrating a semiconductor memory device according to some embodiments.

[0020] Figures 17 to 19 is a diagram for illustrating a semiconductor memory device according to some embodiments.

[0021] Fig. 20 and Fig.21 is a diagram for illustrating a semiconductor memory device according to some embodiments.

[0022] Fig. 22 is a diagram for illustrating a semiconductor memory device according to some embodiments.

[0023] Fig.23 is a diagram for illustrating a semiconductor memory device according to some embodiments.

[0024] Fig.24 It is along Fig. 22 A cross-sectional view taken along lines DD and EE.

[0025] Fig.25 is a layout diagram for illustrating a semiconductor memory device according to some embodiments.

[0026] Fig.26 is a perspective view for illustrating a semiconductor memory device according to some embodiments.

[0027] Fig. 27 is a diagram for illustrating a semiconductor memory device according to some embodiments.

[0028] Figures 28 to 34 are diagrams of intermediate structures corresponding to intermediate steps for illustrating a method for fabricating a semiconductor memory device according to some embodiments.

[0029] Fig.35 and Fig.36 are diagrams of intermediate structures corresponding to intermediate steps of a method for manufacturing a semiconductor memory device according to some embodiments. DETAILED DESCRIPTION

[0030] References and Attachments Figure 1 From the embodiments described in detail later, the advantages and features of the present disclosure and the methods for achieving these advantages and features will become clear. However, the embodiments of the present disclosure are not limited to the embodiments disclosed herein, but can be implemented in various different forms. Therefore, these embodiments are set forth only to make the present disclosure complete and to fully inform the scope of the present disclosure to those of ordinary skill in the technical field to which the present disclosure belongs.

[0031] For the simplicity and clarity of illustration, the elements in the drawings are not necessarily drawn to scale. The same reference numerals in different drawings represent the same or similar elements, and therefore perform similar functions. In addition, for the simplicity of description, the description and details of known steps and elements are omitted. In addition, in the following detailed description of the present disclosure, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it should be understood that the present disclosure can be practiced without these specific details. In other examples, known methods, processes, components and circuits have not yet been described in detail, so as not to unnecessarily obscure the various aspects of the present disclosure. The examples of various embodiments are further described and described below. It should be understood that the description herein is not intended to limit the claims to the specific embodiments described. On the contrary, the description herein is intended to cover alternatives, modifications and equivalent forms as may be included in the subject matter and scope of the present disclosure as defined by the appended claims.

[0032] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for the purpose of explaining the embodiments of the present disclosure are illustrative, and the embodiments of the present disclosure are not limited thereto.

[0033] The term used herein is only devoted to the purpose of describing a particular embodiment, and is not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular formation "one" and "one" are also intended to include plural formations. It should be further understood that the terms "include", "include", "comprise" and "comprises" when used in this specification specify the existence of stated features, integers, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, integers, operations, elements, parts and / or parts thereof. As used herein, the term "and / or" includes any and all combinations of one or more related enumerated items. Such as "at least one of ... " when before the list of elements, the entire list of elements can be modified, and each element of the list may not be modified. In the interpretation of numerical values, even when there is no explicit description thereof, errors or tolerances may also occur therein.

[0034] It should also be understood that when a first element or layer is referred to as being present "on" a second element or layer, the first element may be directly disposed on the second element or may be indirectly disposed on the second element, wherein a third element or layer is disposed between the first element or layer and the second element or layer. It should also be understood that when a first element or layer is referred to as being present "under" a second element or layer, the first element may be directly disposed under the second element or may be indirectly disposed under the second element, wherein a third element or layer is disposed between the first element or layer and the second element or layer.

[0035] It will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly connected or coupled to the other element or layer, or one or more intervening elements or layers may be present therebetween.

[0036] In addition, it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may be present therebetween.

[0037] In addition, as used herein, when a layer, film, region, plate, etc. is disposed "on" or "above" another layer, film, region, plate, etc., the former may contact the latter, or another layer, film, region, plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is disposed "directly" "on" or "above" another layer, film, region, plate, etc., the former contacts the latter, and another layer, film, region, plate, etc. is not disposed between the former and the latter. In addition, as used herein, when a layer, film, region, plate, etc. is disposed "below" or "below" another layer, film, region, plate, etc., the former may contact the latter, or another layer, film, region, plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is disposed "directly" "below" or "below" another layer, film, region, plate, etc., the former contacts the latter, and another layer, film, region, plate, etc. is not disposed between the former and the latter.

[0038] In descriptions of temporal relationships (e.g., temporal precedent relationships between two events such as “after,” “successfully after,” “before,” etc.), unless “directly after,” “directly subsequent to,” or “directly before,” is indicated, another event may occur in between.

[0039] When a certain embodiment can be implemented differently, the function or operation specified in a particular block may occur in an order different from the order specified in the flow chart. For example, depending on the function or operation involved, two consecutive blocks may actually be performed substantially simultaneously, or the two blocks may be performed in reverse order.

[0040] It should be understood that although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part described below can be referred to as the second element, component, region, layer or part.

[0041] For ease of illustration, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to illustrate the relationship of one element or feature to another element or feature as illustrated in the various figures. It should be understood that in addition to the orientations depicted in the various figures, the spatially relative terms are also intended to encompass different orientations of the device in use or in operation. For example, when the device in the accompanying drawings can be turned over, the elements described as "below other elements or features" or "below other elements or features" or "below other elements or features" will then be oriented "above" the other elements or features. Therefore, the example terms "below" and "below" can encompass both orientations of above and below. The device can be oriented in other ways, for example, rotated 90 degrees or in other orientations, and the spatially relative descriptors used herein should be interpreted accordingly.

[0042] The features of various embodiments of the present disclosure may be partially or completely combined with each other, and may be technically associated with each other or operate with each other. The embodiments may be implemented independently of each other, and may be implemented together in an associated relationship.

[0043] When interpreting numerical values, unless there is an explicit description to the contrary, the values ​​are interpreted as including the error range.

[0044] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by those skilled in the art to which the inventive concept belongs. It should be further understood that, unless explicitly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0045] As used herein, "embodiment," "example," "aspect," etc. should not be construed as preferring or advantageous over any aspect or design described over other aspects or designs.

[0046] Furthermore, the term "or" is intended to mean an inclusive or rather than an exclusive or. That is, unless stated otherwise or clear from the context, the phrase "x employs a or b" means any of the natural inclusive permutations.

[0047] The terms used in the following description have been selected to be general and common in the relevant technical field. However, depending on the development and / or change of technology, convention, preference of technicians, etc., there may be other terms besides these terms, and therefore, the terms used in the following description should not be understood as limiting the technical ideas, but should be understood as examples of terms used to illustrate the embodiments.

[0048] In addition, in certain cases, the terms may be arbitrarily selected by the applicant, and in this case, their detailed meanings will be described in the corresponding description section. Therefore, the terms used in the following description should be understood not only based on the names of the terms, but also based on the meanings of the terms and the content throughout the present disclosure.

[0049] Figure 1 is a schematic layout diagram of a semiconductor memory device according to some embodiments. Figure 2 As Figure 1 Layout diagram of region R, a portion of the unit region. Figure 3 It only shows Figure 2 Layout diagram of the word lines and active areas. Figure 4 It is along Figure 1 A cross-sectional view taken along line AA in FIG. Figure 5 and Figure 6 Along the Figure 2 A cross-sectional view taken along lines BB and CC. Figure 7 and Figure 8 They are Figure 4 Magnified view of part P.

[0050] For reference, Figure 4 1 may be an illustrative cross-sectional view of a transistor formation region in a peripheral region. Figure 1 , line AA is shown to extend along the first direction D1. However, embodiments of the present disclosure are not limited thereto. Unlike what is shown, line AA may extend along the second direction D2.

[0051] In the drawings of the semiconductor memory device according to some embodiments, a dynamic random access memory (DRAM) is shown as an example. However, the embodiments of the present disclosure are not limited thereto.

[0052] refer to Figures 1 to 3 , a semiconductor memory device according to some embodiments may include a cell region 20 , a cell region isolation film 22 , and a peripheral region 24 .

[0053] The cell region isolation film 22 may be disposed around the cell region 20. The cell region isolation film 22 may isolate the cell region 20 and the peripheral region 24 from each other. The peripheral region 24 may be defined around the cell region 20.

[0054] The cell region 20 may include a plurality of cell active regions ACT. The cell active region ACT may be formed on a substrate ( Figure 5 100) in the unit element isolation film ( Figure 5As the design rules of the semiconductor memory device are reduced, the unit active area ACT may extend in a diagonal or oblique strip shape. For example, the unit active area ACT may be as shown in FIG. Figure 3 It is shown extending in the third direction D3.

[0055] A plurality of gate electrodes may extend in a first direction D1 and span across the cell active area ACT. A plurality of gate electrodes may extend in parallel with each other. A plurality of gate electrodes may be, for example, a plurality of word lines WL. The word lines WL may be arranged to be spaced apart from each other at equal intervals. The width of the word lines WL and / or the interval between the word lines WL may be determined based on a design rule.

[0056] Two word lines WL extending in the first direction D1 may divide each cell active region ACT into three parts. The cell active region ACT may include a bit line connection region 103a and a storage connection region 103b. The bit line connection region 103a may be located at a middle portion of the cell active region ACT, and the storage connection region 103b may be located at an end of the cell active region ACT.

[0057] A plurality of bit lines BL extending in the second direction D2 and orthogonal to the word line WL may be disposed on the word line WL. The plurality of bit lines BL may extend in parallel with each other. The bit lines BL may be arranged to be spaced apart from each other at equal intervals. The width of the bit lines BL and / or the intervals between the bit lines BL may be determined based on a design rule.

[0058] A semiconductor memory device according to some embodiments may include various contact arrays formed on a cell active area ACT. The various contact arrangements may include, for example, a direct contact (DC), a buried contact (BC), and a landing pad (LP).

[0059] In this regard, the direct contact DC may mean a contact that electrically connects the cell active region ACT to the bit line BL. The buried contact BC may mean a contact that connects the cell active region ACT to the first lower electrode ( Figure 5 Due to the layout structure, the contact area between the buried contact BC and the cell active region ACT may be small. Therefore, in order to increase the contact area between the buried contact BC and the cell active region ACT and the contact area between the buried contact BC and the first lower electrode ( Figure 5 191) a contact area between the conductive landing pads LP may be introduced.

[0060] The landing pad LP may be disposed between the buried contact BC and the first lower electrode ( Figure 5191) between the cell active region ACT and the buried contact BC. In the semiconductor memory device according to some embodiments, the landing pad LP may be disposed between the buried contact BC and the first lower electrode ( Figure 5 The contact area can be increased due to the introduction of the landing pad LP, so that the cell active area ACT and the first lower electrode ( Figure 5 The contact resistance between 191) can be reduced.

[0061] The direct contact DC may be connected to the bit line connection region 103a. The buried contact BC may be connected to the storage connection region 103b. Since the buried contact BC is disposed at each of the two opposite ends of the cell active region ACT, the landing pad LP may be disposed adjacent to each of the two opposite ends of the cell active region ACT so as to partially overlap with the buried contact BC. In other words, the buried contact BC may be formed to overlap with the cell active region ACT and the cell element isolation film ( Figure 5 105) each of which partially overlaps.

[0062] The word line WL may be formed as a structure buried in the substrate 100. The word line WL may extend across a portion of the cell active region ACT disposed between the direct contact DC or the buried contact BC. As shown, two word lines WL may intersect one cell active region ACT. As the cell active region ACT extends along the third direction D3, the word line WL may define an angle of less than 90 degrees relative to the cell active region ACT.

[0063] The direct contact DC may be arranged symmetrically. The buried contact BC may be arranged symmetrically. Therefore, the direct contact DC may be arranged in a straight line along each of the first direction D1 and the second direction D2. The buried contact BC may be arranged in a straight line along each of the first direction D1 and the second direction D2. In one example, unlike the direct contact DC and the buried contact BC, the landing pad LP may be arranged in a zigzag pattern along the second direction D2 in which the bit line BL extends. In addition, the landing pads LP may overlap with the same side of the bit lines BL arranged in the first direction D1 extending along the word line WL, respectively. For example, the landing pads LP of the first line extending in the first direction D1 may overlap with the left side surface of the corresponding bit line BL, respectively, and the landing pads LP of the second line extending in the first direction D1 may overlap with the right side surface of the corresponding bit line BL, respectively.

[0064] refer to Figures 1 to 8According to some embodiments, a semiconductor memory device may include multiple unit gate structures 110, multiple bit line structures 140ST, multiple storage contacts 120, multiple storage pads 160, data storage patterns 190, peripheral gate structures 240ST, peripheral wiring lines 265 and peripheral wiring cover films 270.

[0065] The substrate 100 may include a cell region 20, a cell region isolation film 22, and a peripheral region 24. The substrate 100 may be a silicon substrate or a silicon-on-insulator (SOI) substrate. Alternatively, the substrate 100 may be formed of or include, but are not limited to, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0066] A plurality of cell gate structures 110, a plurality of bit line structures 140ST, a plurality of storage contacts 120, a plurality of storage pads 160, and a data storage pattern 190 may be disposed in the cell region 20. A peripheral gate structure 240ST, a peripheral wiring line 265, and a peripheral wiring capping film 270 may be disposed in the peripheral region 24.

[0067] The cell element isolation film 105 may be formed in the cell region 20 of the substrate 100. The cell element isolation film 105 may have a shallow trench isolation (STI) structure having excellent element isolation capability. The cell element isolation film 105 may define a cell active region ACT in the cell region 20. Figure 2 and Figure 3 As shown, the cell active region ACT defined by the cell element isolation film 105 may be in the shape of an elongated island including short sides and long sides. The cell active region ACT may extend in a diagonal direction so as to define an angle less than 90 degrees with respect to an extension direction of a word line WL formed in the cell element isolation film 105. In addition, the cell active region ACT may extend in a diagonal direction so as to define an angle less than 90 degrees with respect to an extension direction of a bit line BL disposed on the cell element isolation film 105.

[0068] The cell region isolation film 22 may be embodied as a cell boundary isolation film having an STI structure. The cell region 20 may be defined by the cell region isolation film 22 .

[0069] Each of the cell element isolation film 105 and the cell region isolation film 22 may be formed of or include at least one of, for example, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. However, the embodiments of the present disclosure are not limited thereto. Figure 5 and Figure 6In the figure, the cell element isolation film 105 is illustrated as being embodied as an insulating film (e.g., a single-layer film). However, this is intended only for the convenience of illustration, and the embodiments of the present disclosure are not limited thereto. Depending on the width of each of the cell element isolation film 105 and the cell region isolation film 22, each of the cell element isolation film 105 and the cell region isolation film 22 may be formed as one insulating film, or may be formed as a stack of multiple insulating films.

[0070] exist Figure 5 and Figure 6 , it is illustrated that the upper surface of the cell element isolation film 105 and the upper surface of the substrate 100 are coplanar with each other. However, this is only for convenience of explanation, and the embodiments of the present disclosure are not limited thereto.

[0071] The cell gate structure 110 may be disposed in the substrate 100 and the cell element isolation film 105. The cell gate structure 110 may extend across the cell element isolation film 105 and the cell active area ACT defined by the cell element isolation film 105. The cell gate structure 110 may include a cell gate trench 115, a cell gate insulating film 111, a cell gate electrode 112, a cell gate capping pattern 113, and a cell gate capping conductive film 114 formed in the substrate 100 and the cell element isolation film 105. In this regard, the cell gate electrode 112 may correspond to a word line WL. Unlike what is illustrated, the cell gate structure 110 may not include a cell gate capping conductive film 114.

[0072] The cell gate trench 115 may be relatively deep in the cell element isolation film 105 and may be relatively shallow in the cell active region ACT. The bottom surface of the cell gate electrode 112 may be curved. That is, the depth of the cell gate trench 115 in the cell element isolation film 105 may be greater than the depth of the cell gate trench 115 in the cell active region ACT.

[0073] The cell gate insulating film 111 may extend along the sidewall and bottom surface of the cell gate trench 115. The cell gate insulating film 111 may extend along the contour of at least a portion of the cell gate trench 115. The cell gate insulating film 111 may be formed of, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material having a dielectric constant higher than that of silicon oxide or include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material having a dielectric constant higher than that of silicon oxide. The high dielectric constant material may include, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. However, the embodiments of the present disclosure are not limited thereto.

[0074] The cell gate electrode 112 may be formed on the cell gate insulating film 111. The cell gate electrode 112 may fill a portion of the cell gate trench 115. The cell gate capping conductive film 114 may extend along the upper surface of the cell gate electrode 112. Figure 7 , it is illustrated that the cell gate capping conductive film 114 does not cover a portion of the upper surface of the cell gate electrode 112. However, the embodiments of the present disclosure are not limited thereto.

[0075] The cell gate electrode 112 may be formed of or include at least one of a metal, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal oxynitride, or a conductive metal oxide. The cell gate electrode 112 may include, for example, TiN, TaC, TaN, TiSiN, TaSiN, TaTiN, TiAlN, TaAlN, WN, Ru, TiAl, TiAlC-N, TiAlC, TiC, TaCN, W, Al, Cu, Co, Ti, Ta, Ni, Pt, Ni-Pt, Nb, NbN, NbC, Mo, MoN, MoC, WC, Rh, Pd, Ir, Ag, Au, Zn, V, RuTiN, TiSi, TaSi, NiSi, CoSi, IrO x 、RuO x At least one or a combination thereof. However, the embodiments of the present disclosure are not limited thereto. The cell gate capping conductive film 114 may be formed of, for example, polysilicon or polycrystalline silicon germanium or include polycrystalline silicon or polycrystalline silicon germanium. However, the embodiments of the present disclosure are not limited thereto.

[0076] The cell gate capping pattern 113 may be disposed on the cell gate electrode 112 and the cell gate capping conductive film 114. The cell gate capping pattern 113 may fill a portion of the cell gate trench 115 that remains after the cell gate electrode 112 and the cell gate capping conductive film 114 have been formed in the cell gate trench 115. Although the cell gate insulating film 111 is illustrated as extending along the sidewall of the cell gate capping pattern 113, embodiments of the present disclosure are not limited thereto. The cell gate capping pattern 113 may be made of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), or a combination thereof, or include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN) or a combination thereof.

[0077] Although not shown, an impurity-doped region may be formed on at least one side of the cell gate structure 110. The impurity-doped region may be a source / drain region of a transistor.

[0078] The bit line structure 140ST may include a cell conductive line 140 and a cell line cover film 144. The cell conductive line 140 may be disposed on a portion of each of the substrate 100 and the cell element isolation film 105 on which the cell gate structure 110 has been disposed.

[0079] The cell conductive line 140 may extend in the second direction D2. The cell conductive line 140 may intersect the cell element isolation film 105 and the cell active area ACT defined by the cell element isolation film 105. The cell conductive line 140 may be formed to intersect the cell gate structure 110. In this regard, the cell conductive line 140 may correspond to the bit line BL.

[0080] The unit conductive line 140 may be embodied as a stack of multiple films. The unit conductive line 140 may include, for example, a first unit conductive film 141, a second unit conductive film 142, and a third unit conductive film 143. The first to third unit conductive films 141, 142, and 143 may be sequentially stacked on the substrate 100 and the unit element isolation film 105. Although the unit conductive line 140 is illustrated as being embodied as a stack of three films, embodiments of the present disclosure are not limited thereto.

[0081] Each of the first unit conductive film 141, the second unit conductive film 142, and the third unit conductive film 143 may be formed of or include at least one of, for example, a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, a two-dimensional (2D) material, and a metal. In a semiconductor memory device according to some embodiments, the two-dimensional material may be a metal material and / or a semiconductor material. The two-dimensional material (2D material) may include a two-dimensional allotrope or a two-dimensional compound. For example, the 2D material may include graphene, molybdenum disulfide (MoS 2 ), Molybdenum diselenide (MoSe 2 ), tungsten diselenide (WSe 2 ) and tungsten disulfide (WS 2 ) at least one of. However, the present disclosure is not limited thereto. In other words, the above two-dimensional materials are listed only as examples. The two-dimensional materials that can be included in the semiconductor memory device of the present disclosure are not limited to the above materials.

[0082] For example, the first unit conductive film 141 may include a doped semiconductor material, the second unit conductive film 142 may include at least one of a conductive silicide compound, a conductive metal nitride, and a two-dimensional material, and the third unit conductive film 143 may include a metal. However, the embodiments of the present disclosure are not limited thereto.

[0083] The bit line contact 146 may be disposed between the cell conductive line 140 and the substrate 100. That is, the cell conductive line 140 may be formed on the bit line contact 146. For example, the bit line contact 146 may be disposed at a point where the cell conductive line 140 intersects the middle portion of the cell active area ACT in the shape of an elongated island. The bit line contact 146 may be formed between the bit line connection region 103a and the cell conductive line 140 in a vertical direction (e.g., a thickness direction of the substrate 100).

[0084] The bit line contact 146 may electrically connect the cell conductive line 140 and the substrate 100 to each other. In this regard, the bit line contact 146 may correspond to a direct contact DC. The bit line contact 146 may be formed of or include, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, or a metal.

[0085] exist Figure 5 In the embodiment of the present invention, in a region overlapping with the upper surface of the bit line contact 146, the cell conductive line 140 may include a second cell conductive film 142 and a third cell conductive film 143. In a region not overlapping with the upper surface of the bit line contact 146, the cell conductive line 140 may include first to third cell conductive films 141, 142, and 143. The thickness of a portion of the cell conductive line 140 in a region overlapping with the upper surface of the bit line contact 146 may be different from the thickness of a portion of the cell conductive line 140 in a region not overlapping with the upper surface of the bit line contact 146.

[0086] The unit line covering film 144 may be disposed on the unit conductive line 140. The unit line covering film 144 may extend in the second direction D2 and along the upper surface of the unit conductive line 140. In this regard, the unit line covering film 144 may be formed of, for example, at least one of silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbon nitride oxide, or include, for example, at least one of silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbon nitride oxide. In a semiconductor memory device according to some embodiments, the unit line covering film 144 may include, for example, a silicon nitride film. Although the unit line covering film 144 is illustrated as embodied as a single film, the embodiments of the present disclosure are not limited thereto. In other words, the unit line covering film 144 may be embodied as a stack of multiple films. However, when the films constituting the stack are made of the same material, the unit line covering film 144 may be considered as a single film.

[0087] The cell insulating film 130 may be disposed on the substrate 100 and the cell element isolation film 105. More specifically, the cell insulating film 130 may be formed on a portion of each of the substrate 100 and the cell element isolation film 105 on which the bit line contact 146 is not disposed. The cell insulating film 130 may be formed, for example, Figure 5 It is shown disposed between the substrate 100 and the unit conductive line 140 and between the unit element isolation film 105 and the unit conductive line 140 .

[0088] It is illustrated that the unit insulating film 130 may be embodied as a stack of a first unit insulating film 131 and a second unit insulating film 132. However, the unit insulating film 130 may be embodied as a single film. For example, the first unit insulating film 131 may include a silicon oxide film, while the second unit insulating film 132 may include a silicon nitride film. However, the embodiments of the present disclosure are not limited thereto. In another example, unlike what is shown, the unit insulating film 130 may include three or more insulating films. When the unit insulating film 130 includes a third unit insulating film, the third unit insulating film may be a silicon oxide film.

[0089] exist Figure 5 In the cross-sectional view of , the upper surface 100US of the substrate may be defined at a boundary between the unit insulating film 130 and the substrate 100 .

[0090] The cell line spacer 150 may be disposed on a sidewall of each of the cell conductive line 140 and the cell line cover film 144. The cell line spacer 150 may be formed in a region surrounding a region where the cell conductive line 140 is disposed on the bit line contact 146 on the substrate 100 and the cell element isolation film 105. The cell line spacer 150 may be disposed on a sidewall of each of the cell conductive line 140, the cell line cover film 144, and the bit line contact 146.

[0091] In a region surrounding a region where the cell conductive line 140 is formed and where the bit line contact 146 does not exist, a cell line spacer 150 may be disposed on the cell insulating film 130. The cell line spacer 150 may be disposed on a sidewall of each of the cell conductive line 140 and the cell line cover film 144.

[0092] The cell line spacer 150 may be disposed on a main sidewall extending in the second direction D2 in an elongated manner among the sidewalls of the bit line structure 140ST.

[0093] The cell line spacer 150 is illustrated as a stack of multiple films including the first to fourth cell line spacers 151, 152, 153 and 154. However, the cell line spacer 150 may be embodied as a single film. For example, each of the first to fourth cell line spacers 151, 152, 153 and 154 may be formed by a silicon oxide film, a silicon nitride film, a silicon oxynitride (SiON) film, a silicon oxycarbonitride (SiOCN) film, one of the air or a combination thereof or include a silicon oxide film, a silicon nitride film, a silicon oxynitride (SiON) film, a silicon oxycarbonitride (SiOCN) film, one of the air or a combination thereof. However, the embodiments of the present disclosure are not limited thereto. For example, the second cell line spacer 152 may not be disposed on the cell insulating film 130, but may be disposed on the sidewall of the bit line contact 146.

[0094] A fence pattern 170 may be provided on the substrate 100 and the cell element isolation film 105. The fence pattern 170 may be formed to overlap the cell gate structure 110 formed in the substrate 100 and the cell element isolation film 105. The fence pattern 170 may be provided between the bit line structures 140ST extending along the second direction D2. The fence pattern 170 may be formed of, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof or include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0095] A plurality of storage contacts 120 may be disposed between the cell conductive lines 140 adjacent to each other along the first direction D1. The storage contacts 120 may be disposed between the fence patterns 170 adjacent to each other along the second direction D2 (see, for example, Figure 6 ). The storage contact 120 may overlap a portion of each of the substrate 100 and the cell element isolation film 105 disposed between adjacent cell conductive lines 140. The storage contact 120 may be connected to the storage connection region 103b of the cell active region ACT. In this regard, the storage contact 120 may correspond to a buried contact BC.

[0096] The storage contact 120 may be formed of or include, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, or a metal.

[0097] A plurality of storage pads 160 may be disposed on the storage contacts 120. The storage pads 160 may be electrically connected to the storage contacts 120. In this regard, the storage pads 160 may correspond to landing pads LP.

[0098] The storage pad 160 may overlap a portion of the upper surface of the bit line structure 140ST. For example, the storage pad 160 may overlap the upper surface 144US of the cell line cover film in the thickness direction of the substrate 100.

[0099] The storage pad 160 may include a storage pad barrier film 161 and a storage pad plug film 162. The storage pad barrier film 161 may be disposed between the storage contact 120 and the storage pad plug film 162. The storage pad barrier film 161 may be connected to the storage contact 120. A portion of the storage pad barrier film 161 may extend along the upper surface 144US of the cell line cover film.

[0100] The storage pad plug film 162 includes an upper surface 160US of the storage pad 160 . The upper surface 160US of the storage pad 160 may be an upper surface of the storage pad plug film 162 .

[0101] Each of the storage pad barrier film 161 and the storage pad plug film 162 may be formed of a conductive material or include a conductive material. The storage pad barrier film 161 may include, for example, at least one of a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, and a conductive metal carbonitride. The storage pad plug film 162 may include a metal. For example, the storage pad plug film 162 may be made of a metal.

[0102] A plurality of storage pad cover films 275 may be disposed on the storage pad 160. The storage pad cover film 275 may be disposed on each storage pad 160.

[0103] The storage pad cover film 275 may contact the upper surface 160US of the storage pad 160. The storage pad cover film 275 may contact the storage pad plug film 162. It should be understood that when an element is referred to as "contacting" another element or "in contact with" another element (or any form of the word "contacting"), there is no intermediate element at the contact point.

[0104] The storage pad cover film 275 may include an upper surface 275US and a bottom surface 275BS opposite to each other. The bottom surface 275BS of the storage pad cover film 275 may face the storage pad 160. The bottom surface 275BS of the storage pad cover film 275 may contact the upper surface 160US of the storage pad.

[0105] In the semiconductor memory device according to some embodiments, the storage pad cover film 275 may be a first storage pad cover film 276. The first storage pad cover film 276 may be formed of or include a metal nitride.

[0106] In one example, the first storage pad cover film 276 may include a nitride of a metal included in the storage pad plug film 162. For example, when the storage pad plug film 162 is made of tungsten (W), the first storage pad cover film 276 may include tungsten nitride (WN).

[0107] In another example, the first storage pad cover film 276 may include a nitride of a metal other than the metal included in the storage pad plug film 162. Hereinafter, an example in which the first storage pad cover film 276 includes a nitride of a metal included in the storage pad plug film 162 is described.

[0108] The pad isolation pattern 180 may be formed on the storage pad 160 and the bit line structure 140ST. For example, the pad isolation pattern 180 may be disposed on the cell line cover film 144.

[0109] The pad isolation pattern 180 may define the area of ​​the storage pad 160 into each of a plurality of isolation areas. The pad isolation pattern 180 may isolate adjacent storage pads 160 from each other. The pad isolation pattern 180 may isolate adjacent storage pad cover films 275 from each other.

[0110] The pad isolation pattern 180 does not cover the upper surface 160US of the storage pad. The pad isolation pattern 180 does not cover the upper surface 275US of the storage pad cover film 275.

[0111] The pad isolation pattern 180 may be formed of an insulating material or include an insulating material. The pad isolation pattern 180 may electrically insulate adjacent storage pads from each other among the plurality of storage pads 160. For example, the pad isolation pattern 180 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon carbon nitride film, and a silicon carbon nitride film.

[0112] For example Figure 5As shown, the height H41 from the upper surface 100US of the substrate 100 to the upper surface 160US of the storage pad 160 is less than the height H42 from the upper surface 100US of the substrate 100 to the upper surface 180US of the pad isolation pattern 180. In the semiconductor memory device according to some embodiments, the height H43 from the upper surface 100US of the substrate 100 to the upper surface 275US of the storage pad cover film 275 may be equal to the height H42 from the upper surface 100US of the substrate 100 to the upper surface 180US of the pad isolation pattern 180. The upper surface 180US of the pad isolation pattern 180 and the upper surface 275US of the storage pad cover film 275 may be coplanar with each other. However, the embodiments of the present disclosure are not limited thereto.

[0113] The upper etch stop film 292 may be disposed on the pad isolation pattern 180 and the storage pad 160. The upper etch stop film 292 may be disposed on the storage pad cover film 275. The upper etch stop film 292 may extend not only to the cell region 20 but also to the peripheral region 24. The upper etch stop film 292 may be formed of or include at least one of a silicon nitride film, a silicon carbon nitride film, a silicon boron nitride (SiBN) film, a silicon oxynitride film, and a silicon oxycarbon film. However, the embodiments of the present disclosure are not limited thereto.

[0114] The data storage pattern 190 may be disposed on the storage pad 160. The data storage pattern 190 may be electrically connected to the storage pad 160. The storage pad cover film 275 may be disposed between the storage pad 160 and the data storage pattern 190. The data storage pattern 190 may contact the storage pad cover film 275.

[0115] A portion of the data storage pattern 190 may be disposed within the upper etch stop film 292. The data storage pattern 190 may include, for example, a capacitor. However, embodiments of the present disclosure are not limited thereto. The data storage pattern 190 includes a first lower electrode 191, a first capacitor dielectric film 192, and a first upper electrode 193.

[0116] The first lower electrode 191 may be disposed on the storage pad 160. The first lower electrode 191 may contact the storage pad cover film 275. The first lower electrode 191 is illustrated as being in a column shape. However, the embodiments of the present disclosure are not limited thereto. In another example, the first lower electrode 191 may be in a cylindrical shape.

[0117] The first capacitor dielectric film 192 is disposed on the first lower electrode 191. The first capacitor dielectric film 192 may be formed along the contour of the first lower electrode 191. The first upper electrode 193 is disposed on the first capacitor dielectric film 192. The first upper electrode 193 may surround an outer sidewall of the first lower electrode 191.

[0118] For example, the first capacitor dielectric film 192 may be disposed to vertically overlap the first upper electrode 193. The first capacitor dielectric film 192 may not extend to the peripheral region 24.

[0119] Each of the first lower electrode 191 and the first upper electrode 193 can be formed of or include, for example, a doped semiconductor material, a conductive metal nitride (such as titanium nitride, tantalum nitride, niobium nitride or tungsten nitride), a metal (such as ruthenium, iridium, titanium or tantalum, etc.) or a conductive metal oxide (such as iridium oxide or niobium oxide, etc.).

[0120] For example, the first capacitor dielectric film 192 may be formed of or include at least one of a ferroelectric material, an antiferroelectric material, and a paraelectric material. For example, the first capacitor dielectric film 192 may include at least one of: a ferroelectric material; an antiferroelectric material; a paraelectric material; a combination of a ferroelectric material and an antiferroelectric material; a combination of a ferroelectric material and a paraelectric material; a combination of a paraelectric material and an antiferroelectric material; or a combination of a ferroelectric material, an antiferroelectric material, and a paraelectric material.

[0121] In one example, the first capacitor dielectric film 192 may include a stacked film structure in which a zirconium oxide film, an aluminum oxide film, and a zirconium oxide film are sequentially stacked. In another example, the first capacitor dielectric film 192 may include a dielectric film having hafnium (Hf). The suggestions regarding the material of the first capacitor dielectric film 192 as described above are merely examples, and the technical idea of ​​the present disclosure is not limited thereto.

[0122] Unlike the above description, the data storage pattern 190 may be a variable resistance pattern that can be switched between two resistance states under an electric pulse applied to the memory element. For example, the data storage pattern 190 may include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material whose crystal state changes depending on the amount of current.

[0123] The peripheral element isolation film 26 may be formed within the substrate 100 and in the peripheral region 24. The peripheral element isolation film 26 may define a peripheral active region in the peripheral region 24. The upper surface of the peripheral element isolation film 26 is shown to be coplanar with the upper surface 100US of the substrate 100. However, the embodiments of the present disclosure are not limited thereto. The peripheral element isolation film 26 may be formed of, for example, at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film or include, for example, at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0124] The peripheral gate structure 240ST may be disposed on the substrate 100 and in the peripheral region 24. The peripheral gate structure 240ST may be disposed on a peripheral active region defined by the peripheral element isolation film 26.

[0125] The peripheral gate structure 240ST may include a peripheral gate insulating film 230, a peripheral gate conductive film 240, and a peripheral capping film 244 sequentially stacked on the substrate 100. The peripheral gate structure 240ST may include a peripheral spacer 245 disposed on sidewalls of the peripheral gate conductive film 240 and the peripheral capping film 244.

[0126] The peripheral gate conductive film 240 may include first to third peripheral conductive films 241, 242, and 243 sequentially stacked on the peripheral gate insulating film 230. For example, an additional conductive film may not be provided between the peripheral gate conductive film 240 and the peripheral gate insulating film 230. In another example, unlike what is shown, an additional conductive film such as a work function conductive film may be provided between the peripheral gate conductive film 240 and the peripheral gate insulating film 230.

[0127] Although two peripheral gate structures 240ST are shown to be disposed between adjacent peripheral element isolation films 26 , this is only for convenience of illustration, and embodiments of the present disclosure are not limited thereto.

[0128] For example, the peripheral gate conductive film 240 may have the same stack structure as that of the unit conductive line 140 . The thickness T21 of the peripheral gate conductive film 240 may be equal to the thickness T11 of the unit conductive line 140 .

[0129] The first peripheral conductive film 241 may include the same material as that of the first unit conductive film 141. The second peripheral conductive film 242 may include the same material as that of the second unit conductive film 142. The third peripheral conductive film 243 may include the same material as that of the third unit conductive film 143.

[0130] The peripheral gate insulating film 230 may be formed of or include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material having a higher dielectric constant than silicon oxide.

[0131] For example, the peripheral spacer 245 may be formed of or include at least one of silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, silicon carbon nitride oxide, and combinations thereof. Although the peripheral spacer 245 is shown as being formed as a single film, this is only for convenience of illustration, and the embodiments of the present disclosure are not limited thereto. In another example, the peripheral spacer 245 may be embodied as a stack of multiple films.

[0132] For example, the peripheral covering film 244 may be formed of or include at least one of a silicon nitride film, silicon oxynitride, and silicon oxide. For example, the thickness T22 of the peripheral covering film 244 is less than the thickness T12 of the cell line covering film 144. In addition, the vertical height of the upper surface 244US of the peripheral covering film 244 is lower than the vertical height of the upper surface 144US of the cell line covering film 144. For example, the thickness T12 of the cell line covering film 144 may be as follows: Figure 5 The thickness of the cell line cover film 144 located on the cell line conductive trace 140 is shown.

[0133] The lower etch stop film 250 may be disposed on the substrate 100. The lower etch stop film 250 may be formed along the contour of the peripheral gate structure 240ST. For example, the lower etch stop film 250 may be formed of or include at least one of silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbon nitride oxide.

[0134] The first peripheral interlayer insulating film 290 may be disposed on the lower etch stop film 250. The first peripheral interlayer insulating film 290 may be disposed around the peripheral gate structure 240ST. For example, the first peripheral interlayer insulating film 290 may be formed of or include a silicon oxide-based insulating material. The first peripheral interlayer insulating film 290 may include, but is not limited to, silicon oxide.

[0135] The vertical height of the upper surface 290US of the first peripheral interlayer insulating film 290 may be lower than the vertical height of the upper surface 244US of the peripheral cover film 244. For example, the height H1 from the upper surface 100US of the substrate 100 to the upper surface 290US of the first peripheral interlayer insulating film 290 may be lower than the height H21 from the upper surface 100US of the substrate 100 to the upper surface 244US of the peripheral cover film 244.

[0136] A height H1 from the upper surface 100US of the substrate 100 to the upper surface 290US of the first peripheral interlayer insulating film 290 may be measured at a position near the center between adjacent peripheral gate structures 240ST. A height H21 from the upper surface 100US of the substrate 100 to the upper surface 244US of the peripheral cover film 244 may be measured at a position near the center of the width of the peripheral cover film 244.

[0137] A height H1 from the upper surface 100US of the substrate 100 to the upper surface 290US of the first peripheral interlayer insulating film 290 may be smaller than a height H22 from the upper surface 100US of the substrate 100 to the top layer of the peripheral spacer 245 .

[0138] For example, a height H21 from the upper surface 100US of the substrate 100 to the upper surface 244US of the peripheral cover film 244 may be equal to a height H22 from the upper surface 100US of the substrate 100 to the top layer of the peripheral spacer 245 .

[0139] Unlike what is shown, in another example, due to an etching process during the manufacturing process, the vertical height of the upper surface of the peripheral spacer 245 may be lower than the vertical height of the upper surface 244US of the peripheral cover film 244. In this case, the height H21 from the upper surface 100US of the substrate 100 to the upper surface 244US of the peripheral cover film 244 may be greater than or equal to the height H22 from the upper surface 100US of the substrate 100 to the top layer of the peripheral spacer 245.

[0140] The inserted interlayer insulating film 291 is disposed on the peripheral gate structure 240ST and the first peripheral interlayer insulating film 290. The inserted interlayer insulating film 291 may cover the peripheral gate structure 240ST and the first peripheral interlayer insulating film 290. The inserted interlayer insulating film 291 may cover a portion of the lower etch stop film 250 that protrudes upward beyond the upper surface 290US of the first peripheral interlayer insulating film 290.

[0141] The upper surface 290US of the first peripheral interlayer insulating film 290 is shown to be flat. However, the embodiments of the present disclosure are not limited thereto. The upper surface 290US of the first peripheral interlayer insulating film 290 may be a curved surface convex toward the substrate 100 .

[0142] The inserted interlayer insulating film 291 may include a material different from that of the first peripheral interlayer insulating film 290. The inserted interlayer insulating film 291 may be formed of or include, for example, a silicon nitride-based insulating material. For example, the inserted interlayer insulating film 291 may include silicon nitride.

[0143] A portion of the inserted interlayer insulating film 291 extends downward into the space between adjacent peripheral gate structures 240ST. In other words, a vertical height of a bottom surface of the inserted interlayer insulating film 291 may be lower than a vertical height of an upper surface 244US of the peripheral cover film 244 .

[0144] Therefore, the inserted interlayer insulating film 291 can protect the first peripheral interlayer insulating film 290 in an etching process included in the process of manufacturing the data storage pattern 190. In the etching process included in the process of manufacturing the data storage pattern 190, the inserted interlayer insulating film 291 can prevent defects caused by etching the first peripheral interlayer insulating film 290.

[0145] The peripheral contact plugs 260 may be disposed at two opposite sides of the peripheral gate structure 240ST, respectively. The peripheral contact plugs 260 may extend to a portion of the substrate 100 in the peripheral region 24 through the interposed interlayer insulating film 291 and the first peripheral interlayer insulating film 290 .

[0146] The peripheral contact plug 260 may include a peripheral plug barrier film 261 and a peripheral plug filling film 262 . The peripheral plug filling film 262 may be disposed on the peripheral plug barrier film 261 .

[0147] The peripheral wiring line 265 may be disposed on the interlayer insulating film 291 inserted. The peripheral wiring line 265 may be disposed on the peripheral gate structure 240ST. The peripheral wiring line 265 may be connected to the peripheral contact plug 260. In the cross-sectional view, at the position where the peripheral wiring line 265 is connected to the peripheral contact plug 260, the peripheral wiring line 265 may be a portion disposed on the upper surface 291US of the interlayer insulating film 291 inserted. The peripheral wiring line 265 may be disposed on the upper surface 291US of the interlayer insulating film inserted.

[0148] The peripheral wiring line 265 may include a peripheral wiring barrier film 266 and a peripheral wiring extension line 267. The peripheral wiring extension line 267 may be disposed on the peripheral wiring barrier film 266.

[0149] The peripheral wiring extension circuit 267 includes an upper surface 265US of the peripheral wiring circuit 265 . The upper surface 267US of the peripheral wiring extension circuit 267 may be the upper surface 265US of the peripheral wiring circuit 265 .

[0150] The peripheral wiring line 265 includes a side wall 265SW. The side wall 265SW of the peripheral wiring line 265 may be defined by a peripheral wiring barrier film 266 and a peripheral wiring extension line 267.

[0151] In the semiconductor memory device according to some embodiments, the peripheral wiring extension line 267 may be directly connected to the peripheral plug filling film 262. The peripheral wiring barrier film 266 may be directly connected to the peripheral plug barrier film 261. The peripheral contact plug 260 and the peripheral wiring line 265 may be formed in the same manufacturing process (e.g., integrally formed).

[0152] The peripheral wiring barrier film 266 may include the same material as that of the peripheral plug barrier film 261. The peripheral wiring barrier film 266 may be formed of or include, for example, at least one of a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, and a conductive metal carbonitride. In the semiconductor memory device according to some embodiments, the peripheral wiring barrier film 266 may include the same material as that of the storage pad barrier film 161.

[0153] The peripheral wiring extension line 267 may include the same material as the peripheral plug filling film 262. The peripheral wiring extension line 267 may be formed of or include a metal. For example, the peripheral wiring extension line 267 may be made of a metal. The peripheral wiring extension line 267 may include the same metal as the metal of the storage pad plug film 162.

[0154] Unlike what is shown, the peripheral contact plug 260 may include a peripheral plug filling film 262 made of metal but may not have a peripheral plug barrier film 261. The peripheral wiring line 265 may include a peripheral wiring extension line 267 made of metal but may not have a peripheral wiring barrier film 266.

[0155] The peripheral wiring cover film 270 may be disposed on the peripheral wiring line 265. The peripheral wiring cover film 270 may be disposed on each peripheral wiring line 265.

[0156] The peripheral wiring cover film 270 may contact the upper surface 265US of the peripheral wiring line 265. The peripheral wiring cover film 270 may contact the peripheral wiring extension line 267.

[0157] The peripheral wiring cover film 270 may include an upper surface 270US and a bottom surface 270BS opposite to each other. The bottom surface 270BS of the peripheral wiring cover film may face the substrate 100. The bottom surface 270BS of the peripheral wiring cover film may contact the upper surface 267US of the peripheral wiring extension line 267. The peripheral wiring cover film 270 includes a side wall 270SW connecting the bottom surface 270BS of the peripheral wiring cover film 270 and the upper surface 270US of the peripheral wiring cover film 270 to each other.

[0158] The width W12 of the bottom surface 270BS of the peripheral wiring cover film 270 is equal to the width W11 of the upper surface 267US of the peripheral wiring extension line 267 (see, for example, Figure 7 ).exist Figure 4 In the cross-sectional view of FIG. 26 , at a position where the plug pattern connected to the peripheral wiring line 265 does not exist, the peripheral wiring cover film 270 may cover the entirety of the upper surface 267US of the peripheral wiring extension line 267. The side wall 270SW of the peripheral wiring cover film 270 may be aligned with the side wall 265SW of the peripheral wiring line 265.

[0159] The peripheral wiring cover film 270 does not extend along the side wall 265SW of the peripheral wiring line 265. The peripheral wiring cover film 270 may not contact the side wall 265SW of the peripheral wiring line 265.

[0160] In the semiconductor memory device according to some embodiments, the peripheral wiring cover film 270 may be a first peripheral wiring cover film 271. The first peripheral wiring cover film 271 may be formed of or include a metal nitride.

[0161] In one example, the first peripheral wiring cover film 271 may include a nitride of a metal included in the peripheral wiring extension line 267. Since the peripheral wiring extension line 267 may include the same metal as that of the storage pad plug film 162, the first peripheral wiring cover film 271 and the first storage pad cover film 276 may include the same metal nitride. When the peripheral wiring extension line 267 is made of tungsten (W), the first peripheral wiring cover film 271 may include tungsten nitride (WN).

[0162] In another example, the first peripheral wiring cover film 271 may include a nitride of a metal other than the metal included in the peripheral wiring extension line 267. Since the first peripheral wiring cover film 271 and the first storage pad cover film 276 are formed in the same process, the first peripheral wiring cover film 271 includes the same metal nitride as that of the first storage pad cover film 276.

[0163] Hereinafter, an example in which the first peripheral wiring cover film 271 includes a nitride of a metal included in the peripheral wiring extension line 267 is described.

[0164] The peripheral wiring isolation pattern 280 may isolate adjacent peripheral wiring lines 265 from each other. The peripheral wiring lines 265 may include, for example, Figure 7 and Figure 8The first peripheral wiring line 265_1 and the second peripheral wiring line 265_2 are shown adjacent to each other. In this case, the peripheral wiring isolation pattern 280 may isolate the first peripheral wiring line 265_1 and the second peripheral wiring line 265_2 from each other.

[0165] The peripheral wiring isolation pattern 280 may isolate adjacent peripheral wiring cover films 270 from each other. The peripheral wiring isolation pattern 280 may isolate a portion of the peripheral wiring cover film 270 contacting the first peripheral wiring line 265_1 and a portion of the peripheral wiring cover film 270 contacting the second peripheral wiring line 265_2 from each other.

[0166] The peripheral wiring isolation pattern 280 may contact the sidewall 265SW of the peripheral wiring line 265. The peripheral wiring isolation pattern 280 may contact the sidewall 270SW of the peripheral wiring cover film 270.

[0167] The peripheral wiring cover film 270 may not extend along the upper surface 280US of the peripheral wiring isolation pattern 280. The peripheral wiring isolation pattern 280 does not cover the upper surface 270US of the peripheral wiring cover film 270.

[0168] The peripheral wiring isolation pattern 280 may be formed of an insulating material or include an insulating material. The peripheral wiring isolation pattern 280 may electrically insulate adjacent peripheral wiring lines 265 from each other. For example, the peripheral wiring isolation pattern 280 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon carbon nitride film, and a silicon carbon nitride film.

[0169] A height H31 from the upper surface 100US of the substrate 100 to the upper surface 267US of the peripheral wiring extension line 267 is less than a height H32 from the upper surface 100US of the substrate 100 to the upper surface 280US of the peripheral wiring isolation pattern 280. In a semiconductor memory device according to some embodiments, a height H33 from the upper surface 100US of the substrate 100 to the upper surface 270US of the peripheral wiring cover film 270 may be equal to a height H32 from the upper surface 100US of the substrate 100 to the upper surface 280US of the peripheral wiring isolation pattern 280.

[0170] exist Figure 7 In the embodiment, the upper surface 280US of the peripheral wiring isolation pattern 280 may be flat. The upper surface 280US of the peripheral wiring isolation pattern 280 may be coplanar with the upper surface 270US of the peripheral wiring cover film 270 .

[0171] exist Figure 8In the embodiment, the upper surface 280US of the peripheral wiring isolation pattern 280 may not be flat. In the cross-sectional view, the upper surface 280US of the peripheral wiring isolation pattern 280 may be in a shape similar to a "V" shape. For example, the vertical height of the upper surface 280US of the peripheral wiring isolation pattern 280 may generally decrease from the edge of the peripheral wiring isolation pattern 280 toward the center thereof.

[0172] exist Figure 7 and Figure 8 , the upper surface 280US of the peripheral wiring isolation pattern 280 may include a closest point 280US_NP in contact with the peripheral wiring cover film 270. For example, a height H32 from the upper surface 100US of the substrate 100 to the upper surface 280US of the peripheral wiring isolation pattern 280 may be a height measured at the closest point 280US_NP of the upper surface 280US of the peripheral wiring isolation pattern 280.

[0173] After the peripheral wiring line 265 has been formed, a subsequent process using an etchant or an oxygen-containing process gas may continue. The peripheral wiring extension line 267 may be oxidized by oxygen used in the subsequent process, thereby generating metal oxide. Due to the generated metal oxide, the resistance of the peripheral wiring line 265 may increase.

[0174] In this regard, the peripheral wiring cover film 270 may be formed on the peripheral wiring line 265. Therefore, the peripheral wiring cover film 270 may prevent the peripheral wiring extension line 267 from being oxidized in a subsequent process using oxygen. Therefore, the performance and reliability of the semiconductor memory device may be improved.

[0175] The upper etch stopper film 292 may be disposed on the peripheral wiring isolation pattern 280 and the peripheral wiring cover film 270. For example, the upper etch stopper film 292 may extend along the upper surface 270US of the peripheral wiring cover film 270 and the upper surface 280US of the peripheral wiring isolation pattern 280.

[0176] The upper etch stopper film 292 does not contact the sidewall 265SW of the peripheral wiring line 265. In the semiconductor memory device according to some embodiments, the upper etch stopper film 292 may not contact the sidewall 270SW of the peripheral wiring cover film 270.

[0177] The second peripheral interlayer insulating film 293 may be disposed on the upper etch stopper film 292. Although not shown, the second peripheral interlayer insulating film 293 may cover the sidewalls of the first upper electrode 193. The second peripheral interlayer insulating film 293 may be formed of or include an insulating material.

[0178] Figures 9 to 11 is a diagram for illustrating a semiconductor memory device according to some embodiments. Fig.12is a diagram for illustrating a semiconductor memory device according to some embodiments. For ease of description, the following will mainly describe the semiconductor memory device described above. Figures 1 to 8 The difference in the content described.

[0179] For reference, Fig. 9 and Fig.12 Along the Figure 1 A cross-sectional view taken along line AA. Fig.10 and Fig.11 They are Fig. 9 Magnified view of part P.

[0180] refer to Figures 9 to 11 In the semiconductor memory device according to some embodiments, a height H32 from the upper surface 100US of the substrate 100 to the upper surface 280US of the peripheral wiring isolation pattern 280 may be smaller than a height H33 from the upper surface 100US of the substrate 100 to the upper surface 270US of the peripheral wiring cover film 270 .

[0181] The vertical height of the upper surface 270US of the peripheral wiring cover film 270 may be higher than the vertical height of the upper surface 280US of the peripheral wiring isolation pattern 280. Therefore, the upper etch stop film 292 may contact the sidewall 270SW of the peripheral wiring cover film 270. The upper etch stop film 292 may cover a portion of the sidewall 270SW of the peripheral wiring cover film 270.

[0182] Although not shown, from the upper surface 100US of the substrate 100 to the upper surface ( Figure 5 A height H43 of the pad isolation pattern 180 (275US in FIG. 275US) may be greater than a height H42 from the upper surface 100US of the substrate 100 to the upper surface 180US of the pad isolation pattern 180.

[0183] exist Fig.10 In the embodiment, the upper surface 280US of the peripheral wiring isolation pattern 280 may be flat. Fig.11 In the embodiment, the upper surface 280US of the peripheral wiring isolation pattern 280 may have a shape similar to a “V” shape.

[0184] refer to Fig.12 , in the semiconductor memory device according to some embodiments, the first capacitor dielectric film 192 may be disposed between the upper etch stop film 292 and the second peripheral interlayer insulating film 293 .

[0185] The first capacitor dielectric film 192 may extend along the boundary between the upper etching stop film 292 and the second peripheral interlayer insulating film 293. In other words, the first capacitor dielectric film 192 may also be provided in the peripheral region ( Figure 1 24) in the above.

[0186] The first capacitor dielectric film 192 may extend along the upper surface 270US of the peripheral wiring cover film 270 and the upper surface 280US of the peripheral wiring isolation pattern 280. The upper etch stop film 292 may be located between the first capacitor dielectric film 192 and the peripheral wiring cover film 270, and may be located between the first capacitor dielectric film 192 and the peripheral wiring isolation pattern 280.

[0187] Figures 13 to 16 is a diagram for illustrating a semiconductor memory device according to some embodiments. For ease of description, the following will mainly describe the semiconductor memory device according to some embodiments. Figures 1 to 8 The difference in the content described.

[0188] For reference, Fig.13 It is along Figure 1 A cross-sectional view taken along line AA in FIG. Fig.14 and Fig.15 Along the Figure 2 A cross-sectional view taken along lines BB and CC. Fig.16 yes Fig.13 Magnified view of part P.

[0189] refer to Figures 13 to 16 In the semiconductor memory device according to some embodiments, the peripheral wiring cover film 270 may be a second peripheral wiring cover film 272 .

[0190] The second peripheral wiring covering film 272 may be formed of a silicon nitride-based insulating material or include a silicon nitride-based insulating material. The silicon nitride-based insulating material may be silicon nitride or an insulating material in which another material is included in the silicon nitride. For example, the second peripheral wiring covering film 272 may include at least one of silicon nitride (SiN), silicon carbon nitride (SiCN), and silicon boron nitride (SiBN). However, the embodiments of the present disclosure are not limited thereto.

[0191] exist Fig.16 In the embodiment, the upper surface 280US of the peripheral wiring isolation pattern 280 is shown to be flat. However, the embodiments of the present disclosure are not limited thereto. In another example, the upper surface 280US of the peripheral wiring isolation pattern 280 may have a similar Figure 8 Same shape as shown.

[0192] The storage pad cover film 275 may be a second storage pad cover film 277. The second storage pad cover film 277 may be formed of or include a silicon nitride-based insulating material. The second storage pad cover film 277 includes the same insulating material as that of the second peripheral wiring cover film 272.

[0193] The first lower electrode 191 may contact the upper surface 160US of the storage pad 160 . The first lower electrode 191 may contact the storage pad plug film 162 .

[0194] Unlike what is shown, the width of the first lower electrode 191 may be greater than the width of the storage pad cover film 275. In this case, the storage pad cover film 275 may not be visible along the line BB and / or the line CC in the cross-sectional view.

[0195] Figures 17 to 19 is a diagram for illustrating a semiconductor memory device according to some embodiments. For ease of description, the following mainly describes the semiconductor memory device described above. Figures 13 to 16 The difference in the content described.

[0196] refer to Figures 17 to 19 In the semiconductor memory device according to some embodiments, the upper etching stop film ( Figure 4 292) is not arranged between the second peripheral interlayer insulating film 293 and the second peripheral wiring cover film 272 and between the second peripheral interlayer insulating film 293 and the peripheral wiring isolation pattern 280.

[0197] For example, the second peripheral interlayer insulating film 293 may contact the upper surface 270US of the peripheral wiring cover film 270 and the upper surface 280US of the peripheral wiring isolation pattern 280 .

[0198] Upper Etch Stop Film ( Figure 5 and Figure 6 The first capacitor dielectric film 192 may not be disposed on the pad isolation pattern 180. For example, the first capacitor dielectric film 192 may contact the upper surface 180US of the pad isolation pattern 180.

[0199] Since each of the second peripheral wiring cover film 272 and the second storage pad cover film 277 includes an insulating material, each of the second peripheral wiring cover film 272 and the second storage pad cover film 277 may function as an etching stopper film.

[0200] Fig. 20 and Fig.21 is a diagram for illustrating a semiconductor memory device according to some embodiments. For ease of description, the following mainly describes the semiconductor memory device according to some embodiments. Figures 1 to 8 The difference in the content described.

[0201] refer to Fig. 20 and Fig.21 , in the semiconductor memory device according to some embodiments, the peripheral wiring extension line 267 is not directly connected to the peripheral plug filling film 262 .

[0202] The peripheral wiring barrier film 266 may be disposed between the peripheral wiring extension line 267 and the peripheral plug filling film 262. For example, after the peripheral contact plug 260 has been formed, the peripheral wiring line 265 may be formed.

[0203] An upper surface of the storage contact 120 may be coplanar with an upper surface 144US of the cell line cover film 144 .

[0204] Fig. 22 is a diagram for illustrating a semiconductor memory device according to some embodiments. Fig.23 is a diagram for illustrating a semiconductor memory device according to some embodiments. Fig.24 It is along Fig. 22 A cross-sectional view taken along lines DD and EE.

[0205] For reference, Fig. 22 Can be Figure 1 An enlarged view of the unit area 20 in FIG.

[0206] refer to Figure 22 to Figure 24 , a semiconductor memory device according to some embodiments may include a substrate 100, a plurality of first conductive lines 420, a channel layer 430, a gate electrode 440, a gate insulating film 450, and a capacitor 480. The semiconductor memory device according to some embodiments may be a memory device including a vertical channel transistor (VCT). The vertical channel transistor may refer to a structure in which the channel length of the channel layer 430 extends from the substrate 100 in a vertical direction.

[0207] The lower insulating layer 412 may be disposed on the substrate 100. The plurality of first conductive lines 420 disposed on the lower insulating layer 412 may be spaced apart from each other in the first direction D1 and may extend in the second direction D2. Each of the plurality of first insulating patterns 422 may be disposed on the lower insulating layer 412 so as to fill a space between adjacent first conductive lines 420 among the plurality of first conductive lines 420. The plurality of first insulating patterns 422 may extend in the second direction D2. The upper surface of each of the plurality of first insulating patterns 422 may be disposed at the same height as the upper surface of each of the plurality of first conductive lines 420. Each of the plurality of first conductive lines 420 may be used as a bit line.

[0208] Each of the plurality of first conductive lines 420 may be formed of or include a doped semiconductor material, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. For example, each of the plurality of first conductive lines 420 may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO, or a combination thereof. x 、RuO x Or a combination thereof. However, the embodiments of the present disclosure are not limited thereto. Each of the plurality of first conductive lines 420 may include a single layer or a stack of multiple layers made of the aforementioned materials. In some embodiments, each of the plurality of first conductive lines 420 may include graphene, carbon nanotubes, or a combination thereof.

[0209] The channel layer 430 may be arranged in a matrix form and may be spaced apart from each other in the first direction D1 and the second direction D2, and may be disposed on a plurality of first conductive lines 420. The channel layer 430 may have a first width along the first direction D1 and a first vertical dimension along the fourth direction D4. The first vertical dimension may be greater than the first width. For example, the first vertical dimension may be approximately 2 to 10 times the first width. However, embodiments of the present disclosure are not limited thereto. In this regard, the fourth direction D4 intersects the first direction D1 and the second direction D2, and may be, for example, a direction perpendicular to the upper surface of the substrate 100. The bottom of the channel layer 430 may be used as a first source / drain region (not shown), and the top of the channel layer 430 may be used as a second source / drain region (not shown), and a portion of the channel layer 430 located between the first source / drain region and the second source / drain region may be used as a channel region (not shown).

[0210] In one example, the channel layer 430 may be formed of or include an oxide semiconductor. For example, the oxide semiconductor may include In x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Znx O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O、Al x Zn y Sn z O, Yb x Ga y Zn z O、In x Ga y O or a combination thereof. The channel layer 430 may include a single layer or multiple layers made of an oxide semiconductor. In some embodiments, the channel layer 430 may have a band gap energy greater than the band gap energy of silicon. For example, the channel layer 430 may have a band gap energy of about 1.5eV to about 5.6eV. For example, when the channel layer 430 has a band gap energy of about 2.0eV to 4.0eV, the channel layer 430 may have an optimal channel performance. For example, the channel layer 430 may be made of a polycrystalline or amorphous material. However, the embodiments of the present disclosure are not limited thereto. In another example, the channel layer 430 may include a two-dimensional (2D) semiconductor material. For example, the 2D semiconductor material may include graphene, carbon nanotubes, or a combination thereof. In yet another example, the channel layer 430 may include a silicon-based semiconductor material. The channel layer 430 may include a single crystal semiconductor material. For example, the channel layer 430 may include single crystal silicon or single crystal silicon germanium, but is not limited thereto.

[0211] The gate electrode 440 may extend in the first direction D1 and may be disposed on each of two opposite side walls of the channel layer 430. The gate electrode 440 may include a first sub-gate electrode 440P1 facing the first side wall of the channel layer 430 and a second sub-gate electrode 440P2 facing the second side wall opposite to the first side wall of the channel layer 430. Since one channel layer 430 is disposed between the first sub-gate electrode 440P1 and the second sub-gate electrode 440P2, the semiconductor memory device may have a dual-gate transistor structure. However, the embodiments of the present disclosure are not limited thereto, and the second sub-gate electrode 440P2 may be omitted, and the first sub-gate electrode 440P1 facing only the first side wall of the channel layer 430 may be formed to implement a single-gate transistor structure. The material of the gate electrode 440 may be the same as that of the cell gate electrode 112.

[0212] The gate insulating film 450 surrounds the sidewall of the channel layer 430 and may be interposed between the channel layer 430 and the gate electrode 440. Fig. 22 As shown, the entire sidewall of the channel layer 430 may be surrounded by the gate insulating film 450, or a portion of the sidewall of the gate electrode 440 may be in contact with the gate insulating film 450. In some other embodiments, the gate insulating film 450 may extend in the extension direction of the gate electrode 440 (i.e., the first direction D1), and only two sidewalls of the channel layer 430 facing the gate electrode 440 may be in contact with the gate insulating layer 450. In some embodiments, the gate insulating film 450 may be formed of or include at least one of a silicon oxide film, a silicon oxynitride film, a film made of a high-k material having a higher dielectric constant than that of silicon oxide, or a combination thereof.

[0213] A plurality of second insulating patterns 432 may be respectively disposed on the plurality of first insulating patterns 422 and may extend along the second direction D2. The channel layer 430 may be disposed between two adjacent second insulating patterns 432 among the plurality of second insulating patterns 432. In addition, a first buried layer 434 and a second buried layer 436 may be disposed in a space between two adjacent second insulating patterns 432 and between two adjacent channel layers 430. The first buried layer 434 may be disposed at the bottom of the space between the two adjacent channel layers 430, and the second buried layer 436 may be formed on the first buried layer 434 to fill the rest of the space between the two adjacent channel layers 430. The upper surface of the second buried layer 436 may be coplanar with the upper surface of the channel layer 430, and the second buried layer 436 may cover the upper surface of the gate electrode 440. Alternatively, the plurality of second insulation patterns 432 may be continuous and monolithic with the plurality of first insulation patterns 422 , respectively, and / or the second buried layer 436 may be continuous and monolithic with the first buried layer 434 .

[0214] The capacitor contact 460 may be disposed on the channel layer 430. The capacitor contact 460 may vertically overlap the channel layer 430. The capacitor contacts 460 may be arranged in a matrix form and may be spaced apart from each other in the first direction D1 and the second direction D2. The capacitor contacts 460 may be made of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO xor a combination thereof. However, the embodiments of the present disclosure are not limited thereto. The upper insulating layer 462 may surround the sidewalls of the capacitor contact 460 and may be disposed on the plurality of second insulating patterns 432 and the second buried layer 436 .

[0215] The etch stop film 470 may be disposed on the upper insulating layer 462. The capacitor 480 may be disposed on the etch stop film 470. The capacitor 480 may include a second lower electrode 482, a second capacitor dielectric film 484, and a second upper electrode 486. The second lower electrode 482 may extend through the etch stop film 470 so as to be electrically connected to the upper surface of the capacitor contact 460. The second lower electrode 482 may be formed into a columnar shape extending in the fourth direction D4. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the second lower electrode 482 may overlap vertically with the capacitor contact 460. The second lower electrodes 482 may be arranged in a matrix form and may be spaced apart from each other in the first direction D1 and the second direction D2. Optionally, a landing pad (not shown) may be further disposed between the capacitor contact 460 and the second lower electrode 482, so that the second lower electrode 482 may be arranged in a hexagonal shape.

[0216] Fig.25 is a layout diagram for illustrating a semiconductor memory device according to some embodiments. Fig.26 is a perspective view for illustrating a semiconductor memory device according to some embodiments. Fig. 27 is a diagram for illustrating a semiconductor memory device according to some embodiments.

[0217] refer to Fig.25 and Fig.26 , a semiconductor memory device according to some embodiments may include a substrate 100, a plurality of first conductive lines 420A, a channel structure 430A, a contact gate electrode 440A, a plurality of second conductive lines 442A, and a capacitor 480. The semiconductor memory device according to some embodiments may be a memory device including a vertical channel transistor (VCT).

[0218] A plurality of active regions AC may be defined in the substrate 100 and defined by the first element isolation pattern 412A and the second element isolation pattern 414A. A channel structure 430A may be disposed in each active region AC. The channel structure 430A may include a first active pillar 430A1 and a second active pillar 430A2 extending in a vertical direction, and a connection portion 430L connected to the bottom of the first active pillar 430A1 and the bottom of the second active pillar 430A2. The first source / drain region SD1 may be disposed in the connection portion 430L. The second source / drain region SD2 may be disposed at the top of each of the first active pillar 430A1 and the second active pillar 430A2. Each of the first active pillar 430A1 and the second active pillar 430A2 may constitute an independent unit memory cell.

[0219] The plurality of first conductive lines 420A may extend to intersect with the plurality of active regions AC. For example, the plurality of first conductive lines 420A may extend in the second direction D2. One of the plurality of first conductive lines 420A may be disposed on the connection portion 430L and between the first active pillar 430A1 and the second active pillar 430A2, and may be disposed on the first source / drain region SD1. Another first conductive line 420A adjacent to the one first conductive line 420A may be disposed between two channel structures 430A adjacent to each other along the first direction D1. One of the plurality of first conductive lines 420A may be used as a common bit line of two unit memory cells including the first active pillar 430A1 and the second active pillar 430A2 disposed on two opposite sides of the one first conductive line 420A, respectively.

[0220] A contact gate electrode 440A may be disposed between two channel structures 430A adjacent to each other along the second direction D2. For example, the contact gate electrode 440A may be disposed between a first active pillar 430A1 included in a channel structure 430A and a second active pillar 430A2 of another channel structure 430A adjacent thereto. A contact gate electrode 440A may be shared by a first active pillar 430A1 and a second active pillar 430A2 disposed on its two sidewalls, respectively. A gate insulating layer 450A may be disposed between the contact gate electrode 440A and the first active pillar 430A1 and between the contact gate electrode 440A and the second active pillar 430A2. A plurality of second conductive lines 442A may extend in the first direction D1 and may be disposed on the upper surface of the contact gate electrode 440A. Each of the plurality of second conductive lines 442A may be used as a word line of a semiconductor memory device.

[0221] The capacitor contact 460A may be disposed on the channel structure 430A. The capacitor contact 460A may be disposed on the second source / drain region SD2. The capacitor 480 may be disposed on the capacitor contact 460A.

[0222] refer to Fig. 27 , a semiconductor memory device according to some embodiments may have a COP (cell on periphery) structure in which a cell array region CA is disposed on a peripheral structure region PA.

[0223] The peripheral structure area PA may correspond to Figure 1 and Figure 4 The cell array region CA may include Figure 22 to Figure 26 Vertical channel transistor (VCT).

[0224] Figures 28 to 34 is a diagram of an intermediate structure corresponding to an intermediate step of a method for manufacturing a semiconductor memory device according to some embodiments. Figures 1 to 8 Those descriptions explained Repeated descriptions are briefly explained or omitted.

[0225] refer to Figure 1 and Fig.28 , a substrate 100 including a cell region 20, a peripheral region 24 and a cell region isolation film 22 is provided.

[0226] A peripheral gate structure 240ST may be formed on the substrate 100 and in the peripheral region 24. The peripheral gate structure 240ST may include a peripheral gate insulating film 230, a peripheral gate conductive film 240, a peripheral capping film 244, and a peripheral spacer 245.

[0227] Subsequently, a lower etch stop film 250 may be formed on the substrate 100. The lower etch stop film 250 may be formed on the peripheral gate structure 240ST. The lower etch stop film 250 may be formed along the outline of the peripheral gate structure 240ST.

[0228] Subsequently, a first preliminary interlayer insulating film 290P may be formed on the lower etch stop film 250. The first preliminary interlayer insulating film 290P may completely cover the lower etch stop film 250. The first preliminary interlayer insulating film 290P may be formed of or include, for example, a silicon oxide-based insulating material.

[0229] refer to Fig.29 , a portion of the first preliminary interlayer insulating film 290P disposed on the upper surface of the peripheral gate structure 240ST may be removed so that a portion of the lower etch stop film 250 disposed on the upper surface of the peripheral gate structure 240ST may be exposed.

[0230] For example, using a chemical mechanical polishing process (CMP), a portion of the first preliminary interlayer insulating film 290P may be removed. That is, using a chemical mechanical polishing process (CMP), a portion of the first preliminary interlayer insulating film 290P disposed on the upper surface of the peripheral gate structure 240ST may be removed.

[0231] Subsequently, another portion of the first preliminary interlayer insulating film 290P may be removed by an etch-back process. Thus, the first peripheral interlayer insulating film 290 may be formed on the lower etch stop film 250 .

[0232] The vertical height of the upper surface 290US of the first peripheral interlayer insulating film 290 may be lower than the vertical height of the upper surface 244US of the peripheral cover film 244 .

[0233] refer to Fig.30 , an interlayer insulating film 291 may be formed on the first peripheral interlayer insulating film 290 .

[0234] The inserted interlayer insulating film 291 may be formed on a portion of the lower etch stop film 250 that protrudes upward beyond the first peripheral interlayer insulating film 290. The inserted interlayer insulating film 291 is formed not only on the peripheral region 24 but also on the cell region ( Figure 1 20) in the above.

[0235] Although not shown, the bit line structure ( Figure 5 140ST) can be formed in the unit area ( Figure 1 20). Unit line spacer ( Figure 5 The fence pattern ( 150 ) may be formed on the sidewall of the bit line structure 140ST. Figure 6 The fence pattern 170 may be formed between the bit line structures 140ST adjacent to each other along the first direction D1. After forming the fence pattern 170, the cell conductive lines ( Figure 5 Storage contacts ( Figure 5 and Figure 6 120 in the table).

[0236] refer to Fig.31 , a peripheral contact plug hole 260H may be formed in the interlayer insulating film 291 inserted and the first peripheral interlayer insulating film 290 .

[0237] The peripheral contact plug hole 260H may extend through the interlayer insulating film 291 and the first peripheral interlayer insulating film 290. The peripheral contact plug hole 260H may expose the substrate 100 in the peripheral region ( Figure 1 Part 24) in .

[0238] refer to Fig.31 and Fig.32 , a pre-blocking conductive film 261 p may be formed along the contours of the upper surface 291US of the peripheral contact plug hole 260H and the interposed interlayer insulating film 291 .

[0239] A prefill conductive film 262 p may be formed on the pre-block conductive film 261 p. The prefill conductive film 262 p may fill the peripheral contact plug hole 260H. The prefill conductive film 262 p may be formed on the upper surface 291US of the interlayer insulating film 291 inserted.

[0240] The pre-blocking conductive film 261p and the pre-filling conductive film 262p may also be formed in the cell region ( Figure 1 20) in the above.

[0241] refer to Fig.33 , a first pre-circuit cover film 271p may be formed on the pre-fill conductive film 262p.

[0242] The first pre-circuit cover film 271p may also be formed in the cell region ( Figure 1 20) in the above.

[0243] In one example, the first pre-circuit cover film 271p may be formed on the pre-fill conductive film 262p using a vapor deposition process. In another example, the first pre-circuit cover film 271p may be formed by nitriding a portion of the pre-fill conductive film 262p. For example, a portion of the pre-fill conductive film 262p may be converted into a nitride by a plasma nitridation process.

[0244] refer to Fig.33 and Fig.34 , a wiring isolation hole 280H may be formed in the pre-blocking conductive film 261p, the pre-filling conductive film 262p, and the first pre-wiring cover film 271p.

[0245] Part of the line isolation hole 280H may be formed within the interlayer insulating film 291 inserted.

[0246] The pre-block conductive film 261p, the pre-fill conductive film 262p, and the first pre-wiring cover film 271p may be isolated from each other via the wiring isolation hole 280H. Thus, the first peripheral wiring cover film 271, the peripheral wiring wiring 265, and the peripheral contact plug 260 may be formed.

[0247] Next, refer to Figure 4 , a peripheral wiring isolation pattern 280 may be formed in the line isolation hole 280H.

[0248] Fig.35 and Fig.36are diagrams of intermediate structures corresponding to intermediate steps of a method for manufacturing a semiconductor memory device according to some embodiments. Fig.35 It can be in Fig.32 The manufacturing process that follows.

[0249] refer to Fig.35 , a second pre-circuit cover film 272p may be formed on the pre-fill conductive film 262p.

[0250] The second pre-circuit cover film 272p may also be formed in the cell region ( Figure 1 For example, a second pre-circuit cover film 272p may be formed on the pre-filled conductive film 262p using a vapor deposition process.

[0251] refer to Fig.35 and Fig.36 , the line isolation hole 280H may be formed in the pre-blocking conductive film 261p, the pre-filling conductive film 262p, and the second pre-line cover film 272p.

[0252] Part of the line isolation hole 280H may be formed within the interlayer insulating film 291 inserted.

[0253] The pre-block conductive film 261p, the pre-fill conductive film 262p, and the second pre-wiring cover film 272p may be isolated from each other via the wiring isolation hole 280H. Thus, the second peripheral wiring cover film 272, the peripheral wiring wiring 265, and the peripheral contact plug 260 may be formed.

[0254] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the embodiments of the present disclosure are not limited to the above-described embodiments, but can be implemented in various different forms. It will be appreciated by those skilled in the art that the present disclosure can be practiced in other specific forms without changing the technical spirit or essential characteristics of the present disclosure. Therefore, it should be understood that the embodiments described above are not restrictive in all aspects, but illustrative.

[0255] At the end of the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the preferred embodiments without departing substantially from the principles of the present invention. Therefore, the disclosed preferred embodiments of the present invention are used only in a general and descriptive sense, and not for a limiting purpose.

Claims

1. A semiconductor memory device, comprising: a substrate including a cell region and a peripheral region defined around the cell region, wherein the cell region includes a cell active region defined by a cell element isolation film; A bit line, the bit line is located on the cell region of the substrate; a peripheral gate located on the peripheral region of the substrate and comprising a peripheral gate conductive film; Peripheral wiring lines, the peripheral wiring lines are located on the peripheral gate, wherein each of the peripheral wiring lines includes a peripheral wiring extension line made of metal; peripheral wiring cover films respectively contacting the peripheral wiring lines, wherein each of the peripheral wiring cover films includes an upper surface and a lower surface opposite to the upper surface; and a peripheral wiring isolation pattern that isolates adjacent peripheral wiring lines from each other and contacts side walls of the isolated peripheral wiring lines, wherein the lower surface of each of the peripheral wiring cover films faces the substrate and contacts the upper surface of the corresponding peripheral wiring extension line, and Wherein, a height from the upper surface of the substrate to the upper surface of each of the peripheral wiring extension lines is smaller than a height from the upper surface of the substrate to the upper surface of the peripheral wiring isolation pattern.

2. The semiconductor memory device according to claim 1, wherein: The peripheral wiring cover film includes metal nitride.

3. The semiconductor memory device according to claim 2, wherein: The metal nitride includes a nitride of a metal included in the peripheral wiring extension line.

4. The semiconductor memory device according to claim 1, wherein: The peripheral wiring cover film includes a silicon nitride-based insulating material.

5. The semiconductor memory device according to claim 1, wherein A height from the upper surface of the substrate to the upper surface of the peripheral wiring isolation pattern is equal to a height from the upper surface of the substrate to the upper surface of each of the peripheral wiring cover films.

6. The semiconductor memory device according to claim 1, wherein A height from the upper surface of the substrate to the upper surface of the peripheral wiring isolation pattern is smaller than a height from the upper surface of the substrate to an upper surface of each of the peripheral wiring cover films.

7. The semiconductor memory device according to claim 1, wherein: The width of the lower surface of each of the peripheral wiring cover films is equal to the width of the upper surface of each of the peripheral wiring extension lines.

8. The semiconductor memory device according to claim 1, further comprising: an etching stopper film extending along the upper surface of the peripheral wiring isolation pattern and the upper surface of each of the peripheral wiring cover films; as well as A peripheral upper interlayer insulating film is located on the etching stopper film.

9. The semiconductor memory device according to claim 8, wherein: The etching stopper film does not contact the side wall of the peripheral wiring line.

10. The semiconductor memory device according to claim 1, further comprising: a storage contact connected to the cell active region; a storage pad connected to the storage contact; a pad isolation pattern, wherein the pad isolation pattern isolates adjacent storage pads from each other; as well as a data storage pattern connected to the storage pad, Wherein, a height from the upper surface of the substrate to an upper surface of the storage pad is smaller than a height from the upper surface of the substrate to an upper surface of the pad isolation pattern.

11. The semiconductor memory device according to claim 10, further comprising a storage pad cover film between the storage pad and the data storage pattern, the storage pad cover film being in contact with the upper surface of the storage pad, in, The data storage pattern is in contact with the storage pad cover film, and Wherein, the storage pad covering film includes metal nitride.

12. The semiconductor memory device according to claim 10, wherein: The data storage pattern contacts the upper surface of the storage pad.

13. A semiconductor memory device, comprising: a substrate including a cell region and a peripheral region defined around the cell region, wherein the cell region includes a cell active region defined by a cell element isolation film; A bit line, the bit line is located on the cell region of the substrate; a peripheral gate located on the peripheral region of the substrate and comprising a peripheral gate conductive film; Peripheral wiring lines, the peripheral wiring lines are located on the peripheral gate, wherein each of the peripheral wiring lines includes a peripheral wiring extension line made of metal; peripheral wiring cover films respectively contacting the peripheral wiring extension lines, wherein each of the peripheral wiring cover films includes an upper surface and a lower surface opposite to the upper surface; and a peripheral wiring isolation pattern that isolates adjacent peripheral wiring lines from each other and contacts side walls of the isolated peripheral wiring lines, The lower surface of each of the peripheral wiring cover films faces the substrate and contacts the upper surface of the corresponding peripheral wiring extension line, but does not contact the upper surface of the peripheral wiring isolation pattern.

14. The semiconductor memory device according to claim 13, wherein: Each of the peripheral wiring cover films extends without contacting the side wall of the peripheral wiring line.

15. The semiconductor memory device according to claim 13, wherein: The peripheral wiring cover film includes a nitride of a metal included in the peripheral wiring extension line.

16. The semiconductor memory device according to claim 13, wherein: The peripheral wiring cover film includes a silicon nitride-based insulating material.

17. The semiconductor memory device according to claim 13, further comprising: a storage contact connected to the cell active region; a storage pad connected to the storage contact; a pad isolation pattern, wherein the pad isolation pattern isolates adjacent storage pads from each other; as well as a data storage pattern connected to the storage pad, Wherein, a height from an upper surface of the substrate to an upper surface of the storage pad is smaller than a height from the upper surface of the substrate to an upper surface of the pad isolation pattern. 18 . The semiconductor memory device according to claim 17 , further comprising an etch stopper film extending along an upper surface of the peripheral wiring isolation pattern, the upper surface of each of the peripheral wiring cover films, and the upper surface of the pad isolation pattern.

19. A semiconductor memory device, comprising: a substrate including a cell region and a peripheral region defined around the cell region, wherein the cell region includes a cell active region defined by a cell element isolation film; A bit line, the bit line is located on the cell region of the substrate; a peripheral gate located on the peripheral region of the substrate and comprising a peripheral gate conductive film; Peripheral wiring lines, the peripheral wiring lines are located on the peripheral gate, wherein each of the peripheral wiring lines includes a peripheral wiring extension line made of metal; Peripheral wiring cover films, the peripheral wiring cover films are in contact with the peripheral wiring extension lines, respectively, wherein each of the peripheral wiring cover films includes an upper surface and a lower surface opposite to the upper surface; a peripheral wiring isolation pattern that isolates adjacent peripheral wiring lines from each other and contacts sidewalls of the isolated peripheral wiring lines; a storage contact connected to the cell active region; storage pads connected to the storage contacts, wherein each of the storage pads includes a storage pad plug film, wherein each of the storage pad plug films is made of the same metal as a metal included in the peripheral wiring extension line; a pad isolation pattern, wherein the pad isolation pattern isolates adjacent storage pads from each other; an etching stopper film extending along an upper surface of the peripheral wiring isolation pattern, the upper surface of each of the peripheral wiring cover films, and an upper surface of the pad isolation pattern; and a data storage pattern extending through the etch stop film to be connected to the storage pad plug film, wherein the lower surface of each of the peripheral wiring cover films faces the substrate and contacts the upper surface of the corresponding peripheral wiring extension line, and Here, a height from an upper surface of the substrate to an upper surface of each of the peripheral wiring cover films is equal to a height from the upper surface of the substrate to an upper surface of the peripheral wiring isolation pattern.

20. The semiconductor memory device according to claim 19, wherein The peripheral wiring cover film includes one of metal nitride and silicon nitride series insulating materials, and The metal nitride is a nitride of a metal included in the peripheral wiring extension line.

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