Memory and preparation method thereof
By using laser annealing in 1T1C DRAM to form a polysilicon thin film with large grain size, the problems of large memory cell occupancy and low transistor performance are solved, and the memory cell area is reduced and the transistor performance is improved.
Patent Information
- Application Number
- CN202411940718.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-04-29
AI Technical Summary
The existing 1T1C DRAM memory cells occupy a large area and have a small size of polysilicon thin film grains, resulting in lower transistor performance.
By depositing the medium and etching to form a first deep hole, doped polysilicon and dielectric sequentially, laser annealing to form a polysilicon thin film with large grain size, and high-performance transistors are prepared.
It reduces the area of memory cells and greatly improves the performance of polycrystalline silicon thin film transistors, making their performance close to single crystal silicon.
Smart Images
Figure CN119907238A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a memory and a preparation method thereof. Background Art
[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory. Its main working principle is to use the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0. The working principle of 1T1C DRAM is based on a transistor and a capacitor to store and read data. Each storage unit consists of a transistor and a capacitor. The transistor acts as a switch of the storage unit to control whether the capacitor allows charge to pass through, while the capacitor is used to store data, and its charge state represents the stored bit value.
[0003] At present, 1T1C DRAM usually adopts the structure of placing peripheral CMOS circuits and DRAM memory in parallel, which has the problem of large storage unit area occupation. In addition, the existing 1T1C DRAM usually prepares transistors on polycrystalline silicon thin films deposited by vapor phase method. The vapor phase method mainly decomposes silicon source gas at high temperature based on thermochemical reaction to deposit silicon on the substrate. The grain size of the polycrystalline silicon thin film formed at this time is relatively small (the grain size is usually about 100nm), which reduces the performance of the transistor to a certain extent.
[0004] In view of this, the present invention is proposed. Summary of the invention
[0005] The object of the present invention is to provide a memory and a method for preparing the same, which reduces the occupied area of the memory unit and greatly improves the performance of the polysilicon thin film transistor; the transistor is prepared from a large-size polysilicon thin film formed after recrystallization and has performance similar to that of single crystal silicon.
[0006] The present invention provides a method for preparing a memory, comprising the following steps:
[0007] 1) depositing a dielectric on a wafer having a peripheral circuit and etching to form a first deep hole;
[0008] 2) depositing doped polysilicon and dielectric sequentially, and then removing the top dielectric and doped polysilicon;
[0009] 3) depositing a capacitor dielectric and etching in the first deep hole to form a second deep hole, and then depositing silicon nitride;
[0010] 4) Deposition of doped amorphous silicon and laser annealing to form a polycrystalline silicon film with large grain size;
[0011] 5) Etching the top active area and preparing transistors, depositing dielectrics and planarizing, then depositing gate dielectrics and doped amorphous silicon in sequence, and laser annealing to form doped polysilicon electrodes;
[0012] 6) Etching to form a gate, then etching a through hole and making metal interconnections to complete the memory preparation.
[0013] In step 1), the wafer with peripheral circuits can be a CMOS wafer (Peripheral CMOS); the material of the medium deposited on the wafer can be silicon oxide (SiO2), silicon nitride (Si3N4), etc.; the thickness of the medium is ≥700nm, for example, 700nm-2μm. Subsequently, a first deep hole can be formed on the medium by dry etching or the like, and the diameter of the first deep hole can be 200-500nm; when etching the first deep hole, ensure that the bottom of the first deep hole is not connected to the wafer to avoid damaging the CMOS circuit of the wafer. In one embodiment, the thickness of the medium can be 1.5-2μm, and the depth of the first deep hole can be 0.9-1μm.
[0014] In step 2), doped polysilicon is first deposited. The purpose of the doped polysilicon is mainly to serve as one electrode of the capacitor. The thickness of the doped polysilicon is ≤100nm, for example, 50-100nm. Then, a medium is deposited. The material of the medium can be silicon oxide (SiO2), silicon nitride (Si3N4), etc. The deposition thickness of the medium ensures that the medium can completely fill the entire first deep hole. The thickness of the medium is, for example, 500-1000nm. After depositing the doped polysilicon and the medium, the medium and doped polysilicon on the top can be removed by chemical mechanical polishing (CMP) and other methods, leaving only the doped polysilicon and the medium inside the first deep hole.
[0015] In step 3), a capacitor dielectric is first deposited. The material of the capacitor dielectric can be silicon oxide (SiO2), silicon nitride (Si3N4), etc., and the thickness of the capacitor dielectric is, for example, 10-100nm; then, a second deep hole is etched in the first deep hole to form a second deep hole, and the diameter of the second deep hole is ≤100nm, for example, 50-100nm, and a certain thickness of the dielectric is retained at the bottom of the second deep hole, and the thickness of the retained dielectric is, for example, 10-100nm; then, silicon nitride is deposited, and the thickness of silicon nitride can be 10-20nm.
[0016] In step 4), doped amorphous silicon is first deposited, and the thickness of the doped amorphous silicon can be 100-200 nm; then, laser annealing is performed to form a polycrystalline silicon film with a large grain size, and the pulse laser energy during laser annealing is 1.5-3 J / cm 2 , the laser wavelength is 248-532nm, and the grain size of the formed polycrystalline silicon film is 1-4μm.
[0017] In step 5), the top active area is etched and transistors are prepared as DRAM read / write tubes; then, a medium is deposited. The material of the medium can be silicon oxide (SiO2), silicon nitride (Si3N4), etc., and the deposition thickness of the medium can be 400-600nm; after the medium is deposited, chemical mechanical polishing (CMP) and other methods are used for flattening, and the thickness of the medium and polysilicon film after flattening is controlled to be 10-20nm.
[0018] After planarization, the gate dielectric is first deposited. The material of the gate dielectric can be silicon oxide, high-K material (such as HfO high-K material), etc. The thickness of the gate dielectric can be 1-10nm; then, doped amorphous silicon is deposited. The thickness of the doped amorphous silicon can be 200-300nm; laser annealing is performed to form a doped polysilicon electrode. The pulse laser energy during laser annealing is 0.5-1J / cm 2 , the laser wavelength is 248-532nm.
[0019] In step 6), when etching the gate, the distance between the gate and the second deep hole is controlled to be 20-50 nm; a conventional method is used to etch the through hole, fill the metal and perform subsequent metal interconnection to complete the preparation of the memory.
[0020] The present invention also provides a memory, which is manufactured according to the above manufacturing method.
[0021] The memory of the present invention adopts a stacking method in which capacitors are arranged at the bottom and transistors are arranged at the top, thereby reducing the occupied area of the storage unit; at the same time, the transistors are prepared on a polycrystalline silicon film formed by laser annealing, and the grain size is much larger than the transistor size, which greatly improves the performance of the polycrystalline silicon thin film transistor; the transistor is prepared from a large-size polycrystalline silicon film formed after recrystallization, and has performance similar to that of single-crystalline silicon. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0023] Figure 1 is a schematic diagram of etching the first deep hole;
[0024] Figure 2 is a schematic diagram of depositing doped polysilicon;
[0025] Figure 3 is a schematic diagram of the deposition medium;
[0026] Figure 4Schematic diagram of removing top dielectric and doped polysilicon;
[0027] Figure 5 A schematic diagram of depositing capacitor dielectric, etching a second deep hole and depositing silicon nitride;
[0028] Figure 6 is a schematic diagram of depositing doped amorphous silicon;
[0029] Figure 7 Schematic diagram of forming polysilicon thin film by laser annealing;
[0030] Figure 8 Schematic diagram for etching the top active area and preparing the transistor;
[0031] Fig. 9 is a schematic diagram of the deposition medium;
[0032] Fig.10 A schematic diagram of planarizing dielectric and polysilicon films;
[0033] Fig.11 A schematic diagram of depositing a gate dielectric, doping amorphous silicon and laser annealing to form a doped polysilicon electrode;
[0034] Fig.12 A schematic diagram of etching to form a gate;
[0035] Fig.13 Schematic diagram of etching through holes and making metal interconnections.
[0036] Description of reference numerals:
[0037] 1: wafer; 2: dielectric; 3: first deep hole; 4: doped polysilicon; 5: dielectric; 6: capacitor dielectric; 7: second deep hole; 8: silicon nitride; 9: doped amorphous silicon; 10: polysilicon film; 11: dielectric; 12: gate dielectric; 13: doped polysilicon electrode; 14: metal. DETAILED DESCRIPTION
[0038] It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.
[0039] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form also includes the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this description, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.
[0040] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0041] Example 1
[0042] This embodiment provides a method for preparing a 1T1C DRAM memory, and the steps are as follows:
[0043] 1) Deposit dielectric and etch to form the first deep hole
[0044] like Figure 1 As shown, a medium 2 is first deposited on a wafer 1 (Peripheral CMOS) having a peripheral circuit. The material of the medium 2 may be silicon oxide (SiO2), silicon nitride (Si3N4), etc. The thickness of the medium 2 is ≥700nm, for example, 700nm-2μm; in the present embodiment, the material of the medium 2 is silicon oxide, and the thickness of the medium 2 is 1.5-2μm.
[0045] After depositing the medium 2, dry etching is used to form a first deep hole 3, and the diameter of the first deep hole 3 can be 200-500nm; when etching the first deep hole 3, ensure that the bottom of the first deep hole 3 is not connected to the wafer 1 to avoid damaging the CMOS circuit of the wafer 1; in this embodiment, the depth of the first deep hole 3 is 0.9-1μm.
[0046] 2) Deposition of doped polysilicon
[0047] like Figure 2 As shown, doped polysilicon 4 is deposited on the surface of the medium 2 as one electrode of the capacitor, and the thickness of the doped polysilicon 4 is ≤100nm; in this embodiment, the thickness of the doped polysilicon 4 is 50-100nm.
[0048] 3) Deposition medium
[0049] like Figure 3 As shown, a medium 5 is deposited on the surface of the doped polysilicon 4. The material of the medium 5 is silicon oxide (SiO2), silicon nitride (Si3N4), etc. The thickness of the medium 5 ensures that the medium 5 can be completely filled in the entire first deep hole 3; in this embodiment, the thickness of the medium 5 is 500-1000nm.
[0050] 4) Remove top dielectric and doped polysilicon
[0051] like Figure 4As shown, the top dielectric 5 and the top doped polysilicon 4 are removed in sequence by chemical mechanical polishing (CMP), and only the doped polysilicon 4 and the dielectric 5 inside the first deep hole 3 are retained.
[0052] 5) Deposit capacitor dielectric, etch the second deep hole and deposit silicon nitride
[0053] like Figure 5 As shown, first, a capacitor dielectric 6 is deposited. The material of the capacitor dielectric 6 is silicon oxide (SiO2), silicon nitride (Si3N4), etc. The thickness of the capacitor dielectric 6 is 10-100nm.
[0054] Next, a second deep hole 7 is formed by etching inside the first deep hole 3, wherein the diameter of the second deep hole 7 is ≤100 nm; in this embodiment, the diameter of the second deep hole 7 is 50-100 nm. When etching the second deep hole 7, a certain thickness of medium is retained at the bottom of the second deep hole 7, and the thickness of the retained medium is, for example, 10-100 nm.
[0055] Subsequently, silicon nitride 8 is deposited. The thickness of silicon nitride 8 may be 10-20 nm.
[0056] 6) Deposition of doped amorphous silicon
[0057] like Figure 6 As shown, doped amorphous silicon 9 is deposited, and the thickness of the doped amorphous silicon 9 may be 100-200 nm.
[0058] 7) Laser annealing
[0059] like Figure 7 As shown, the pulsed laser energy is 1.5-3J / cm 2 , laser annealing is performed using a laser with a laser wavelength of 248-532 nm to form a polycrystalline silicon film 10 with a large grain size, wherein the grain size of the polycrystalline silicon in the polycrystalline silicon film 10 is 1-4 μm.
[0060] 8) Etching the active area
[0061] like Figure 8 As shown, the top active area is etched and transistors (DRAM read / write tubes) are prepared.
[0062] 9) Deposition medium
[0063] like Fig. 9 As shown, a medium 11 is deposited. The material of the medium 11 is silicon oxide (SiO2), silicon nitride (Si3N4), etc. The deposition thickness of the medium 11 can be 400-600nm.
[0064] 10) Planarization
[0065] like Fig.10As shown, chemical mechanical polishing (CMP) or the like is used for planarization to remove a portion of the dielectric 11 and the polysilicon film 10, and the thickness of the dielectric 11 and the polysilicon film 10 after planarization is controlled to be 10-20 nm.
[0066] 11) Deposition of gate dielectric and doping of amorphous silicon, laser annealing
[0067] like Fig.11 As shown, a gate dielectric 12 is first deposited. The material of the gate dielectric 12 may be silicon oxide, HfO high-K material, etc. The thickness of the gate dielectric 12 may be 1-10 nm.
[0068] Subsequently, doped amorphous silicon is deposited, and the thickness of the doped amorphous silicon can be 200-300nm; the pulsed laser energy is 0.5-1J / cm 2 , laser annealing is performed using a laser with a wavelength of 248-532 nm to form a doped polysilicon electrode 13.
[0069] 12) Gate etching
[0070] like Fig.12 As shown, the doped polysilicon electrode 13 and the gate dielectric 12 are etched to form a gate, and the distance between the gate and the second deep hole 7 is controlled to be 20-50 nm.
[0071] 13) Etching through holes and metal interconnects
[0072] like Fig.13 As shown, the memory is prepared by etching through holes, filling metal 14 and subsequently interconnecting metal 14 in a conventional manner.
[0073] The memory of this embodiment adopts a stacking method in which a capacitor is arranged at the bottom and a transistor is arranged at the top, thereby reducing the occupied area of the memory unit; at the same time, the transistor is prepared on a polycrystalline silicon film formed by laser annealing, and the grain size is much larger than the transistor size. The mobility of the polycrystalline silicon is 400cm 2 / Vs, which greatly improves the performance of polysilicon thin film transistors.
[0074] Comparative Example 1
[0075] This comparative example is basically the same as Example 1 except for steps 6) and 7).
[0076] In this comparative example, a polycrystalline silicon film is prepared by a vapor phase method. The grain size of the polycrystalline silicon in the polycrystalline silicon film is only about 100nm, and the mobility is 80-100cm 2 / Vs, which is not conducive to improving the performance of transistors.
[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for preparing a memory, characterized in that: The steps include: 1) depositing a dielectric on a wafer having a peripheral circuit and etching to form a first deep hole; 2) depositing doped polysilicon and dielectric sequentially, and then removing the top dielectric and doped polysilicon; 3) depositing a capacitor dielectric and etching in the first deep hole to form a second deep hole, and then depositing silicon nitride; 4) Deposition of doped amorphous silicon and laser annealing to form a polycrystalline silicon film with large grain size; 5) Etching the top active area and preparing transistors, depositing dielectrics and planarizing, then depositing gate dielectrics and doped amorphous silicon in sequence, and laser annealing to form doped polysilicon electrodes; 6) Etching to form a gate, then etching a through hole and making metal interconnections to complete the memory preparation.
2. The preparation method according to claim 1, characterized in that: In step 1), the thickness of the medium is ≥700 nm; the diameter of the first deep hole is 200-500 nm.
3. The preparation method according to claim 1, characterized in that: In step 2), the thickness of the doped polysilicon is ≤100 nm.
4. The preparation method according to claim 1, characterized in that: In step 3), the diameter of the second deep hole is ≤100 nm; the thickness of silicon nitride is 10-20 nm.
5. The preparation method according to claim 1, characterized in that: In step 4), the thickness of the doped amorphous silicon is 100-200 nm; the grain size of the polycrystalline silicon film is 1-4 μm.
6. The preparation method according to claim 1, characterized in that: In step 5), the thickness of the dielectric and polysilicon film after planarization is controlled to be 10-20 nm; the thickness of the gate dielectric is controlled to be 1-10 nm; and the thickness of the doped amorphous silicon is controlled to be 200-300 nm.
7. The preparation method according to claim 1, characterized in that: In step 6), the distance between the control gate and the second deep hole is 20-50 nm.
8. The preparation method according to claim 1, characterized in that: The material of the dielectric is silicon oxide or silicon nitride; the material of the capacitor dielectric is silicon oxide or silicon nitride; the material of the gate dielectric is silicon oxide or high-K material.
9. The preparation method according to claim 1, characterized in that: In step 4), the pulse laser energy during laser annealing is 1.5-3J / cm 2 , the laser wavelength is 248-532nm; in step 5), the pulse laser energy during laser annealing is 0.5-1J / cm 2 , the laser wavelength is 248-532nm.
10. A memory, characterized in that: Prepared according to any one of the preparation methods of claims 1-9.