Semiconductor device and data storage system including same

Abstract

The invention provides a semiconductor device and a data storage system including the same. The semiconductor device may include: a plate layer; gate electrodes spaced apart from each other in a first direction perpendicular to the upper surface of the plate layer on the plate layer, extending to different lengths in a second direction perpendicular to the first direction, and forming a step region; channel structures passing through the gate electrode, extending in the first direction, and each including a channel layer; an isolation region passing through the gate electrode and extending in the first direction and the second direction; sacrificial insulating layers on the same height as the gate electrodes, respectively; a through via passing through the sacrificial insulating layer and extending in the first direction; a dam structure surrounding the through passage; and a protection structure horizontally spaced apart from the dam structure and having a closed loop shape around the dam structure in plan view.

Description

Technical Field

[0001] Aspects of the present disclosure relate to a semiconductor device and to a data storage system including the semiconductor device. Background Art

[0002] There is an increasing need for semiconductor devices that can store large amounts of data in data storage systems. Therefore, methods for increasing the data storage capacity of semiconductor devices have been studied. For example, one proposed method for increasing the data storage capacity of semiconductor devices is to arrange storage cells three-dimensionally rather than two-dimensionally. Summary of the invention

[0003] Some embodiments of the present disclosure provide semiconductor devices with improved reliability.

[0004] Some embodiments of the present disclosure provide a data storage system including a semiconductor device having improved reliability.

[0005] According to some embodiments of the present disclosure, a semiconductor device may include: a first semiconductor structure, the first semiconductor structure including a substrate, a circuit device located on the substrate, and a circuit interconnection line located on the circuit device; and a second semiconductor structure, the second semiconductor structure is located on the first semiconductor structure and has a through interconnection region, wherein the second semiconductor structure includes: a plate layer; a gate electrode, the gate electrodes are spaced apart from each other on the plate layer along a first direction perpendicular to an upper surface of the plate layer, the gate electrodes extend to different lengths along a second direction perpendicular to the first direction and form a step region; an interlayer insulating layer, the interlayer insulating layer and the gate electrode are alternately stacked; a channel structure, the channel structure extends through the gate electrode along the first direction and each includes a channel layer; an isolation region, the isolation region extending The invention relates to a semiconductor structure comprising a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer comprises a first semiconductor layer and a second semiconductor layer. The first semiconductor layer comprises a first semiconductor layer and a second semiconductor layer. The first semiconductor layer comprises a first semiconductor layer and a second semiconductor layer. The first semiconductor layer comprises a first semiconductor layer and a second semiconductor layer. The first semiconductor layer comprises a first semiconductor layer and a second semiconductor layer. The first semiconductor layer comprises a first semiconductor layer and a second semiconductor layer. The first semiconductor layer comprises a first semiconductor layer and a second semiconductor layer. The first semiconductor layer comprises a first semiconductor layer and a second semiconductor layer. The first semiconductor layer comprises a first semiconductor layer and a second semiconductor layer. The first semiconductor layer comprises a first semiconductor layer and a second semiconductor layer. The first semiconductor layer comprises a first semiconductor layer and a second semiconductor layer.

[0006] According to some embodiments of the present disclosure, a semiconductor device includes: a plate layer; a gate electrode, which is spaced apart from each other on the plate layer along a first direction perpendicular to an upper surface of the plate layer, extends to different lengths along a second direction perpendicular to the first direction and forms a step region; a channel structure, which extends through the gate electrode along the first direction and each includes a channel layer; an isolation region, which extends through the gate electrode and extends along the first direction and the second direction; a sacrificial insulating layer, which is parallel to the gate electrode, respectively; a through-path, which extends through the sacrificial insulating layer along the first direction; a dam structure, which surrounds the through-path; and a protective structure, which is horizontally spaced apart from the dam structure and has a closed loop shape surrounding the dam structure in a plan view.

[0007] According to some embodiments of the present disclosure, a data storage system includes: a semiconductor memory device, the semiconductor memory device including a first semiconductor structure having a circuit device, a second semiconductor structure located on a first side of the first semiconductor structure, and an input / output pad electrically connected to the circuit device; and a controller, the controller being electrically connected to the semiconductor memory device through the input / output pad and configured to control the semiconductor memory device, wherein the second semiconductor structure includes: a plate layer; gate electrodes, the gate electrodes being spaced apart from each other on the plate layer along a first direction perpendicular to an upper surface of the plate layer, the gate electrodes extending to different lengths along a second direction perpendicular to the first direction and forming a stepped region; and a channel. structures, the channel structures extending through the gate electrode along the first direction and each including a channel layer; an isolation region extending through the gate electrode and extending along the first direction and the second direction; a sacrificial insulating layer, the sacrificial insulating layers being parallel to the gate electrodes, respectively; a through-path extending through the sacrificial insulating layer along the first direction; a dam structure surrounding the through-path; and a protective structure horizontally spaced apart from the dam structure and surrounding the dam structure, wherein each of the gate electrodes includes a first region located on the outer side of the protective structure and a second region surrounded by the protective structure, and wherein the first region and the second region are electrically isolated from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a plan view showing a semiconductor device according to some embodiments of the present disclosure;

[0010] Figure 2A , Figure 2B and Figure 2C is a cross-sectional view showing a semiconductor device according to some embodiments of the present disclosure;

[0011] Figure 3A , Figure 3B and Figure 3C is a cross-sectional view showing a semiconductor device according to some embodiments of the present disclosure;

[0012] Figure 4 is a cross-sectional view showing a semiconductor device according to some embodiments of the present disclosure;

[0013] Figure 5A and Figure 5B are plan views and cross-sectional views showing semiconductor devices according to some embodiments of the present disclosure;

[0014] Fig. 6A and Figure 6B is a plan view showing a semiconductor device according to some embodiments of the present disclosure;

[0015] Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A and Fig. 11B is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0016] Fig.12 is a diagram illustrating a data storage system including a semiconductor device according to some embodiments of the present disclosure;

[0017] Fig.13 is a perspective view showing a data storage system including a semiconductor device according to some embodiments of the present disclosure; and

[0018] Fig.14 is a cross-sectional view illustrating a semiconductor package according to some embodiments of the present disclosure.

[0019] Specific implementation method

[0020] Hereinafter, some embodiments of the present disclosure will be described with reference to the accompanying drawings as follows.

[0021] Figure 1 is a plan view showing a semiconductor device according to some embodiments of the present disclosure.

[0022] Figure 2A , Figure 2B and Figure 2Cis a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. Figure 2A is along Figure 1 The cross section taken along the midline Ⅰ-Ⅰ', Figure 2B is along Figure 1 The cross section taken along the midline II-II', and Figure 2C is along Figure 1 Cross section taken along the midline II-II'.

[0023] refer to Figure 1 , Figure 2A , Figure 2B and Figure 2C , the semiconductor device 100 may include a peripheral circuit region (also referred to herein as a peripheral circuit structure) PERI and a memory cell region CELL, the peripheral circuit region PERI may be a first semiconductor structure including a substrate 201, and the memory cell region CELL is a second semiconductor structure including a board layer 101. The memory cell region CELL may be on the peripheral circuit region PERI (e.g., located above the peripheral circuit region PERI in the Z direction). On the contrary, in some embodiments, the memory cell region CELL may be below the peripheral circuit region PERI.

[0024] The peripheral circuit region PERI may include a substrate 201 , an impurity region 205 and a device isolation layer 210 in the substrate 201 , a circuit device 220 on the substrate 201 , a peripheral region insulating layer 290 , a circuit contact plug 270 , and a circuit interconnection line 280 .

[0025] The substrate 201 may have an upper surface extending in the X direction and the Y direction. The X direction, the Y direction, and the Z direction may be perpendicular to each other. The active region may be defined on the substrate 201 by the device isolation layer 210. The impurity region 205 including impurities may be in a portion of the active region. The substrate 201 may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The substrate 201 may be provided as a bulk wafer or an epitaxial layer.

[0026] The circuit devices 220 may include planar transistors. Each of the circuit devices 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. The impurity regions 205 may be source / drain regions on both sides of the circuit gate electrode 225 in the substrate 201.

[0027] The peripheral region insulating layer 290 may be located on the circuit device 220 on the substrate 201. The peripheral region insulating layer 290 may include a plurality of insulating layers that may be formed in different manufacturing processes. The peripheral region insulating layer 290 may be formed of an insulating material.

[0028] The circuit contact plug 270 and the circuit interconnection line 280 may form a circuit interconnection structure electrically connected to the circuit device 220 and the impurity region 205. The circuit contact plug 270 may have a cylindrical shape, and the circuit interconnection line 280 may have a linear shape. An electrical signal may be applied to the circuit device 220 through the circuit contact plug 270 and the circuit interconnection line 280. In an area not shown, the circuit contact plug 270 may also be connected to the circuit gate electrode 225. The circuit interconnection line 280 may be connected to the circuit contact plug 270 and may be located in a plurality of layers. The circuit contact plug 270 and the circuit interconnection line 280 include conductive materials such as tungsten (W), copper (Cu) or aluminum (Al), etc., and each component may also include a diffusion barrier. In some embodiments, the number of layers of the circuit contact plug 270 and the circuit interconnection line 280 may vary.

[0029] The memory cell region CELL may have a first region R1 and a second region R2, and may include: a plate layer 101, a gate electrode 130 stacked on the plate layer 101, a channel structure CH extending in the first region R1 and passing through the stack structure of the gate electrode 130, a first isolation region MS1 ​​and a second isolation region MS2a and MS2b extending and passing through the stack structure of the gate electrode 130, a sacrificial insulating layer 118 in parallel with the gate electrode 130 in the second region R2, a through-path 170 passing through the stack structure of the sacrificial insulating layer 118 and extending to the peripheral circuit region PERI and forming a through-path 170 passing through the interconnection region TR, a dam structure DS surrounding the through-path 170, and a protection structure GS spaced apart from and surrounding the dam structure DS.

[0030] The memory cell region CELL may include: a first horizontal conductive layer 102 located on the plate layer 101 in the first region R1, a horizontal insulating layer 110 arranged in parallel with the first horizontal conductive layer 102 in the second region R2, a second horizontal conductive layer 104 located on the first horizontal conductive layer 102 and the horizontal insulating layer 110, a substrate insulating layer 109 extending and penetrating the plate layer 101, an interlayer insulating layer 120 alternately stacked with gate electrodes 130, an upper isolation region SS extending and penetrating a portion of the gate electrode 130, a dummy channel structure DCH extending in the second region R2 and passing through the stacked structure of the gate electrode 130, a gate contact plug 175 connected to the gate electrode 130, an upper plug 178, an interconnection line 180, and a cell region insulating layer 190.

[0031] In the memory cell region CELL, in the first region R1, the gate electrode 130 may be stacked in a vertical direction and the channel structure CH may be arranged, and the memory cell may be disposed in the first region R1, while in the second region R2, the gate electrode 130 may extend to different lengths, and the second region R2 may electrically connect the memory cell to the peripheral circuit structure PERI. The second region R2 may be disposed on at least one end of the first region R1 in at least one direction (e.g., an X direction).

[0032] The plate layer 101, the first horizontal conductive layer 102, and the second horizontal conductive layer 104 may form a source structure including a common source line of the semiconductor device 100. The plate layer 101 may have a plate shape and may be used as at least a portion of the common source line. The plate layer 101 may have an upper surface extending in the X direction and the Y direction. The plate layer 101 may include a conductive material. For example, the plate layer 101 may include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor may include silicon, germanium, or silicon germanium. The plate layer 101 may also include impurities. For example, the plate layer 101 may be provided as a polycrystalline semiconductor layer such as a polycrystalline silicon layer, or an epitaxial layer.

[0033] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may be sequentially stacked on the upper surface of the plate layer 101 in the first region R1. The first horizontal conductive layer 102 may be used as a portion of a common source line of the semiconductor device 100 and may be used as a common source line together with the plate layer 101. Figure 2B As shown, the first horizontal conductive layer 102 may be directly connected to the channel layer 140 around the channel layer 140 of each of the channel structures CH.

[0034] The second horizontal conductive layer 104 may contact the board layer 101 in some areas where the first horizontal conductive layer 102 and the horizontal insulating layer 110 are not provided. The second horizontal conductive layer 104 may cover the ends of the first horizontal conductive layer 102 or the horizontal insulating layer 110 in the above areas, and the second horizontal conductive layer 104 may be bent and may extend to the board layer 101.

[0035] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may include a semiconductor material such as polysilicon. In this case, at least the first horizontal conductive layer 102 may be a layer doped with impurities of the same conductivity type as that of the plate layer 101 .

[0036] The horizontal insulating layer 110 may be located on the plate layer 101 in at least a portion of the second region R2 and parallel to the first horizontal conductive layer 102. The horizontal insulating layer 110 may include first to third horizontal insulating layers 111, 112, and 113 sequentially stacked on the plate layer 101. The horizontal insulating layer 110 may be a layer remaining after a portion is replaced by the first horizontal conductive layer 102 in a process of manufacturing the semiconductor device 100.

[0037] The horizontal insulating layer 110 may include silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The first horizontal insulating layer 111 and the third horizontal insulating layer 113 may include different insulating materials from the second horizontal insulating layer 112. The first horizontal insulating layer 111 and the third horizontal insulating layer 113 may include the same material. For example, the first horizontal insulating layer 111 and the third horizontal insulating layer 113 may be formed of the same material as the interlayer insulating layer 120, and the second horizontal insulating layer 112 may be formed of the same material as the sacrificial insulating layer 118.

[0038] The substrate insulating layer 109 may extend in a portion of the second region R2 and may be located in the plate layer 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104. The upper surface of the substrate insulating layer 109 may be coplanar with the upper surface of the second horizontal conductive layer 104, but the present disclosure is not limited thereto. The substrate insulating layer 109 may include an insulating material such as silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. In some embodiments, the substrate insulating layer 109 may be arranged as a plurality of layers to surround each through-via in the through-via 170.

[0039] The gate electrodes 130 may be spaced apart from each other in the vertical direction on the plate layer 101, may be stacked, and may form a stacked structure. The gate electrode 130 may include a lower gate electrode 130L forming a gate of a ground selection transistor, a memory gate electrode 130M forming a plurality of memory cells, and an upper gate electrode 130U forming a gate of a string selection transistor. Depending on the capacity of the semiconductor device 100, the number of memory gate electrodes included in the memory cell may be determined. In some embodiments, the number of each of the upper gate electrode 130U and the lower gate electrode 130L may be 1 to 4 or more, and may have a structure that is the same as or different from that of the memory gate electrode 130M. In some embodiments, the gate electrode 130 may also include a gate electrode 130 disposed on one side of the upper gate electrode 130U and / or the lower gate electrode 130L and forming an erase transistor for an erase operation using a gate induced drain leakage (GIDL) phenomenon. Also, a portion of the gate electrodes 130 (eg, the memory gate electrode 130M adjacent to the upper gate electrode 130U or the lower gate electrode 130L) may be a dummy gate electrode.

[0040] The gate electrodes 130 may be stacked in the first region R1 in the vertical direction and may be spaced apart from each other, may extend from the first region R1 to the second region R2 at different lengths, and may form a stepped structure having a staircase shape. The gate electrodes 130 may form a stepped structure between the gate electrodes 130 along the X direction, such as Figure 2C As shown. In some embodiments, at least a portion of the gate electrodes 130 (for example, two to six gate electrodes 130) may form a gate group, and the gate group may form a step structure in the X direction. In this case, the gate electrode 130 forming one of the gate groups may have a step structure in the Y direction. Through the step structure, the gate electrode 130 may form a stepped shape in which the lower gate electrode 130 may extend longer in length than the upper gate electrode 130 above the lower gate electrode 130 in one or more horizontal directions, and the stepped shape may provide an end portion exposed upward from the interlayer insulating layer 120. In some embodiments, the gate electrode 130 may have an increased thickness at the end portion.

[0041] like Figure 1 As shown, the gate electrodes 130 may be isolated from each other in the Y direction due to the first isolation region MS1 ​​extending in the X direction. The gate electrodes 130 between a pair of first isolation regions MS1 may form a memory block, but the embodiment of the memory block is not limited thereto. A portion of the gate electrodes 130 (e.g., the memory gate electrode 130M) may form a layer in the memory block.

[0042] The gate electrode 130 may include a metal material such as tungsten (W). In example embodiments, the gate electrode 130 may include polysilicon or a metal silicide material. In some embodiments, the gate electrode 130 may further include a diffusion barrier. For example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0043] Interlayer insulating layers 120 may be between gate electrodes 130. Similar to gate electrodes 130, interlayer insulating layers 120 may be spaced apart from each other in a direction perpendicular to the upper surface of plate layer 101 and may extend in the X direction. Interlayer insulating layers 120 may include an insulating material such as silicon oxide or silicon nitride.

[0044] The first isolation region MS1 ​​and the second isolation regions MS2a and MS2b may pass through the gate electrode 130 and may extend in the X direction. The first isolation region MS1 ​​and the second isolation regions MS2a and MS2b may be parallel to each other. The first isolation region MS1 ​​and the second isolation regions MS2a and MS2b may pass through all the gate electrodes 130 stacked on the board layer 101 and may be connected to the board layer 101. The first isolation region MS1 ​​may extend as an integrated region along the X direction, and the second isolation regions MS2a and MS2b may extend intermittently between a pair of first isolation regions MS1, or the second isolation regions MS2a and MS2b may be only in a portion of the region. For example, the second isolation region (also referred to as the second central isolation region) MS2a may extend from the first region R1 as an integrated region and may extend intermittently from the second region R2 along the X direction. The second isolation region (also referred to as the second auxiliary isolation region) MS2b may be only in the second region R2 and may extend intermittently along the X direction. However, in some embodiments, the arrangement order and number of the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b are not limited to Figure 1 The first isolation region MS1 ​​and the second isolation regions MS2a and MS2b may not overlap with the through interconnection region TR but may be spaced apart from the through interconnection region TR.

[0045] like Figure 2A and Figure 2B As shown, the gate isolation insulating layer 105 may be located in the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b. Due to the high aspect ratio of the gate isolation insulating layer, the gate isolation insulating layer 105 may have a shape in which its width decreases toward the plate layer 101, but the present disclosure is not limited thereto. The gate isolation insulating layer 105 may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, a conductive layer may also be provided in the gate isolation insulating layer 105 in the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b. In this case, the conductive layer may be used as a common source line or a contact plug connected to the common source line of the semiconductor device 100.

[0046] The upper isolation region SS may extend in the X direction between the first isolation region MS1 ​​and the second central isolation region MS2a and between the second central isolation regions MS2a in the first region R1. Figure 1 The upper isolation region SS may penetrate a portion of the gate electrode 130 including the uppermost gate electrode 130U among the gate electrodes 130. Figure 2BAs shown, for example, the upper isolation region SS can isolate the four gate electrodes 130 including the upper gate electrode 130U from each other in the Y direction. However, the number of gate electrodes 130 isolated by the upper isolation region SS can vary in different embodiments or implementations. The upper gate electrodes 130U isolated by all the upper isolation regions SS can form different string selection lines. The upper isolation region SS may include an insulating material. The insulating material may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0047] The channel structure CH may extend or pass through the gate electrode 130, may extend in the Z direction, and may be connected to the board layer 101. Each of the channel structures CH may form a memory cell string, and the channel structures CH may be spaced apart from each other while forming rows and columns in the first region R1. The channel structure CH may form a grid pattern or be formed in a zigzag pattern in one direction. The channel structure CH may have a columnar shape, and according to an aspect ratio, the channel structure CH may have an inclined side surface so that its width decreases toward the board layer 101. The channel structure CH may include a lower channel structure CH1 and an upper channel structure CH2 that may be stacked in a vertical direction. The channel structure CH may have a form in which the lower channel structure CH1 and the upper channel structure CH2 are connected to each other, and may have a curved portion due to a difference in width in a connection region.

[0048] like Figure 2B As shown in the enlarged view in FIG. 1 , each of the channel structures CH may include a channel layer 140 located in the channel hole, a gate dielectric layer 145, a channel filling insulating layer 150, and a channel pad 155. The channel layer 140 may be formed in a ring shape surrounding the channel filling insulating layer 150, but in some embodiments, the channel layer 140 may have a columnar shape such as a cylindrical shape or a prism shape, and the channel filling insulating layer 150 may not exist or be omitted. The lower portion of the channel layer 140 may be connected to the first horizontal conductive layer 102. The channel layer 140 may include a semiconductor material such as polycrystalline silicon or single crystal silicon.

[0049] The channel pad 155 may be located on the channel layer 140 in the channel structure CH. The channel pad 155 may cover the upper surface of the channel filling insulating layer 150 and may be electrically connected to the channel layer 140. The channel pad 155 may include, for example, doped polysilicon.

[0050] The gate dielectric layer 145 may be between the gate electrode 130 and the channel layer 140. Although not specifically shown, the gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a blocking layer stacked sequentially starting from the channel layer 140. The tunneling layer may tunnel charges into the charge storage layer, and may include, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N4 ), silicon oxynitride (SiON), or a combination thereof. The charge storage layer may be a charge trapping layer or a floating gate conductive layer. The blocking layer may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), a high-κ dielectric material, or a combination thereof. In some embodiments, at least a portion of the gate dielectric layer 145 may extend in a horizontal direction along the gate electrode 130. In this case, a portion of the gate dielectric layer 145 may refer to a portion of the gate electrode 130.

[0051] The dummy channel structure DCH may pass through the gate electrode 130, may extend in the Z direction and may be connected to the board layer 101. The dummy channel structure DCH may have an internal structure that is the same as or similar to the channel structure CH, and may have a height that is substantially the same as the height of the channel structure CH. However, unlike the channel structure CH in the semiconductor device 100, the dummy channel structure DCH may not be electrically connected to the upper interconnect structure or may not form a memory cell string. The dummy channel structure DCH may be spaced apart from each other in rows and columns in the second region R2. The dummy channel structure DCH may be in the first region R1 adjacent to the second region R2. The dummy channel structure DCH may be configured to support a stacked structure of the interlayer insulating layer 120 during the process of manufacturing the semiconductor device 100.

[0052] like Figure 2A As shown, the dummy channel structure DCH in the second region R2 may penetrate the horizontal insulating layer 110 along the Z direction. The lower portion of the dummy channel structure DCH may be surrounded by the second horizontal conductive layer 104 and the horizontal insulating layer 110. Specifically, the dummy channel structure DCH may penetrate the interlayer insulating layer 120 and the gate electrode 130, and may penetrate the second horizontal conductive layer 104 and the horizontal insulating layer 110 at the lower end. Each of the dummy channel structures DCH may include a channel layer 140, a gate dielectric layer 145, a channel filling insulating layer 150, and a channel pad 155 located in a dummy channel hole, and may be similar in structure to the channel structure CH. In addition, similar to the channel structure CH, each of the dummy channel structures DCH may have a shape in which a lower dummy channel structure and an upper dummy channel structure are stacked, and may have a bent portion accordingly.

[0053] The through via 170 may electrically connect the memory cell region CELL and the peripheral circuit structure PERI to each other. The through via 170 may form a through interconnect region TR together with the sacrificial insulating layer 118, the interlayer insulating layer 120, and the substrate insulating layer 109. In some embodiments, the region in the dam structure DS may be referred to as a through interconnect region TR. Alternatively, the region in the protection structure GS may be referred to as a through interconnect region TR.

[0054] For example, one through interconnect region TR may be provided for each memory block, and the through interconnect region TR may be disposed in the first region R1. In this case, in the first region R1, the sacrificial insulating layer 118 of the through interconnect region TR may be at a height corresponding to the entire gate electrode 130 (e.g., parallel to the gate electrode 130), and the dam structure DS and the protection structure GS surrounding the through interconnect region TR may be in contact with or adjacent to the sacrificial insulating layer 118. The number, size, arrangement type, and shape of the through interconnect regions TR may vary in different embodiments or implementations. For example, in some embodiments, one through interconnect region TR may be provided for each plurality of memory blocks. As Figure 1 As shown, the through interconnection region TR may be spaced apart from the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b. For example, the through interconnection region TR may be spaced apart from the first isolation regions MS1 adjacent to each other in the Y direction and may be disposed between a pair of first isolation regions MS1.

[0055] The through via 170 may extend through the mold structure of the sacrificial insulating layer 118 in a vertical direction and may extend into the peripheral circuit structure PERI. The through via 170 may electrically connect the gate electrode 130 and / or the channel structure CH of the memory cell region CELL to the circuit device 220 of the peripheral circuit structure PERI. The through via 170 may be connected to the upper plug 178 and the interconnection line 180 at an upper portion. The through via 170 may be connected to the circuit interconnection line 280 of the peripheral circuit structure PERI at a lower portion.

[0056] The through via 170 may penetrate the interlayer insulating layer 120 and the sacrificial insulating layer 118, and may penetrate the substrate insulating layer 109 at the bottom. In different embodiments and implementations, the number and arrangement of the through vias 170 in the through interconnection region TR may vary. The through via 170 may include a conductive material such as tungsten (W), copper (Cu), aluminum (Al), etc.

[0057] In the through-interconnect region TR, the sacrificial insulating layer 118 may be at a height substantially the same as that of the gate electrode 130 (e.g., parallel to the gate electrode 130), respectively. The sacrificial insulating layer 118 may be alternately stacked with the interlayer insulating layer 120 in the through-interconnect region TR, and a molded structure may be formed. The sacrificial insulating layer 118 may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. The sacrificial insulating layer 118 may be formed of a material different from that of the interlayer insulating layer 120. In the through-interconnect region TR, the width of the sacrificial insulating layer 118 may be greater than the width of the substrate insulating layer 109, but the present disclosure is not limited thereto, and in different embodiments and implementations, the sacrificial insulating layer 118 may have the same width.

[0058] The dam structure DS may surround the through interconnection region TR in the second region R2. Figure 1 As shown, the through interconnect region TR may be closer to one side relative to the center between the adjacent first isolation regions MS1 in the Y direction, and therefore, the dam structure DS may also be closer to one of the first isolation regions MS1. The dam structure DS may have a closed loop shape (e.g., a single closed loop shape) surrounding the through via 170 in a plan view, such as a quadrilateral ring, a circular ring, or an elliptical ring shape. In a plan view, the dam structure DS may include a horizontal region extending in the X direction and a vertical region extending in the Y direction.

[0059] like Figure 2A and Figure 2C As shown, the dam structure DS may extend or pass through the interlayer insulating layer 120, may extend in the Z direction, may be connected to the plate layer 101, and may be on the boundary between the gate electrode 130 and the sacrificial insulating layer 118. The outer side surface of the dam structure DS may contact the gate electrode 130, and the inner side surface of the dam structure DS may contact the sacrificial insulating layer 118. The dam structure DS may be at a height substantially the same as that of the channel structure CH and the dummy channel structure DCH (e.g., coplanar therewith), which may be because the dam structure DS may be formed in a trench formed in the same process as that of forming the channel structure CH and the dummy channel structure DCH. Similar to the arrangement of the dummy channel structure DCH in the second region R2, the dam structure DS may extend or pass through the second horizontal conductive layer 104 and the horizontal insulating layer 110.

[0060] The dam structure DS may have an internal structure that is the same as or similar to that of the dummy channel structure DCH and the channel structure CH. Similar to the channel structure CH, the dam structure DS may include a channel layer 140, a gate dielectric layer 145, a channel filling insulating layer 150, and a channel pad 155 located in the trench. Similar to the channel structure CH, the dam structure DS may have a shape in which a lower dam structure and an upper dam structure are stacked, and may have a curved portion accordingly.

[0061] The protection structure GS may be horizontally spaced apart from the dam structure DS in the second region R2 and may surround the dam structure DS. In a plan view, the protection structure GS may have a closed loop shape (e.g., a single closed loop shape) similar to the dam structure DS and may have, for example, a quadrilateral ring shape, a circular ring shape, or an elliptical ring shape. The protection structure GS may also be spaced apart from the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b. In example embodiments, the spacing distance D1 between the protection structure GS and the dam structure DS may vary.

[0062] In a plan view, the protective structure GS may include a first horizontal region GSh1 and a second horizontal region GSh2 extending in the X direction and a first vertical region GSl1 and a second vertical region GSl2 extending in the Y direction. Each of the first horizontal region GSh1 and the second horizontal region GSh2 and the first vertical region GSl1 and the second vertical region GSl2 may extend in the form of a line in a plan view. The first horizontal region GSh1 and the second horizontal region GSh2 may be in a straight line with the second isolation regions MS2a and MS2b, but the present disclosure is not limited thereto. The second width W2 of the first horizontal region GSh1 and the second horizontal region GSh2 may be substantially equal to the first width W1 of the first isolation region MS1 ​​and the second isolation region MS2a and MS2b. However, in some embodiments, the second width W2 may be less than or greater than the first width W1. The second width W2 of the first horizontal region GSh1 and the second horizontal region GSh2 may be substantially the same as the width of the first vertical region GSl1 and the second vertical region GSl2, but the present disclosure is not limited thereto.

[0063] like Figure 2A and Figure 2CAs shown, the protection structure GS may pass through the interlayer insulating layer 120 and the gate electrode 130, may extend in the Z direction, and may be connected to the board layer 101. Both the outer side surface and the inner side surface of the protection structure GS may contact the gate electrode 130. In a plan view, the protection structure GS may isolate (e.g., completely isolate) the region of the gate electrode 130 inside the protection structure GS from the region of the gate electrode 130 outside the protection structure GS. The protection structure GS may isolate each of the gate electrodes 130 into two electrically isolated regions. The protection structure GS may be at a height substantially the same as that of the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b (e.g., coplanar therewith), which may be because the protection structure GS is formed in a trench formed in the same process as that of forming the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b. Similar to the arrangement of the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b in the second region R2, the protection structure GS may be located in a region where the second horizontal conductive layer 104 is in direct contact with the board layer 101. Therefore, the protection structure GS may extend or pass through the second horizontal conductive layer 104 at a lower portion, may contact the horizontal conductive layer 104, and may be spaced apart from the first horizontal conductive layer 102 and the horizontal insulating layer 110. The height of the protection structure GS may be different from the height of the dam structure DS. The height at which the upper end of the protection structure GS is located may be higher than the height of the upper end of the dam structure DS.

[0064] The internal structure of the protection structure GS may be different from the internal structure of the dam structure DS. The protection structure GS may have an internal structure that is the same as or similar to the internal structure of the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b. The protection structure GS may include a gate isolation insulating layer 105, which may be a single insulating layer in a trench, such as the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b. Unlike the dam structure DS, the protection structure GS may have a side surface without a curved portion. However, in some embodiments, similar to the channel structure CH, in the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b and the protection structure GS, the lower region and the upper region may be stacked, and a curved portion may be formed therein.

[0065] The semiconductor device 100 may include a dam structure DS to prevent the material forming the gate electrode 130 from flowing into the through-interconnection region TR during the manufacturing process and to control the region in which the gate electrode 130 extends. However, since the dam structure DS is formed together with the channel structure CH, the side surface may have unevenness, and misalignment may occur between the lower dam structure and the upper dam structure. In this case, defects such as vertical connection of the gate electrode 130 may occur in the region adjacent to the dam structure DS. However, the semiconductor device 100 may also include a protection structure GS so that the gate electrode 130 inside the protection structure GS can be completely isolated from the gate electrode 130 outside the protection structure GS. Therefore, even when a defect occurs in the gate electrode 130 in the region adjacent to the dam structure DS, the operation of the semiconductor device 100 will not be affected.

[0066] The gate contact plug 175 , the upper plug 178 , and the interconnection line 180 may be part of an upper interconnection structure electrically connected to the memory cells in the memory cell region CELL.

[0067] like Figure 2C As shown, in the second region R2, the gate contact plug 175 can be connected to the gate electrode 130 whose upper surface is exposed among the gate electrodes 130. In some embodiments, the gate contact plug 175 can extend or pass through the gate electrode 130, and can extend into the peripheral circuit structure PERI. In this case, each of the gate contact plugs 175 can be connected to the uppermost gate electrode 130 and can be spaced apart from the lower gate electrode 130 by another insulating layer. The upper plug 178 can be connected to the upper end of the through-path 170 and the upper end of the channel structure CH. The interconnection line 180 can be electrically connected to, for example, the through-path 170, the gate electrode 130 and the channel structure CH. In different embodiments and implementations, the number of contact plugs and interconnection lines included in the interconnection structure can vary. Each of the gate contact plug 175, the upper plug 178 and the interconnection line 180 can include a conductive material, such as tungsten (W), copper (Cu), aluminum (Al), etc.

[0068] The cell region insulating layer 190 may cover the gate electrode 130. The cell region insulating layer 190 may be formed of an insulating material, and may be formed of a plurality of insulating layers.

[0069] FIG. 3A to FIG. 3C is a cross-sectional view illustrating a semiconductor device according to some embodiments. FIG. 3A to FIG. 3C Shows the corresponding Figure 2A area.

[0070] refer to Figure 3A In the semiconductor device 100a, the arrangement position of the sacrificial insulating layer 118 adjacent to the through interconnection region TR may be different from that according to Figures 1 to 2C The end of the sacrificial insulating layer 118 in the horizontal direction may be between the dam structure DS and the protection structure GS. Therefore, both the outer and inner surfaces of the dam structure DS may contact the sacrificial insulating layer 118. Both the outer and inner surfaces of the protection structure GS may contact the gate electrode 130.

[0071] refer to Figure 3B , in the semiconductor device 100b, the lower dam structure DS1 and the upper dam structure DS2 of the dam structure DS may not be aligned with each other. The lower dam structure DS1 and the upper dam structure DS2 may be offset from each other in the horizontal direction, and the length of the offset may vary in different embodiments and implementations. The upper dam structure DS2 may include an area connected to the side surface of the lower dam structure DS1. In this case, the height at which the lower end of the upper dam structure DS2 is located may be lower than the height of the upper end of the lower dam structure DS1. However, in some embodiments, the lower end of the upper dam structure DS2 may be on the lower dam structure DS1. In some embodiments, the lower dam structure DS1 and the upper dam structure DS2 may not be connected to each other and may be completely offset. In some embodiments, similar to the dam structure DS, at least one dummy channel structure in the dummy channel structure DCH may have a shape in which the lower area and the upper area are offset from each other.

[0072] refer to Figure 3C , in the semiconductor device 100c, the horizontal insulating layer 110 may not be in the through-interconnection region TR. In the through-interconnection region TR, the second horizontal conductive layer 104 may be in direct contact with the plate layer 101. Therefore, similar to the arrangement of the protection structure GS, the dam structure DS may extend or pass through the second horizontal conductive layer 104 at the lower portion, may be in contact with the horizontal conductive layer 104, and may be spaced apart from the first horizontal conductive layer 102 and the horizontal insulating layer 110.

[0073] Figure 4 is a cross-sectional view illustrating a semiconductor device according to some embodiments. Figure 4 Shows the corresponding Figure 2A area.

[0074] refer to Figure 4 In the semiconductor device 100d, the internal structures of the dummy channel structure DCH and the dam structure DS may be different from those according to Figures 1 to 2C In some embodiments, the dummy channel structure DCH and the dam structure DS may have an internal structure different from that of the channel structure CH. The dummy channel structure DCH and the dam structure DS may include a supporting insulating layer 107. The supporting insulating layer 107 may include a material that is the same as or different from that of the gate isolation insulating layer 105. The supporting insulating layer 107 may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. For example, the supporting insulating layer 107 may be a single insulating layer.

[0075] Figure 5A and Figure 5B are plan views and cross-sectional views illustrating a semiconductor device according to some embodiments. Figure 5A Shows the corresponding Figure 1 area. Figure 5B Shows the corresponding Figure 2A area.

[0076] refer to Figure 5A and Figure 5B In the semiconductor device 100e, the dummy channel structure DCH may be between the dam structure DS and the protection structure GS. When the distance D2 between the dam structure DS and the protection structure GS is relatively large, the dummy channel structure DCH may be in the region therebetween, as shown. The dummy channel structure DCH may pass through the gate electrode 130 in the insertion region. Figure 5A and Figure 5B In the embodiment, the dummy channel structures DCH may be arranged in a row in the insertion region, but in example embodiments, the number of the dummy channel structures DCH in the insertion region and the arrangement form thereof may vary.

[0077] Fig. 6A and Figure 6B is a plan view illustrating a semiconductor device according to some embodiments. Fig. 6A and Figure 6B Each of the Figure 1 area.

[0078] refer to Fig. 6A In the semiconductor device 100f, the dam structure DS and the protection structure GS may be in the form of a symmetrical shape relative to the center in the Y direction between the first isolation regions MS1 adjacent to each other. The first horizontal region GSh1 and the second horizontal region GSh2 may be collinear with the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b. However, in some example embodiments, the first horizontal region GSh1 and the second horizontal region GSh2 may not be collinear or aligned with the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b. In some embodiments, the size and shape of the dam structure DS and the protection structure GS may vary within the range that the dam structure DS and the protection structure GS each form a closed loop (e.g., a single closed loop).

[0079] refer to Figure 6BIn the semiconductor device 100g, the side surface of the dam structure DS may have unevenness in a plan view. For example, the dam structure DS may have a shape in which circular patterns are connected to each other, and thus may have unevenness. Since the semiconductor device 100g includes the protection structure GS, the design freedom regarding the shape of the dam structure DS may be increased, and thus the shape of the dam structure DS may be varied.

[0080] 7A to 11B is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments. Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A and Fig.11A Each of the Figure 2A area, and Figure 7B , Figure 8B , Fig. 9B , Fig. 10B and Fig. 11B Each of the Figure 2C area.

[0081] refer to Fig. 7A and Figure 7B A peripheral circuit structure PERI including a circuit device 220 and a lower interconnect structure can be formed on a substrate 201, a plate layer 101, a horizontal insulating layer 110, a second horizontal conductive layer 104 and a substrate insulating layer 109 on which a storage cell area CELL is arranged can be formed on the peripheral circuit structure PERI, a lower molding structure can be formed by alternately stacking sacrificial insulating layers 118 and interlayer insulating layers 120, and a lower vertical sacrificial layer 119 can be formed.

[0082] First, a device isolation layer 210 may be formed in a substrate 201, and a circuit gate dielectric layer 222 and a circuit gate electrode 225 may be sequentially formed on the substrate 201. The device isolation layer 210 may be formed, for example, by a shallow trench isolation (STI) process. The circuit gate dielectric layer 222 and the circuit gate electrode 225 may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 222 may be formed of silicon oxide, and the circuit gate electrode 225 may be formed of at least one of polysilicon or a metal silicide layer, but the present disclosure is not limited thereto. Thereafter, a spacer layer 224 and an impurity region 205 may be formed on both sidewalls of the circuit gate dielectric layer 222 and both sidewalls of the circuit gate electrode 225. In some embodiments, the spacer layer 224 may include a plurality of layers. Thereafter, the impurity region 205 may be formed by performing an ion implantation process.

[0083] The circuit contact plug 270 of the lower interconnect structure may be formed by forming a portion of the peripheral region insulating layer 290, removing a portion by etching, and filling a conductive material therein. For example, the circuit interconnection line 280 may be formed by depositing a conductive material and patterning the material.

[0084] The peripheral region insulating layer 290 may include a plurality of insulating layers. A portion of the peripheral region insulating layer 290 may be formed in each process for forming the lower interconnection structure, and a portion thereof may be formed on the uppermost circuit interconnection line 280, so that the peripheral region insulating layer 290 may cover the circuit device 220 and the lower interconnection structure.

[0085] Thereafter, the plate layer 101 may be formed on the peripheral region insulating layer 290. The plate layer 101 may be formed of, for example, polysilicon, and may be formed by a CVD process. The polysilicon forming the plate layer 101 may include impurities.

[0086] The first to third horizontal insulating layers 111, 112, and 113 forming the horizontal insulating layer 110 may be sequentially (eg, sequentially) stacked on the board layer 101. Through subsequent processes, a portion of the horizontal insulating layer 110 may be Figure 2B and Figure 2C The horizontal insulating layer 110 may be removed by a patterning process in a partial area.

[0087] The second horizontal conductive layer 104 may be formed on the horizontal insulating layer 110 and may contact the board layer 101 in the region from which the horizontal insulating layer 110 has been removed. Therefore, the second horizontal conductive layer 104 may be bent along the end of the horizontal insulating layer 110, may cover the end, and may extend to the board layer 101.

[0088] The substrate insulating layer 109 may be formed by removing a portion of the plate layer 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104 in the through-interconnection region TR and filling the insulating material. The substrate insulating layer 109 may be formed in the entire region of the through-interconnection region TR, or may be formed in a region smaller than the entire region. After filling the insulating material, a planarization process may also be performed using a chemical mechanical polishing (CMP) process. Therefore, the upper surface of the substrate insulating layer 109 may be substantially coplanar with the upper surface of the second horizontal conductive layer 104.

[0089] A channel structure CH (see Figure 2C ) of the lower channel structure CH1 (see Figure 2C ) is arranged at a height thereon to form a lower molded structure.

[0090] A portion of the sacrificial insulating layer 118 may be replaced by the gate electrode 130 through a subsequent process (see Figure 2A ). The sacrificial insulating layer 118 may be formed of a material different from that of the interlayer insulating layer 120, and may be formed of a material having an etching selectivity to the interlayer insulating layer 120 under specific etching conditions. For example, the interlayer insulating layer 120 may be formed of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layer 118 may be formed of a material different from that of the interlayer insulating layer 120 selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In some embodiments, the thickness of the interlayer insulating layer 120 may be different. For example, the interlayer insulating layer 120 forming the uppermost layer of the lower mold structure may have a relatively large thickness. The thickness of the interlayer insulating layer 120 and the sacrificial insulating layer 118 and the number of films included therein may be different from the example shown. Thereafter, in the second region R2, a portion of the lower mold structure may be removed so that the sacrificial insulating layer 118 may extend to different lengths and a stepped structure may be formed. In some example embodiments, all of the above processes may be performed at one time after the upper mold structure described below is formed. A cell region insulating layer 190 may be formed on the uppermost sacrificial insulating layer 118 .

[0091] A lower vertical sacrificial layer 119 may be formed at a position corresponding to the lower channel structure CH1. Figure 2A A lower vertical sacrificial layer 119 is formed in an area corresponding to a lower area of ​​the dummy channel structure DCH and a lower area of ​​the dam structure DS. The lower vertical sacrificial layer 119 may be formed by forming a hole and a groove extending through the lower molding structure, filling a material forming the lower vertical sacrificial layer 119, and performing a planarization process. The lower vertical sacrificial layer 119 may include, for example, carbon (C), but the present disclosure is not limited thereto.

[0092] refer to Fig. 8A and Figure 8B , an upper mold structure may be formed, and a channel structure CH, a dummy channel structure DCH, and a dam structure DS may be formed.

[0093] The upper channel structure CH2 (see FIG. 1 ) on which the first channel structure CH is arranged may be formed on the lower mold structure. Figure 2C ). The upper mold structure may be formed by alternately stacking sacrificial insulating layers 118 and lower interlayer insulating layers 120 in the same manner as the lower mold structure. Thereafter, in the second region R2, a portion of the upper mold structure may be removed so that the sacrificial insulating layer 118 may extend to different lengths and a stepped structure may be formed. The cell region insulating layer 190 may be formed on the uppermost sacrificial insulating layer 118. Thereafter, upper vertical sacrificial layers respectively connected to the lower vertical sacrificial layers 119 may be formed.

[0094] Thereafter, a channel hole, a dummy channel hole, and a dam structure trench may be formed by removing the lower vertical sacrificial layer 119 and the upper vertical sacrificial layer. For example, when the lower vertical sacrificial layer 119 and the upper vertical sacrificial layer include carbon (C), the lower vertical sacrificial layer 119 and the upper vertical sacrificial layer may be removed by an ashing process.

[0095] The channel structure CH, the dummy channel structure DCH, and the dam structure DS may be formed by depositing at least a portion of the gate dielectric layer 145 , the channel layer 140 , the channel filling insulating layer 150 , and the channel pad 155 in each of the channel hole, the dummy channel hole, and the dam structure trench.

[0096] The gate dielectric layer 145 may be formed to have a relatively uniform or substantially uniform thickness using an ALD or CVD process. In this process, the gate dielectric layer 145 may be partially or completely formed, and a portion extending perpendicularly to the plate layer 101 along the channel structure CH may be formed in this process. The channel layer 140 may be formed on the gate dielectric layer 145 in the channel hole, the dummy channel hole, and the dam structure groove. The channel filling insulating layer 150 may fill the channel hole, the dummy channel hole, and the dam structure groove, and may be an insulating material. A channel pad 155 may be formed after partially removing the channel filling insulating layer 150. The channel pad 155 may be formed of a conductive material such as polysilicon. Therefore, the channel structure CH, the dummy channel structure DCH, and the dam structure DS formed as above may have the same internal structure. Thereafter, a cell region insulating layer 190 may also be formed.

[0097] refer to Fig.9A and Fig. 9B , first and second openings OP1 and OP2 of the mold structure extending or passing through the sacrificial insulating layer 118 may be formed.

[0098] The first opening OP1 may be formed at a position adjacent to the first isolation region MS1 ​​and the second isolation regions MS2a and MS2b (see Figure 1 ), and the second opening OP2 may be formed in a region corresponding to the protective structure GS (see Figure 2A ) in an area corresponding to the first opening OP1 and the second opening OP2. The first opening OP1 and the second opening OP2 may be formed by forming a mask layer using a photolithography process and anisotropically etching the mold structure. The first opening OP1 may be formed in a groove shape extending along the X direction, and the second opening OP2 may be formed in a quadrilateral ring shape or a shape similar thereto. The board layer 101 may be exposed through the bottom surface of the first opening OP1 and the bottom surface of the second opening OP2.

[0099] In some embodiments, a lower vertical sacrificial layer 119 and an upper vertical sacrificial layer may be formed at positions where the first opening OP1 and the second opening OP2 are formed in the above process. In this case, the first opening OP1 and the second opening OP2 may be formed by removing the lower vertical sacrificial layer 119 and the upper vertical sacrificial layer in this process.

[0100] refer to Fig. 10A and Fig. 10B , after forming the first horizontal conductive layer 102 , the tunnel portion TL may be formed by removing a portion of the sacrificial insulating layer 118 through the first opening OP1 and the second opening OP2 .

[0101] First, an etch-back process may be performed while a sacrificial spacer layer is formed in the first opening OP1 and the second opening OP2, thereby exposing the second horizontal insulating layer 112 in the first region R1. The second horizontal insulating layer 112 may be selectively removed from the exposed region, and the first horizontal insulating layer 111 and the third horizontal insulating layer 113 located above and below it may be removed. For example, the first to third horizontal insulating layers 111, 112, and 113 may be removed by a wet etching process. During the process of removing the first horizontal insulating layer 111 and the third horizontal insulating layer 113, a portion of the gate dielectric layer 145 exposed in the region from which the second horizontal insulating layer 112 has been removed may also be removed. The first horizontal conductive layer 102 may be formed by depositing a conductive material in the region from which the first to third horizontal insulating layers 111, 112, and 113 have been removed, and the sacrificial spacer layer may be removed. Through this process, the first horizontal conductive layer 102 may be formed in the first region R1.

[0102] Thereafter, the sacrificial insulating layer 118 may be removed from the outside or outer side of the through interconnect region TR. In the through interconnect region TR, the sacrificial insulating layer 118 may remain and may form an insulating region of the through interconnect region TR together with the interlayer insulating layer 120 and the substrate insulating layer 109. The sacrificial insulating layer 118 may be selectively removed relative to the interlayer insulating layer 120, the second horizontal conductive layer 104, and the substrate insulating layer 109, for example, using wet etching. Thus, a plurality of tunnel portions TL may be formed between the interlayer insulating layers 120. The region in which the through interconnect region TR is formed may be spaced apart from the first opening OP1 and the second opening OP2, and may be blocked by the dam structure DS so that the etchant cannot reach the region, and the sacrificial insulating layer 118 may remain.

[0103] refer to Fig.11A and Fig. 11B, a gate electrode 130 may be formed by filling the tunneling portion TL with a conductive material, a first isolation region MS1 ​​and a second isolation region MS2a and MS2b and a protection structure GS may be formed, and a through via 170 (see FIG. 1 ) may be formed in the through interconnect region TR. Figure 2A ) through hole VH.

[0104] The conductive material forming the gate electrode 130 may fill the tunneling portion TL. The conductive material may include a metal, polysilicon, or a metal silicide material. The side surface of the gate electrode 130 may contact the outer side surface of the dam structure DS. When the gate electrode 130 is formed, the dam structure DS may prevent the conductive material from flowing into the through-interconnection region TR. After the gate electrode 130 is formed, the conductive material deposited in the first opening OP1 and the second opening OP2 may be removed by an additional process. The gate isolation insulating layer 105 may fill the first opening OP1 and the second opening OP2. Therefore, the first isolation region MS1 ​​and the second isolation region MS2a and MS2b and the protection structure GS may be formed together and have the same internal structure. Each gate electrode in the gate electrode 130 may be physically and electrically isolated into two regions by the protection structure GS.

[0105] Before forming the through hole VH, the cell region insulating layer 190 may be formed to cover the gate isolation insulating layer 105. Thereafter, in the through interconnection region TR, a through hole VH penetrating the cell region insulating layer 190, the interlayer insulating layer 120, the sacrificial insulating layer 118, and the substrate insulating layer 109 may be formed. The circuit interconnection line 280 of the peripheral circuit structure PERI may be exposed at the lower end of the through hole VH. In this process, a contact hole PH may also be formed to form a gate contact plug 175 connected to the gate electrode 130 (see Figure 2C ).

[0106] After that, refer to Figures 1 to 2C , a through via 170 and a gate contact plug 175 may be formed by filling the through hole VH and the contact hole PH with conductive materials, respectively. An upper plug 178 may be formed on the through via 170 and the gate contact plug 175, and an interconnection line 180 connected to an upper end of the upper plug 178 may be formed, thereby manufacturing the semiconductor device 100.

[0107] Fig.12 is a view illustrating a data storage system including a semiconductor device according to some embodiments.

[0108] refer to Fig.12, the data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be implemented as a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be implemented as a solid state drive (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0109] The semiconductor device 1100 may be implemented as a nonvolatile memory device, for example, as described in the foregoing embodiments. Figures 1 to 6B The NAND flash memory device described herein. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S located on the first structure 1100F. In some embodiments, the first structure 1100F may be on the side of the second structure 1100S. The first structure 1100F may be implemented as a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be implemented as a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR disposed between the bit line BL and the common source line CSL.

[0110] In the second structure 1100S, each memory cell string in the memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. In different embodiments and implementations, the number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary.

[0111] In some embodiments, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The gate lower lines LL1 and LL2 may be configured as gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be configured as a gate electrode of the memory cell transistor MCT, and the gate upper lines UL1 and UL2 may be configured as gate electrodes of the upper transistors UT1 and UT2, respectively.

[0112] In some embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series to each other. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series to each other. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation for erasing data stored in the memory cell transistor MCT using the GIDL phenomenon.

[0113] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word lines WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through the first connection interconnection 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through the second connection interconnection 1125 extending from the first structure 110F to the second structure 1100S.

[0114] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by a logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through an input / output connection line 1135 extending from the first structure 1100F to the second structure 1100S.

[0115] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In some embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor devices 1100 .

[0116] The processor 1210 may control the overall operation of the data storage system 1000 including the controller 1200. The processor 1210 may operate according to a predetermined firmware, and may access the semiconductor device 1100 by controlling the NAND controller 1220. The NAND controller 1220 may include a controller interface 1221 configured to handle communication with the semiconductor device 1100. Through the controller interface 1221, a control command for controlling the semiconductor device 1100, data to be written to the memory cell transistor MCT of the semiconductor device 1100, and data to be read from the memory cell transistor MCT of the semiconductor device 1100 may be transmitted. The host interface 1230 may provide a communication function between the data storage system 1000 and an external host. When a control command from an external host is received through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0117] Fig.13 is a perspective view illustrating a data storage system including a semiconductor device according to example embodiments.

[0118] refer to Fig.13 , the data storage system 2000 in some embodiments may include a mainboard 2001, a controller 2002 mounted on the mainboard 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through an interconnection pattern 2005 formed on the mainboard 2001.

[0119] The mainboard 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary according to the communication interface between the data storage system 2000 and the external host. In some embodiments, the data storage system 2000 may communicate with the external host according to one of the interfaces among the universal serial bus (USB), the peripheral component interconnect fast (PCI-Express), the serial advanced technology attachment (SATA), or the M-Phy for universal flash memory (UFS). In some embodiments, the data storage system 2000 may operate by power supplied from the external host via the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) for distributing the power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0120] The controller 2002 may write data to the semiconductor package 2003 or may read data from the semiconductor package, and may increase the operation speed of the data storage system 2000 .

[0121] The DRAM 2004 may be configured as a buffer memory for alleviating a difference in speed between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the data storage system 2000 may be used as a buffer memory and may provide a space for temporarily storing data in a control operation of the semiconductor package 2003. When the data storage system 2000 may include the DRAM 2004, the controller 2002 may include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0122] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. The first semiconductor package 2003a and the second semiconductor package 2003b may each be configured as a semiconductor package including a plurality of semiconductor chips 2200. The first semiconductor package 2003a and the second semiconductor package 2003b may each include a package substrate 2100, a semiconductor chip 2200 located on the package substrate 2100, an adhesive layer 2300 on the lower surface of the semiconductor chip 2200, respectively, a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a mold layer 2500 covering the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0123] The package substrate 2100 may be configured as a printed circuit board including the upper package pads 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Fig.12 Each of the semiconductor chips 2200 may include a gate stack structure 3210 and a channel structure 3220. Each of the semiconductor chips 2200 may include the aforementioned reference Figures 1 to 6B The semiconductor device described in the described embodiments.

[0124] In some embodiments, the connection structure 2400 may be configured as a bonding wire that electrically connects the input / output pad 2210 to the upper package pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by a bonding wire method, and may be electrically connected to the upper package pad 2130 of the package substrate 2100. In some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by a connection structure including a through-hole electrode (TSV) instead of the connection structure 2400 of the bonding wire method.

[0125] In some embodiments, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In some embodiments, the controller 2002 and the semiconductor chip 2200 may be mounted on an interposer substrate different from the mainboard 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other through interconnects formed on the interposer substrate.

[0126] Fig.14 is a cross-sectional view showing a semiconductor package according to some embodiments, showing a cross-sectional view taken along line IV-IV' Fig.13 An example embodiment of a semiconductor package 2003 in FIG.

[0127] refer to Fig.14 In the semiconductor package 2003, the package substrate 2100 may be implemented as a printed circuit substrate. The package substrate 2100 may include a package substrate body portion 2120, an upper package pad 2130 located on the upper surface of the package substrate body portion 2120, a lower pad 2125 located on the lower surface of the package substrate body portion 2120 or exposed through the lower surface, and an internal interconnect 2135 in the package substrate body portion 2120 that electrically connects the upper package pad 2130 to the lower pad 2125. Fig.13 As shown, the lower pad 2125 may be connected to the interconnection pattern 2005 of the main board 2001 of the data storage system 2000 through the conductive connection portion 2800 .

[0128] Each of the semiconductor chips 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including a peripheral interconnect 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 located on the common source line 3205, a channel structure 3220 passing through the gate stack structure 3210, a bit line 3240 electrically connected to the channel structure 3220, and a word line WL electrically connected to the gate stack structure 3210 (see Fig.12 ) of the contact plug 3235. As shown in reference Figures 1 to 6B As described in the aforementioned embodiments, each of the semiconductor chips 2200 may sequentially include the dam structure DS and the protection structure GS surrounding the through interconnection region TR.

[0129] Each of the semiconductor chips 2200 may include a through-interconnect 3245 electrically connected to the peripheral interconnect 3110 of the first structure 3100 and extending into the second structure 3200. The through-interconnect 3245 may be located outside the gate stack structure 3210 and may also be disposed to pass through the gate stack structure 3210. Each of the semiconductor chips 2200 may also include an input / output pad 2210 electrically connected to the peripheral interconnect 3110 of the first structure 3100 (see Fig.13 ).

[0130] According to the inventive concepts set forth herein, a semiconductor device having improved reliability and a data storage system including the semiconductor device may be provided by including a dam structure and a protection structure surrounding the dam structure.

[0131] Although some examples of embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made to the inventive concepts herein without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: A first semiconductor structure, the first semiconductor structure comprising a substrate, a circuit device located on the substrate, and a circuit interconnection line located on the circuit device; as well as a second semiconductor structure, the second semiconductor structure being located on the first semiconductor structure and having a through interconnect region, Wherein, the second semiconductor structure comprises: Lamellar; Gate electrodes, the gate electrodes are spaced apart from each other on the plate layer along a first direction perpendicular to an upper surface of the plate layer, the gate electrodes extend to different lengths along a second direction perpendicular to the first direction and form a step region; an interlayer insulating layer, wherein the interlayer insulating layer and the gate electrode are alternately stacked; channel structures extending through the gate electrode along the first direction, and each of the channel structures comprising a channel layer; isolation regions extending through the gate electrode, extending along the first direction and the second direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction; a sacrificial insulating layer, the sacrificial insulating layer being alternately stacked with the interlayer insulating layer in the through-interconnection region; a through via extending through the sacrificial insulating layer and the interlayer insulating layer in the through interconnect region and extending into the first semiconductor structure along the first direction; a dam structure surrounding the through via, extending through the interlayer insulating layer in the first direction, and including the channel layer; and a protection structure horizontally spaced apart from the dam structure, surrounding the dam structure, and extending through the interlayer insulating layer along the first direction, Wherein, the dam structure and the protection structure have different internal structures.

2. The semiconductor device according to claim 1, wherein An outer surface and an inner surface of the protection structure are in contact with the gate electrode.

3. The semiconductor device according to claim 1, wherein An inner surface of the dam structure contacts the sacrificial insulating layer.

4. The semiconductor device according to claim 1, in, The dam structure and the channel structure have the same internal structure, and Wherein, the protection structure and the isolation area have the same internal structure.

5. The semiconductor device according to claim 4, wherein: Each of the channel structure and the dam structure includes a gate dielectric layer, the channel layer, and a channel filling insulating layer arranged in sequence from the gate electrode.

6. The semiconductor device according to claim 4, wherein: The protection structure includes a single insulating layer.

7. The semiconductor device according to claim 1, wherein The protection structure and the dam structure both have a closed loop shape.

8. The semiconductor device according to claim 1, wherein When viewed in a plan view, the protection structure has a quadrilateral ring shape, a circular ring shape, or an elliptical ring shape.

9. The semiconductor device according to claim 1, wherein: The upper end of the dam structure and the upper end of the protection structure are not coplanar.

10. The semiconductor device according to claim 1, wherein The protection structure is spaced apart from the isolation region.

11. The semiconductor device according to claim 1, in, The protection structure includes a first region extending along the second direction and a second region extending along the third direction, and The first region is arranged in a straight line with the isolation region along the second direction.

12. The semiconductor device according to claim 1, in, The second semiconductor structure further includes a dummy channel structure extending along the first direction and penetrating at least a portion of the gate electrode, and Wherein, at least one of the dummy channel structures is located between the dam structure and the protection structure.

13. A semiconductor device, comprising: Lamellar; Gate electrodes, the gate electrodes being spaced apart from each other on the plate layer along a first direction perpendicular to an upper surface of the plate layer, extending to different lengths along a second direction perpendicular to the first direction and forming a step region; channel structures extending through the gate electrode and along the first direction, and each of the channel structures includes a channel layer; an isolation region extending through the gate electrode and extending along the first direction and the second direction; A sacrificial insulating layer, wherein the sacrificial insulating layer is parallel to the gate electrodes respectively; a through via extending through the sacrificial insulating layer along the first direction; a dam structure surrounding the through passage; as well as A protection structure is horizontally spaced apart from the dam structure and has a closed loop shape surrounding the dam structure in plan view.

14. The semiconductor device according to claim 13, in, Each of the gate electrodes includes a first region located outside the protection structure and a second region surrounded by the protection structure, and The first region and the second region are electrically isolated from each other.

15. The semiconductor device according to claim 13, wherein: The dam structure and the protection structure have different internal structures.

16. The semiconductor device according to claim 13, wherein: At least one of the dam structure and the protection structure includes a single insulating layer.

17. The semiconductor device according to claim 13, wherein: An inner surface of the dam structure contacts the sacrificial insulating layer, and an outer surface of the dam structure contacts the gate electrode.

18. The semiconductor device according to claim 13, wherein: The dam structure and the protection structure have different heights in the first direction.

19. A data storage system, the data storage system comprising: A semiconductor memory device including a first semiconductor structure having a circuit device, a second semiconductor structure located on a first side of the first semiconductor structure, and an input / output pad electrically connected to the circuit device; as well as a controller electrically connected to the semiconductor memory device through the input / output pad and configured to control the semiconductor memory device, wherein the second semiconductor structure comprises: Lamellar; Gate electrodes, the gate electrodes being spaced apart from each other on the plate layer along a first direction perpendicular to an upper surface of the plate layer, the gate electrodes extending to different lengths along a second direction perpendicular to the first direction and forming a stepped region; channel structures, the channel structures extending through the gate electrode along the first direction and each comprising a channel layer; an isolation region extending through the gate electrode and extending along the first direction and the second direction; A sacrificial insulating layer, wherein the sacrificial insulating layer is parallel to the gate electrode respectively; a through via extending through the sacrificial insulating layer along the first direction; a dam structure surrounding the through passage; and a protective structure horizontally spaced apart from and surrounding the dam structure, Each of the gate electrodes includes a first region located on an outer side of the protection structure and a second region surrounded by the protection structure, and the first region and the second region are electrically isolated from each other.

20. The data storage system according to claim 19, wherein: The protection structure has a closed loop shape in a plan view.

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